A busbar charging control device and power supply system

Abstract

The present invention discloses a bus charging control device and a power supply system, the device comprising: a rectifying unit, configured to rectify the input alternating current and output direct current to the bus; a driving signal generating unit, configured to generate a driving signal based on the control power supply and the bus voltage of the positive electrode of the bus capacitor module when the control power supply is powered on; a first charging control module, configured to generate a first control signal capable of controlling the first switch control module to be turned on or off based on the driving signal; and a second charging control module, configured to generate a second control signal capable of controlling the second switch control module to be turned on or off based on the driving signal. This solution can realize the bus charging control of the bus charging control circuit without CPU, and can reduce the difficulty of designing and developing the bus charging circuit without CPU control.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuits, and specifically relates to a bus charging control device and a power supply system, and more particularly to a bus charging control circuit and a power supply system with a protection function. Background Art

[0002] The commonly used AC input voltage is 220V or 380V. During the bus charging process after rectification, since there is a large energy storage capacitor on the bus, the bus charging usually uses PTC (positive temperature coefficient) resistors and switching devices to charge the capacitor in sections.

[0003] The switching devices of the bus charging circuit are all realized through CPU control. However, in the bus charging circuit without CPU control, in order to realize the logic control of bus charging, an additional CPU control circuit is required, which increases the difficulty of design and development.

[0004] The above contents are only used to assist in understanding the technical solution of the present invention and do not constitute an admission that the above contents are prior art. Summary of the invention

[0005] The object of the present invention is to provide a bus charging control device and a power supply system to solve the problem that an additional CPU control circuit is required in a bus charging circuit without CPU control, which increases the difficulty of design and development, thereby achieving the effect of reducing the difficulty of design and development of a bus charging circuit without CPU control.

[0006] The present invention provides a bus charging control device, comprising: a rectifier unit, a drive signal generating unit, a charging control unit and a bus charging unit; the charging control unit comprises: a first charging control module and a second charging control module; the bus charging unit comprises: a first switch control module, a second switch control module, a charging resistor module and a bus capacitor module; the output end of the rectifier unit is connected to the first connection end of the first switch control module and also connected to the first connection end of the second switch control module; the second connection end of the first switch control module is connected to the positive electrode of the bus capacitor module after passing through the charging resistor module; the second connection end of the second switch control module is connected to the positive electrode of the bus capacitor module; The control end is connected to the output end of the first charging control module, and the control end of the second switch control module is connected to the output end of the second charging control module; wherein the rectifier unit is configured to rectify the input alternating current and output direct current to the bus; the drive signal generating unit is configured to generate a drive signal based on the control power supply and the bus voltage of the positive electrode of the bus capacitor module when the control power supply is powered on; the first charging control module is configured to generate a first control signal capable of controlling the first switch control module to be turned on or off based on the drive signal; the second charging control module is configured to generate a second control signal capable of controlling the second switch control module to be turned on or off based on the drive signal.

[0007] In some embodiments, when the bus voltage at the positive electrode of the bus capacitor module is lower than the first set voltage, the level of the drive signal generated by the drive signal generating unit is the first set level, the first control signal controls the first switch control module to turn on, the second control signal controls the second switch control module to turn off, and the bus supplies power to the bus capacitor module through the first switch control module and the charging resistor module; when the bus voltage at the positive electrode of the bus capacitor module exceeds the first set voltage, the level of the drive signal generated by the drive signal generating unit is the second set level, the first control signal controls the first switch control module to turn off, the second control signal controls the second switch control module to turn on, and the bus supplies power to the bus capacitor module through the second switch control module.

[0008] In some embodiments, the drive signal generating unit includes: a first comparison module and a first adjustment module; wherein, the non-phase input terminal of the first comparison module can input the power signal of the control power supply; the inverting input terminal of the first comparison module can input the bus voltage of the positive electrode of the bus capacitor module; the output terminal of the first comparison module can output the drive signal generated by the drive signal generating unit; the first adjustment module is set at the non-phase input terminal of the first comparison module and the inverting input terminal of the first comparison module, and is configured to adjust the first set voltage.

[0009] In some embodiments, the first charging control module includes: a first AND gate module, a first buffer module and a first switch tube module; wherein the first input end of the first AND gate module can input the power signal of the control power supply; the second input end of the first AND gate module can input the drive signal; the output end of the first AND gate module is connected to the input end of the first switch tube module after passing through the first buffer module; the output end of the first switch tube module is connected to the control end of the first switch control module; the second charging control module includes: a NOT gate module, a second AND gate module, a second buffer module and a second switch tube module; wherein the first input end of the second AND gate module can input the power signal of the control power supply; the second input end of the second AND gate module can input the reverse drive signal output after the drive signal is processed by the NOT gate module; the output end of the second AND gate module is connected to the input end of the second switch tube module after passing through the second buffer module; the output end of the second switch tube module is connected to the control end of the second switch control module.

[0010] In some embodiments, it also includes: at least one of an undervoltage protection unit and an overvoltage protection unit; wherein the undervoltage protection unit is configured to perform undervoltage detection on the bus voltage of the positive electrode of the bus capacitor module and output an undervoltage protection signal; wherein, when the bus voltage of the positive electrode of the bus capacitor module is less than a first set voltage, the level of the undervoltage protection signal output by the undervoltage protection unit is a first set level; when the bus voltage of the positive electrode of the bus capacitor module is greater than or equal to the first set voltage and less than a second set voltage, the undervoltage protection unit outputs the The level of the undervoltage protection signal is the second set level; the overvoltage protection unit is configured to perform overvoltage detection on the bus voltage at the positive electrode of the bus capacitor module and output an overvoltage protection signal; wherein, when the bus voltage at the positive electrode of the bus capacitor module is greater than or equal to the second set voltage, the level of the overvoltage protection signal output by the overvoltage protection unit is the first set level; when the bus voltage at the positive electrode of the bus capacitor module is greater than or equal to the first set voltage and less than the second set voltage, the level of the undervoltage protection signal output by the overvoltage protection unit is the second set level.

[0011] In some embodiments, the overvoltage protection unit includes: a second comparison module and a second adjustment module; the in-phase input terminal of the second comparison module can input the bus voltage of the positive electrode of the bus capacitor module; the inverting input terminal of the second comparison module can input the power signal of the control power supply; the output terminal of the second comparison module can output the overvoltage protection signal; the second adjustment module is set at the in-phase input terminal of the second comparison module and the inverting input terminal of the second comparison module, and is configured to adjust the first set voltage and the second set voltage.

[0012] In some embodiments, the undervoltage protection unit includes: a third comparison module and a third adjustment module; wherein, the non-inverting input terminal of the third comparison module can input the power signal of the control power supply; the inverting input terminal of the third comparison module can input the bus voltage of the positive electrode of the bus capacitor module; the output terminal of the third comparison module can output the undervoltage protection signal; the third adjustment module is arranged at the non-inverting input terminal of the third comparison module and the inverting input terminal of the third comparison module, and is configured to adjust the second set voltage.

[0013] In some embodiments, it also includes: a delay unit; the delay unit is configured to generate a delay control signal according to the first input signal of the first buffer module and the second input signal of the second buffer module, and according to the delay control signal, after a delay setting time, output an enable signal for enabling control of the undervoltage protection unit or the overvoltage protection unit; wherein the enable signal can be output to the enable control terminal of the first buffer module in the first charging control module, and can also be output to the enable control terminal of the second buffer module in the second charging control module.

[0014] In some embodiments, the delay unit includes: a delay module, an XNOR gate module, an optocoupler module, and an OR gate module; wherein the first input end of the XNOR gate module can input the first input signal of the first buffer module; the second input end of the XNOR gate module can input the second input signal of the second buffer module; the cathode on the diode side of the optocoupler module can input the output signal of the XNOR gate module; the emitter on the transistor side of the optocoupler module can output a delay control signal to the delay control end of the delay module; the delay module can delay the overvoltage protection signal or the undervoltage protection signal under the control of the delay control signal; the OR gate module performs OR logic processing on the overvoltage protection signal or the undervoltage protection signal after the delay processing, and outputs an enable signal for enabling the undervoltage protection unit or the overvoltage protection unit.

[0015] In some embodiments, the delay module includes: a third switch tube module, a timing module and a third buffer module; wherein, the input end of the third switch tube module can input the delay control signal; the output end of the third switch tube module is input to the third buffer module after passing through the timing module, and the third buffer module can perform delay processing based on the undervoltage protection signal.

[0016] Matching the above-mentioned device, the present invention further provides a power supply system on the other hand, including: the bus charging control device mentioned above.

[0017] Therefore, the scheme of the present invention can realize the CPU-free bus charging control of the bus charging control circuit through the driving signal generating circuit and the switch driving circuit, thereby avoiding the need to add an additional CPU control circuit when performing bus charging control for the bus charging circuit without CPU control, thereby reducing the difficulty of designing and developing the bus charging circuit without CPU control.

[0018] Furthermore, the scheme of the present invention can also set up a bus charging control circuit with a protection function through an overvoltage detection circuit and an undervoltage detection circuit, in conjunction with a delay circuit, which can shorten the processing time of the control logic or alarm logic when the bus generates overvoltage or undervoltage, and can also close the switching device in time, thereby improving the control reliability and safety of the bus charging circuit.

[0019] Other features and advantages of the present invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the present invention.

[0020] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a structural schematic diagram of an embodiment of a bus charging control device of the present invention;

[0022] Figure 2 It is a structural schematic diagram of an embodiment of a bus charging circuit;

[0023] Figure 3 A schematic structural diagram of an embodiment of a circuit for charging a bus bar by controlling a switch device through a CPU;

[0024] Figure 4 It is a structural schematic diagram of an embodiment of a rectifier circuit in a bus charging control circuit;

[0025] Figure 5 It is a structural schematic diagram of an embodiment of a driving signal generating circuit in a bus charging control circuit;

[0026] Figure 6 It is a structural schematic diagram of an embodiment of an overvoltage detection circuit in a bus charging control circuit;

[0027] Figure 7 It is a structural schematic diagram of an embodiment of an undervoltage detection circuit in a bus charging control circuit;

[0028] Figure 8 It is a structural schematic diagram of an embodiment of a delay circuit in a bus charging control circuit;

[0029] Fig. 9 A schematic structural diagram of an embodiment of a switch driving circuit in a bus charging control circuit;

[0030] Fig.10 Schematic diagram of the signal logic truth table.

[0031] In conjunction with the accompanying drawings, the reference numerals in the embodiments of the present invention are as follows:

[0032] 1-Rectifier circuit; 2-Generate switch drive signal; 3-Overvoltage detection; 4-Undervoltage detection; 5-Delay circuit; 6-Switch drive circuit. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the specific embodiments of the present invention and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0034] According to an embodiment of the present invention, a busbar charging control device is provided, and a 220V AC input voltage is used as an example for description. Figure 1 The schematic diagram of the structure of an embodiment of the device of the present invention is shown. The bus charging control device includes: a rectifier unit, a drive signal generating unit, a charging control unit and a bus charging unit. The rectifier unit, such as the rectifier circuit 1, includes a rectifier bridge. The drive signal generating unit, such as the drive signal generating circuit 2. The charging control unit and the bus charging unit, such as the switch driving circuit 6. The charging control unit includes: a first charging control module and a second charging control module. The bus charging unit includes: a first switch control module, a second switch control module, a charging resistor module and a bus capacitor module. The first switch control module is such as the first relay K1, and the second switch control module is such as the second relay K2. Of course, the first switch control module and the second switch control module can also be replaced by other controllable switch devices, such as MOS tubes, transistors, triodes, IGBTs, etc., which can also achieve the same purpose. Charging resistor module, such as PTC resistor R29. Bus capacitor module, such as a bus capacitor module composed of more than one bus capacitor, when the number of bus capacitors is more than two, two bus capacitors are arranged in parallel. The output end of the rectifier unit is connected to the first connection end of the first switch control module and also connected to the first connection end of the second switch control module. The second connection end of the first switch control module is connected to the positive electrode of the bus capacitor module through the charging resistor module. The second connection end of the second switch control module is connected to the positive electrode of the bus capacitor module. The control end of the first switch control module is connected to the output end of the first charging control module, and the control end of the second switch control module is connected to the output end of the second charging control module.

[0035] The rectifying unit is configured to rectify the input alternating current and output direct current to the bus.

[0036] The driving signal generating unit is configured to generate a driving signal based on the control power supply and the bus voltage of the positive electrode of the bus capacitor module when the control power supply is powered on. The control power supply is, for example, a P12V power supply.

[0037] In some embodiments, the driving signal generating unit includes: a first comparing module and a first adjusting module.

[0038] The non-inverting input terminal of the first comparison module can be input with the power supply signal of the control power supply, the inverting input terminal of the first comparison module can be input with the bus voltage of the positive electrode of the bus capacitor module, and the output terminal of the first comparison module can output the drive signal generated by the drive signal generating unit.

[0039] The first regulating module is arranged at the non-inverting input terminal of the first comparing module and the inverting input terminal of the first comparing module, and is configured to regulate the first setting voltage to achieve regulating the switching voltages of the first switch control module and the second switch control module.

[0040] Specifically, the resistance values ​​of the resistors (such as the resistor R1 and the resistor R2 ) at the positive and negative input electrodes of the comparator U6 in the driving signal generating circuit 2 may be adjusted to adjust the voltage when the second relay K2 is switched.

[0041] The first charging control module is configured to generate a first control signal capable of controlling the first switch control module to be turned on or off based on the driving signal.

[0042] The second charging control module is configured to generate a second control signal capable of controlling the second switch control module to be turned on or off based on the driving signal.

[0043] Specifically, in the rectifier circuit 1, the rectifier bridge obtains DC signals DC+ and PGND after rectifying the AC input power input to the three-phase AC input terminals R, S, and T. The DC signal DC+ is connected to the input terminals of the first relay K1 and the second relay K2, and the output terminal of the first relay K1 is connected to the positive electrode DCP of the bus capacitor module after being connected in series with a PTC resistor R29; the output terminal of the second relay K2 is directly connected to the positive electrode DCP of the bus capacitor module. Before the control power supply P12V is powered on, the bus charging control circuit does not work, the first relay K1 and the second relay K2 are disconnected, the bus is disconnected from the rectifier circuit 1, and the bus is not charged; when the control power supply P12V is established, the bus charging control circuit starts to work, and the control function of the bus charging circuit begins to be realized.

[0044] Therefore, by adopting a pure hardware circuit control method, by using a hardware circuit to detect the bus voltage to generate a relay driver signal, an overvoltage detection signal, and an undervoltage detection signal, combined with a delay control circuit, a logic control circuit, and a buffer, etc., the bus circuit charging and overvoltage and undervoltage protection functions can be completed without the participation of the CPU, thereby realizing CPU-free control of the bus power supply circuit.

[0045] When the bus charging process is controlled, when the bus voltage at the positive electrode of the bus capacitor module is lower than the first set voltage, the level of the drive signal generated by the drive signal generating unit is the first set level, the first control signal controls the first switch control module to turn on, and the second control signal controls the second switch control module to turn off, and the direct current output by the rectifier unit supplies power to the bus capacitor module via the bus through the first switch control module and the charging resistor module.

[0046] When the bus voltage at the positive electrode of the bus capacitor module exceeds the first set voltage, the level of the drive signal generated by the drive signal generating unit is a second set level, the first control signal controls the first switch control module to be turned off, and the second control signal controls the second switch control module to be turned on, and the direct current output by the rectifier unit supplies power to the bus capacitor module via the bus through the second switch control module.

[0047] The first set voltage is, for example, 270 V. The first set level is, for example, a high level. The second set level is, for example, a low level.

[0048] Therefore, by controlling the control circuit that can supply power to the bus by controlling different charging circuits during the bus power-on stage, the bus charging can get rid of the dependence of the bus charging on the CPU control, and the bus charging control can be realized without the CPU, which can solve the problem that it is difficult to realize the bus charging logic control in the bus charging circuit without CPU control. Moreover, in the bus charging circuit with CPU control, the bus charging control does not require the participation of the CPU, and the bus charging control does not occupy CPU resources.

[0049] In some implementations, the first charging control module includes: a first AND gate module, a first buffer module and a first switch tube module.

[0050] The first input end of the first AND gate module can be used to input the power supply signal of the control power supply. The second input end of the first AND gate module can be used to input the drive signal. The output end of the first AND gate module is connected to the input end of the first switch tube module after passing through the first buffer module. The output end of the first switch tube module is connected to the control end of the first switch control module.

[0051] Specifically, the first AND gate module is such as the AND gate U2. The first buffer module is such as the buffer U4. The first switch tube module is such as the first switch tube Q1. The output end of the AND gate U2 is output to the input end B of the buffer U4, and the output end A of the buffer U4 is output to the base of the first switch tube Q1 (such as a triode). The collector of the first switch tube Q1 (such as a triode) is connected to the control end of the first relay K1, that is, the collector of the first switch tube Q1 (such as a triode) is connected to the first end of the coil of the first relay K1, and the second end of the coil of the first relay K1 is connected to the control power supply P12.

[0052] The second charging control module includes: a NOT gate module, a second AND gate module, a second buffer module and a second switch tube module.

[0053] The first input end of the second AND gate module can be used to input the power supply signal of the control power supply. The second input end of the second AND gate module can be used to input the reverse driving signal output after the driving signal is processed by the NOT gate module. The output end of the second AND gate module is connected to the input end of the second switch tube module after passing through the second buffer module. The output end of the second switch tube module is connected to the control end of the second switch control module.

[0054] Specifically, a NOT gate module, such as a NOT gate U1. A second AND gate module, such as an AND gate U3. A second buffer module, such as a buffer U5. A second switch tube module, such as a second switch tube Q2. The output end of the AND gate U3 is output to the input end B of the buffer U5, and the output end A of the buffer U5 is output to the base of the second switch tube Q2 (such as a triode), and the collector of the second switch tube Q2 (such as a triode) is connected to the control end of the second relay K2, that is, the collector of the second switch tube Q2 (such as a triode) is connected to the first end of the coil of the second relay K2, and the second end of the coil of the second relay K2 is connected to the control power supply P12.

[0055] During operation, after the control power supply P12V is established, the drive signal generating circuit 2 generates a switch drive signal Driver, and the bus charging control circuit starts to work. The bus voltage charging control is realized through the comparator U6. When the bus voltage is lower than 270V, the switch drive signal Driver is at a high level, and after passing through the AND gate U2, it outputs a high level to the input end of the buffer U4. At the same time, after passing through the NOT gate U1, it outputs a low level to the input end of the buffer U5 through the AND gate U3. At this time, the enable signal Protect of the buffer U4 and the buffer U5 is at a low level, the buffer U4 outputs the first drive signal Driver1 at a high level, and the buffer U5 outputs the second drive signal Driver2 at a low level; at this time, through the first switch tube Q1, the first control signal Relay1 of the first relay K1 is pulled low, and the first relay K1 is closed; through the second switch tube Q2, the second control signal Relay2 of the second relay K2 is at a high level, and the second relay K2 is disconnected, and the bus supplies power to the bus capacitor module through the first relay K1 and the PTC resistor R29.

[0056] After the bus voltage exceeds 270V, the drive signal generating circuit 2 generates a switch drive signal Driver at a low level, and outputs a low level to the input end of the buffer U4 after passing through the AND gate U2. At the same time, it passes through the NOT gate U1 and then the AND gate U3 to output a high level to the input end of the buffer U5. At this time, the enable signal Protect of the buffer U4 and the buffer U5 is a low level, the buffer U4 outputs the first drive signal Driver1 at a low level, and the buffer U5 outputs the second drive signal Driver2 at a high level; at this time, the first relay K1 control signal Relay1 is a high level, and the first relay K1 is disconnected; the second relay K2 control signal Relay2 is a low level, and the second relay K2 is closed, and the bus supplies power to the bus capacitor module through the second relay K2.

[0057] In some embodiments, the bus charging control device further includes: at least one of an undervoltage protection unit and an overvoltage protection unit.

[0058] Wherein, the undervoltage protection unit is configured to perform undervoltage detection on the bus voltage of the positive electrode of the bus capacitor module and output an undervoltage protection signal. Wherein, when the bus voltage of the positive electrode of the bus capacitor module is less than the first set voltage, the level of the undervoltage protection signal output by the undervoltage protection unit is the first set level. When the bus voltage of the positive electrode of the bus capacitor module is greater than or equal to the first set voltage and less than the second set voltage, the level of the undervoltage protection signal output by the undervoltage protection unit is the second set level.

[0059] The overvoltage protection unit is configured to perform overvoltage detection on the bus voltage of the positive electrode of the bus capacitor module and output an overvoltage protection signal. Wherein, when the bus voltage of the positive electrode of the bus capacitor module is greater than or equal to the second set voltage, the level of the overvoltage protection signal output by the overvoltage protection unit is the first set level. When the bus voltage of the positive electrode of the bus capacitor module is greater than or equal to the first set voltage and less than the second set voltage, the level of the undervoltage protection signal output by the overvoltage protection unit is the second set level.

[0060] In some implementations, the overvoltage protection unit includes: a second comparison module and a second adjustment module.

[0061] The in-phase input terminal of the second comparison module can input the bus voltage of the positive electrode of the bus capacitor module, the inverting input terminal of the second comparison module can input the power signal of the control power supply, and the output terminal of the second comparison module can output the overvoltage protection signal.

[0062] The second regulating module is arranged at the non-inverting input terminal of the second comparing module and the inverting input terminal of the second comparing module, and is configured to regulate the first setting voltage and the second setting voltage to adjust the protection voltage of the overvoltage protection unit.

[0063] Specifically, the overvoltage protection value can be adjusted by adjusting the resistance values ​​of the resistors (such as the resistor R6 and the resistor R8) at the positive and negative input electrodes of the comparator U7 in the overvoltage detection circuit 3.

[0064] In some implementations, the undervoltage protection unit includes: a third comparison module and a third adjustment module.

[0065] The in-phase input terminal of the third comparison module can be input with the power supply signal of the control power supply, the inverting input terminal of the third comparison module can be input with the bus voltage of the positive electrode of the bus capacitor module, and the output terminal of the third comparison module can output the undervoltage protection signal.

[0066] The third regulating module is arranged at the non-inverting input terminal of the third comparing module and the inverting input terminal of the third comparing module, and is configured to regulate the second setting voltage to adjust the protection voltage of the undervoltage protection unit.

[0067] Specifically, by adjusting the resistors (such as the resistor R11 and the resistor R13 ) on the positive and negative input electrodes of the comparator U8 in the undervoltage detection circuit 4 , the undervoltage protection value can be adjusted.

[0068] During operation, when the undervoltage detection circuit 4 takes effect, if the bus is short-circuited or fails, and the bus voltage is lower than 270V, the comparator U8 in the undervoltage detection circuit 4 outputs a high-level signal DVC, that is, the output signal DVP of the buffer U11 is high. The comparator U7 in the overvoltage detection circuit 3 outputs a low-level signal OVP, and the logic device or gate U9 outputs a high-level signal Protect, triggering the protection, and the outputs of the buffers U4 and U5 are turned off, stopping power supply to the bus.

[0069] When the undervoltage protection circuit 4 takes effect, if the bus voltage is greater than 270V and less than 390V, the output signal OVP of the overvoltage detection circuit 3 and the output signal DVC of the undervoltage detection circuit 4 are both low level. At this time, the bus works normally and the bus is powered by the second relay K2.

[0070] When the bus voltage exceeds 390V, the comparator U7 output signal OVP in the overvoltage detection circuit 3 is high, and the DVP signal is low at this time. The U9 output signal Protect is high, triggering the protection function, turning off the buffer U4 and buffer U5 outputs. At this time, the first relay K1 control signal Relay1 and the second relay K2 control signal Relay2 are pulled high, the first relay K1 and the second relay K2 are disconnected, and the bus power supply stops.

[0071] Therefore, pure hardware control can greatly shorten the logic / alarm logic processing time when the busbar produces overvoltage or undervoltage, shut down the switching devices in time, and improve the reliability and safety of the controller.

[0072] In some embodiments, the bus charging control device further includes: a delay unit. The delay unit is configured to generate a delay control signal (such as the output signal DVP_DIR output by the emitter of the transistor side of the optocoupler U12) according to the first input signal of the first buffer module (such as the input signal Driver_in1 of the buffer U4) and the second input signal of the second buffer module (such as the input signal Driver_in2 of the buffer U5), and output an enable signal for enabling the undervoltage protection unit or the overvoltage protection unit after delaying for a set period of time according to the delay control signal.

[0073] The enable signal can be output to the enable control terminal of the first buffer module in the first charging control module, and can also be output to the enable control terminal of the second buffer module in the second charging control module.

[0074] In some embodiments, the delay unit includes: a delay module, an XNOR gate module, an optical coupler module, and an OR gate module. The delay module is such as the delay circuit 5. The XNOR gate module is such as the XNOR gate U13. The optical coupler module is such as the optical coupler U12. The OR gate module is such as the OR gate U9.

[0075] The first input terminal of the XNOR gate module can be used to input the first input signal of the first buffer module, and the second input terminal of the XNOR gate module can be used to input the second input signal of the second buffer module.

[0076] The anode on the diode side of the optical coupling module can input the power supply signal of the control power supply. The cathode on the diode side of the optical coupling module can input the output signal of the XNOR gate module. The collector on the transistor side of the optical coupling module is connected to the control power supply. The emitter on the transistor side of the optical coupling module can output a delay control signal to the delay control end of the delay module.

[0077] The delay module can perform delay processing on the overvoltage protection signal or the undervoltage protection signal under the control of the delay control signal.

[0078] The OR gate module performs OR logic processing on the overvoltage protection signal or the undervoltage protection signal after the delay processing, and outputs an enable signal for enabling and controlling the undervoltage protection unit or the overvoltage protection unit.

[0079] Therefore, by using pure hardware circuits to generate switch control signals, bus circuit charging and bus overvoltage and undervoltage protection functions can be completed without CPU control, thereby controlling bus charging and realizing bus protection, solving the problem that bus charging control and overvoltage and undervoltage protection depend on the CPU, realizing CPU-free bus charging control and protection functions, reducing the use of CPU resources, and shortening the logic / alarm logic processing time when the bus generates overvoltage or undervoltage, and timely shutting down switching devices, thereby improving the reliability and safety of the controller.

[0080] In some embodiments, the delay module includes: a third switch tube module, a timing module and a third buffer module. The third switch tube module is such as a third switch tube Q3 (such as a triode). The timing module is such as a timer U10. The third buffer module is such as a buffer U11.

[0081] The input end of the third switch module can input the delay control signal. The output end of the third switch module is input to the third buffer module after passing through the timing module, and the third buffer module can perform delay processing based on the undervoltage protection signal.

[0082] Specifically, the emitter of the transistor side in the optical coupling module is connected to the input end of the delay module, specifically connected to the input end of the third switch tube module in the delay module, such as the base of the third switch tube Q3 (such as a triode). By adjusting the values ​​of the capacitor Ct and the resistors R19 and R20 on the delay circuit 5, the time for triggering the undervoltage protection can be adjusted.

[0083] During operation, after the control power supply P12V is established, the bus voltage is lower than 270V, and the switch drive signal Driver output by the comparator U6 in the drive signal generating circuit 2 is high. At this time, the buffer U4 input signal Driver_in1 is high, and the buffer U5 input signal Driver_in2 is low. After Driver_in1 and Driver_in2 pass through the XOR gate U13, the output signal Relay_tr is low, that is, the optocoupler U12 is turned on, and the optocoupler U12 output signal DVP_DIR is pulled high, that is, the delay circuit 5 starts to work. After about the set delay time (such as 10s), the 555 timer U10 outputs a low level (if the delay circuit 5 does not work, the output is high, the undervoltage detection circuit 4 does not work, and the output signal DVP of the buffer U11 is low), the buffer U11 enable signal is pulled low, the output signal DVP of the buffer U11 is the same as the input signal DVC, and the undervoltage detection circuit 4 starts to work.

[0084] Therefore, through the pure hardware control circuit, there is no need for the participation of software programs and CPU, and it has overvoltage protection and undervoltage protection functions. Since it is pure hardware control, the protection time is triggered in time, which can more effectively protect the controller, avoid damage to the controller due to overvoltage or loss of control of the controller due to undervoltage, making the controller safer and more reliable.

[0085] After a large number of experiments and verifications, the technical solution of the present invention is adopted, through the driving signal generating circuit and the switch driving circuit, the bus charging control of the bus charging control circuit can be realized without CPU, the bus charging dependence on CPU control can be eliminated, and the bus charging control can be realized without CPU, which can solve the problem that it is difficult to realize bus charging logic control in the bus charging circuit without CPU control; in the bus charging circuit with CPU control, the bus charging control does not require CPU participation, and the bus charging control does not occupy CPU resources.

[0086] According to an embodiment of the present invention, a power supply system corresponding to the bus charging control device is also provided. The power supply system may include: the bus charging control device described above.

[0087] Figure 2 FIG. 1 is a schematic diagram of a structure of an embodiment of a bus charging circuit. Figure 2As shown, the bus capacitor circuit includes: a first switch device, a second switch device, a PTC resistor and a bus capacitor module. Figure 2 In the example shown, the first switch device is turned on after power-on, and the bus capacitor module is charged through the PTC resistor. After the bus voltage reaches the set value, the second switch device is switched to directly power the bus. The bus charging usually uses PTC (positive temperature coefficient) resistors, as well as the first switch device and the second switch device to charge the capacitor in segments, which can avoid large surge currents when power is turned on, thereby damaging the controller device or causing the air switch to trip.

[0088] The first switch device and the second switch device of the bus charging circuit are both realized through CPU control. Figure 3 FIG. 1 is a schematic diagram of a circuit for charging a bus bar by controlling a switch device through a CPU. Figure 3 As shown, the circuit for charging the busbar by controlling the switch device through the CPU includes: a first switch device, a second switch device, a PTC resistor, a busbar capacitor module, a CPU and a voltage sampling circuit. Figure 3 In the example shown, after power-on, the CPU sends a control signal to the first switching device to control the first switching device to turn on, charge the bus through the PTC resistor, sample the bus voltage through the voltage sampling circuit and return it to the CPU. If the bus voltage does not reach the set value after a period of time, the CPU issues a related alarm for bus charging abnormality; if the bus voltage reaches the set value within the CPU set time, the second switching device is turned on to directly power the bus, and the CPU continuously detects the bus voltage. When the bus voltage is relatively high, an overvoltage alarm message is generated after exceeding a certain set value, and an undervoltage alarm is generated when the bus voltage drops to a certain set value.

[0089] In a bus charging circuit without CPU control, in order to realize the logic control of bus charging, an additional CPU control circuit needs to be added, which increases the difficulty of design and development.

[0090] In some embodiments, the scheme of the present invention provides a bus charging control circuit with a protection function, specifically a control circuit applied to the bus power-on stage and capable of supplying power to the bus by controlling different charging circuits. The bus charging can get rid of the dependence of the bus charging on the CPU control and realize the CPU-free bus charging control. The problem that the bus charging logic control is difficult to realize in the bus charging circuit without CPU control can be solved. Moreover, in the bus charging circuit with CPU control, the bus charging control does not require the participation of the CPU, and the bus charging control does not occupy CPU resources. The processing time of the control logic or the alarm logic when the bus is over-voltage or under-voltage can be shortened, and the switching device can be turned off in time to improve the control reliability and safety of the bus charging circuit.

[0091] Specifically, the scheme of the present invention adopts a pure hardware circuit control method. By using a hardware circuit to detect the bus voltage to generate a relay driver signal, an overvoltage detection signal and an undervoltage detection signal, combined with a delay control circuit, a logic control circuit and a buffer, etc., the bus circuit charging and overvoltage and undervoltage protection functions can be completed without the participation of a CPU, thereby realizing CPU-free control of the bus power supply circuit; at the same time, pure hardware control can greatly shorten the logic / alarm logic processing time when the bus generates overvoltage or undervoltage, and promptly shut down the switching device, thereby improving the reliability and safety of the controller.

[0092] In this way, a pure hardware circuit control method is adopted, and a switch control signal is generated by using a pure hardware circuit to realize the bus circuit charging and bus overvoltage and undervoltage protection functions without CPU control, thereby controlling the bus charging and realizing bus protection, solving the problem that the bus charging control and overvoltage and undervoltage protection depend on the CPU, realizing the bus charging control and protection functions without CPU, reducing the use of CPU resources, and shortening the logic / alarm logic processing time when the bus generates overvoltage or undervoltage, and timely shutting down the switching devices, thereby improving the reliability and safety of the controller.

[0093] The solution of the present invention is applicable to any circuit with input AC input voltage. Figures 4 to 10 The example shown takes AC 220V input as an example to illustrate the specific implementation process of the solution of the present invention.

[0094] In the controller, controlling bus charging is an indispensable part of a complete controller. The solution of the present invention provides a pure hardware control circuit to control bus charging, breaking the bus charging control dependence of the CPU through software control in the related solution. This circuit does not require the participation of software programs and CPU, and has overvoltage protection and undervoltage protection functions. Because it is pure hardware control, the protection is triggered in time, which can more effectively protect the controller, avoid damage to the controller due to overvoltage or loss of control of the controller due to undervoltage, and make the controller safer and more reliable. It can be seen that the solution of the present invention can solve the problem that the additional CPU control circuit is required in the bus charging circuit without CPU control, which increases the difficulty of design and development, and the CPU resource consumption is large in the bus charging circuit with CPU control, resulting in great difficulty in controlling the bus charging circuit, thereby reducing the difficulty of controlling the bus charging circuit.

[0095] Figure 4 FIG. 1 is a schematic diagram of a structure of a rectifier circuit in a bus charging control circuit according to an embodiment of the present invention. Figure 4 As shown, the rectifier circuit 1 includes: a rectifier bridge. Figure 4 In the rectifier circuit 1 shown, the rectifier bridge obtains DC signals DC+ and PGND after rectifying the AC input power inputted from the three-phase AC input terminals R, S, and T.

[0096] Fig. 9 FIG. 1 is a schematic diagram of a structure of an embodiment of a switch driving circuit in a bus charging control circuit. Fig. 9 As shown, the switch driving circuit 6 mainly includes: a NOT gate U1, an AND gate U2, an AND gate U3, a buffer U4, a buffer U5, an OR gate U9, an XNOR gate U13, an optical coupler U12, a first relay K1, a second relay K2, a first switch tube Q1, a second switch tube Q2, a PTC resistor R29 and a busbar capacitor module. Fig. 9 In the switch driving circuit 6 shown, DC+ is connected to the input end of the first relay K1 and the second relay K2, and the output end of the first relay K1 is connected to the positive electrode DCP of the bus capacitor module after being connected in series with a PTC resistor R29; the output end of the second relay K2 is directly connected to the positive electrode DCP of the bus capacitor module. Before the control power supply P12V is powered on, the bus charging control circuit does not work, the first relay K1 and the second relay K2 are disconnected, the bus is disconnected from the rectifier circuit 1, and the bus is not charged; when the control power supply P12V is established, the bus charging control circuit starts to work, and the control function of the bus charging circuit begins to be realized.

[0097] Figure 5 FIG. 1 is a schematic diagram of a structure of an embodiment of a driving signal generating circuit in a bus charging control circuit. Figure 5 and Fig. 9 In the example shown, after the control power supply P12V is established, Figure 5 The driving signal generating circuit 2 generates the switch driving signal Driver, and the bus charging control circuit starts to work. The bus voltage charging control is realized through the comparator U6. When the bus voltage is lower than 270V, the switch driving signal Driver is high level. Fig. 9 The AND gate U2 in the circuit outputs a high level to the input end of the buffer U4, and at the same time, after passing through the NOT gate U1 and the AND gate U3, it outputs a low level to the input end of the buffer U5. At this time, the enable signal Protect of the buffer U4 and the buffer U5 is low, the buffer U4 outputs the first drive signal Driver1 as a high level, and the buffer U5 outputs the second drive signal Driver2 as a low level; at this time, through the first switch tube Q1, the first control signal Relay1 of the first relay K1 is pulled low, and the first relay K1 is closed; through the second switch tube Q2, the second control signal Relay2 of the second relay K2 is high, the second relay K2 is disconnected, and the bus supplies power to the bus capacitor module through the first relay K1 and the PTC resistor R29.

[0098] After the bus voltage exceeds 270V, the drive signal generating circuit 2 generates a switch drive signal Driver at a low level, and outputs a low level to the input end of the buffer U4 after passing through the AND gate U2. At the same time, it passes through the NOT gate U1 and then the AND gate U3 to output a high level to the input end of the buffer U5. At this time, the enable signal Protect of the buffer U4 and the buffer U5 is a low level, the buffer U4 outputs the first drive signal Driver1 at a low level, and the buffer U5 outputs the second drive signal Driver2 at a high level; at this time, the first relay K1 control signal Relay1 is a high level, and the first relay K1 is disconnected; the second relay K2 control signal Relay2 is a low level, and the second relay K2 is closed, and the bus supplies power to the bus capacitor module through the second relay K2.

[0099] Figure 8 This is a schematic diagram of the structure of an embodiment of a delay circuit in a bus charging control circuit. Figure 5 , Figure 8 and Fig. 9 In the example shown, after the control power supply P12V is established, the bus voltage is lower than 270V, and the switch drive signal Driver output by the comparator U6 in the drive signal generating circuit 2 is high. At this time, the buffer U4 input signal Driver_in1 is high, and the buffer U5 input signal Driver_in2 is low. After Driver_in1 and Driver_in2 pass through the XOR gate U13, the output signal Relay_tr is low, that is, the optocoupler U12 is turned on, and the optocoupler U12 output signal DVP_DIR is pulled high, that is, the delay circuit 5 starts to work. After about the set delay time (such as 10s), the 555 timer U10 outputs a low level (if the delay circuit 5 does not work, the output is high, the undervoltage detection circuit 4 does not work, and the output signal DVP of the buffer U11 is low), the buffer U11 enable signal is pulled low, the output signal DVP of the buffer U11 is the same as the input signal DVC, and the undervoltage detection circuit 4 starts to work.

[0100] Figure 7 FIG. 1 is a schematic diagram of a structure of an embodiment of an undervoltage detection circuit in a bus charging control circuit. Figure 7 As shown, the undervoltage detection circuit 4 mainly includes: a comparator U8. Figure 6 FIG. 1 is a schematic diagram of the structure of an embodiment of an overvoltage detection circuit in a bus charging control circuit. Figure 6As shown, the overvoltage detection circuit 3 mainly includes: comparator U7. When the undervoltage detection circuit 4 works, if the bus is short-circuited or fails at this time, the bus voltage is lower than 270V, and the comparator U8 in the undervoltage detection circuit 4 outputs a signal DVC of high level, that is, the output signal DVP of the buffer U11 is high level. The comparator U7 in the overvoltage detection circuit 3 outputs a signal OVP of low level, and the logic device or gate U9 outputs a signal Protect of high level, triggering the protection, and the buffer U4 and buffer U5 outputs are closed, and the power supply to the bus is stopped.

[0101] When the undervoltage protection circuit 4 takes effect, if the bus voltage is greater than 270V and less than 390V, the output signal OVP of the overvoltage detection circuit 3 and the output signal DVC of the undervoltage detection circuit 4 are both low level. At this time, the bus works normally and the bus is powered by the second relay K2.

[0102] When the bus voltage exceeds 390V, the comparator U7 output signal OVP in the overvoltage detection circuit 3 is high, and the DVP signal is low at this time. The U9 output signal Protect is high, triggering the protection function, turning off the buffer U4 and buffer U5 outputs. At this time, the first relay K1 control signal Relay1 and the second relay K2 control signal Relay2 are pulled high, the first relay K1 and the second relay K2 are disconnected, and the bus power supply stops.

[0103] In some embodiments, the resistance value of the resistors (such as resistors R1 and R2) on the positive and negative input electrodes of the comparator U6 in the drive signal generating circuit 2 can be adjusted to adjust the voltage when switching the second relay K2; the resistance value of the resistors (such as resistors R6 and R8) on the positive and negative input electrodes of the comparator U7 in the overvoltage detection circuit 3 can be adjusted to adjust the overvoltage protection value; the resistance value of the resistors (such as resistors R11 and R13) on the positive and negative input electrodes of the comparator U8 in the undervoltage detection circuit 4 can be adjusted to adjust the undervoltage protection value; the value of the capacitor Ct and the resistors R19 and R20 on the delay circuit 5 can be adjusted to adjust the time to trigger the undervoltage protection; the above parameters can be adjusted according to actual needs and are not fixed values.

[0104] Fig.10 is a schematic diagram of the signal logic truth table. Fig.10In the signal logic truth table shown, 1 represents a high level and 0 represents a low level; Driver is a drive signal; OVP is an overvoltage detection signal, 1 indicates that the bus voltage exceeds the overvoltage protection setting value; DVC is an undervoltage detection signal, 1 indicates that the bus voltage is lower than the undervoltage protection setting value; Protect is a protection signal, 0 indicates no protection is triggered, and 1 indicates that alarm protection exists; DVP_DIR is a delay circuit trigger signal, 1 indicates that the undervoltage detection circuit works; Driver1 and Driver2 are output signals of the buffer; Relay1 and Relay2 are control signals of the relay, 0 indicates that the relay is closed; the table only lists the situations where the control circuit works after the control power is powered on, and the situations where it is not powered on or cannot exist are not listed; the first row in the table indicates the situation where the second relay K2 is closed to supply power to the bus, and the fourth row indicates the situation where the first relay K1 is closed to supply power to the bus.

[0105] In some embodiments, the relays used in the scheme of the present invention (such as the first relay K1 and the second relay K2, etc.) can be replaced by other controllable switching devices, such as MOS tubes, transistors, triodes, IGBTs, etc., which can also achieve the same purpose; the gate circuit devices used (such as NOT gate U1, AND gate U2, AND gate U3, OR gate U9, XNOR gate U13, etc.) can be adjusted according to the actual control logic; the delay circuit used can be replaced by other delay circuits.

[0106] Since the processing and functions implemented by the power supply system of this embodiment are basically corresponding to the aforementioned Figure 1 The embodiments, principles and examples of the device shown are as follows. Therefore, for matters not fully described in the description of this embodiment, reference can be made to the relevant descriptions in the aforementioned embodiments, and no further elaboration will be given here.

[0107] After a large number of experiments and verifications, the technical solution of this embodiment is adopted, through the driving signal generating circuit and the switch driving circuit, combined with the overvoltage detection circuit and the undervoltage detection circuit, and in conjunction with the delay circuit, a bus charging control circuit with a protection function is set, which can realize the bus charging control of the bus charging control circuit without CPU, and can get rid of the bus charging dependence on the CPU control, and realize the bus charging control without CPU, which can solve the problem that it is difficult to realize the bus charging logic control in the bus charging circuit without CPU control; and, in the bus charging circuit with CPU control, the bus charging control does not require the participation of the CPU, and the bus charging control does not occupy CPU resources, and can also shorten the processing time of the control logic or the alarm logic when the bus generates overvoltage or undervoltage, and can also close the switching device in time, thereby improving the control reliability and safety of the bus charging circuit.

[0108] In summary, it is easy for those skilled in the art to understand that, under the premise of no conflict, the above-mentioned advantageous methods can be freely combined and superimposed.

[0109] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention shall be included in the scope of the claims of the present invention.

Claims

1. A bus charging control device, characterized in that: include: Rectification unit, drive signal generating unit, charging control unit and bus charging unit; The charging control unit includes: a first charging control module and a second charging control module; the bus charging unit includes: a first switch control module, a second switch control module, a charging resistor module and a bus capacitor module; the output end of the rectifier unit is connected to the first connection end of the first switch control module and also connected to the first connection end of the second switch control module; the second connection end of the first switch control module is connected to the positive electrode of the bus capacitor module after passing through the charging resistor module; the second connection end of the second switch control module is connected to the positive electrode of the bus capacitor module; the control end of the first switch control module is connected to the output end of the first charging control module, and the control end of the second switch control module is connected to the output end of the second charging control module; wherein, The rectifying unit is configured to rectify the input alternating current and output direct current to the bus; The drive signal generating unit is configured to generate a drive signal based on the control power supply and the bus voltage of the positive electrode of the bus capacitor module when the control power supply is powered on; The first charging control module is configured to generate a first control signal capable of controlling the first switch control module to be turned on or off based on the driving signal; The second charging control module is configured to generate a second control signal capable of controlling the second switch control module to be turned on or off based on the driving signal.

2. The bus charging control device according to claim 1, characterized in that: in, When the bus voltage of the positive electrode of the bus capacitor module is lower than the first set voltage, the level of the drive signal generated by the drive signal generating unit is the first set level, the first control signal controls the first switch control module to turn on, the second control signal controls the second switch control module to turn off, and the bus supplies power to the bus capacitor module through the first switch control module and the charging resistor module; When the bus voltage at the positive electrode of the bus capacitor module exceeds the first set voltage, the level of the drive signal generated by the drive signal generating unit is a second set level, the first control signal controls the first switch control module to turn off, and the second control signal controls the second switch control module to turn on, and the bus supplies power to the bus capacitor module through the second switch control module.

3. The bus charging control device according to claim 1 or 2, characterized in that: The driving signal generating unit includes: a first comparison module and a first adjustment module; wherein, The non-inverting input terminal of the first comparison module can input the power supply signal of the control power supply; the inverting input terminal of the first comparison module can input the bus voltage of the positive electrode of the bus capacitor module; the output terminal of the first comparison module can output the drive signal generated by the drive signal generating unit; The first adjustment module is provided at the non-inverting input terminal of the first comparison module and the inverting input terminal of the first comparison module, and is configured to adjust a first set voltage.

4. The bus charging control device according to claim 1 or 2, characterized in that: The first charging control module includes: a first AND gate module, a first buffer module and a first switch tube module; wherein, The first input end of the first AND gate module can input the power signal of the control power supply; the second input end of the first AND gate module can input the drive signal; the output end of the first AND gate module is connected to the input end of the first switch tube module after passing through the first buffer module; the output end of the first switch tube module is connected to the control end of the first switch control module; The second charging control module includes: a NOT gate module, a second AND gate module, a second buffer module and a second switch tube module; wherein, The first input end of the second AND gate module can input the power signal of the control power supply; the second input end of the second AND gate module can input the reverse driving signal output after the driving signal is processed by the NOT gate module; the output end of the second AND gate module is connected to the input end of the second switch tube module after passing through the second buffer module; the output end of the second switch tube module is connected to the control end of the second switch control module.

5. The bus charging control device according to claim 4, characterized in that: Also includes: At least one of an undervoltage protection unit and an overvoltage protection unit; wherein, The undervoltage protection unit is configured to perform undervoltage detection on the bus voltage of the positive electrode of the bus capacitor module and output an undervoltage protection signal; Wherein, when the bus voltage of the positive electrode of the bus capacitor module is less than the first set voltage, the level of the undervoltage protection signal output by the undervoltage protection unit is the first set level; when the bus voltage of the positive electrode of the bus capacitor module is greater than or equal to the first set voltage and less than the second set voltage, the level of the undervoltage protection signal output by the undervoltage protection unit is the second set level; The overvoltage protection unit is configured to perform overvoltage detection on the bus voltage of the positive electrode of the bus capacitor module and output an overvoltage protection signal; Among them, when the bus voltage at the positive electrode of the bus capacitor module is greater than or equal to the second set voltage, the level of the overvoltage protection signal output by the overvoltage protection unit is the first set level; when the bus voltage at the positive electrode of the bus capacitor module is greater than or equal to the first set voltage and less than the second set voltage, the level of the undervoltage protection signal output by the overvoltage protection unit is the second set level.

6. The bus charging control device according to claim 5, characterized in that: The overvoltage protection unit comprises: a second comparison module and a second adjustment module; The in-phase input terminal of the second comparison module can input the bus voltage of the positive electrode of the bus capacitor module; the inverting input terminal of the second comparison module can input the power signal of the control power supply; the output terminal of the second comparison module can output the overvoltage protection signal; The second adjustment module is arranged at the non-inverting input terminal of the second comparison module and the inverting input terminal of the second comparison module, and is configured to adjust the first setting voltage and the second setting voltage.

7. The bus charging control device according to claim 5, characterized in that: The undervoltage protection unit includes: a third comparison module and a third adjustment module; wherein, The in-phase input terminal of the third comparison module can input the power supply signal of the control power supply; the inverting input terminal of the third comparison module can input the bus voltage of the positive electrode of the bus capacitor module; the output terminal of the third comparison module can output the undervoltage protection signal; The third adjustment module is arranged at the non-inverting input terminal of the third comparison module and the inverting input terminal of the third comparison module, and is configured to adjust the second set voltage.

8. The bus charging control device according to claim 5, characterized in that: Also includes: Delay unit; The delay unit is configured to generate a delay control signal according to the first input signal of the first buffer module and the second input signal of the second buffer module, and output an enable signal for enabling the undervoltage protection unit or the overvoltage protection unit after delaying for a set time according to the delay control signal; The enable signal can be output to the enable control terminal of the first buffer module in the first charging control module, and can also be output to the enable control terminal of the second buffer module in the second charging control module.

9. The bus charging control device according to claim 8, characterized in that: The delay unit includes: a delay module, an XNOR gate module, an optical coupler module, and an OR gate module; wherein, The first input terminal of the XNOR gate module can input the first input signal of the first buffer module; the second input terminal of the XNOR gate module can input the second input signal of the second buffer module; The cathode on the diode side of the optical coupling module can input the output signal of the XNOR gate module; the emitter on the transistor side of the optical coupling module can output the delay control signal to the delay control terminal of the delay module; The delay module can delay the overvoltage protection signal or the undervoltage protection signal under the control of the delay control signal; The OR gate module performs OR logic processing on the overvoltage protection signal or the undervoltage protection signal after the delay processing, and outputs an enable signal for enabling and controlling the undervoltage protection unit or the overvoltage protection unit.

10. The bus charging control device according to claim 9, characterized in that: The delay module includes: a third switch module, a timing module and a third buffer module; wherein, The input end of the third switch tube module can input the delay control signal; the output end of the third switch tube module is input to the third buffer module after passing through the timing module, and the third buffer module can perform delay processing based on the undervoltage protection signal.

11. A power supply system, characterized in that: include: A bus charging control device as claimed in any one of claims 1 to 10.

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