Comparator providing offset calibration and integrated circuit including the comparator

Abstract

Disclosed are a comparator for providing offset calibration and an integrated circuit including the comparator, wherein the comparator is configured to calibrate the offset according to a control signal, the comparator comprising: an input circuit configured to receive a first input signal and a second input signal, and generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplifier circuit configured to consume a power supply current flowing from a positive voltage node having a positive power supply voltage to a negative voltage node having a negative power supply voltage, and generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve configured to adjust at least a portion of the power supply current based on the control signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2019-0104575 filed in the Korean Intellectual Property Office on August 26, 2019, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to comparators, and more particularly, to comparators providing offset calibration and integrated circuits including the comparators. Background Art

[0004] A comparator that generates an output signal indicating a comparison result by comparing an input signal can be used in various applications. For example, an analog-to-digital converter (ADC) for converting an analog signal into a digital signal can include multiple comparators and generate a digital signal by encoding the output signals of the multiple comparators. In addition, a switching regulator can include a comparator for comparing a feedback signal with a reference signal.

[0005] The performance and efficiency of the application may depend on the characteristics of the comparator, such as power consumption, operating speed, noise properties, area, accuracy, etc., and some characteristics of the comparator may be in a trade-off relationship. Therefore, it may not be easy to implement a comparator with good characteristics without sacrificing other characteristics. Summary of the invention

[0006] According to an embodiment, a comparator configured to calibrate an offset according to a control signal includes: an input circuit, which is configured to receive a first input signal and a second input signal, and generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplifier circuit, which is configured to consume a power supply current flowing from a positive voltage node with a positive power supply voltage to a negative voltage node with a negative power supply voltage, and generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve, which is configured to adjust at least a portion of the power supply current based on the control signal.

[0007] According to an embodiment, a comparator configured to calibrate an offset according to a control signal includes: an input circuit, which is configured to receive a first input signal and a second input signal, and generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplifier circuit, which is configured to generate an output signal by amplifying the difference between the first internal signal and the second internal signal; and a current valve, which includes at least one transistor, the at least one transistor having a control electrode configured to receive the control signal, wherein the at least one transistor is connected in series to the differential amplifier circuit and one of a positive voltage node having a positive power supply voltage and a negative voltage node having a negative power supply voltage.

[0008] According to an embodiment, an integrated circuit includes: a plurality of comparators, wherein each of the plurality of comparators is configured to calibrate an offset according to a control signal; and an offset controller, wherein the offset controller is configured to generate the control signal for adjusting the offset in a calibration mode and to generate a constant control signal in a normal mode, wherein each of the comparators includes: a differential amplifier circuit, wherein the differential amplifier circuit is configured to generate at least one of a plurality of output signals by consuming a power supply current; and a current valve, wherein the current valve is configured to adjust at least a portion of the power supply current based on the control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] These and other aspects will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1A and Figure 1B is a block diagram of an example of a comparator according to an embodiment;

[0011] Figure 2A and Figure 2B is a block diagram of an example of a comparator according to an embodiment;

[0012] Figure 3A and Figure 3B is a circuit diagram of an example of a comparator according to an embodiment;

[0013] Figure 4 is a circuit diagram of an example of a comparator according to an embodiment;

[0014] Figure 5 is a circuit diagram of an example of a comparator according to an embodiment;

[0015] Fig. 6A and Figure 6B is a block diagram of an example of a comparator according to an embodiment;

[0016] Figure 7 is a circuit diagram of an example of a comparator according to an embodiment;

[0017] Figure 8 is a circuit diagram of an example of a comparator according to an embodiment;

[0018] Fig.9A , Fig. 9B and Fig. 9C is a circuit diagram of an example of a comparator according to an embodiment;

[0019] Fig. 10A and Fig. 10B is a circuit diagram of an example of a comparator according to an embodiment;

[0020] Fig.11 is a block diagram of an example of an integrated circuit including a comparator according to an embodiment;

[0021] Fig.12 is a block diagram of an example of a comparator according to an embodiment;

[0022] Fig.13 is a flow chart of an example of a method of calibrating an offset of a comparator according to an embodiment;

[0023] Fig.14A and Fig. 14B is a block diagram of an example of an offset controller according to an embodiment; and

[0024] Fig.15 is a block diagram of an example of a baseband processor according to an embodiment. DETAILED DESCRIPTION

[0025] The embodiments provide a comparator that provides high accuracy without sacrificing other characteristics and an integrated circuit including the comparator. The embodiments provided herein are exemplary, and thus, the inventive concept is not limited thereto.

[0026] Figure 1A and Figure 1B is a block diagram of an example of a comparator according to an embodiment. Figure 1A and Figure 1B Repeated description of .

[0027] Reference Figure 1A, the comparator 10a may receive a first input signal IN1 and a second input signal IN2, and compare the first input signal IN1 and the second input signal IN2 to generate an output signal OUT. For example, the comparator 10a may compare the voltage of the first input signal IN1 and the voltage of the second input signal IN2, and when the voltage of the first input signal IN1 is higher than the voltage of the second input signal IN2, the output signal OUT may have a high voltage (or a high level), and when the voltage of the second input signal IN2 is higher than the voltage of the first input signal IN1, the output signal OUT may have a low voltage (or a low level). Hereinafter, the embodiment will be described mainly with reference to a comparator for comparing the voltage of an input signal, but it will be understood that the embodiment may also be applied to other types of comparators, for example, a comparator for comparing the current of an input signal. The comparator 10a may be connected to a positive voltage node to which a positive power supply voltage VDD is applied and a negative voltage node to which a negative power supply voltage VSS (which may be referred to as a ground potential) is applied, and may receive power from the positive voltage node and the negative voltage node. Hereinafter, a positive voltage node to which a positive power supply voltage VDD is applied may be referred to as a positive power supply voltage VDD, and a negative voltage node to which a negative power supply voltage VSS is applied may be referred to as a negative power supply voltage VSS. Figure 1A As shown, the comparator 10a may include an input circuit 12a, a differential amplifier circuit 14a, and a top current valve CVp and a bottom current valve CVn.

[0028] The input circuit 12a may generate the first internal signal INT1 and the second internal signal INT2 based on the first input signal IN1 and the second input signal IN2. For example, the input circuit 12a may have a high input impedance and a low output impedance, and generate the first internal signal INT1 and the second internal signal INT2 corresponding to the first input signal IN1 and the second input signal IN2, respectively. According to some embodiments, the input circuit 12a may include transistors for generating the first internal signal INT1 and the second internal signal INT2 having an inverted level of the first input signal IN1 and an inverted level of the second input signal IN2, respectively, as described below with reference to Figure 4 , Figure 8 etc. described.

[0029] The differential amplifier circuit 14a may receive the first internal signal INT1 and the second internal signal INT2, and generate an output signal OUT by amplifying the difference (e.g., voltage difference) between the first internal signal INT1 and the second internal signal INT2. The differential amplifier circuit 14a may have any structure that amplifies the difference between the first internal signal INT1 and the second internal signal INT2, according to some embodiments, as described below with reference to Figure 2A and Figure 2BAs described, the differential amplifier circuit 14a may include a cross-coupled amplifier circuit. According to some embodiments, the differential amplifier circuit 14a may generate the output signal OUT as a single-ended signal, and according to some other embodiments, the differential amplifier circuit 14a may generate the output signal OUT as a differential signal. The differential amplifier circuit 14a may perform amplification by consuming a power supply current flowing from the positive power supply voltage VDD to the negative power supply voltage VSS via the differential amplifier circuit 14a. For example, Figure 1A As shown, the differential amplifier circuit 14a can receive a power supply current I from the positive power supply voltage VDD. S , and the power supply current I S ' is discharged to the negative power supply voltage VSS. According to some embodiments, the power supply current I S and I S 'The two may have different sizes according to the first internal signal INT1 and the second internal signal INT2 and / or the output signal OUT, but in this specification it is assumed that the power supply current I S and I S 'Both have substantially the same size (I S =I S ').

[0030] The comparator 10a may include at least one current valve configured to adjust the power supply current I consumed by the differential amplifier circuit 14a. S or I S In this specification, the current valve may refer to an element capable of adjusting the magnitude of the current flowing through it according to a control signal or a circuit including the element. For example, Figure 1A As shown, the top current valve CVp can adjust the power supply current I flowing from the positive power supply voltage VDD to the differential amplifier circuit 14a according to the top control signal CTRp. S The bottom current valve CVn can adjust the power supply current I flowing from the differential amplifier circuit 14a to the negative power supply voltage VSS according to the bottom control signal CTRn. S According to some embodiments, the power supply current I S or I S ' can be changed according to the operation of the differential amplifier circuit 14a, and the top current valve CVp can set the power supply current I according to the top control signal CTRp S The upper limit value of the bottom current valve CVn can set the power supply current I according to the bottom control signal CTRn S According to some embodiments, the comparator 10a may include only one of the top current valve CVp and the bottom current valve CVn, and in this specification, the top current valve CVp and the bottom current valve CVn may be collectively referred to as a current valve.

[0031] Due to the deviation between the first path on which the first input signal IN1 is processed and the second path on which the second input signal IN2 is processed, the comparator 10a may have an offset (which may be an input offset). For example, when the voltage of the first input signal IN1 is lower than the voltage obtained by adding the voltage of the second input signal IN2 to the positive offset voltage, the comparator 10a may generate an output signal OUT indicating that the first input signal IN1 is lower than the second input signal IN2. As the offset increases, the accuracy of the comparator 10a decreases, and therefore, the comparator 10a may provide an operation for compensating for the offset, for example, offset calibration. Figure 1A As shown, the comparator 10a can adjust the power supply current I provided to the differential amplifier circuit 14a. S or the power supply current I discharged from the differential amplifier circuit 14a S ', to provide offset calibration for compensating the offset, therefore, as shown below with reference Figure 7 As described, a wide offset adjustment range and a high offset adjustment resolution can be provided without affecting other characteristics of the comparator 10a.

[0032] Reference Figure 1B , similar to Figure 1A The comparator 10a in the embodiment of the present invention can receive the first input signal IN1 and the second input signal IN2, generate the output signal OUT, and include an input circuit 12b, a differential amplifier circuit 14b, and a top current valve CVp and a bottom current valve CVn. Figure 1A Compared with the top current valve CVp and the bottom current valve CVn in Figure 1B The top current valve CVp in the circuit can adjust the power supply current I provided not only to the differential amplifier circuit 14b but also to the input circuit 12b according to the top control signal CTRp. S at least part of Figure 1B The bottom current valve CVn in the circuit can also adjust the power supply current I discharged not only from the differential amplifier circuit 14b but also from the input circuit 12b according to the bottom control signal CTRn. S According to some embodiments, Figure 1A The input circuit 12a and the differential amplifier circuit 14a in the embodiment can be connected in parallel between the positive power supply voltage VDD and the negative power supply voltage VSS, and Figure 1B The input circuit 12b and the differential amplifier circuit 14b in the embodiment may be connected in series between the positive power supply voltage VDD and the negative power supply voltage VSS. Figure 1B Unlike what is shown in FIG. 1 , the comparator 10 b may include only one of the top current valve CVp and the bottom current valve CVn.

[0033] Figure 2A and Figure 2Bis a block diagram of an example of a comparator according to an embodiment. In detail, Figure 2A The block diagram shows an example of a differential amplifier circuit and a top current valve, Figure 2B The block diagram shows an example of a differential amplifier circuit and a bottom current valve.

[0034] Reference Figure 2A , the comparator 20a may include a differential amplifier circuit 24a and a first top current valve CVp1 and a second top current valve CVp2. The differential amplifier circuit 24a may include a first amplifier circuit A1 and a second amplifier circuit A2 that respectively generate complementary first output signals OUT1 and OUT2 and are cross-coupled, and the first top current valve CVp1 and the second top current valve CVp2 may respectively adjust the first power supply current I provided to the first amplifier circuit A1. S1 and the second power supply current I provided to the second amplifier circuit A2 S2 The first top current valve CVp1 can adjust the first power current I based on the first top control signal CTRp1. S1 The second top current valve CVp2 can adjust the second power current I based on the second top control signal CTRp2. S2 , and a value of at least one of the first top control signal CTRp1 and the second top control signal CTRp2 may be determined according to the sign and the magnitude of the offset.

[0035] Reference Figure 2B , the comparator 20b may include a differential amplifier circuit 24b and a first bottom current valve CVn1 and a second bottom current valve CVn2. The differential amplifier circuit 24b may include a first amplifier circuit A1 and a second amplifier circuit A2 that respectively generate complementary first output signals OUT1 and OUT2 and are cross-coupled, and the first bottom current valve CVn1 and the second bottom current valve CVn2 may respectively adjust the first power supply current I discharged from the first amplifier circuit A1. S1 ' and the second power supply current I discharged from the second amplifier circuit A2 S2 The first bottom current valve CVn1 can adjust the first power current I based on the first bottom control signal CTRn1. S1 ', the second bottom current valve CVn2 can adjust the second power current I based on the second bottom control signal CTRn2 S2 ', and a value of at least one of the first bottom control signal CTRn1 and the second bottom control signal CTRn2 may be determined according to the sign and the size of the offset.

[0036] Figure 3A and Figure 3B is a circuit diagram of an example of a comparator according to an embodiment. In detail, Figure 3A The circuit diagram shows Figure 2A An example of a portion of the first amplifying circuit A1 and the first top current valve CVp1, Figure 3B The circuit diagram shows Figure 2B According to some embodiments, Figure 2A The second amplifier circuit A2 and the second top current valve CVp2 in the circuit may also have the same Figure 3A A structure similar to the structure shown in Figure 2B The second amplifier circuit A2 and the second bottom current valve CVn2 in the circuit may also have the same Figure 3B A structure similar to the structure shown in .

[0037] Reference Figure 3A The comparator 30a may include a first amplifier circuit A1a and a first top current valve CVp1'. The first top current valve CVp1' may adjust a first power current I provided from the positive power voltage VDD to the first amplifier circuit A1a based on a first top control signal CTRp1. S1 .like Figure 3A As shown, the first top current valve CVp1' may include a plurality of first transistors P11 to P18, each of which has a control electrode receiving the first top control signal CTRp1 and is connected in series to the positive power supply voltage VDD and the first amplifier circuit A1a. According to some embodiments, the plurality of first transistors P11 to P18 may be p-channel field effect transistors (PFETs) and have different sizes, for example, different current driving capabilities. According to some embodiments, the first top current valve CVp1' may include Figure 3A The number of first transistors shown in FIG. 1 is different from the number of first transistors shown in FIG.

[0038] According to some embodiments, the first top control signal CTRp1 may be a multi-bit signal as a digital signal, and each of the plurality of first transistors P11 to P18 may be turned on or off by receiving one bit of the first top control signal CTRp1. According to some other embodiments, the first top control signal CTRp1 may have a continuously variable voltage as an analog signal, and each of the plurality of first transistors P11 to P18 may operate in a triode region according to the voltage of the first top control signal CTRp1.

[0039] The first amplifying circuit A1a may include a plurality of second transistors P21 to P25 connected to the first top current valve CVp1′. Figure 3AAs shown, the plurality of second transistors P21 to P25 may respectively have a commonly connected control electrode, a commonly connected first electrode, and a second electrode each connected to at least one of the plurality of first transistors P11 to P18. For example, the plurality of second transistors P21 to P25 may be PFETs, and have a commonly connected gate and a commonly connected drain. In addition, the source of each of the plurality of second transistors P21 to P25 may be connected to at least one of the plurality of first transistors P11 to P18. Therefore, at the node connected to the drain of the plurality of second transistors P21 to P25, regardless of the state of the plurality of first transistors P11 to P18 (e.g., on or off state), the load (e.g., capacitance) of the plurality of second transistors P21 to P25 may function, and therefore, other characteristics of the comparator 30a are not affected.

[0040] According to some embodiments, the plurality of second transistors P21 to P25 may have different sizes, that is, different current driving capabilities. In addition, according to some embodiments, the first amplification circuit A1a may include a first top current valve CVp1′ connected to the first top current valve CVp1′. Figure 3A In the drawings of this specification, the transistors connected to the top current valve in the differential amplifier circuit (for example, Figure 3A The multiple second transistors P21 to P25 in FIG. 4 may be illustrated as a single transistor depicted in bold.

[0041] The plurality of first transistors P11 to P18 in the first top current valve CVp1′ may include a transistor for providing a first power supply current I S1 The first transistor of the coarse adjustment and the first power supply current I S1 The first transistor is fine-tuned. Figure 3A As shown, the four first transistors P11 to P14 respectively connected to the four second transistors P21 to P24 can control the first power current I according to the first top control signal CTRp1. S1 The four first transistors P15 to P18 commonly connected to the second transistor P25 can adjust the first power current I according to the first top control signal CTRp1. S1 The first power supply current I adjusted according to the first top control signal CTRp1 S1 The size of may depend not only on the connection relationship between the plurality of first transistors P11 to P18 and the plurality of second transistors P21 to P25, but also on the size of the plurality of first transistors P11 to P18 and the plurality of second transistors P21 to P25, for example, the current driving capability. Figure 5 An example of such adjustment according to an embodiment is described.

[0042] Reference Figure 3B The comparator 30b may include a first amplifier circuit A1b and a first bottom current valve CVn1'. The first bottom current valve CVn1' may adjust the first power current I discharged from the first amplifier circuit A1b to the negative power supply voltage VSS based on the first bottom control signal CTRn1. S1 '.like Figure 3B As shown, the first bottom current valve CVn1' may include a plurality of first transistors N11 to N18, each of which has a control electrode receiving the first bottom control signal CTRn1 and is connected in series to the negative power supply voltage VSS and the first amplifier circuit A1b. According to some embodiments, the plurality of first transistors N11 to N18 may be n-channel field effect transistors (NFETs) and have different sizes, for example, different current driving capabilities. According to some embodiments, the first bottom current valve CVn1' may include Figure 3B The number of first transistors shown in FIG. 1 is different from the number of first transistors shown in FIG.

[0043] According to some embodiments, the first bottom control signal CTRn1 may be a multi-bit signal as a digital signal, and each of the plurality of first transistors N11 to N18 may be turned on or off by receiving one bit of the first bottom control signal CTRn1. According to some other embodiments, the first bottom control signal CTRn1 may have a continuously variable voltage as an analog signal, and each of the plurality of first transistors N11 to N18 may operate in a triode region according to the voltage of the first bottom control signal CTRn1.

[0044] The first amplifying circuit A1b may include a plurality of second transistors N21 to N25 connected to the first bottom current valve CVn1'. Figure 3B As shown, the plurality of second transistors N21 to N25 may respectively have a commonly connected control electrode, a commonly connected first electrode, and a second electrode each connected to at least one of the plurality of first transistors N11 to N18. For example, the plurality of second transistors N21 to N25 may be NFETs and have a commonly connected gate and a commonly connected drain. In addition, the source of each of the plurality of second transistors N21 to N25 may be connected to at least one of the plurality of first transistors N11 to N18. According to some embodiments, the plurality of second transistors N21 to N25 may have different sizes, that is, different current driving capabilities. In addition, according to some embodiments, the first amplification circuit A1b may include a first bottom current valve CVn1' connected to the first bottom current valve CVn1'. Figure 3B In the drawings of this specification, the transistors connected to the bottom current valve in the differential amplifier circuit (for example, Figure 3BThe multiple second transistors N21 to N25 in FIG. 4 may be illustrated as a single transistor depicted in bold.

[0045] Refer to above Figure 3A Similar to the description, four first transistors N11 to N14 among the plurality of first transistors N11 to N18 can provide a first power supply current I S1 ', the other four first transistors N15 to N18 can provide the first power supply current I S1 ' of fine tuning.

[0046] Hereinafter, example embodiments will be described primarily with reference to comparators including PFETs or NFETs as examples of transistors, but it will be understood that the embodiments may also be applied to comparators including transistors such as: unipolar transistors including FETs, bipolar transistors including bipolar junction transistors (BJTs), and the like.

[0047] Figure 4 is a circuit diagram of an example of a comparator according to an embodiment. In detail, Figure 4 The circuit diagram in FIG. 4 shows an example of a comparator 40, and Figure 1B Similar to the comparator 10b in FIG. 1 , the comparator 40 includes an input circuit 42 and a differential amplifier circuit 44 connected in series between a positive power supply voltage VDD and a negative power supply voltage VSS, and includes a first top current valve CVp1 and a second top current valve CVp2.

[0048] Reference Figure 4 The input circuit 42 may include a first NFET N41 and a second NFET N42 that receive the first input signal IN1 and the second input signal IN2, respectively. The first NFET N41 and the second NFET N42 may respectively generate a first power supply current I S1 and the second power supply current I S2 Flows through and provides the first internal signal INT1 and the second internal signal INT2 to the differential amplifier circuit 44.

[0049] The differential amplifier circuit 44 may include a first amplifier circuit A41 and a second amplifier circuit A42 that generate complementary first output signals OUT1 and second output signals OUT2, respectively, and are cross-coupled. The first amplifier circuit A41 may include a third NFET N43 connected to the input circuit 42 and a first PFET P41 connected to the first top current valve CVp1. In addition, the second amplifier circuit A42 may include a fourth NFET N44 connected to the input circuit 42 and a second PFET P42 connected to the second top current valve CVp2. As described above with reference to Figure 3AAs described, the first PFET P41 may include a plurality of PFETs, and the second PFET P42 may also include a plurality of PFETs.

[0050] The first top current valve CVp1 can adjust the first power current I based on the first top control signal CTRp1. S1 The second top current valve CVp2 can adjust the second power current I based on the second top control signal CTRp2. S2 As mentioned above Figure 3A As described, the first top current valve CVp1 may include a plurality of PFETs, the first power supply current I S1 The second top current valve CVp2 may include a plurality of PFETs, and the second power supply current I S2 The current may flow from the second top current valve CVp2 to the second PFET P42 via a plurality of lines.

[0051] Figure 5 is a circuit diagram of an example of a comparator according to an embodiment. In detail, Figure 5 The circuit diagram shows Figure 4 An example of the first top current valve CVp1 and the first amplifier circuit A41 in FIG. Figure 5 As shown, the comparator 50 may include a first amplification circuit A51 and a first top current valve CVp1". According to some embodiments, Figure 5 The first top current valve CVp1" and the first amplifier circuit A51 in the embodiment may be Figure 4 The example of the second top current valve CVp2 and the second amplifier circuit A42 in the embodiment or otherwise corresponds to Figure 4 The second top current valve CVp2 and the second amplifier circuit A42 in the embodiment of the present invention may be included in the embodiment of the present invention. Figure 4 The comparators 40 are different from the comparators in FIG.

[0052] Reference Figure 5 The first top current valve CVp1" may include a plurality of first transistors T11 to T16. The first top current valve CVp1" may adjust the first power current I supplied from the positive power voltage VDD to the first amplifying circuit A51 based on the 4-bit first top control signal CTRp1[4:1]. S1. The first top current valve CVp1" may include four first transistors T12 to T15, the gates of the four first transistors T12 to T15 receive corresponding bits in the first top control signal CTRp1[4:1], and the four first transistors T12 to T15 may be turned on or off according to the first top control signal CTRp1[4:1]. In the present specification, transistors controlled according to the control signal, like the four first transistors T12 to T15, may be referred to as dynamic control transistors. The first top current valve CVp1" may include not only dynamic control transistors, but also two first transistors T11 and T16 having gates receiving a negative power supply voltage VSS, so the two first transistors T11 and T16 may operate in a triode region according to a drain voltage. In the present specification, transistors having gates to which a constant voltage is applied, like the two first transistors T11 and T16, may be referred to as static control transistors.

[0053] The first amplifying circuit A51 may include a plurality of second transistors T21 to T25, wherein four second transistors T21 to T24 of the plurality of second transistors T21 to T25 may be connected to the four first transistors T11 to T14, respectively, and the remaining second transistors T25 may be connected to the two first transistors T15 and T16. Figure 5 An example is shown in which one dynamic control transistor T15 and one static control transistor T16 are connected to one second transistor T25, but in some embodiments, two or more dynamic control transistors and two or more static control transistors among the plurality of first transistors included in the current valve may be connected to one second transistor among the plurality of second transistors included in the amplification circuit. Figure 3A and Figure 3B As described, the four first transistors T11 to T14 can provide a first power supply current I S1 For coarse adjustment, the two first transistors T15 and T16 can provide the first power supply current I S1 of fine tuning.

[0054] According to some embodiments, the size (e.g., current driving capability) of each of the plurality of first transistors T11 to T16 included in the first top current valve CVp1″ may be greater than or equal to the size (e.g., current driving capability) of the second transistor connected thereto. For example, Figure 5As shown, the size of the first transistor T12 receiving the fourth bit CTRp1[4] of the first top control signal CTRp1[4:1] may be "×16", and the size of the second transistor T22 connected to the first transistor T12 may be "×4". In addition, at least some of the plurality of second transistors T21 to T25 may have different sizes, and the size of each of the plurality of first transistors T11 to T16 may be proportional to the size of the second transistor connected thereto. In this specification, the size of a transistor may be referred to as the current driving capability of the transistor, and may be determined by the channel width and channel length of the transistor. For example, when the channel lengths of the transistors included in the comparator 50 are the same, the size of the transistor may be proportional to its channel width. In addition, when the comparator 50 includes unit transistors having the same channel width and channel length, the size of the transistor may be determined by the number of unit transistors connected in parallel.

[0055] According to some embodiments, when Figure 4 The first top current valve CVp1 and the first amplifier circuit A41 in the comparator 40 are implemented as Figure 5 When the first top current valve CVp1" and the first amplifying circuit A51 are the same, the offset will change according to the first top control signal CTRp1[4:1] as shown in Table 1.

[0056] [Table 1]

[0057] CTRp1[4:1] 0000 0001 0010 ... 1101 1110 1111 Offset(mV) 0 1 2 ... 13 14 15

[0058] and Figure 5 Similar to that shown in , the bottom current valve may include a plurality of first transistors, such as NFETs, and the size (e.g., current driving capability) of each of the plurality of first transistors may have a size (e.g., current driving capability) greater than the size (e.g., current driving capability) of a second transistor connected thereto in the amplifier circuit, and have a circuit driving capability proportional to the current driving capability of the second transistor. In addition, according to some embodiments, the plurality of first transistors included in the bottom current valve may include at least one dynamically controlled transistor and at least one statically controlled transistor (e.g., a transistor having a gate receiving a positive power supply voltage VDD). In addition, the dynamically controlled transistor among the plurality of first transistors included in the bottom current valve may have a gate receiving one bit of the bottom control signal.

[0059] Fig. 6A and Figure 6B is a block diagram of an example of a comparator according to an embodiment. In detail, Fig. 6A and Figure 6B The block diagram shows a dynamic comparator receiving a clock signal CLK. Fig. 6A and Figure 6B No more repeated references in the description Figure 1A and Figure 1B Description of the process.

[0060] Reference Fig. 6A , the comparator 60a may include an input circuit 62a and a differential amplifier circuit 64a. In addition, the comparator 60a may include a top current valve CVp and a bottom current valve CVn. According to some embodiments, the comparator 60a may include only one of the top current valve CVp and the bottom current valve CVn. The comparator 60a may receive a clock signal CLK, and may generate an output signal OUT corresponding to a comparison result of the first input signal IN1 and the second input signal IN2 in response to a rising edge or a falling edge of the clock signal CLK. As described above, the comparator 60a that generates the output signal OUT in response to the clock signal CLK may be referred to as a dynamic comparator, and the dynamic comparator may reduce static power consumption. At least one of the input circuit 62a and the differential amplifier circuit 64a may receive the clock signal CLK, which will be referred to below. Figures 8 to 10B An example of the comparator 60 a will be described.

[0061] Reference Figure 6B , the comparator 60b may include an input circuit 62b and a differential amplifier circuit 64b. In addition, the comparator 60b may include a top current valve CVp and a bottom current valve CVn. According to some embodiments, the comparator 60b may include only one of the top current valve CVp and the bottom current valve CVn. The comparator 60b may receive a clock signal CLK, and generate an output signal OUT corresponding to a comparison result of the first input signal IN1 and the second input signal IN2 in response to a rising edge or a falling edge of the clock signal CLK. At least one of the input circuit 62b and the differential amplifier circuit 64b may receive the clock signal CLK, which will be referred to below. Figure 7 An example of the comparator 60 b is described.

[0062] In the following, as described below with reference to the accompanying drawings, Fig. 6A and Figure 6B The top current valve CVp in can be arranged on the positive power supply voltage VDD side on a path unrelated to the clock signal CLK. In addition, Fig. 6A and Figure 6B The bottom current valve CVn in can be arranged on the negative power supply voltage VSS side on a path unrelated to the clock signal CLK.

[0063] Figure 7 is a circuit diagram of an example of a comparator according to an embodiment. In detail, Figure 7 The circuit diagram in FIG. 1 shows an example of a comparator 70, and Figure 6BSimilar to the comparator 60b in FIG. 1 , the comparator 70 includes an input circuit 72 and a differential amplifier circuit 74 connected in series between a positive power supply voltage VDD and a negative power supply voltage VSS, includes a first top current valve CVp1 and a second top current valve CVp2, and receives a clock signal CLK. Figure 4 The comparator 40 compares Figure 7 The comparator 70 in FIG. 1 is a dynamic comparator and may further include a third PFET P73 to a sixth PFET P76 and a fifth NFET N75 receiving a clock signal CLK. Figure 7 No more repeated references in the description Figure 4 Description of the process.

[0064] The input circuit 72 may include a first NFET N71 and a second NFET N72 that receive a first input signal IN1 and a second input signal IN2, respectively, and further include a fifth NFET N75 that receives a clock signal CLK. The differential amplifier circuit 74 may include a first amplifier circuit A71 and a second amplifier circuit A72. The first amplifier circuit A71 may include a first PFET P71 and a third NFET N73 that receive a second output signal OUT2 and generate a first output signal OUT1, and further include a third PFET P73 and a fifth PFET P75 that receive a clock signal CLK. In addition, the second amplifier circuit A72 may include a second PFET P72 and a fourth NFET N74 that receive a first output signal OUT1 and generate a second output signal OUT2, and further include a fourth PFET P74 and a sixth PFET P76 that receive a clock signal CLK. The first top current valve CVp1 may be connected to the first PFET P71 depicted as bold, and the second top current valve CVp2 may be connected to the second PFET P72 depicted as bold in the illustration.

[0065] When the clock signal CLK has a low level, the fifth NFET N75 can make the first power current I S1 and the second power supply current I S2is zero. In addition, the node at which the fifth PFET P75 generates the first internal signal INT1 and the node at which the sixth PFET P76 generates the second internal signal INT2 can be precharged to the positive power supply voltage VDD, and the node at which the third PFET P73 generates the first output signal OUT1 and the node at which the fourth PFET P74 generates the second output signal OUT2 can also be precharged to the positive power supply voltage VDD. At the rising edge of the clock signal CLK, the fifth NFET N75 can be turned on, and the third PFET P73 to the sixth PFET P76 can be turned off, so that the first output signal OUT1 and the second output signal OUT2 corresponding to the comparison result of the first input signal IN1 and the second input signal IN2 can be generated.

[0066] and Figure 7 Unlike the comparator 70 including the first top current valve CVp1 and the second top current valve CVp2 controlled by the first top control signal CTRp1 and the second top control signal CTRp2, respectively, a structure for adjusting the load capacitance of the comparator to calibrate the offset can be considered. For example, a variable capacitor can be added to the nodes generating the first internal signal INT1 and the second internal signal INT2, respectively, and the offset can be compensated by adjusting the capacitance of the variable capacitor. However, the structure of adjusting the load capacitance will result in large power consumption and will cause the operating speed of the comparator to decrease. Alternatively, a structure including an additional pull-down path to calibrate the offset can be considered. For example, two NFETs connected in parallel to the first NFET N71 and the second NFET N72, respectively, and having a gate for receiving a control signal can also be included. However, the structure including an additional pull-down path will result in the addition of an analog circuit such as a charge pump to continuously adjust the gate voltage of the other NFET, and will have a weak noise characteristic.

[0067] On the other hand, Figure 7 As shown, a comparator including a current valve for offset calibration can provide a wide offset adjustment range and a high offset adjustment resolution without affecting other characteristics of the comparator (eg, operating speed, power consumption, noise properties, area, etc.).

[0068] Figure 8 is a circuit diagram of an example of a comparator according to an embodiment. In detail, Figure 8 The circuit diagram in FIG. 8 shows an example of a comparator 80, with Fig. 6A Similar to the comparator 60a in FIG. 1 , the comparator 80 includes an input circuit 82 and a differential amplifier circuit 84 connected in parallel between a positive power supply voltage VDD and a negative power supply voltage VSS, includes a first top current valve CVp1 and a second top current valve CVp2, and receives a clock signal CLK. According to some embodiments, Figure 8The comparator 80 in may be referred to as a Miyahara comparator including a top current valve.

[0069] The input circuit 82 may include a first NFET N81 and a second NFET N82 that receive a first input signal IN1 and a second input signal IN2, respectively, and include a third NFET N83 that receives a clock signal CLK and a first PFET P81 and a second PFET P82 that receive the clock signal CLK. The differential amplifier circuit 84 may include a first amplifier circuit A81 and a second amplifier circuit A82. The first amplifier circuit A81 may include a fifth PFET P85 and a fourth NFET N84 that receive a second output signal OUT2 and generate a first output signal OUT1, and may include a third PFET P83 that receives a first internal signal INT1 and a sixth NFET N86 and an eighth NFET N88 that receive the first internal signal INT1. In addition, the second amplifier circuit A82 may include a sixth PFET P86 and a fifth NFET N85 that receive a first output signal OUT1 and generate a second output signal OUT2, and may include a fourth PFET P84 that receives a second internal signal INT2 and a seventh NFET N87 and a ninth NFET N89 that receive a second internal signal INT2. The first top current valve CVp1 may be connected to the third PFET P83 depicted in bold, and the second top current valve CVp2 may be connected to the fourth PFET P84 depicted in bold.

[0070] When the clock signal CLK has a low level, the nodes at which the third NFET N83 and the first and second PFETs P81 and P82 generate the first and second internal signals INT1 and INT2 may be precharged to the positive power supply voltage VDD. At the rising edge of the clock signal CLK, the third NFET N83 may be turned on, and the first and second PFETs P81 and P82 may be turned off, and thus, the first and second output signals OUT1 and OUT2 corresponding to the comparison results of the first and second input signals IN1 and IN2 may be generated.

[0071] Fig.9A , Fig. 9B and Fig. 9C is a circuit diagram of an example of a comparator according to an embodiment. In detail, Fig.9A , Fig. 9B and Fig. 9C The circuit diagrams in FIG. 1 and FIG. 2 respectively show examples of Miyahara comparators including differently arranged bottom current valves. Fig.9A , Fig. 9B and Fig. 9C The comparators 90a, 90b and 90c in the embodiment may include Figure 8The input circuit 82 in FIG. 1 has the same structure as the input circuit. For the convenience of drawing, Fig.9A , Fig. 9B and Fig. 9C The input circuit is not shown in FIG. Figure 8 describe Fig.9A , Fig. 9B and Fig. 9C , and in reference Fig.9A , Fig. 9B and Fig. 9C No more repeated references in the description Figure 8 Description of the process.

[0072] As mentioned above Figure 8 As described, the input circuit 82 can receive the clock signal CLK, and Fig.9A , Fig. 9B and Fig. 9C The differential amplifier circuits 94a, 94b, and 94c in the differential amplifier circuits 94a, 94b, and 94c may not receive the clock signal CLK. Therefore, a bottom current valve may be added to each of the mutually corresponding nodes among the nodes connected to the negative power supply voltage VSS of the first amplifier circuit and the second amplifier circuit in the differential amplifier circuits 94a, 94b, and 94c.

[0073] Reference Fig.9A , the comparator 90a may include a differential amplifier circuit 94a and a first bottom current valve CVn1 and a second bottom current valve CVn2, and the differential amplifier circuit 94a may include a first amplifier circuit A91a and a second amplifier circuit A92a. The first amplifier circuit A91a may include a fifth PFET P95a and a fourth NFET N94a that receive the second output signal OUT2 and generate the first output signal OUT1, and may include a third PFET P93a that receives the first internal signal INT1, and a sixth NFET N96a and an eighth NFET N98a that receive the first internal signal INT1. In addition, the second amplifier circuit A92a may include a sixth PFET P96a and a fifth NFET N95a that receive the first output signal OUT1 and generate the second output signal OUT2, and may include a fourth PFET P94a that receives the second internal signal INT2, and a seventh NFET N97a and a ninth NFET N99a that receive the second internal signal INT2. The first bottom current valve CVn1 may be connected to a fourth NFET N94a depicted in bold, and the second bottom current valve CVn2 may be connected to a fifth NFET N95a depicted in bold.

[0074] Reference Fig. 9B, the comparator 90b may include a differential amplifier circuit 94b and a first bottom current valve CVn1 and a second bottom current valve CVn2, and the differential amplifier circuit 94b may include a first amplifier circuit A91b and a second amplifier circuit A92b. The first amplifier circuit A91b may include a fifth PFET P95b and a fourth NFET N94b that receive the second output signal OUT2 and generate the first output signal OUT1, and may include a third PFET P93b that receives the first internal signal INT1, and a sixth NFET N96b and an eighth NFET N98b that receive the first internal signal INT1. In addition, the second amplifier circuit A92b may include a sixth PFET P96b and a fifth NFET N95b that receive the first output signal OUT1 and generate the second output signal OUT2, and may include a fourth PFET P94b that receives the second internal signal INT2, and a seventh NFET N97b and a ninth NFET N99b ​​that receive the second internal signal INT2. The first bottom current valve CVn1 may be connected to the sixth NFET N96b depicted in bold, and the second bottom current valve CVn2 may be connected to the seventh NFET N97b depicted in bold.

[0075] Reference Fig. 9C , the comparator 90c may include a differential amplifier circuit 94c and a first bottom current valve CVn1 and a second bottom current valve CVn2, and the differential amplifier circuit 94c may include a first amplifier circuit A91c and a second amplifier circuit A92c. The first amplifier circuit A91c may include a fifth PFET P95c and a fourth NFET N94c that receive the second output signal OUT2 and generate the first output signal OUT1, and may include a third PFET P93c that receives the first internal signal INT1, and a sixth NFET N96c and an eighth NFET N98c that receive the first internal signal INT1. In addition, the second amplifier circuit A92c may include a sixth PFET P96c and a fifth NFET N95c that receive the first output signal OUT1 and generate the second output signal OUT2, and may include a fourth PFET P94c that receives the second internal signal INT2, and a seventh NFET N97c and a ninth NFET N99c that receive the second internal signal INT2. The first bottom current valve CVn1 may be connected to the eighth NFET N98c depicted in bold, and the second bottom current valve CVn2 may be connected to the ninth NFET N99c depicted in bold.

[0076] Fig. 10A and Fig. 10B is a circuit diagram of an example of a comparator according to an embodiment. In detail, Fig. 10A and Fig. 10BThe circuit diagram in FIG. 1 shows comparators 100a and 100b, with Fig. 6A Similar to the comparator 60a in FIG. 1 , the comparators 100a and 100b include an input circuit and a differential amplifier circuit connected in parallel between a positive power supply voltage VDD and a negative power supply voltage VSS and receiving a clock signal CLK. Fig. 10A The comparator 100a and Fig. 10B The comparator 100b in each embodiment may include Figure 8 The input circuit 82 in FIG. 1 has the same structure as the input circuit. For the convenience of drawing, Fig. 10A and Fig. 10B The input circuit is not shown. According to some embodiments, Fig. 10A The comparator 100a and Fig. 10B The comparator 100b in FIG. 1 may be referred to as a Nauta comparator including a current valve.

[0077] Reference Fig. 10A , the comparator 100a may include a differential amplifier circuit 104a and a first top current valve CVp1 and a second top current valve CVp2. The differential amplifier circuit 104a may include a first amplifier circuit A101a and a second amplifier circuit A102a, and in addition to the first internal signal INT1 and the second internal signal INT2, the first amplifier circuit A101a and the second amplifier circuit A102a may also receive an inverted clock signal CLKb. The first amplifier circuit A101a may include a first PFET P101a and a first NFET N101a receiving a second output signal OUT2, a third PFET P103a receiving the first internal signal INT1, and a third NFET N103a receiving the inverted clock signal CLKb. In addition, the second amplifier circuit A102a may include a second PFET P102a and a second NFET N102a receiving the first output signal OUT1, a fourth PFET P104a receiving the second internal signal INT2, and a fourth NFET N104a receiving the inverted clock signal CLKb. The first top current valve CVp1 may be connected to the first PFET P101a depicted in bold, and the second top current valve CVp2 may be connected to the second PFET P102a depicted in bold.

[0078] When the clock signal CLK has a low level, for example, when the inverted clock signal CLKb has a high level, as described above with reference to Figure 8As described, the first internal signal INT1 and the second internal signal INT2 may be the same as the positive power supply voltage VDD, and the node where the third NFET N103a generates the first output signal OUT1 and the node where the fourth NFET N104a generates the second output signal OUT2 may be precharged to the negative power supply voltage VSS. At the rising edge of the clock signal CLK, for example, at the falling edge of the inverted clock signal CLKb, the third NFET N103a and the fourth NFET N104a may be turned off, and thus, the first output signal OUT1 and the second output signal OUT2 corresponding to the comparison result of the first input signal IN1 and the second input signal IN2 may be generated.

[0079] Reference Fig. 10B , the comparator 100b may include a differential amplifier circuit 104b and a first bottom current valve CVn1 and a second bottom current valve CVn2. The differential amplifier circuit 104b may include a first amplifier circuit A101b and a second amplifier circuit A102b, and in addition to the first internal signal INT1 and the second internal signal INT2, the first amplifier circuit A101b and the second amplifier circuit A102b may also receive an inverted clock signal CLKb. The first amplifier circuit A101b may include a first PFET P101b and a first NFET N101b that receive the second output signal OUT2, a third PFET P103b that receives the first internal signal INT1, and a third NFET N103b that receives the inverted clock signal CLKb. In addition, the second amplifier circuit A102b may include a second PFET P102b and a second NFET N102b that receive the first output signal OUT1, a fourth PFET P104b that receives the second internal signal INT2, and a fourth NFET N104b that receives the inverted clock signal CLKb. The first bottom current valve CVn1 may be connected to the first NFET N101b depicted in bold, and the second bottom current valve CVn2 may be connected to the second NFET N102b depicted in bold.

[0080] Fig.11 is a block diagram of an example of an integrated circuit including a comparator according to an embodiment. In detail, Fig.11 The block diagram in shows an example of an analog-to-digital converter (ADC) 110 as an example of an integrated circuit.

[0081] Reference Fig.11 ADC 110 may receive an analog input A_IN and generate a digital output signal D_OUT by converting the analog input A_IN. ADC 110 may have any structure, including, as non-limiting examples, a flash ADC structure, a loop-unrolled successive approximation register (SAR) ADC structure, a time-interleaved ADC structure, etc. Fig.11 As shown, the ADC 110 may include a first comparator CMP1 to an m-th comparator CMPm and an offset controller 112, where m is an integer greater than 1. The first comparator CMP1 to the m-th comparator CMPm may compare the analog input A_IN, the reference signal, the analog signal generated based on the analog input A_IN and / or the reference signal, etc. with each other according to the structure of the ADC 110. The first comparator CMP1 to the m-th comparator CMPm may each include a current valve for offset calibration as described above with reference to the accompanying drawings, and thus, the performance and efficiency of the ADC 110 may be improved.

[0082] The first comparator CMP1 to the mth comparator CMPm may include current valves, respectively, and receive first control signals CTR1 to mth control signals CTRm for controlling the current valves, respectively. The ADC 110 may be set to a calibration mode or a normal mode, wherein in the calibration mode, the offsets of the first comparator CMP1 to the mth comparator CMPm may be calibrated, and in the normal mode, a digital output signal D_OUT corresponding to the analog input A_IN may be generated.

[0083] The offset controller 112 may compensate for the offsets of the first comparator CMP1 to the mth comparator CMPm through the first control signal CTR1 to the mth control signal CTRm in the calibration mode. In addition, the offset controller 112 may maintain the first control signal CTR1 to the mth control signal CTRm corresponding to the compensated offset in the normal mode. The offset controller 112 may include at least one of logic hardware and a processing unit, the logic hardware being designed by logic synthesis, the processing unit including a processor and software, the software including a series of instructions to be executed by the processor. According to some embodiments, the offset controller 112 may receive a signal indicating an operating mode (e.g., a calibration mode or a normal mode) from outside the ADC 110, for example, Fig.14A The following will refer to Fig.13 An example of the operation of the offset controller 112 is described.

[0084] Fig.12 is a block diagram of an example of a comparator according to an embodiment. Figure 1A Similar to comparator 10a in, Fig.12 The comparator 120 in the embodiment may include an input circuit 122, a differential amplifier circuit 124, a top current valve CVp and a bottom current valve CVn, and may also include a switch SW connected between a node (e.g., a first input terminal T1) to which a first input signal IN1 is applied and a node (e.g., a second input terminal T2) to which a second input signal IN2 is applied. According to some embodiments, the comparator 120 may be configured as Fig. 6AAccording to some embodiments, the comparator 120 may include only one of the top current valve CVp and the bottom current valve CVn. In addition, although not shown, it will be understood that other embodiments (e.g., Figure 1B The comparator 10b in FIG. 10a is added with a switch connected between a node to which the first input signal IN1 is applied and a node to which the second input signal IN2 is applied.

[0085] The switch SW can receive the switch control signal CTRs and electrically connect or disconnect the first input terminal T1 and the second input terminal T2 according to the switch control signal CTRs. Fig.13 As described, the switch SW can be turned on in the calibration mode to electrically connect the first input terminal T1 and the second input terminal T2, and turned off in the normal mode to electrically disconnect the first input terminal T1 and the second input terminal T2. When the switch SW is turned on, the comparator 120 can receive the first input signal IN1 and the second input signal IN2 having substantially the same potential, and in an embodiment, the output signal OUT can have an intermediate voltage between a high level and a low level, or oscillate between a high level and a low level. In an embodiment, when the comparator 120 has an offset, although the first input signal IN1 and the second input signal IN2 have substantially the same potential, the output signal OUT can have a high level or a low level. Therefore, the offset calibration can be performed by turning on the switch SW in the calibration mode.

[0086] Fig.13 is a flow chart of an example of a method for calibrating an offset of a comparator according to an embodiment. In detail, Fig.13 The flowchart in Figure 1 shows a method for calibrating the offset of a comparator such as Fig.12 The comparator 120 in FIG. 1 includes a switch SW connected between the first input terminal T1 and the second input terminal T2. According to some embodiments, Fig.13 The method can be Fig.12 The offset controller 112 in Fig.13 In the description, it is assumed that the offset controller 112 controls Fig.12 The comparator 120 in the reference Fig.11 and Fig.12 .

[0087] Reference Fig.13In operation S20, the operation mode may be determined. According to some embodiments, the offset controller 112 may receive a signal indicating the operation mode from outside the ADC 110. According to some embodiments, when power is supplied to the ADC 110, the offset controller 112 may determine the calibration mode, and when the calibration mode is completed, the offset controller 112 may determine the normal mode. Fig.13 As shown, operation S40 may be performed in the calibration mode, and operation S60 may be performed in the normal mode.

[0088] like Fig.13 As shown, operation S40 performed in the calibration mode may include operations S42, S44, S46, and S48. In operation S42, the switch SW may be turned on. For example, the offset controller 112 may provide the comparator 120 with a switch control signal CTRs for turning on the switch SW, and thus, the first input terminal T1 and the second input terminal T2 may be electrically connected.

[0089] In operation S44, the offset may be adjusted. For example, the offset controller 112 may adjust the offset of the comparator 120 by changing at least one of the top control signal CTRp and the bottom control signal CTRn. As described above with reference to the accompanying drawings, the comparator 120 may provide a wide offset adjustment range and a high offset adjustment resolution without affecting other characteristics of the comparator 120.

[0090] In operation S46, it is determined whether the offset is compensated. For example, the output signal OUT of the comparator 120 may be fed back to the offset controller 112, and when the output signal OUT oscillates between a high level and a low level at a duty cycle of approximately 50%, or when the output signal OUT has an intermediate level between a high level and a low level, the offset controller 112 may determine that the offset compensation is completed. Fig.13 As shown, when the offset compensation is completed, operation S48 may be subsequently performed, otherwise, operations S44 and S46 may be repeatedly performed.

[0091] In operation S48, the switch may be turned off. For example, since the offset has been compensated in operation S46, the offset controller 112 may output a switch control signal CTRs for turning off the switch SW, so that the comparator 120 compares the first input signal IN1 and the second input signal IN2 in the normal mode, and thus, the first input terminal T1 and the second input terminal T2 may be electrically disconnected.

[0092] In the normal mode, operation S60 may be performed, in which a constant control signal corresponding to the compensated offset may be output. For example, the offset controller 112 may generate a top control signal CTRp and a bottom control signal CTRn corresponding to the offset compensated in the calibration mode. Therefore, the comparator 120 may generate an output signal OUT by comparing the first input signal IN1 and the second input signal IN2 in a state where the offset has been compensated.

[0093] Fig.14A and Fig. 14B is a block diagram of an example of an offset controller according to an embodiment. Fig.12 Described, Fig.14A The offset controller 140a and Fig. 14B The offset controller 140b in the embodiment can generate a control signal CTR for adjusting the offset of the comparator. Fig.14A and Fig. 14B Repeated description of .

[0094] Reference Fig.14A , the offset controller 140a may generate the control signal CTR as a multi-bit signal and may include a control logic 142a and a memory 144a. According to some embodiments, the control logic 142a may be as follows Fig.14A Receive the mode signal MD as shown by the dotted line in , and determine the calibration mode or the normal mode based on the mode signal MD. According to some embodiments, the control logic 142a can enter the calibration mode when power is supplied to the bias controller 140a, and enter the normal mode by releasing the calibration mode when the offset compensation is completed in the calibration mode. The current valve may include a first transistor that receives the bit of the control signal CTR, and the power supply current provided to the comparator may be adjusted by the first transistor that is turned on or off according to the bit of the control signal CTR. According to some embodiments, the control logic 142a may also output a control logic 142a for controlling the current valve. Fig.12 The switch control signal CTRs of the switch SW in.

[0095] The control logic 142a may store the compensated offset or the value of the control signal CTR corresponding to the compensated offset in the memory 144a in the calibration mode, and may output a constant control signal CTR according to the value stored in the memory 144a in the normal mode. The memory 144a may include a volatile memory such as a latch, a flip-flop, a static random access memory (SRAM), or a dynamic random access memory (DRAM) as a non-limiting example, and a non-volatile memory such as a flash memory or an electrically erasable programmable read-only memory (EEPROM) as a non-limiting example.

[0096] Reference Fig. 14B, the offset controller 140b may generate at least one control signal CTR as an analog signal, and include a control logic 142b, a memory 144b, and a variable voltage source 146. The control logic 142b may provide a bias control signal BIAS to the variable voltage source 146 in a calibration mode, and the variable voltage source 146 may output at least one control signal CTR having a magnitude (e.g., voltage) corresponding to the bias control signal BIAS. The current valve may include a first transistor that receives at least one control signal CTR, and may adjust the power supply current provided to the comparator by adjusting the first transistor through which the current flows according to the magnitude of the at least one control signal CTR. According to some embodiments, the bias control signal BIAS may be a digital signal, and the variable voltage source 146 may include a digital-to-analog converter (DAC).

[0097] Fig.15 is a block diagram of an example of a baseband processor according to an embodiment. The baseband processor may be included in a communication device for wireless communication and may be referred to as a modem, a communication processor, etc. Fig.15 As shown, the baseband processor 150 may include a plurality of ADCs 152 , a plurality of DACs 154 , and a data processor 156 .

[0098] The baseband processor 150 may receive a baseband input signal BB_IN as an analog signal and generate a baseband output signal BB_OUT as an analog signal. For example, the baseband processor 150 may receive the baseband input signal BB_IN from a radio frequency integrated circuit (RFIC) or a transceiver and may provide the baseband output signal BB_OUT to the RFIC or the transceiver. Fig.15 As shown, the baseband input signal BB_IN can be received via multiple paths, so the baseband processor 150 can include multiple ADCs 152 to process the baseband input signal BB_IN. Similarly, the baseband output signal BB_OUT can be output via multiple paths, so the baseband processor 150 can include multiple DACs 154 to generate the baseband output signal BB_OUT. Multiple ADCs 152 can each include multiple comparators, and multiple comparators can each include a current valve for offset calibration according to an embodiment. Therefore, the performance and efficiency of multiple ADCs 152 can be improved, and therefore, the practicality of the baseband processor 150 can be improved.

[0099] The data processor 156 may extract information received through wireless communication by processing digital signals provided from the plurality of ADCs 152. For example, the data processor 156 may perform demodulation, decoding, etc. In addition, the data processor 156 may provide digital signals including information to be transmitted through wireless communication to the plurality of DACs 154. For example, the data processor 156 may generate digital signals provided to the plurality of DACs 154 by performing modulation, encoding, etc.

[0100] While embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A comparator, the comparator being configured to calibrate an offset according to a control signal, the comparator comprising: an input circuit configured to receive a first input signal and a second input signal and generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplifier circuit configured to consume a power supply current flowing from a positive voltage node having a positive power supply voltage to a negative voltage node having a negative power supply voltage and to generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve configured to adjust at least a portion of the supply current based on the control signal, The current valve includes a plurality of first transistors, which are connected in series between the differential amplifier circuit and one of the positive voltage node and the negative voltage node. The differential amplifier circuit includes a plurality of second transistors having commonly connected control electrodes. Each of the plurality of second transistors is connected to at least one of the plurality of first transistors.

2. The comparator according to claim 1, in, The plurality of first transistors includes at least one dynamically controlled transistor having a control electrode configured to receive the control signal.

3. The comparator according to claim 2, in, A first current driving capability of each of the plurality of first transistors is greater than or equal to a second current driving capability of a second transistor connected to the first transistor.

4. The comparator according to claim 2, in, The plurality of second transistors include at least two second transistors having different current driving capabilities, and The first current driving capability of each of the plurality of first transistors is proportional to the second current driving capability of a second transistor connected to the first transistor.

5. The comparator according to claim 2, wherein: The plurality of first transistors and the plurality of second transistors each include at least one unit transistor connected in parallel.

6. The comparator according to claim 2, wherein: The plurality of first transistors includes at least one static control transistor having a control electrode configured to receive the positive power supply voltage or the negative power supply voltage.

7. The comparator according to claim 6, in, The plurality of first transistors include the at least one dynamically controlled transistor and the at least one statically controlled transistor, and The at least one dynamic control transistor and the at least one static control transistor are connected to one second transistor among the plurality of second transistors.

8. The comparator according to claim 2, wherein: The at least one dynamic control transistor is configured to be turned on or off according to the control signal.

9. The comparator according to claim 1, in, The differential amplifier circuit includes a first amplifier circuit and a second amplifier circuit which are cross-coupled. Wherein, the first amplification circuit is configured to generate a first output signal, The second amplification circuit is configured to generate a second output signal complementary to the first output signal, and Wherein, the current valve comprises: a first current valve configured to adjust a first power supply current flowing through the first amplifying circuit; and A second current valve is configured to adjust a second power supply current flowing through the second amplifier circuit.

10. The comparator according to claim 1, wherein: The current valve, the differential amplifier circuit, and the input circuit are connected in series between the positive voltage node and the negative voltage node.

11. The comparator according to claim 1, in, The input circuit is connected to the positive voltage node and the negative voltage node, and The current valve is connected in series to at least a portion of the differential amplifier circuit between the positive voltage node and the negative voltage node.

12. The comparator according to claim 1, in, At least one of the input circuit and the differential amplifier circuit is configured to receive a clock signal, wherein the output signal corresponds to a result of a comparison between the first input signal and the second input signal, and The comparison is performed based on a rising edge or a falling edge of the clock signal.

13. A comparator, the comparator being configured to calibrate an offset according to a control signal, the comparator comprising: an input circuit configured to receive a first input signal and a second input signal and generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplifier circuit configured to generate an output signal by amplifying a difference between the first internal signal and the second internal signal; as well as a current valve comprising at least one first transistor having a control electrode configured to receive the control signal, wherein the at least one first transistor is connected in series to the differential amplifier circuit and one of a positive voltage node having a positive power supply voltage and a negative voltage node having a negative power supply voltage, The differential amplifier circuit includes a plurality of second transistors having commonly connected control electrodes. Each of the plurality of second transistors is connected to at least one of the at least one first transistor.

14. The comparator according to claim 13, in, The current valve includes a plurality of first p-channel field effect transistors having sources connected to the positive voltage node, The differential amplifier circuit includes a plurality of second p-channel field effect transistors having commonly connected gates and commonly connected drains, wherein a source of each of the plurality of second p-channel field effect transistors is connected to a drain of at least one first p-channel field effect transistor of the plurality of first p-channel field effect transistors, and The gate of at least one first p-channel field effect transistor among the plurality of first p-channel field effect transistors is configured to receive the control signal.

15. The comparator according to claim 13, in, The current valve includes a plurality of first n-channel field effect transistors having sources connected to the negative voltage node, The differential amplifier circuit includes a plurality of second n-channel field effect transistors having commonly connected gates and commonly connected drains. wherein a source of each of the plurality of second n-channel field effect transistors is connected to a drain of at least one first n-channel field effect transistor of the plurality of first n-channel field effect transistors, and The gate of at least one first n-channel field effect transistor among the plurality of first n-channel field effect transistors is configured to receive the control signal.

16. The comparator according to claim 13, in, The differential amplifier circuit includes a first amplifier circuit and a second amplifier circuit which are cross-coupled. Wherein, the first amplification circuit is configured to generate a first output signal, The second amplification circuit is configured to generate a second output signal complementary to the first output signal, and Wherein, the current valve comprises: at least one first control transistor having a first control electrode configured to receive a first control signal and connected in series to the first amplification circuit and the positive voltage node or the negative voltage node; and At least one second control transistor has a second control electrode configured to receive a second control signal and is connected in series to the second amplification circuit and the positive voltage node or the negative voltage node.

17. An integrated circuit, comprising: a plurality of comparators, wherein each comparator of the plurality of comparators is configured to calibrate an offset according to a control signal; and an offset controller configured to generate the control signal for adjusting the offset in a calibration mode and to generate a constant control signal in a normal mode, Wherein, each of the comparators comprises: a differential amplifier circuit configured to generate at least one of a plurality of output signals by consuming a power supply current; and a current valve configured to adjust at least a portion of the supply current based on the control signal, The current valve includes a plurality of first transistors, the plurality of first transistors are connected in series to the differential amplifier circuit and one of a positive voltage node and a negative voltage node, wherein the power supply current flows from the positive voltage node to the negative voltage node, The differential amplifier circuit includes a plurality of second transistors having commonly connected control electrodes. Each of the plurality of second transistors is connected to at least one of the plurality of first transistors.

18. The integrated circuit according to claim 17, in, Each of the comparators includes a switch connected between a first input terminal and a second input terminal, and The offset controller is further configured to control the switch so that the first input terminal and the second input terminal are electrically connected when entering the calibration mode, and so that the first input terminal and the second input terminal are electrically disconnected when releasing the calibration mode.

19. The integrated circuit according to claim 17, in, The offset controller is further configured to generate the control signal as a multi-bit signal, and The current valve includes a plurality of transistors having a plurality of control electrodes configured to receive bits of the control signal.

20. The integrated circuit according to claim 17, in, The offset controller is further configured to generate the control signal as a bias voltage, and The current valve includes at least one transistor having a control electrode configured to receive the bias voltage.

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