Display device

Abstract

The present application relates to a display device. The display device includes a display panel and an input sensing panel. Among them, the display panel includes a plurality of pixels and display pads connected to the pixels. The input sensing panel is on the display panel, and the input sensing panel includes an input sensing layer, an electrostatic sensing circuit, and a floating pattern circuit. Among them, the input sensing layer includes sensing electrodes for sensing inputs, sensing lines connected to the sensing electrodes, and sensing pads connected to the sensing lines. The electrostatic sensing circuit is spaced apart from the sensing pads. The floating pattern circuit is electrically insulated from the input sensing layer and includes bridging patterns. The bridging patterns are connected to the electrostatic sensing circuit.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority and benefit of Korean Patent Application No. 10 - 2019 - 0109658, filed on September 4, 2019, the entire content of which is incorporated herein by reference. Technical field

[0003] Aspects of exemplary embodiments of the present disclosure relate to an input sensing panel having improved durability and a display device including the input sensing panel. Background art

[0004] A display device may include a display panel for displaying an image and an input sensing panel for sensing an external input. The input sensing panel may include sensing electrodes, sensing lines, and sensing pads. The sensing lines may transmit and / or receive signals.

[0005] The above information disclosed in this background art section is for enhancing understanding of the background art of the present disclosure, and thus, it may include information that does not constitute the prior art. Summary of the invention

[0006] One or more exemplary embodiments of the present disclosure relate to an input sensing panel having improved durability and a display device including the input sensing panel.

[0007] According to one or more exemplary embodiments of the present disclosure, a display device includes a display panel and an input sensing panel. The display panel includes a plurality of pixels and display pads connected to the pixels. The input sensing panel is on the display panel, and the input sensing panel includes an input sensing layer, an electrostatic sensing circuit, and a floating pattern circuit. The input sensing layer includes sensing electrodes configured to sense an input, sensing lines connected to the sensing electrodes, and sensing pads connected to the sensing lines. The electrostatic sensing circuit is spaced apart from the sensing pads. The floating pattern circuit is electrically insulated from the input sensing layer and includes bridging patterns. The bridging patterns are connected to the electrostatic sensing circuit.

[0008] In an embodiment, the floating pattern circuit may include a resistance test pattern and an alignment pattern connected to the resistance test pattern.

[0009] In an embodiment, the electrostatic sensing circuit may include: a first electrostatic sensing pad and a second electrostatic sensing pad spaced apart from the first electrostatic sensing pad, and a sensing pad between the first electrostatic sensing pad and the second electrostatic sensing pad; a first electrostatic sensing line surrounding a part of the sensing electrode and including one end connected to the first electrostatic sensing pad; and a second electrostatic sensing line surrounding another part of the sensing electrode and including one end connected to the second electrostatic sensing pad. The other ends of the first electrostatic sensing line and the second electrostatic sensing line may be spaced apart from each other.

[0010] In an embodiment, a bridging pattern may connect one of the first electrostatic sensing pad and the second electrostatic sensing pad to a resistance test pattern.

[0011] In an embodiment, a bridging pattern may connect one of the first electrostatic sensing line and the second electrostatic sensing line to an alignment pattern.

[0012] In an embodiment, the input sensing panel may further include a dummy pattern between the electrostatic sensing circuit and the floating pattern circuit.

[0013] In an embodiment, the dummy pattern may have one of a polygonal shape, an oval shape, and a circular shape.

[0014] In an embodiment, the input sensing panel may include a first conductive layer on the display panel, a first insulating layer covering the first conductive layer, and a second conductive layer on the first insulating layer.

[0015] In an embodiment, the first conductive layer may include a metal, the second conductive layer may include a transparent conductive material, and the bridging pattern may be defined as a part of the first conductive layer.

[0016] In an embodiment, the second conductive layer may include a metal, the first conductive layer may include a transparent conductive material, and the bridging pattern may be defined as a part of the second conductive layer.

[0017] In an embodiment, the display device may further include: an active area defined in a first direction and a second direction intersecting the first direction, the active area configured to provide light generated from the display panel; and a peripheral area surrounding the active area. Display pads may be arranged on one side of the peripheral area along the first direction, and sensing pads and a floating pattern circuit may be arranged on the other side of the peripheral area along the first direction to be spaced apart from the display pads in the second direction, and the active area is located between the display pads and the sensing pads and the floating pattern circuit.

[0018] In an embodiment, the display device may further include a coupling member, and the display panel and the input sensing panel may be coupled to each other through the coupling member.

[0019] In an embodiment, the input sensing panel may be directly disposed on the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other aspects and features of the present disclosure will become more apparent to those skilled in the art from the following detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0021] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure;

[0022] Figure 2 is an exploded perspective view of a display device according to an embodiment of the present disclosure;

[0023] Figure 3A is a cross-sectional view of a display module according to an embodiment of the present disclosure;

[0024] Figure 3B is a cross-sectional view of a display module according to an embodiment of the present disclosure;

[0025] Figure 4A is a plan view of a display panel according to an embodiment of the present disclosure;

[0026] Figure 4B is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure;

[0027] Figure 5 is a plan view of an input sensing panel according to an embodiment of the present disclosure;

[0028] Figure 6A is an enlarged view showing a region of an input sensing panel according to an embodiment of the present disclosure;

[0029] Figure 6B is along Figure 6A a cross-sectional view taken along line I-I';

[0030] Figure 6C is a cross-sectional view of an input sensing panel according to an embodiment of the present disclosure;

[0031] Figure 7 is an enlarged view showing a region of an input sensing panel according to an embodiment of the present disclosure;

[0032] Figure 8 is an enlarged view showing a region of an input sensing panel according to an embodiment of the present disclosure; and

[0033] Figures 9A to 9C is a plan view of a dummy pattern according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0034] Hereinafter, exemplary embodiments will be described in more detail with reference to the accompanying drawings, in which like reference numerals refer to like elements throughout. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary for a person of ordinary skill in the art to completely understand the aspects and features of the present disclosure may not be described. Unless otherwise noted, in all the drawings and the written description, like reference numerals refer to like elements, and thus, their description may not be repeated.

[0035] In the drawings, for clarity, the relative dimensions of elements, layers, and regions may be exaggerated and / or simplified. For ease of explanation, spatial relative terms, such as "below", "beneath", "lower", "under", "above", "upper", etc., may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the figures. It should be understood that, in addition to the orientation depicted in the figures, spatial relative terms are intended to encompass different orientations of the device during use or operation. For example, if the device in the figures is turned over, an element described as "below" or "beneath" or "under" another element or feature will then be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "beneath" can encompass both an above and a below orientation. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0036] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, first component, first region, first layer, or first section described below may be referred to as a second element, second component, second region, second layer, or second section without departing from the spirit and scope of the present disclosure.

[0037] It will be understood that when an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or there may be one or more intervening elements or layers. Further, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0038] The terms used herein are for the purpose of describing particular embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to also include the plural forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "comprises," "comprising," "includes," "including," "has," "have," and "having" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When the expression such as "at least one of..." is located after the elements of a list, it modifies the entire list of elements rather than modifying the individual elements in the list.

[0039] As used herein, the terms "substantially," "about," and similar terms are used as approximate terms and not as terms of degree, and are intended to leave a margin for the inherent deviations in measured or calculated values that would be recognized by a person of ordinary skill in the art. Additionally, "may" when used in the description of embodiments of the present disclosure represents "one or more embodiments of the present disclosure." As used herein, the terms "use," "using," and "used" may be understood to be synonymous with the terms "utilize," "utilizing," and "utilized," respectively. Additionally, the term "exemplary" is intended to represent an example or illustration.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0041] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure. [[ID=!3]] Figure 2 is an exploded perspective view of a display device according to an embodiment of the present disclosure.

[0042] Refer to Figure 1 and Figure 2, the display device EA can be a device activated according to an electrical signal. The display device EA can be implemented by (or used in) various electronic devices. For example, the display device EA can be used in large electronic devices such as televisions, monitors, external billboards, etc., and small and / or medium-sized electronic devices such as smart phones, tablets, personal computers, laptop computers, personal digital terminals, car navigation units (e.g., car navigation devices), game consoles, portable electronic devices, cameras, etc. However, the present disclosure is not limited thereto, and the above electronic devices are only provided as various examples. Therefore, without departing from the spirit and scope of the present disclosure, the display device EA can be used in other suitable electronic equipment and / or electronic devices. Hereinafter, as an illustrative example, the display device EA will be described as being included in a smart phone.

[0043] The display device EA can display an image IM in a third direction DR3 (e.g., toward the third direction DR3) on a display surface FS that is parallel to or substantially parallel to each of the first direction DR1 and the second direction DR2. The image IM can include a still image and / or a dynamic image (e.g., a moving image). In Figure 1 , as an illustrative example, the image IM is shown to include a clock and various icons. The display surface FS on which the image IM is displayed can correspond to the front surface of the display device EA and can also correspond to the front surface of the window panel WP.

[0044] As used herein, the front surface (e.g., the top surface) or the rear surface (e.g., the bottom surface) of each component can be defined according to (e.g., based on) the direction of the displayed image IM (e.g., the direction toward the displayed image IM). For example, the front surface and the rear surface can face away from each other in the third direction DR3 (e.g., can be opposite surfaces). The normal direction of each of the front surface and the rear surface can be parallel to or substantially parallel to the third direction DR3. The directions indicated as the first direction DR1, the second direction DR2, and the third direction DR3 can be relative, and thus, can be differently modified to different suitable directions. Hereinafter, the first to third directions can be the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 shown in the figure and can be represented by the same reference signs, respectively. As used herein, the terms "on a plane" and "in a plan view" can refer to an observation from the third direction DR3 (e.g., an observation from a plane in the third direction DR3).

[0045] The display device EA can include a window panel WP, an antireflection panel RPP, a display module (e.g., a display or a display assembly) DM, and a housing HU. In the present embodiment, the window panel WP and the housing HU can be coupled to each other to define the appearance of the display device EA.

[0046] The window panel WP may include an optically transparent insulating material. For example, the window panel WP may include glass and / or plastic. The window panel WP may have a single-layer structure or a multi-layer structure. For example, the window panel WP may include a plurality of plastic films bonded to each other using an adhesive, or may include a glass substrate and a plastic film that may be bonded to each other using an adhesive.

[0047] As described above, the front surface FS of the window panel WP may define the front surface of the display device EA. The front surface FS may include a transmissive region TA and a border region BZA. The transmissive region TA may be an optically transparent region. For example, the transmissive region TA may be a region having a visible light transmittance of about 90% or greater.

[0048] The border region BZA may be a region having a light transmittance relatively less than that of the transmissive region TA. The border region BZA may define the shape of the transmissive region TA. For example, the border region BZA may be arranged adjacent to the transmissive region TA and may at least partially surround the transmissive region TA (e.g., around the periphery of the transmissive region TA).

[0049] The border region BZA may have a suitable or desired color (e.g., a predetermined color). The border region BZA may cover the peripheral region NAA of the display module DM to prevent or substantially prevent the peripheral region NAA from being visible from the outside. However, the present disclosure is not limited thereto. For example, in the window panel WP according to an embodiment of the present disclosure, the border region BZA may be omitted.

[0050] The anti-reflection panel RPP may be provided below the window panel WP (e.g., beneath or below the window panel WP). The anti-reflection panel RPP may reduce the reflectance of external light incident on it from the upper side of the window panel WP. However, the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the anti-reflection panel RPP may be omitted, or may be provided as a component included in the display module DM.

[0051] The display module DM may display an image IM and may sense an external input. The display module DM includes a front surface IS, and the front surface IS includes an active region AA and a peripheral region NAA. The active region AA may be a region activated according to an electrical signal. The peripheral region NAA may at least partially surround the active region AA (e.g., around the periphery of the active region AA). However, the present disclosure is not limited thereto. For example, in various embodiments, the peripheral region NAA may be omitted, the peripheral region NAA in one direction may be omitted, or the peripheral region NAA may only be adjacent to two or fewer sides of the active region AA.

[0052] In Figure 2In the embodiment shown, the active area AA can be an area in which an image IM is displayed, and can also be an area in which an external input is sensed. The transmissive area TA can at least overlap with the active area AA. For example, the transmissive area TA can overlap with the entire surface of at least a part of the active area AA. Thus, a user can observe the image IM through the transmissive area TA and / or can provide an external input through the transmissive area TA. However, the present disclosure is not limited thereto. For example, the area of the active area AA in which the image IM is displayed and the area of the active area AA in which the external input is sensed can be separated from each other, but are not limited to a specific embodiment.

[0053] The peripheral area NAA can be an area covered by the border area BZA. The peripheral area NAA can be adjacent to the active area AA. The peripheral area NAA can at least partially surround the active area AA (e.g., surround the periphery of the active area AA). A driving circuit and / or driving lines for driving the active area AA can be provided in the peripheral area NAA.

[0054] The display module DM can include a display panel DP and an input sensing panel ISL. In addition, the display module DM can include driving circuits CF1, CF2, and MB electrically connected to the display panel DP and the input sensing panel ISL.

[0055] The display panel DP can include (e.g., can be) components (e.g., elements) that generate or substantially generate the image IM. The image IM generated by the display panel DP can be seen from the outside by a user through the transmissive area TA.

[0056] The input sensing panel ISL can sense an external input applied from the outside. As described above, the input sensing panel ISL can sense an external input provided to the window panel WP.

[0057] The driving circuits CF1, CF2, and MB can be electrically connected to the display panel DP and the input sensing panel ISL. The driving circuits CF1, CF2, and MB can include a main circuit board MB, a first circuit board CF1, and a second circuit board CF2.

[0058] The first circuit board CF1 can be electrically connected to the display panel DP. The first circuit board CF1 can connect the display panel DP to the main circuit board MB. In this embodiment, the first circuit board CF1 can be provided as a flexible circuit film. However, the present disclosure is not limited thereto. For example, in other embodiments, the first circuit board CF1 can not be connected to the main circuit board MB, and / or the first circuit board CF1 can be a rigid circuit board.

[0059] The first circuit board CF1 can be connected to pads (e.g., display pads) provided in the peripheral area NAA of the display panel DP. The first circuit board CF1 provides an electrical signal for driving the display panel DP to the display panel DP. The electrical signal can be generated in the first circuit board CF1 or can be generated in the main circuit board MB.

[0060] The second circuit board CF2 can be electrically connected to the input sensing panel ISL. The second circuit board CF2 can connect the input sensing panel ISL to the main circuit board MB. In this embodiment, the second circuit board CF2 can be provided as a flexible circuit film. However, the present disclosure is not limited thereto. For example, the second circuit board CF2 can be not connected to the main circuit board MB, and / or the second circuit board CF2 can be a rigid circuit board.

[0061] The second circuit board CF2 can be connected to pads (e.g., sensing pads) provided in the peripheral area NAA of the input sensing panel ISL. The second circuit board CF2 provides an electrical signal for driving the input sensing panel ISL to the input sensing panel ISL. The electrical signal can be generated in the second circuit board CF2 or can be generated in the main circuit board MB.

[0062] The main circuit board MB can include various driving circuits for driving the display module DM and connectors for power supply. Each of the first circuit board CF1 and the second circuit board CF2 can be connected to the main circuit board MB. According to an embodiment of the present disclosure, the display module DM can be controlled (e.g., can be easily controlled) by one main circuit board MB. However, the present disclosure is not limited thereto. For example, in the display module DM according to an embodiment of the present disclosure, the display panel DP and the input sensing panel ISL can be respectively connected to different main boards, or one of the first circuit board CF1 and the second circuit board CF2 can be not connected to one main circuit board MB, but is not limited to a specific embodiment.

[0063] The first circuit board CF1 and the second circuit board CF2 can be bent in a direction toward the rear surface of the display panel DP. In this case, in a state where the first circuit board CF1 and the second circuit board CF2 are bent, the first contact portion CN1 of the second circuit board CF2 can be connected to the second contact portion CN2 of the main circuit board MB.

[0064] In this embodiment, the first circuit board CF1 and the second circuit board CF2 may be disposed at different sides of the display module DM (e.g., disposed in different sides of the display module DM or disposed on different sides of the display module DM). For example, the first circuit board CF1 and the second circuit board CF2 may be spaced apart from each other in the second direction DR2, and the active area AA is located between the first circuit board CF1 and the second circuit board CF2. Accordingly, the second circuit board CF2 may be disposed at a side of the display module DM adjacent to the first edge DM-E1 of the display module DM, and the first circuit board CF1 may be disposed at the other side of the display module DM adjacent to the second edge DM-E2 of the display module DM. In an embodiment, the first edge DM-E1 may be spaced apart from the second edge DM-E2 in the second direction DR2. However, the present disclosure is not limited thereto. For example, in another embodiment, the first circuit board CF1 and the second circuit board CF2 may be disposed at the same side of the display module DM.

[0065] According to this embodiment, since the first circuit board CF1 and the second circuit board CF2 may be disposed at different sides of the display module DM, the peripheral area NAA (e.g., unnecessary portions of the peripheral area NAA) may be reduced. Accordingly, a display module DM including a reduced border (e.g., a narrow border) may be provided.

[0066] The housing HU may be coupled to the window panel WP. The housing HU may be coupled to the window panel WP to provide a suitable or desired internal space (e.g., a predetermined internal space). The display module DM may be accommodated in the internal space.

[0067] The housing HU may include a material having relatively high rigidity. For example, the housing HU may include glass, plastic, and / or metal, or may include a plurality of frames and / or plates made of a combination of glass, plastic, and / or metal. The housing HU may protect or substantially protect (e.g., may stably protect) components (e.g., assemblies) of the display device EA that may be accommodated in the internal space from external impacts.

[0068] Figure 3A is a cross-sectional view of a display module according to an embodiment of the present disclosure. Figure 3B is a cross-sectional view of a display module according to an embodiment of the present disclosure.

[0069] Referring to Figure 3A , the display module (e.g., a display or a display assembly) DM may include a display panel DP, an input sensing panel ISL, and a coupling member SLM.

[0070] The display panel DP according to an embodiment of the present disclosure may be an emissive display panel, but the present disclosure is not limited thereto. For example, the display panel DP may be an organic light emitting display panel, a quantum dot light emitting display panel, a liquid crystal display panel, etc.

[0071] The display panel DP may include a first substrate BS1, a display circuit layer ML-D, and a display element layer EML. The input sensing panel ISL may include a second substrate BS2 and a sensing circuit layer ML-T.

[0072] Each of the first substrate BS1 and the second substrate BS2 may be a silicon substrate, a plastic substrate, an insulating film, or a laminated structure including a plurality of insulating layers.

[0073] The display circuit layer ML-D may be disposed on the first substrate BS1. The display circuit layer ML-D may include a plurality of insulating layers, a plurality of conductive layers, and a semiconductor layer. The plurality of conductive layers of the display circuit layer ML-D may define (e.g., may constitute) signal lines and / or control circuits of pixels.

[0074] The display element layer EML may be disposed on the display circuit layer ML-D. The display element layer EML may be a layer that generates light and / or controls light transmittance. For example, the display element layer EML of an organic light emitting display panel may include an organic light emitting material. The display element layer EML of a quantum dot light emitting display panel may include at least one of quantum dots, quantum rods, etc. The display element layer EML of a liquid crystal display panel may include a liquid crystal layer.

[0075] The second substrate BS2 may be disposed on the display element layer EML. A space (e.g., a predetermined space) may be defined between the second substrate BS2 and the display element layer EML. This space may be filled with air and / or an inert gas. In an embodiment of the present disclosure, the space may be filled with a filler, for example, a silicone-based polymer, an epoxy-based resin, or an acrylic-based resin.

[0076] The sensing circuit layer ML-T may be disposed on the second substrate BS2. The sensing circuit layer ML-T may include a plurality of insulating layers and a plurality of conductive layers. The plurality of conductive layers may define (e.g., may constitute) sensing electrodes for sensing external inputs, sensing lines connected to the sensing electrodes, and / or sensing pads connected to the sensing lines.

[0077] The coupling member SLM may be disposed between the first substrate BS1 and the second substrate BS2. The coupling member SLM may couple the first substrate BS1 to the second substrate BS2. The coupling member SLM may include an organic material, such as a photo-curable resin or a photo-plastic resin, or may include an inorganic material, such as a glass frit seal, but the present disclosure is not limited thereto.

[0078] Refer toFigure 3B The display module (e.g., a display or a display assembly) DM-1 may include a display panel DP-1 and an input sensing unit (e.g., an input sensing layer) ISL-1. The input sensing unit ISL-1 may be referred to as an input sensing layer.

[0079] The display panel DP-1 may include a first substrate BS1, a display circuit layer ML-D, a display element layer EML, and a thin film encapsulation layer ECL. The input sensing unit ISL-1 may include a base layer ECL and a sensing circuit layer ML-T. The thin film encapsulation layer ECL and the base layer ECL may be the same layer.

[0080] According to an embodiment of the present disclosure, the display panel DP-1 and the input sensing unit ISL-1 may be formed by a continuous process. In other words, the sensing circuit layer ML-T may be directly disposed on the thin film encapsulation layer ECL.

[0081] Figure 4A is a plan view of a display panel according to an embodiment of the present disclosure. Figure 4B is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure.

[0082] Referring to Figure 4A , the display panel DP may include a plurality of pixels PX, a plurality of signal lines GL, DL, PL, and ECL, and a plurality of display pads PDD.

[0083] The active area AA of the display panel DP may be an area in which an image is displayed, and the peripheral area NAA may be an area in which a driving circuit and / or driving lines are provided. In Figure 4A , the active area AA and the peripheral area NAA of the display panel DP are shown. A plurality of pixels PX may be provided in the active area AA.

[0084] The plurality of signal lines GL, DL, PL, and ECL may be connected to the pixels PX to transmit electrical signals to the pixels PX. As an example, in Figure 4A , the scan lines GL, data lines DL, power lines PL, and emission control lines ECL among the signal lines provided in the display panel DP are shown. However, the present disclosure is not limited thereto. For example, the signal lines may further include an initialization voltage line, but the present disclosure is not limited thereto.

[0085] Referring to Figure 4B , a signal circuit diagram of one pixel PX among the plurality of pixels PX is shown as a representative example. Figure 4B An example of a pixel PX connected to the i-th scan line GLi and the i-th emission control line ECLi (where i is a natural number) is shown.

[0086] A pixel PX may include a light-emitting element EE and a pixel circuit CC. The pixel circuit CC may include a plurality of transistors T1 to T7 and a capacitor CP. The plurality of transistors T1 to T7 may be formed by a low-temperature polycrystalline silicon (LTPS) process or a low-temperature polycrystalline oxide (LTPO) process.

[0087] The pixel circuit CC may control the amount of current flowing through the light-emitting element EE in response to a data signal. The light-emitting element EE may emit light having a desired brightness (e.g., a predetermined brightness) corresponding to the amount of current provided from the pixel circuit CC. In this case, the level (e.g., voltage level or potential level) of the first power supply ELVDD may be set to be greater than the level (e.g., voltage level or potential level) of the second power supply ELVSS. The light-emitting element EE may include an organic light-emitting element or a quantum dot light-emitting element.

[0088] Each of the plurality of transistors T1 to T7 may include an input electrode (e.g., a source electrode), an output electrode (e.g., a drain electrode), and a control electrode (e.g., a gate electrode). For convenience, as used in this specification, one of the input electrode and the output electrode may be referred to as the first electrode, and the other of the input electrode and the output electrode may be referred to as the second electrode.

[0089] The first electrode of the first transistor T1 may be connected to the first power supply ELVDD via the fifth transistor T5. The second electrode of the first transistor T1 may be connected to the anode electrode of the light-emitting element EE via the sixth transistor T6. In this specification, the first transistor T1 may be referred to as a driving transistor.

[0090] The first transistor T1 may control the amount of current flowing through the light-emitting element EE according to the voltage applied to the control electrode of the first transistor T1.

[0091] The second transistor T2 may be connected between the data line DL and the first electrode of the first transistor T1. The control electrode of the second transistor T2 may be connected to the i-th scan line GLi. When the i-th scan signal is applied to the i-th scan line GLi, the second transistor T2 may be turned on to electrically connect the data line DL to the first electrode of the first transistor T1.

[0092] The third transistor T3 may be connected between the second electrode of the first transistor T1 and the control electrode of the first transistor T1. The control electrode of the third transistor T3 may be connected to the i-th scan line GLi. When the i-th scan signal is applied to the i-th scan line GLi, the third transistor T3 is turned on to electrically connect the second electrode of the first transistor T1 to the control electrode of the first transistor T1. Thus, when the third transistor T3 is turned on, the first transistor T1 is connected in the form of a diode (e.g., the first transistor T1 is diode-connected).

[0093] The fourth transistor T4 can be connected between the node ND and an initialization power generation unit (e.g., an initialization power supply). The control electrode of the fourth transistor T4 can be connected to the (i - 1)-th scan line GLi-1. When the (i - 1)-th scan signal is provided to the (i - 1)-th scan line GLi-1, the fourth transistor T4 is turned on to supply an initialization voltage Vint to the node ND.

[0094] The fifth transistor T5 can be connected between the power line PL and the first electrode of the first transistor T1. The control electrode of the fifth transistor T5 can be connected to the i-th emission control line ECLi.

[0095] The sixth transistor T6 can be connected between the second electrode of the first transistor T1 and the anode electrode of the light-emitting element EE. The control electrode of the sixth transistor T6 can be connected to the i-th emission control line ECLi.

[0096] The seventh transistor T7 can be connected between the initialization power generation unit and the anode electrode of the light-emitting element EE. The control electrode of the seventh transistor T7 can be connected to the (i + 1)-th scan line GLi+1. When the (i + 1)-th scan signal is provided to the (i + 1)-th scan line GLi+1, the seventh transistor T7 is turned on to supply an initialization voltage Vint to the anode electrode of the light-emitting element EE.

[0097] The seventh transistor T7 can improve the black display ability of the pixel PX. For example, when the seventh transistor T7 is turned on, the parasitic capacitor of the light-emitting element EE can be discharged. Therefore, when realizing black luminance, the light-emitting element EE can not emit light due to the leakage current from the first transistor T1, and thus, the black display performance can be improved.

[0098] Although Figure 4B it is shown that the control electrode of the seventh transistor T7 can be connected to the (i + 1)-th scan line GLi+1, the present disclosure is not limited thereto. For example, in another embodiment of the present disclosure, the control electrode of the seventh transistor T7 can be connected to the i-th scan line GLi or the (i - 1)-th scan line GLi-1.

[0099] The capacitor CP can be provided between the power line PL and the node ND. The capacitor CP stores a voltage corresponding to the data signal. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing through the first transistor T1 can be determined according to the voltage stored in the capacitor CP.

[0100] However, the present disclosure is not limited to Figure 4BThe equivalent circuit diagram of the pixel PX shown in. For example, according to another embodiment of the present disclosure, the pixel PX may have various suitable structures and / or shapes capable of causing the light-emitting element EE to emit light. Although each of the transistors T1 to T7 is shown as a PMOS transistor in Figure 4B this is not limited to the present disclosure. For example, in another embodiment of the present disclosure, each of the transistors T1 to T7 of the pixel circuit CC may be implemented as an NMOS transistor (e.g., may be composed of NMOS transistors). In another example, in an embodiment of the present disclosure, the transistors T1 to T7 of the pixel circuit CC may be implemented as any suitable combination of NMOS transistors and PMOS transistors (e.g., may be composed of any suitable combination of NMOS transistors and PMOS transistors).

[0101] Referring again to Figure 4A , the power supply pattern VDD may be provided in the peripheral area NAA. In this embodiment, the power supply pattern VDD may be connected to a plurality of power lines PL. Therefore, the display panel DP may include the power supply pattern VDD to provide the same or substantially the same first power signal to the plurality of pixels PX.

[0102] The display pad PDD may include a first pad D1 and a second pad D2. The first pad D1 may be provided in plurality, and the plurality of first pads D1 may be respectively connected to the data lines DL. The second pad D2 may be connected to the power supply pattern VDD and may be electrically connected to the power line PL. The display panel DP may provide an externally provided (e.g., provided from the outside) electrical signal to the pixel PX through the display pad PDD. In addition to the first pad D1 and the second pad D2, the display pad PDD may further include pads for receiving other electrical signals, but the present disclosure is not limited thereto.

[0103] Figure 5 is a plan view of an input sensing panel according to an embodiment of the present disclosure. Figure 6A is an enlarged view showing a region of an input sensing panel according to an embodiment of the present disclosure. Figure 6B is a cross-sectional view taken along the line I-I' of Figure 6A ; Figure 6C is a cross-sectional view of an input sensing panel according to an embodiment of the present disclosure.

[0104] Referring to Figure 5 , the input sensing panel ISL may include a second substrate BS2 (see Figure 3A) The first sensing electrode TE1, the second sensing electrode TE2, multiple sensing lines TL1, TL2, and TL3, multiple sensing pads TP1, TP2, and TP3, electrostatic sensing units (e.g., electrostatic sensors or electrostatic sensing circuits) ED1, ED2, EL1, and EL2, and a floating pattern unit (e.g., floating pattern circuit) PT including a bridging pattern PB. The first sensing electrode TE1, the second sensing electrode TE2, multiple sensing lines TL1, TL2, and TL3, and multiple sensing pads TP1, TP2, and TP3 according to the present embodiment may be defined as an input sensing unit (e.g., input sensing layer or input sensing circuit). The input sensing unit may be included in (e.g., may constitute) the sensing circuit layer ML-T described in reference to Figure 3A or Figure 3B The sensing circuit layer ML-T described in (e.g., may be included in the sensing circuit layer ML-T).

[0105] An effective area AA-I and a peripheral area NAA-I may be defined on the second substrate BS2. The peripheral area NAA-I may at least partially surround the effective area AA-I (e.g., surround the periphery of the effective area AA-I).

[0106] The first sensing electrode TE1 and the second sensing electrode TE2 may be disposed in the effective area AA-I. The input sensing panel ISL may obtain information corresponding to an external input through a capacitance change between the first sensing electrode TE1 and the second sensing electrode TE2.

[0107] The first sensing electrode TE1 may include a first sensing pattern SP1 and a first connection pattern BP1. The first sensing electrode TE1 may extend in a first direction DR1 and may be arranged along a second direction DR2. The first sensing patterns SP1 may be arranged to be spaced apart from each other in the first direction DR1. At least one first connection pattern BP1 may connect two adjacent first sensing patterns SP1 to each other.

[0108] The second sensing electrode TE2 may include a second sensing pattern SP2 and a second connection pattern BP#. The second sensing electrode TE2 may extend in the second direction DR2 and may be arranged along the first direction DR1. The second sensing patterns SP2 may be arranged to be spaced apart from each other in the second direction DR2. At least one second connection pattern BP2 may connect two adjacent second sensing patterns SP2 to each other.

[0109] The sensing lines TL1, TL2, and TL3 may be disposed in the peripheral area NAA-I. The sensing lines TL1, TL2, and TL3 may include a first sensing line TL1, a second sensing line TL2, and a third sensing line TL3.

[0110] The first sensing line TL1 can be connected to the first sensing electrode TE1. The second sensing line TL2 can be connected to one end of the second sensing electrode TE2. The third sensing line TL3 can be connected to the other end of the second sensing electrode TE2. The other end of the second sensing electrode TE2 can be an end opposite to the one end of the second sensing electrode TE2.

[0111] According to one or more embodiments of the present disclosure, the second sensing electrode TE2 can be connected to the second sensing line TL2 and the third sensing line TL3. Accordingly, the sensitivity of the region with respect to the second sensing electrode TE2 can be maintained or substantially maintained (e.g., can be uniformly maintained), where the second sensing electrode TE2 can have a length relatively longer than that of the first sensing electrode TE1. However, the present disclosure is not limited thereto. For example, in an embodiment, the third sensing line TL3 can be omitted, but the present disclosure is not limited thereto.

[0112] The sensing pads TP1, TP2, and TP3 can be disposed in the peripheral region NAA-I. The sensing pads TP1, TP2, and TP3 can include a first sensing pad TP1, a second sensing pad TP2, and a third sensing pad TP3. The first sensing pad TP1 can be connected to the first sensing line TL1 and can be electrically connected to the first sensing electrode TE1. The second sensing pad TP2 can be connected to the second sensing line TL2, and the third sensing pad TP3 can be connected to the third sensing line TL3. Accordingly, the second sensing pad TP2 and the third sensing pad TP3 can be electrically connected to the second sensing electrode TE2.

[0113] In this embodiment, the sensing pads TP1, TP2, and TP3 and the display pads PDD of the display panel DP can be disposed at different sides (e.g., in or on the sides) of the display module DM (e.g., see Figure 2 ). For example, the sensing pads TP1, TP2, and TP3 can be disposed to be spaced apart from the display pads PDD in the second direction DR2, and the active area AA-I is located between the sensing pads TP1, TP2, and TP3 and the display pads PDD. Accordingly, the sensing pads TP1, TP2, and TP3 can be disposed at a side (e.g., in or on a side) of the display module DM adjacent to the first edge DM-E1 of the display module DM, and the display pads PDD can be disposed at the other side (e.g., in or on the other side) of the display module DM adjacent to the second edge DM-E2 of the display module DM, where the second edge DM-E2 is spaced apart from the first edge DM-E1 in the second direction DR2. For convenience, the display panel DP, the first circuit board CF1, and the display pads PDD are shown in dashed lines in Figure 5 .

[0114] The electrostatic sensing units ED1, ED2, EL1, and EL2 can be disposed in the peripheral region NAA-I. The electrostatic sensing units ED1, ED2, EL1, and EL2 can include a first electrostatic sensing pad ED1, a second electrostatic sensing pad ED2, a first electrostatic sensing line EL1, and a second electrostatic sensing line EL2.

[0115] The first electrostatic sensing pad ED1 and the second electrostatic sensing pad ED2 can be spaced apart from each other, and the sensing pads TP1, TP2, and TP3 are interposed between the first electrostatic sensing pad ED1 and the second electrostatic sensing pad ED2. For example, the first electrostatic sensing pad ED1 can be disposed between the first sensing pad TP1 and the floating pattern unit PT, and the second electrostatic sensing pad ED2 can be disposed to be spaced apart from the third sensing pad TP3. One end of the first electrostatic sensing line EL1 can be connected to the first electrostatic sensing pad ED1, and one end of the second electrostatic sensing line EL2 can be connected to the second electrostatic sensing pad ED2.

[0116] In an embodiment, the first electrostatic sensing line EL1 and the second electrostatic sensing line EL2 can surround the sensing electrodes TE1 and TE2 (e.g., around the periphery of the sensing electrodes TE1 and TE2). For example, the first electrostatic sensing line EL1 can surround the right side of each of the sensing electrodes TE1 and TE2 (e.g., the right side of the active region AA-I) (e.g., around the periphery of the above right side), and the second electrostatic sensing line EL2 can surround the left side of each of the sensing electrodes TE1 and TE2 (e.g., the left side of the active region AA-I) (e.g., around the periphery of the above left side). The other ends of the first electrostatic sensing line EL1 and the second electrostatic sensing line EL2 can be spaced apart from each other. Accordingly, the first electrostatic sensing line EL1 and the second electrostatic sensing line EL2 can be electrically insulated from each other.

[0117] According to one or more embodiments of the present disclosure, the electrostatic sensing units ED1, ED2, EL1, and EL2 surrounding the sensing electrodes TE1 and TE2 (e.g., around the periphery of the sensing electrodes TE1 and TE2) can be disposed to determine (e.g., easily determine) whether the input sensing unit is damaged by static electricity flowing from the outside to the input sensing unit.

[0118] The floating pattern unit PT can include a bridging pattern PB and a plurality of patterns RR, BR, and AM that will be described in more detail below. The floating pattern unit PT (e.g., the floating pattern) can be electrically insulated from the input sensing unit. In Figure 6A which, an example in which the floating pattern unit PT is disposed at the edge of the input sensing panel ISL and adjacent to the first electrostatic sensing pad ED1 is shown.

[0119] The floating pattern unit PT can be disposed within the floating region PTA. In the process of forming the input sensing panel ISL, the floating region PTA can be an area electrically insulated from the input sensing unit, and patterns RR, BR, and AM required for process convenience are provided in this area.

[0120] The patterns RR, BR, and AM included in the floating pattern unit PT can be electrically connected to each other. Therefore, each of the sensing pads TP1, TP2, and TP3 and the electrostatic sensing pads ED1 and ED2 can have a relatively large area.

[0121] The floating pattern unit PT can be electrically connected to components (e.g., one component) of the electrostatic sensing units ED1, ED2, EL1, and EL2 through the bridging pattern PB. For example, as Figure 5 shown, the floating pattern unit PT and the first electrostatic sensing pad ED1 can be connected to each other through the bridging pattern PB.

[0122] Referring to Figure 6A , in an embodiment, the floating pattern unit PT can include a resistance test pattern RR, an alignment pattern AM, and a connection pattern BR. The resistance test pattern RR, the alignment pattern AM, and the connection pattern BR can be electrically insulated from the input sensing unit.

[0123] The alignment pattern AM can be used to align pads (not shown) disposed on the second circuit board CF2 (e.g., see Figure 2 ) and the sensing pads TP1, TP2, and TP3, or can be used to identify the positions of the pads when a signal is applied to the electrostatic sensing units ED1, ED2, EL1, and EL2 or to the resistance test pattern RR. Although one alignment pattern AM having a Figure 6A shape is shown in , the present disclosure is not limited thereto. For example, multiple alignment patterns AM can be provided, and / or they can have various suitable shapes, but the present disclosure is not limited thereto.

[0124] The resistance test pattern RR can be disposed adjacent to the first electrostatic sensing pad ED1. The resistance test pattern RR can include (e.g., can be) pads for determining whether the second circuit board CF2 (e.g., see Figure 2 ) is bonded to the sensing pads TP1, TP2, and TP3. Although one resistance test pattern RR is shown in Figure 6A , the present disclosure is not limited thereto, and multiple resistance test patterns RR can be provided.

[0125] The connection pattern BR can connect the resistance test pattern RR to the alignment pattern AM. For convenience, the connection pattern BR is described as a separate component (e.g., a separate element), but the patterns constituting the floating pattern unit PT can be formed by the same or substantially the same process. Thus, the patterns can include the same or substantially the same materials as each other and can be provided on the same insulating layer.

[0126] The floating pattern unit PT can be provided adjacent to the outermost side of the input sensing panel ISL and can have an area larger than the area of each of the relatively adjacent pads TP1, TP2, TP3, ED1, and ED2, such that static electricity flowing from the outside can be charged in the floating pattern unit PT (e.g., can be easily charged in the floating pattern unit PT). The static electricity charged in the floating pattern unit PT may flow into the adjacent sensing lines TL1, TL2, and TL3, and / or may flow into a component (e.g., an element) of the input sensing unit, which may cause defects in the input sensing panel ISL.

[0127] In Figure 6A FIG., an example in which static electricity charged in the alignment pattern AM of the floating pattern unit PT flows into the first sensing line TL1 to cause a defect SP is shown as a dashed arrow.

[0128] According to one or more embodiments of the present disclosure, the floating pattern unit PT can be connected to the electrostatic sensing units ED1, ED2, EL1, and EL2 that are electrically insulated from the input sensing unit to provide a path through which the static electricity charged in the floating pattern unit PT can be introduced into the electrostatic sensing units ED1, ED2, EL1, and EL2. Thus, the path through which the static electricity charged in the floating pattern unit PT is introduced into the input sensing unit can be blocked or substantially blocked to reduce the defects in the input sensing panel ISL that may be caused by static electricity. Accordingly, a display device having improved reliability can be provided.

[0129] Referring to Figure 6B FIG., the sensing circuit layer ML-T of the input sensing panel ISL according to an embodiment of the present disclosure can include a first insulating layer TIL1, a second insulating layer TIL2, a first conductive layer TC1, and a second conductive layer TC2. Although examples of components (e.g., elements) corresponding to the sensing circuit layer ML-T provided on the ​ and ​ are shown in ​ the second substrate BS2, the present disclosure is not limited thereto. For example, components (e.g., elements) corresponding to the sensing circuit layer ML-T of ​ and ​ can be equally or substantially equally applied to ​The sensing circuit layer ML-T. In this case, components (e.g., elements) corresponding to the sensing circuit layer ML-T shown in ​ and ​ can be disposed on the base layer (e.g., thin film encapsulation layer) ECL shown in ​ instead of being disposed on the second substrate BS2 shown in ​ and ​ The first conductive layer TC1 is disposed on the second substrate BS2. In an embodiment, the first conductive layer TC1 may include a metallic material. For example, the first conductive layer TC1 may include molybdenum, silver, titanium, copper, aluminum, or a combination thereof (e.g., an alloy). In an embodiment, the alloy may be, for example, molybdenum niobium.

[0130] When the first conductive layer TC1 includes a metal, the first conductive layer TC1 may be defined as a part of the first connection pattern BP1, the first sensing line TL1, the electrostatic sensing pads ED1 and ED2, the electrostatic sensing lines EL1 and EL2, and the floating pattern unit PT (e.g., the bridging pattern PB, the connection pattern BR, and a part of the resistance test pattern RR) among the components (e.g., elements) of the input sensing panel ISL shown in

[0131] ​ In an embodiment, the connection pattern BR and the bridging pattern PB may be disposed at the same layer as each other (e.g., disposed in the same layer as each other or disposed on the same layer as each other).

[0132] ​ ​ shows an exemplary cross-sectional view taken along the line I-I' of in which the first sensing line TL1 among the sensing lines TL1, TL2, and TL3, the first electrostatic sensing pad ED1 among the electrostatic sensing pads ED1 and ED2, and the first electrostatic sensing line EL1 among the electrostatic sensing lines EL1 and EL2 are shown.

[0133] The first insulating layer TIL1 may cover the first conductive layer TC1. The first insulating layer TIL1 may include an inorganic material, for example, including at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide.

[0134] The second conductive layer TC2 may be disposed on the first insulating layer TIL1. In an embodiment, the second conductive layer TC2 may include a transparent conductive material. As used in this specification, transparent may refer to a light transmittance greater than or equal to a reference (e.g., a predetermined reference). For example, the reference may be about 90%, but the present disclosure is not limited thereto. The second conductive layer TC2 may include a transparent conductive oxide, for example, including at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), and indium gallium zinc oxide (IGZO), or including a mixture / compound thereof. However, the present disclosure is not limited thereto.

[0135] When the second conductive layer TC2 includes a transparent conductive material, the second conductive layer TC2 may be defined as ​ components (e.g., elements) of the input sensing panel ISL such as sensing patterns SP1 and SP2, the remaining portions of the second connection pattern BP2, the electrostatic sensing pads ED1 and ED2, and the remaining portions of the floating pattern unit PT (e.g., the remaining portion of the resistance test pattern RR and the alignment pattern AM).

[0136] In an embodiment, the first sensing pattern SP1 and the first connection pattern BP1 may be connected to each other through contact holes extending through (e.g., passing through) the first insulating layer TIL1.

[0137] The second insulating layer TIL2 may cover the second conductive layer TC2. The second insulating layer TIL2 may include an inorganic material, for example, including at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide.

[0138] Referring to ​ FIG., the sensing circuit layer ML-T0 of the input sensing panel ISL-0 according to an embodiment of the present disclosure may include a first insulating layer TIL1-0, a second insulating layer TIL2-0, a first conductive layer TC1-0, and a second conductive layer TC2-0. The first insulating layer TIL1-0 and the second insulating layer TIL2-0 may be the same as or substantially the same as the first insulating layer TIL1 and the second insulating layer TIL2 described in reference ​ FIG.

[0139] In an embodiment, the first conductive layer TC1-0 may include a transparent conductive material, and the second conductive layer TC2-0 may include a metal.

[0140] Since the first conductive layer TC1-0 includes a transparent conductive material, the first conductive layer TC1-0 may be defined as ​The sensing patterns SP1 and SP2, the second connection pattern BP2, a part of the electrostatic sensing pads ED1-0 and ED2-0, and a part of the floating pattern unit (e.g., floating pattern circuit) PT-0 (e.g., a part of the resistance test pattern RR-0 and the alignment pattern AM-0) in components (e.g., assemblies) of the input sensing panel ISL.

[0141] When the second conductive layer TC2-0 includes metal, the second conductive layer TC2-0 can be defined as ​ The first connection pattern BP1, the first sensing line TL1-0, the remaining parts of the electrostatic sensing pads ED1-0 and ED2-0, the electrostatic sensing lines EL1-0 and EL2-0, and the remaining part of the floating pattern unit PT-0 (e.g., the bridging pattern PB-0, the connection pattern BR-0, and the remaining part of the resistance test pattern RR-0) in components (e.g., assemblies) of the input sensing panel ISL. In an embodiment, the connection pattern BR-0 and the bridging pattern PB-0 can be formed at the same layer as each other (e.g., formed in the same layer as each other or formed on the same layer as each other).

[0142] In an embodiment, the first sensing pattern SP1 and the first connection pattern BP1 can be connected to each other through a contact hole extending through (e.g., passing through) the first insulating layer TIL1.

[0143] ​ Shows an exemplary cross-sectional view taken along ​ Line I-I' of, in which the first sensing line TL1-0 among the sensing lines TL1-0, TL2, and TL3, the first electrostatic sensing pad ED1-0 among the electrostatic sensing pads ED1-0 and ED2, and the first electrostatic sensing line EL1-0 among the electrostatic sensing lines EL1-0 and EL2 are shown.

[0144] ​ Is an enlarged view showing a region of an input sensing panel according to an embodiment of the present disclosure. ​ Is an enlarged view showing a region of an input sensing panel according to an embodiment of the present disclosure. The same / similar reference numerals are used for components that are the same or substantially the same (or similar) as ​ The components of, and thus, the redundant description thereof can be simplified or may not be repeated.

[0145] Referring to ​ According to an embodiment, the bridging pattern PB-1 can be connected to the alignment pattern AM and the first electrostatic sensing line EL1.

[0146] According to an embodiment, the bridging pattern PB-1 may be connected to a portion of the alignment pattern AM closest to the first sensing line TL1. For example, the bridging pattern PB-1 may be connected to a protruding portion of the alignment pattern AM extending toward (e.g., facing) the first sensing line TL1, and the bridging pattern PB-1 may be disposed on the first electrostatic sensing line EL1 to prevent or substantially prevent (e.g., effectively prevent) static electricity introduced from the outside from being introduced into the first sensing line TL1. However, the present disclosure is not limited thereto. For example, when the bridging pattern PB-1 is connected to a region where the alignment pattern AM protrudes adjacent to the input sensing unit and is connected to the second electrostatic sensing line EL2 to provide a path through which static electricity introduced from the outside flows through the electrostatic sensing units ED1, ED2, EL1, and EL2, the connection position and / or shape of the bridging pattern PB-1 may not be limited to a specific embodiment.

[0147] Referring to ​ , according to an embodiment, the input sensing panel ISL (see ​ ) may further include dummy patterns DMP disposed between the floating pattern unit PT and the electrostatic sensing units ED1 and EL1 and electrically insulated from the input sensing unit. The dummy patterns DMP may be provided in plural and may be spaced apart from each other in a first direction DR1 and a second direction DR2.

[0148] The dummy patterns DMP may be disposed at the same layer as the layer of the bridging pattern PB (e.g., disposed in the same layer as the layer of the bridging pattern PB or disposed on the same layer as the layer of the bridging pattern PB). The dummy patterns DMP may include metal.

[0149] When the input sensing panel ISL includes the dummy patterns DMP, the dummy patterns DMP may be disposed between the floating pattern unit PT and the electrostatic sensing units ED1 and EL1 such that static electricity charged in the floating pattern unit PT may be introduced into the dummy patterns DMP, thereby providing a display device with improved reliability.

[0150] ​ is a plan view of a dummy pattern according to one or more embodiments of the present disclosure. The same / similar reference numerals are used to denote components and / or configurations that are the same or substantially the same (or similar) as those of ​ and ​ , and thus, the redundant description thereof may be simplified or may not be repeated.

[0151] Referring to ​, in an embodiment, the dummy pattern DMP-A may be set to a triangular shape. In an embodiment, the dummy pattern DMP-B may be set to an oval shape. In an embodiment, the dummy pattern DMP-C may be set to a trapezoidal shape. However, the present disclosure is not limited thereto. For example, the dummy pattern may be set to a polygonal shape and / or a circular shape, may be set to multiple ones, and / or may have different shapes, such that the dummy patterns may be set to different shapes from each other, but the present disclosure is not limited thereto.

[0152] Referring to ​ and ​ , although the circuit boards CF1 and CF2 according to one or more embodiments of the present disclosure are described as being provided on different edges DM-EI and DM-E2 of the display module DM from each other, the present disclosure is not limited thereto. For example, the circuit boards CF1 and CF2 may be provided on adjacent edges of the display module DM from each other, but the present disclosure is not limited thereto.

[0153] According to one or more exemplary embodiments of the present disclosure, the floating pattern unit may be connected to the electrostatic sensing unit electrically insulated from the input sensing unit to provide a path through which the static electricity charged in the floating pattern unit may flow into the electrostatic sensing unit. Accordingly, the path through which the static electricity charged in the floating pattern unit may be introduced into the input sensing unit may be blocked or substantially blocked to prevent or reduce defects of the input sensing panel due to static electricity. Accordingly, a display device having improved reliability may be provided.

[0154] Although some exemplary embodiments have been described, those skilled in the art will readily understand that various modifications may be made to the exemplary embodiments without departing from the spirit and scope of the present disclosure. It should be understood that, unless otherwise described, the description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Accordingly, it should be understood that the foregoing is illustrative of various exemplary embodiments and should not be construed as limited to the specific exemplary embodiments disclosed herein, and that various modifications to the disclosed exemplary embodiments as well as other exemplary embodiments are intended to be included within the spirit and scope of the present disclosure as defined by the appended claims and their equivalents.

Claims

1. Display devices, including: A display panel comprising a plurality of pixels and display pads connected to the pixels; as well as An input sensing panel is on the display panel, and the input sensing panel includes: Input sensing layer, including: a sensing electrode configured to sense an input; a sensing line connected to the sensing electrode; and a sensing pad connected to the sensing line; an electrostatic sensing circuit spaced apart from the sensing pad; and a floating pattern circuit electrically insulated from the input sensing layer and including a bridge pattern, wherein the floating pattern circuit includes a resistance test pattern and an alignment pattern connected to the resistance test pattern, The electrostatic sensing circuit includes a first electrostatic sensing pad and a second electrostatic sensing pad spaced apart from the first electrostatic sensing pad, and the sensing pad is located between the first electrostatic sensing pad and the second electrostatic sensing pad; and The bridge pattern is connected to the first static electricity sensing pad and the resistance test pattern.

2. The display device according to claim 1, wherein The electrostatic sensing circuit includes: a first electrostatic sensing line surrounding a portion of the sensing electrode, the first electrostatic sensing line including one end connected to the first electrostatic sensing pad; and a second electrostatic sensing line surrounding another portion of the sensing electrode, and including one end connected to the second electrostatic sensing pad; The other end of the first electrostatic sensing line and the other end of the second electrostatic sensing line are spaced apart from each other.

3. The display device according to claim 2, wherein The bridge pattern connects one of the first electrostatic sensing line and the second electrostatic sensing line to the alignment pattern. The display device according to claim 1 , wherein: The input sensing panel further includes a dummy pattern between the electrostatic sensing circuit and the floating pattern circuit.

5. The display device according to claim 4, wherein The dummy pattern has one of a polygonal shape, an elliptical shape, and a circular shape. The display device according to claim 1 , wherein: The input sensing panel includes: a first conductive layer, on the display panel; a first insulating layer covering the first conductive layer; and A second conductive layer is on the first insulating layer.

7. The display device according to claim 6, wherein The first conductive layer comprises metal, The second conductive layer includes a transparent conductive material, and The bridge pattern is defined as a portion of the first conductive layer.

8. The display device according to claim 6, wherein The second conductive layer comprises metal, The first conductive layer includes a transparent conductive material, and The bridge pattern is defined as a portion of the second conductive layer.

9. The display device according to claim 1, further comprising: an active area defined in a first direction and a second direction intersecting the first direction, the active area being configured to provide light generated from the display panel; as well as a peripheral area, surrounding the active area, wherein the display pad is arranged at one side of the peripheral area along the first direction, and The sensing pad and the floating pattern circuit are arranged at the other side of the peripheral area along the first direction to be spaced apart from the display pad in the second direction, and the active area is located between the sensing pad, the floating pattern circuit and the display pad.

10. The display device according to claim 1, further comprising a coupling member, in, The display panel and the input sensing panel are coupled to each other through the coupling member.

11. The display device according to claim 1, wherein The input sensing panel is directly disposed on the display panel.

Images