Memory controller and operating method thereof

Abstract

A memory controller capable of sequentially increasing or decreasing the total current consumed by a plurality of memory devices controls the plurality of memory devices connected through a plurality of channels. The memory controller includes: a request checker for identifying a memory device corresponding to a request received from a host among the plurality of memory devices and generating device information about the identified memory device to perform an operation corresponding to the request; a virtual manager for outputting a request for controlling a virtual pulse to be applied to a channel of a memory device selected according to the device information among the plurality of channels; and a virtual pulse generator for sequentially applying a virtual pulse to a channel connected to the selected memory device based on the request for controlling the virtual pulse.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2019-0108259, filed on September 2, 2019, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to an electronic device, and more particularly, to a memory controller and an operating method thereof. Background Art

[0004] A storage device stores data under the control of a host device such as a computer, smartphone, or smart tablet. The storage device may be a type that stores data on a magnetic disk, such as a hard disk drive (HDD), or a type that stores data on a semiconductor memory, i.e., a non-volatile memory, such as a solid-state drive (SSD) or a memory card.

[0005] The storage device may include a memory device for storing data and a memory controller for controlling the memory device. The memory device may be a volatile memory device or a non-volatile memory device. The non-volatile memory device may be any one of a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (RRAM), and / or a ferroelectric RAM (FRAM). Summary of the Invention

[0006] Embodiments provide a memory controller capable of sequentially increasing or decreasing a total current consumed by a plurality of memory devices, and an operating method of the memory controller.

[0007] According to one aspect of the present disclosure, there is provided a memory controller for controlling a plurality of memory devices coupled through a plurality of channels, the memory controller comprising: a request checker configured to identify a memory device corresponding to a request received from a host among the plurality of memory devices and generate device information about the identified memory device to perform an operation corresponding to the request; a virtual manager configured to output a request for controlling a virtual pulse to be applied to a channel of a memory device selected according to the device information among the plurality of channels; and a virtual pulse generator configured to sequentially apply virtual pulses to the channel coupled to the selected memory device based on the request for controlling the virtual pulse.

[0008] According to another aspect of the present disclosure, there is provided a method for operating a memory controller for controlling a plurality of memory devices coupled through a plurality of channels, the method comprising: identifying, among the plurality of memory devices, a memory device corresponding to a request received from a host, generating device information for the memory device to perform an operation corresponding to the request, outputting a request for controlling a dummy pulse to be applied to a channel of a memory device selected according to the device information among the plurality of channels, and sequentially applying the dummy pulse to the channel coupled to the selected memory device based on the request for controlling the dummy pulse.

[0009] According to yet another aspect of the present disclosure, a memory controller is provided for controlling a plurality of memory devices coupled through a plurality of channels, the memory controller including: a data transmitter configured to transmit data among the plurality of channels through a channel corresponding to a request received from a host; and a trigger transmitter configured to generate a virtual trigger in one or more channels other than a channel transmitting data, wherein the virtual trigger is a pulse of a specific amplitude applied to the memory device coupled to the channel corresponding to the request.

[0010] According to yet another aspect of the present disclosure, a method for operating a controller for controlling a plurality of memory devices through respective channels is provided, the method comprising: selecting two or more memory devices based on a request, and sequentially increasing a total current supplied to the selected memory devices by sequentially applying dummy pulses of set durations to the selected memory devices to reach a peak value when the selected memory devices simultaneously begin performing their respective requested operations.

[0011] According to yet another aspect of the present disclosure, a method for operating a controller for controlling a plurality of memory devices through respective channels is provided, the method comprising: selecting two or more of the memory devices based on chip enable signals respectively corresponding to the memory devices, and sequentially reducing a total current supplied to the selected memory devices by sequentially applying dummy pulses of set durations to the selected memory devices to reach a peak value when the selected memory devices simultaneously stop performing their respective requested operations.

[0012] According to another aspect of the present disclosure, there is provided a method for operating a controller for controlling a plurality of memory devices through respective channels, the method comprising: selecting two or more memory devices based on chip enable signals respectively corresponding to the memory devices, and sequentially increasing a total current supplied to the selected memory devices by sequentially applying dummy pulses of set duration to one or more first memory devices among the selected memory devices to reach a peak value when the selected memory devices simultaneously stop executing respective requested operations, wherein the selected memory devices include a first memory device and a single second memory device, wherein each of the first memory devices has one or more commands to be serviced, and wherein the single second memory device does not have any commands to be serviced. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Various embodiments will be described more fully hereinafter with reference to the accompanying drawings; however, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art.

[0014] In the accompanying drawings, dimensions may be exaggerated for ease of illustration. It will be understood that when an element is referred to as being "between" two elements, it may be the only element between the two elements, or one or more intermediate elements may be present. The same reference numerals always refer to the same elements. Furthermore, throughout this specification, references to "an embodiment," "another embodiment," etc. do not necessarily refer to only one embodiment, and different references to any such phrase do not necessarily refer to the same embodiment.

[0015] Figure 1 is a block diagram illustrating a storage device.

[0016] Figure 2 is to show that Figure 1 A diagram illustrating the structure of a memory device is shown.

[0017] Figure 3 is a diagram illustrating a memory block.

[0018] Figure 4 is a diagram illustrating an embodiment of a memory device coupled to multiple channels.

[0019] Figure 5 is a diagram illustrating another embodiment of a memory device coupled to multiple channels.

[0020] Figure 6 is a graph showing changes in total current consumption and noise of a voltage source when memory devices connected to a plurality of channels start or end operations at the same time.

[0021] Figure 7 is a diagram illustrating changes in total current consumption and noise of a voltage source when a plurality of memory devices simultaneously end operations while performing operations.

[0022] Figure 8 is a diagram showing the application of a virtual pulse to each channel. Figure 1 A diagram of the structure of the memory controller is shown.

[0023] Figure 9 is a diagram illustrating a method for sequentially increasing and decreasing the total current consumption.

[0024] Figure 10 is a diagram illustrating another embodiment of sequentially increasing and decreasing the total current consumption.

[0025] Figure 11 is shown to sequentially reduce the total current consumption Figure 1 A diagram of the structure of the memory controller is shown.

[0026] Figure 12 is a diagram illustrating application or interruption of a virtual pulse determined based on a command queue.

[0027] Figure 13 is a diagram illustrating a dummy pulse output based on a chip enable signal.

[0028] Figure 14 is a diagram illustrating the operation of a memory controller according to an embodiment of the present disclosure.

[0029] Figure 15 is a diagram illustrating the operation of a memory controller according to an embodiment of the present disclosure.

[0030] Figure 16 is a diagram illustrating the operation of a memory controller according to an embodiment of the present disclosure.

[0031] Figure 17 is a diagram illustrating the operation of a memory controller according to an embodiment of the present disclosure.

[0032] Figure 18 is to show that Figure 1 A diagram of another embodiment of a memory controller is shown.

[0033] Figure 19 is a block diagram illustrating a solid-state drive (SSD) system to which a storage device is applied according to an embodiment of the present disclosure.

[0034] Figure 20 is a block diagram exemplarily illustrating a user system of an application storage device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] The specific structural and functional descriptions disclosed herein are only for the purpose of describing the embodiments according to the embodiments of the present disclosure. However, the present invention can be implemented in various forms and is therefore not limited to the embodiments set forth herein.

[0036] Various embodiments of the present disclosure are described in detail below with reference to the accompanying drawings so that those skilled in the art can easily implement and practice the present invention.

[0037] Figure 1 is a block diagram illustrating a storage device.

[0038] Reference Figure 1 , the storage device 50 may include a memory device 100 and a memory controller 200 .

[0039] The storage device 50 may be used to store data under the control of a host computer 300 such as a mobile phone, smart phone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0040] The storage device 50 may be configured as any of various types of storage devices according to a host interface as a communication scheme with the host 300. For example, the storage device 50 may be implemented as a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced size MMC (RS-MMC), a micro MMC (micro-MMC), a secure digital (SD) card, a mini SD card, a micro SD card, a universal serial bus (USB) storage device, a universal flash memory (UFS) device, a compact flash (CF) card, a smart media card (SMC), and / or a memory stick.

[0041] The memory device 50 may be manufactured in any of a variety of package types. For example, the memory device 50 may be manufactured in a package-on-package (POP), a system-in-package (SIP), a system-on-chip (SOC), a multi-chip package (MCP), a chip-on-board (COB), a wafer-level fabricated package (WFP), and / or a wafer-level stacked package (WSP).

[0042] The memory device 100 can store data. The memory device 100 operates under the control of the memory controller 200. The memory device 100 may include a memory cell array including a plurality of memory cells for storing data. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells that may constitute a plurality of pages. In embodiments, a page may be a unit for storing data in the memory device 100 or for reading data stored in the memory device 100. A memory block may be a unit for erasing data.

[0043] In an embodiment, the memory device 100 may be a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate 4 (LPDDR4) SDRAM, a graphics double data rate (GDDR) SRAM, a low power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a perpendicular NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), etc. In this specification, by way of example, features and aspects of the present invention are described in the context of the memory device 100 being a NAND flash memory.

[0044] In an embodiment, the memory device 100 may be implemented in a two-dimensional array structure or a three-dimensional array structure. The following describes an example of implementing the memory device 100 in a three-dimensional array structure as an embodiment; however, the present disclosure is not limited to a three-dimensional array structure. The present disclosure can be applied not only to flash memory devices in which a charge storage layer is configured using a floating gate (FG), but also to charge trap flash memories (CTFs) in which a charge storage layer is configured using an insulating layer.

[0045] In an embodiment, the memory device 100 may operate using a single-level cell (SLC) scheme in which one data bit is stored in one memory cell. Alternatively, the memory device 100 may operate using a scheme in which at least two data bits are stored in one memory cell. For example, the memory device 100 may operate using a multi-level cell (MLC) scheme in which two data bits are stored in one memory cell, a triple-level cell (TLC) scheme in which three data bits are stored in one memory cell, or a quad-level cell (QLC) scheme in which four data bits are stored in one memory cell.

[0046] The memory device 100 is configured to receive commands and addresses from the memory controller 200 and access the area selected by the address in the memory cell array. That is, the memory device 100 can perform operations corresponding to the commands on the area selected by the address. For example, the memory device 100 can perform write (program) operations, read operations, and erase operations according to the received commands. For example, when a program command is received, the memory device 100 can program data in the area selected by the address. When a read command is received, the memory device 100 can read data from the area selected by the address. When an erase command is received, the memory device 100 can erase data stored in the area selected by the address.

[0047] In an embodiment, multiple instances of the memory device 100 may be provided. That is, the memory device 50 may include multiple memory devices.

[0048] The plurality of memory devices may be coupled to the memory controller 200 through channels so as to communicate with the memory controller 200. For example, the memory controller 200 may instruct an operation of each of the plurality of memory devices, and each of the plurality of memory devices may perform an operation corresponding to the instruction of the memory controller 200. In addition, each of the plurality of memory devices may output a result obtained by performing the operation to the memory controller 200.

[0049] The memory controller 200 may include a request checker 210. The request checker 210 may receive a request from the host 300 and may check to which memory device the received request is directed among a plurality of memory devices. The request checker 210 may generate device information by checking a memory device for which an operation corresponding to the request received from the host 300 is to be performed based on the request. The device information may identify the memory device for which the operation is to be performed.

[0050] When operations are simultaneously executed or terminated in a memory device, the total current consumption of the memory device rapidly increases or decreases, and thus noise may occur in the voltage source. Therefore, to prevent noise from occurring in the voltage source, the operation to be performed on the memory device may be delayed before the operation is performed on the memory device, or a dummy pulse may be applied to the memory device.

[0051] Therefore, operations corresponding to requests received from the host 300 can be delayed and executed at a later time. That is, when requests received from the host 300 allow operations to be executed simultaneously, these operations can be executed in a manner such that the next memory device performs an operation when another memory device completes an operation.

[0052] However, when an operation corresponding to a request received from the host 300 is delayed and executed later, program time is extended, and thus program performance may be degraded. That is, a delay corresponding to the delayed time may occur.

[0053] Therefore, in an embodiment of the present disclosure, a method of applying a dummy pulse to a plurality of memory devices before performing an operation on the plurality of memory devices is provided.

[0054] According to an embodiment of the present disclosure, memory devices do not delay and perform operations but simultaneously perform operations after a dummy pulse is applied to the memory devices on which operations are to be performed, so that data can be transferred quickly and / or signals can be transmitted quickly.

[0055] In an embodiment, before performing an operation on the memory devices identified in the device information, a dummy pulse may be applied to each channel connected to the corresponding memory devices. Rather than applying the dummy pulse to multiple channels simultaneously, the dummy pulse may be applied to each channel sequentially. That is, after applying the dummy pulse to one of the multiple channels, the dummy pulse may be applied to another channel every time a set time has passed.

[0056] The memory controller 200 may include a virtual manager 220. The virtual manager 220 may output a request for applying or interrupting a virtual pulse.

[0057] Specifically, when it is determined that multiple memory devices have begun operating simultaneously, virtual manager 220 may output a virtual pulse generation request based on the device information. That is, virtual manager 220 may output a request to sequentially generate virtual pulses and apply them to the channels to which the memory devices included in the device information are connected. For example, after a certain time has passed since a virtual pulse was applied to a first channel, virtual manager 220 may request that a virtual pulse be applied to a second channel. Furthermore, after performing the operation, virtual manager 220 may immediately determine to discontinue application of the virtual pulses. In other words, since the memory devices have begun operating, there is no longer a need to generate virtual pulses to gradually increase total current consumption.

[0058] Furthermore, when it is determined that a plurality of memory devices suspend or end operations at the same time, the virtual manager 220 may output a virtual pulse generation request or a virtual pulse interruption request based on the chip enable signal and the command queue level.

[0059] Specifically, at least one of the plurality of memory devices may suspend operation. Whether a memory device suspends operation may be determined based on a high-state chip enable signal received from the enable signal generator 240. For example, the enable signal generator 240 may output a low-state chip enable signal to a selected memory device and output a high-state chip enable signal to a memory device whose operation has been completed or to an unselected memory device.

[0060] The virtual manager 220 may receive a command queue level of a memory device corresponding to a high-state chip enable signal. The command queue level may be determined based on the number of commands queued in the command queue. When the command queue level is not 0, the virtual manager 220 may request that a virtual pulse be applied to a channel connected to the memory device corresponding to the corresponding command queue level.

[0061] To prevent multiple memory devices from suspending operations simultaneously, the dummy manager 220 may apply dummy pulses to channels connected to the multiple memory devices and then sequentially interrupt the applied dummy pulses. For example, when memory devices connected to the first to third channels suspend operations, the dummy manager 220 may request that dummy pulses be applied to the first to third channels and then request that the application of dummy pulses be sequentially interrupted starting from the first channel.

[0062] The memory controller 200 may include a dummy pulse generator 230. The dummy pulse generator 230 may be a trigger transmitter that generates a dummy trigger and transmits the generated dummy trigger to the memory device. The dummy trigger may represent a set of dummy pulses to be applied to a channel. The trigger transmitter may generate the dummy trigger in one or more channels other than the channel used to transmit data. The trigger transmitter may generate the dummy trigger before transmitting data.

[0063] The trigger transmitter may generate a virtual trigger based on a preheat enable signal generated based on a request received from the host 300. The preheat enable signal may identify a plurality of channels coupled to a memory device on which an operation is to be performed in response to the request received from the host 300.

[0064] In an embodiment, the trigger transmitter may sequentially increase the current flowing through the input / output pins connected thereto, or sequentially apply the virtual trigger to the input / output pins to increase the number of input / output pins to which the virtual trigger is applied among the input / output pins.

[0065] In an embodiment, the virtual pulse generator 230 may generate or interrupt a virtual pulse by receiving a virtual pulse generation request or a virtual pulse interrupt request from the virtual manager 220 .

[0066] For example, when the dummy pulse generator 230 receives a dummy pulse generation request, the dummy pulse generator 230 may generate dummy pulses to be applied to the plurality of channels. Furthermore, when the dummy pulse generator 230 receives a dummy pulse interruption request, the dummy pulse generator 230 may interrupt the application of dummy pulses to the plurality of channels by suspending the generation of dummy pulses. The plurality of channels to which the dummy pulses are applied or interrupted may be channels other than the channels used to transmit data corresponding to the request received from the host.

[0067] In an embodiment, when multiple memory devices start operating simultaneously, the dummy pulse generator 230 may generate dummy pulses to be sequentially applied to the multiple channels. The dummy pulse generator 230 may adjust the degree to which the total current consumption of the multiple memory devices increases by setting the period of the dummy pulses, the level of the dummy pulses, or the time at which the dummy pulses are applied.

[0068] In an embodiment, when multiple memory devices simultaneously terminate operations, dummy pulse generator 230 may generate dummy pulses to be applied to the channels to which the memory devices terminating operations are connected, and then sequentially interrupt the dummy pulses. Similarly, dummy pulse generator 230 may adjust the degree of reduction in the total current consumption of the multiple memory devices by setting the dummy pulse period, dummy pulse level, or dummy pulse duration.

[0069] The memory controller 200 may include an enable signal generator 240. The enable signal generator 240 may generate a signal for controlling the selected memory device 100 according to an address, and transmit the generated signal through a control signal line coupled to the selected memory device 100. The control signal lines may include a chip enable line CE#, a write enable line WE#, a read enable line RE#, an address latch enable line ALE, a command latch enable line CLE, a write prevent line WP#, and a ready / busy line RB.

[0070] For example, the enable signal generator 240 can generate a chip enable signal input through the chip enable line CE#, a write enable signal input through the write enable line WE#, a read enable signal input through the read enable line RE#, an address latch enable signal input through the address latch enable line ALE, a command latch enable signal input through the command latch enable line CLE, and a write prevent signal input through the write prevent line WP#.

[0071] In an embodiment, the chip enable signal generated by the enable signal generator 240 may be a signal that enables communication between the memory controller 200 and the memory device 100. For example, when the chip enable signal is in a low state, communication between the memory controller 200 and the memory device 100 is enabled. When the chip enable signal is in a high state, communication between the memory controller 200 and the memory device 100 is disabled.

[0072] The enable signal generator 240 may generate a chip enable signal to be provided to the memory device 100 and the virtual manager 220. The memory device 100 may communicate with the memory controller 200 by receiving the chip enable signal, and the virtual manager 220 may determine whether a dummy pulse is applied to a channel connected to a plurality of memory devices by receiving the chip enable signal.

[0073] The memory controller 200 may include a command queue group 250. The command queue group 250 may include command queues respectively corresponding to a plurality of memory devices.

[0074] For example, the number of command queues in the command queue group 250 may correspond to the number of memory devices. Therefore, commands executed in each of the plurality of memory devices may be queued in the corresponding command queue. The command queue group 250 may output the number of commands queued in the command queue for the corresponding memory device in response to a request from the virtual manager 220. The number of commands queued in each command queue may be a command queue level. For example, when the number of commands queued in the command queue corresponding to a memory device is "0", the command queue level of the corresponding memory device may be "0". When the number of commands queued in the command queue corresponding to a memory device is "1", the command queue level of the corresponding memory device may be "1".

[0075] In an embodiment, the channel to which the dummy pulse is applied may be determined based on the command queue level. That is, although the memory device 100 temporarily ends an operation, when the memory device will immediately perform another operation, a dummy pulse may be applied to the channel connected to the corresponding memory device.

[0076] The memory controller 200 may include a data transmitter (not shown). The data transmitter may transmit data via a channel corresponding to a request received from the host. For example, when the request received from the host is a programming request for a first memory device among a plurality of memory devices, the data transmitter may transmit data via a first channel connected to the first memory device. The channel through which data is transmitted may be different from the channel through which the dummy pulse is applied or interrupted.

[0077] The memory controller 200 may control the overall operations of the memory device 50 .

[0078] When a power supply voltage is applied to the memory device 50, the memory controller 200 may execute firmware (FW). When the memory device 100 is a flash memory device, the memory controller 200 may execute FW such as a flash translation layer (FTL) to control communication between the host 300 and the memory device 100.

[0079] In an embodiment, the memory controller 200 may include firmware (not shown) capable of receiving data and a logical block address (LBA) from the host 300, and converting the LBA into a physical block address (PBA), which represents an address of a memory cell included in the memory device 100 where the data is to be stored. In addition, the memory controller 200 may store a logical-physical address mapping table in a buffer memory, the logical-physical address mapping table establishing a mapping relationship between the LBA and the PBA.

[0080] The memory controller 200 can control the memory device 100 to perform a program operation, a read operation, an erase operation, etc. in response to a request from the host 300. For example, when receiving a program request from the host 300, the memory controller 200 can change the program request into a program command and provide the program command, PBA, and data to the memory device 100. When receiving a read request together with an LBA from the host 300, the memory controller 200 can change the read request into a read command, select a PBA corresponding to the LBA, and then provide the read command and PBA to the memory device 100. When receiving an erase request together with an LBA from the host 300, the memory controller 200 can change the erase request into an erase command, select a PBA corresponding to the LBA, and then provide the erase command and PBA to the memory device 100.

[0081] In an embodiment, the memory controller 200 may autonomously generate a program command, an address, and data without any request from the host 300, and transmit the program command, address, and data to the memory device 100. For example, the memory controller 200 may provide commands, addresses, and data to the memory device 100 to perform background operations such as a program operation for wear leveling and a program operation for garbage collection.

[0082] In an embodiment, the memory device 50 may further include a buffer memory (not shown). The memory controller 200 may control data exchange between the host 300 and the buffer memory. Alternatively, the memory controller 200 may temporarily store system data used to control the memory device 100 in the buffer memory. For example, the memory controller 200 may temporarily store data input from the host 300 in the buffer memory and then transfer the data temporarily stored in the buffer memory to the memory device 100.

[0083] In various embodiments, the buffer memory may be used as a working memory or cache memory for the memory controller 200. The buffer memory may store codes or commands executed by the memory controller 200. Alternatively, the buffer memory may store data processed by the memory controller 200.

[0084] In an embodiment, the buffer memory may be implemented with a dynamic random access memory (DRAM) such as double data rate synchronous DRAM (DDR SDRAM), DDR4 SDRAM, low power double data rate 4 (LPDDR4) SDRAM, graphics double data rate (GDDR) SRAM, low power DDR (LPDDR) or Rambus dynamic random access memory (RDRAM), or a static random access memory (SRAM).

[0085] In various embodiments, the buffer memory may be external to the memory device 50 and coupled to the memory device 50. Thus, an externally disposed volatile memory device coupled to the memory device 50 may perform the function of the buffer memory.

[0086] In an embodiment, the memory controller 200 may control at least two memory devices. The memory controller 200 may control the memory devices according to an interleaving scheme to improve operation performance.

[0087] The host 300 may communicate with the storage device 50 using at least one of various communication protocols such as Universal Serial Bus (USB), Serial AT Attachment (SATA), High-Speed ​​Interchip (HSIC), Small Computer System Interface (SCSI), Firewire, Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD) card, MultiMediaCard (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM) and / or Load Reduced DIMM (LRDIMM).

[0088] Figure 2 It shows Figure 1 A diagram illustrating the structure of a memory device is shown.

[0089] Reference Figure 2 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic 130 .

[0090] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are coupled to a row decoder 121 via row lines RL. The plurality of memory blocks BLK1 to BLKz are coupled to a page buffer group 123 via bit lines BL1 to BLn. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells may be nonvolatile memory cells. Memory cells coupled to the same word line may be defined as a page. Therefore, a memory block may include multiple pages.

[0091] The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line.

[0092] Each memory cell included in the memory cell array 110 may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) storing four data bits.

[0093] The peripheral circuit 120 may perform a program operation, a read operation, or an erase operation on a selected region of the memory cell array 110 under the control of the control logic 130. The peripheral circuit 120 may drive the memory cell array 110. For example, the peripheral circuit 120 may apply various operating voltages to the row lines RL and the bit lines BL1 to BLn, or discharge the applied voltages under the control of the control logic 130.

[0094] The peripheral circuit 120 may include a row decoder 121 , a voltage generator 122 , a page buffer group 123 , a column decoder 124 , an input / output circuit 125 , and a sensing circuit 126 .

[0095] The row decoder 121 is coupled to the memory cell array 110 via row lines RL. The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line. In one embodiment, the word lines may include normal word lines and dummy word lines. In one embodiment, the row lines RL may further include a pipe select line.

[0096] The row decoder 121 decodes the row address RADD received from the control logic 130. The row decoder 121 selects at least one memory block from among the memory blocks BLK1 to BLKz according to the decoded address. In addition, the row decoder 121 may select at least one word line of the selected memory block according to the decoded address to apply the voltage generated by the voltage generator 122 to the at least one word line WL.

[0097] For example, in a program operation, the row decoder 121 may apply a program voltage to a selected word line and a program pass voltage having a level lower than the program voltage to unselected word lines. In a program verification operation, the row decoder 121 may apply a verification voltage to a selected word line and a verification pass voltage having a level higher than the verification voltage to unselected word lines.

[0098] In a read operation, the row decoder 121 may apply a read voltage to a selected word line and apply a read pass voltage having a level higher than the read voltage level to unselected word lines.

[0099] In an embodiment, an erase operation of the memory device 100 is performed in memory block units. In the erase operation, the row decoder 121 may select a memory block according to a decoded address. In the erase operation, the row decoder 121 may apply a ground voltage to a word line connected to the selected memory block.

[0100] The voltage generator 122 operates under the control of the control logic 130. The voltage generator 122 generates a plurality of voltages by using an external power supply voltage supplied to the memory device 100. Specifically, the voltage generator can generate various operating voltages Vop used in program operations, read operations, and erase operations in response to the operation signal OPSIG. For example, the voltage generator 122 can generate a program voltage, a verification voltage, a pass voltage, a read voltage, an erase voltage, etc. under the control of the control logic 130.

[0101] In an embodiment, the voltage generator 122 may generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as an operating voltage of the memory device 100.

[0102] In an embodiment, the voltage generator 122 may generate a plurality of voltages by using an external power supply voltage or an internal power supply voltage.

[0103] For example, the voltage generator 122 may include a plurality of pumping capacitors for receiving an internal power supply voltage, and generate a plurality of voltages by selectively activating the plurality of pumping capacitors under the control of the control logic 130 .

[0104] The row decoder 121 may supply a plurality of generated voltages to the memory cell array 110 .

[0105] The page buffer group 123 includes first to nth page buffers PB1 to PBn, which are connected to the memory cell array 110 via first to nth bit lines BL1 to BLn, respectively. The first to nth bit lines BL1 to BLn operate under the control of the control logic 130. Specifically, the first to nth bit lines BL1 to BLn can operate in response to the page buffer control signal PBSIGNALS. For example, the first to nth page buffers PB1 to PBn can temporarily store data received via the first to nth bit lines BL1 to BLn, or sense the voltage or current of the bit lines BL1 to BLn during a read operation or a verify operation.

[0106] Specifically, during a program operation, when a program voltage is applied to a selected word line, the first to nth page buffers PB1 to PBn can transmit data DATA received through the input / output circuit 125 to the selected memory cells through the first to nth bit lines BL1 to BLn. Based on the transmitted data DATA, the memory cells of the selected page are programmed. During a program verification operation, the first to nth page buffers PB1 to PBn read page data by sensing the voltage or current received from the selected memory cells through the first to nth bit lines BL1 to BLn.

[0107] In a read operation, the first to nth page buffers PB1 to PBn read data DATA from memory cells of a selected page through the first to nth bit lines BL1 to BLn and output the read data DATA to the input / output circuit 125 under the control of the column decoder 124 .

[0108] In an erase operation, the first to nth page buffers PB1 to PBn may float the first to nth bit lines BL1 to BLn or apply an erase voltage.

[0109] The column decoder 124 may communicate data between the input / output circuit 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 may communicate data with the first to nth page buffers PB1 to PBn through the data lines DL or with the input / output circuit 125 through the column lines CL.

[0110] The input / output circuit 125 may transfer a command CMD and an address ADDR received from the memory controller 200 to the control logic 130 or exchange data DATA with the column decoder 124 .

[0111] In a read operation or a verification operation, the sensing circuit 126 may generate a reference current in response to the enable bit VRYBIT signal and output a pass signal PASS or a fail signal FAIL by comparing the sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current.

[0112] The control logic 130 can control the peripheral circuit 120 by outputting an operation signal OPSIG, a row address RADD, a page buffer control signal PBSIGNALS, and an enable bit VRYBIT in response to a command CMD and an address ADDR. For example, the control logic 130 can control a read operation of a selected memory block in response to a sub-block read command and address. In addition, the control logic 130 can control an erase operation of a selected sub-block included in a selected memory block in response to a sub-block erase command and address. In addition, the control logic 130 can determine whether a verification operation has passed or failed in response to a pass signal PASS or a fail signal FAIL.

[0113] Each memory cell included in the memory cell array 110 may be programmed to a program state among a plurality of program states according to data stored therein. A target program state of the memory cell may be determined to be one of the plurality of program states according to data stored therein.

[0114] Figure 3 is a diagram illustrating a memory block.

[0115] Reference Figure 2 and Figure 3 , Figure 3 It is shown that Figure 2 1 is a circuit diagram of a memory block BLKa among a plurality of memory blocks BLK1 to BLKz in the memory cell array 110 .

[0116] In the memory block BLKa, the first selection line, the word line, and the second selection line arranged in parallel may be connected to each other. For example, the word line may be arranged in parallel between the first selection line and the second selection line. The first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL.

[0117] More specifically, the memory block BLKa may include a plurality of strings coupled between bit lines BL1 to BLn and a source line SL. The bit lines BL1 to BLn may be coupled to these strings individually, and the source line SL may be coupled to these strings in common. The strings may be configured identically to one another, and thus, the string ST coupled to the first bit line BL1 will be described in detail as an example.

[0118] The string ST may include a source select transistor SST, a plurality of memory cells F1 to F16, and a drain select transistor DST, which are connected in series between a source line SL and a first bit line BL1. At least one source select transistor SST and at least one drain select transistor DST may be included in one string ST, and more than 16 memory cells (F1 to F16) shown in the figure may be included in one string ST.

[0119] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. The memory cells F1 to F16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings can be commonly connected to the source select line SSL, and the gates of the drain select transistors DST included in different strings can be commonly connected to the drain select line DSL. The gates of the memory cells F1 to F16 can be respectively connected to a plurality of word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different strings can be referred to as a physical page PPG. Therefore, a physical page corresponding to the number of word lines WL1 to WL16 can be included in the memory block BLKa.

[0120] A memory cell can store one bit of data. Memory cells are often referred to as single-level cells (SLCs). A physical page PPG can store one logical page (LPG) of data. An LPG can include many data bits, with the number of data bits corresponding to the number of cells included in a physical page PPG. Alternatively, a memory cell MC can store two or more bits of data. Memory cells are often referred to as multi-level cells (MLCs). A physical page PPG can store two or more LPGs of data.

[0121] Memory cells for storing two or more bits of data are generally referred to as MLCs. As memory cells with higher storage capacities have been developed, the term MLC has taken on a more specific meaning, referring to memory cells for storing two bits of data. In this case, a memory cell for storing three or more bits of data is referred to as a triple-level cell (TLC), and a memory cell for storing four or more bits of data is referred to as a quad-level cell (QLC). Embodiments of the present invention can be applied to a memory system having memory cells in which each cell stores two or more bits of data.

[0122] In another embodiment, each of the plurality of memory blocks may have a three-dimensional structure. Each memory block may include a plurality of memory cells stacked on a substrate. The plurality of memory cells may be arranged along +X, +Y, and +Z directions.

[0123] Figure 4 is a diagram illustrating an embodiment of a plurality of memory devices coupled to a memory controller via a plurality of channels, respectively.

[0124] Reference Figure 4 , Figure 4 shows a circuit coupled to the memory controller 200. Figure 1 The storage device 50 shown is a plurality of memory devices. Figure 4 In the embodiment of the present invention, there are four memory devices, namely the first memory device 100_1 to the fourth memory device 100_4, but the present invention is not limited to this number. In the embodiment of multiple memory devices, the storage device 50 can include any appropriate number of memory devices.

[0125] In the illustrated embodiment, the memory controller 200 may be coupled to the first memory device 100_1 through a first channel CH1 , to the second memory device 100_2 through a second channel CH2 , to the third memory device 100_3 through a third channel CH3 , and to the fourth memory device 100_4 through a fourth channel CH4 .

[0126] In an embodiment, each of the first to fourth channels CH1 to CH4 may include not only a channel for transmitting data from ( Figure 1The host 300 also includes a channel for applying or interrupting a virtual trigger.

[0127] The memory controller 200 can generate the same Figure 1 The host 300 generates a command corresponding to a request received by the host 300 (as shown), and outputs the generated command to one of the first to fourth memory devices 100_1 to 100_4. The request received from the host 300 may be a program request, a read request, or an erase request for one of the first to fourth memory devices 100_1 to 100_4.

[0128] For example, when the request received from the host 300 is a read request for the first memory device 100_1, the memory controller 200 may generate a command corresponding to the read request and output the generated command to the first memory device 100_1 through the first channel CH1. In addition to the command corresponding to the read request, the memory controller 200 may also output an address corresponding to the read request to the first memory device 100_1 through the first channel CH1.

[0129] When the request received from the host 300 is a program request for the second memory device 100_2, the memory controller 200 may generate a command corresponding to the program request and output the generated command to the second memory device 100_2 through the second channel CH2. The memory controller 200 may also output an address and data corresponding to the program request to the second memory device 100_2 through the second channel CH2.

[0130] As described above, the memory controller 200 can generate commands, addresses, and / or data corresponding to requests received from the host 300. When the corresponding request is directed to the first memory device 100_1, the memory controller 200 can output the generated commands, generated addresses, and / or generated data via the first channel CH1. When the corresponding request is directed to the second memory device 100_2, the memory controller 200 can output the generated commands, generated addresses, and / or generated data via the second channel CH2. When the corresponding request is directed to the third memory device 100_3, the memory controller 200 can output the generated commands, generated addresses, and / or generated data via the third channel CH3. When the corresponding request is directed to the fourth memory device 100_4, the memory controller 200 can output the generated commands, generated addresses, and / or generated data via the fourth channel CH4.

[0131] Therefore, the memory controller 200 can communicate with multiple memory devices through multiple channels.

[0132] In an embodiment, when each of the plurality of memory devices performs an operation corresponding to a command received via a channel, current may be consumed. In particular, when the plurality of memory devices simultaneously start or end operations, the total current consumption of the plurality of memory devices may rapidly increase or decrease. When the total current consumption rapidly increases or decreases, noise may occur in the voltage source, and thus, operational reliability may be reduced.

[0133] Therefore, embodiments of the present disclosure provide a method for sequentially applying dummy pulses to channels when the first to fourth memory devices 100_1 to 100_4 simultaneously start operating. Furthermore, embodiments of the present disclosure provide a method for sequentially applying dummy pulses to channels when the first to fourth memory devices 100_1 to 100_4 simultaneously end operating and then sequentially interrupting the dummy pulses.

[0134] Figure 5 is a diagram illustrating another embodiment of a memory device coupled to multiple channels.

[0135] and Figure 4 Similar arrangement as shown, in Figure 5 In the embodiment, a plurality of memory devices (in this case, the first to eighth memory devices 100_1 to 100_8) may be coupled to the memory controller 200 through a plurality of channels. Figure 4 shows a structure where one memory device is connected to one channel, and Figure 5 A structure in which two memory devices are coupled to one channel is shown. In another embodiment, three or more memory devices may be coupled to one channel.

[0136] In an embodiment, first memory device 100_1 and second memory device 100_2 are coupled to first channel CH1 via first and second paths WAY1 and WAY2, respectively. Furthermore, third memory device 100_3 and fourth memory device 100_4 are coupled to second channel CH2 via third and fourth paths WAY3 and WAY4, respectively.

[0137] In an embodiment, the fifth and sixth memory devices 100_5 and 100_6 are coupled to the third channel CH3 via fifth and sixth paths WAY5 and WAY6, respectively. Furthermore, the seventh and eighth memory devices 100_7 and 100_8 are coupled to the fourth channel CH4 via seventh and eighth paths WAY7 and WAY8, respectively.

[0138] In an embodiment, each of the first to fourth channels CH1 to CH4 may include not only a channel for transmitting data received from the host 300 , but also a channel for applying or interrupting a virtual trigger.

[0139] In an embodiment, the memory controller 200 may generate a command corresponding to a request received from the host 300 and output the generated command to any one of the first to eighth memory devices 100_1 to 100_8. The request received from the host 300 may be a program request, a read request, or an erase request for any one of the first to eighth memory devices 100_1 to 100_8.

[0140] For example, when the request received from the host 300 is a read request for the first memory device 100_1, the memory controller 200 may generate a command corresponding to the read request and output the generated command to the first memory device 100_1 through the first channel CH1. In addition to the command corresponding to the read request, the memory controller 200 may also output an address corresponding to the read request to the first memory device 100_1 through the first channel CH1.

[0141] When the request received from the host 300 is a program request for the second memory device 100_2, the memory controller 200 may generate a command corresponding to the program request and output the generated command to the second memory device 100_2 through the first channel CH1. The memory controller 200 may also output an address and data corresponding to the program request to the second memory device 100_2 through the first channel CH1.

[0142] As described above, when the request received from the host 300 is for the first memory device 100_1 or the second memory device 100_2, the memory controller 200 may output a command, address, and / or data corresponding to the request from the host 300 to the first memory device 100_1 or the second memory device 100_2 through the first channel CH1. Furthermore, when the request received from the host 300 is for the third memory device 100_3 or the fourth memory device 100_4, the memory controller 200 may output a command, address, and / or data corresponding to the request from the host 300 to the third memory device 100_3 or the fourth memory device 100_4 through the second channel CH2.

[0143] In an embodiment, when the request received from the host 300 is for the fifth memory device 100_5 or the sixth memory device 100_6, the memory controller 200 may output a command, address, and / or data corresponding to the request from the host 300 to the fifth memory device 100_5 or the sixth memory device 100_6 via the third channel CH3. Furthermore, when the request received from the host 300 is for the seventh memory device 100_7 or the eighth memory device 100_8, the memory controller 200 may output a command, address, and / or data corresponding to the request from the host 300 to the seventh memory device 100_7 or the eighth memory device 100_8 via the fourth channel CH4.

[0144] Therefore, as in Figure 4 In the arrangement shown, Figure 5 In an arrangement, the memory controller 200 can communicate with multiple memory devices through multiple channels.

[0145] In an embodiment, when each of the multiple memory devices performs an operation corresponding to a command received via a channel, current may be consumed. In particular, when the multiple memory devices simultaneously start or end operations, the total current consumption of the multiple memory devices may rapidly increase or decrease. When the total current consumption rapidly increases or decreases, noise may occur in the voltage source, and thus, operational reliability may be degraded.

[0146] According to an embodiment of the present disclosure, to prevent a rapid change in total current consumption, the memory controller 200 may apply dummy pulses to channels before a plurality of memory devices start operating, or apply dummy pulses to channels when a memory device ends operating, and then sequentially interrupt the dummy pulses.

[0147] Figure 6 is a graph showing changes in total current consumption and noise of a voltage source when memory devices connected to a plurality of channels start or end operations at the same time.

[0148] Reference Figure 6 , the horizontal axis represents time t, and the vertical axis represents the total current consumption I_TOT of the plurality of memory devices and the voltage source Vsource applied to the plurality of memory devices. In this example, the voltage source Vsource applied to the plurality of memory devices is V1.

[0149] In an embodiment, each of a plurality of memory devices coupled to a memory controller through a plurality of channels may perform an operation corresponding to a command received from the memory controller. The plurality of memory devices may perform the operation simultaneously or at different times.

[0150] Figure 6Shown are the total current consumption I_TOT and the voltage source Vsource when a plurality of memory devices simultaneously perform operations.

[0151] Reference Figure 6 , the voltage applied to multiple memory devices can be kept constant. However, when multiple memory devices start or end operations at the same time, noise may appear in the voltage source.

[0152] For example, at t1, multiple memory devices may begin operating simultaneously. Therefore, at t1, the total current consumption I_TOT of the multiple memory devices may rapidly increase from Ia to I1. Noise may occur in the voltage source Vsource, causing the voltage source to decrease and then return to V1. The presence of noise in the voltage source Vsource may cause the multiple memory devices to perform abnormally.

[0153] Subsequently, at t2, the multiple memory devices may simultaneously terminate their operations. Therefore, at t2, the total current consumption I_TOT of the multiple memory devices may rapidly decrease from I1 to Ia. Noise may occur in the voltage source Vsource, causing the voltage source Vsource to increase and return to V1. Furthermore, the presence of noise in the voltage source Vsource may cause the multiple memory devices to perform abnormally.

[0154] Therefore, when multiple memory devices operate simultaneously, the total current consumption I_TOT may change rapidly, and noise may appear in the voltage source Vsource. The noise in the voltage source Vsource may cause the multiple memory devices to operate abnormally; therefore, it is necessary to prevent the total current consumption I_TOT from changing rapidly.

[0155] Therefore, in order to prevent noise from occurring in the voltage source Vsource, operations to be performed on multiple memory devices can be delayed and performed later than they would otherwise be performed, or the operations can be performed simultaneously after applying a dummy pulse to the memory devices on which the operations are to be performed among the multiple memory devices.

[0156] When operations to be performed by multiple memory devices are delayed and executed later, the memory devices can be controlled to perform their operations sequentially. That is, after one memory device completes an operation, another memory device begins operating until all memory devices have completed their respective operations. However, with this serial approach, the overall program time may be extended. As a result, program performance may be reduced. In other words, a delay corresponding to the delayed time may occur.

[0157] Therefore, embodiments of the present disclosure provide a method for applying a dummy pulse to a channel coupled to a memory controller and a plurality of memory devices, or interrupting a dummy pulse in a channel coupled to a memory controller and a plurality of memory devices, to prevent a total current consumption I_TOT from changing rapidly.

[0158] According to an embodiment of the present disclosure, memory devices do not delay and perform operations but simultaneously perform operations after applying a dummy pulse to the memory devices, so that data can be quickly transferred or a signal can be quickly transmitted.

[0159] Figure 7 is a graph showing changes in total current consumption and voltage source noise when a plurality of memory devices simultaneously end operations while performing operations.

[0160] Reference Figure 7 , the horizontal axis represents time t, and the vertical axis represents the total current consumption I_TOT of the plurality of memory devices and the voltage source Vsource applied to the plurality of memory devices. In this example, the voltage source Vsource applied to the plurality of memory devices is V3.

[0161] Reference Figure 6 and Figure 7 , Figure 6 shows the total current consumption I_TOT and the voltage source Vsource when multiple memory devices start or end operations at the same time, and Figure 7 1 shows the total current consumption I_TOT and the voltage source Vsource when a plurality of memory devices suspend or end operations at the same time and then start operating again. Here, the plurality of memory devices start operating at different times.

[0162] exist Figure 7 , a case where the memory controller is coupled to a first memory device via a first channel and to a second memory device via a second channel is shown.

[0163] In an embodiment, at t3, the first memory device may begin operating. Therefore, the total current consumption I_TOT may increase from Ia to I2. That is, the total current consumption I_TOT when the first memory device is operating may be I2. Since the total current consumption I_TOT does not increase rapidly, the voltage source Vsource may remain at V3.

[0164] Subsequently, at t4, the second memory device may begin operating. Therefore, the total current consumption I_TOT may increase from I2 to I3. When the first memory device begins operating at t3, the total current consumption I_TOT increases to I2. However, since the additional increase in total current consumption I_TOT to I3 at t4 does not increase rapidly when the second memory device begins operating, the voltage source Vsource may remain at V3.

[0165] From t4 to t5, both the first memory device and the second memory device are performing operations. Therefore, the total current consumption I_TOT may be I3, and the voltage source Vsource may be V3.

[0166] Subsequently, at t5, both the first memory device and the second memory device may terminate operations. That is, the first memory device and the second memory device may have an idle period or interval (t5 to t6) during which the first memory device and the second memory device temporarily terminate (or suspend) operations. Since the first memory device and the second memory device terminate operations at the same time, when the first memory device and the second memory device simultaneously start (or resume) operations, the total current consumption I_TOT may decrease rapidly and then increase rapidly again.

[0167] Therefore, during the interval t5 to t6, noise may occur in the voltage source Vsource. That is, from t5 to t6, when the total current consumption I_TOT decreases rapidly, the voltage source Vsource may increase. When the total current consumption I_TOT increases rapidly, the voltage source Vsource may decrease and then become V3 again.

[0168] Therefore, from t5 to t6, when the total current consumption I_TOT changes, noise may appear in the voltage source.

[0169] In an embodiment, both the first memory device and the second memory device may end their operations and then resume operations at t6, and continue to perform operations after t6 until t7. That is, the first memory device and the second memory device may have another idle period from t7 to t8. As in the interval t5 to t6, noise may occur in the voltage source Vsource during the interval t7 to t8, as a result of a rapid decrease and subsequent rapid increase in the total current consumption I_TOT.

[0170] Subsequently, at t9, the first memory device may end the operation. As a result, the total current consumption I_TOT may decrease from I3 to I4. That is, the total current consumption I_TOT when the second memory device performs the operation alone may be I4. Since the total current consumption I_TOT does not decrease rapidly, the voltage source Vsource may remain at V3.

[0171] At t10, the second memory device may also end the operation. Therefore, the total current consumption I_TOT may decrease from I4 to Ia. Similar to t9, since the total current consumption does not decrease rapidly, the voltage source Vsource may remain at V3.

[0172] Therefore, when the total current consumption I_TOT decreases or increases rapidly, noise may occur in the voltage source Vsource, which in turn may cause errors in the operations performed by the memory devices during this period. Therefore, it is necessary to ensure that multiple memory devices perform operations reliably.

[0173] Therefore, embodiments of the present disclosure provide a method of applying a dummy pulse through a channel or interrupting the dummy pulse so applied to prevent noise from occurring in a voltage source Vsource. The following describes operations for preventing or minimizing the occurrence of noise in the voltage source Vsource.

[0174] Figure 8 It shows Figure 1 FIG. 1 is a diagram illustrating the structure of a memory controller that applies a dummy pulse to each channel.

[0175] Reference Figure 8 , Figure 8 The memory controller 200 shown may include a request checker 210, a virtual manager 220, and a virtual pulse generator 230. The memory controller 200 may also include an enable signal generator 240 and a command queue group 250 (both in Figure 1 ), but for clarity, it is shown in Figure 8 Omitted in .

[0176] By way of example, in Figure 8 It is shown in ( Figure 1 The memory devices 100 in the memory device 50 shown in FIG. 1 are arranged with first to fourth memory devices 100_1 to 100_4. The first to fourth memory devices 100_1 to 100_4 may be coupled to the memory controller 200 through first to fourth channels CH1 to CH4, respectively.

[0177] Therefore, according to an embodiment of the present disclosure, dummy pulses can be applied to the first to fourth memory devices 100_1 to 100_4 through the first to fourth channels CH1 to CH4. The dummy pulses can be input to the first to fourth channels CH1 to CH4 through input / output pins (IO pins) of the memory devices or through general-purpose input / output pins (GPIO pins).

[0178] In an embodiment, each of the first to fourth channels CH1 to CH4 may include not only a channel for transmitting data received from the host 300 , but also a channel for applying or interrupting a virtual trigger.

[0179] In another embodiment, the storage device 50 may include Figure 8 The number of memory devices shown may be small or large.

[0180] Although not shown in the drawing, the dummy pulse may be generated by internal elements respectively included in the first to fourth memory devices 100_1 to 100_4 instead of the memory controller 200. That is, the total current consumption of the memory devices may be sequentially increased or decreased by such internal elements.

[0181] exist Figure 8 , an example of generating a dummy pulse by the dummy pulse generator 230 in the memory controller 200 is shown.

[0182] In an embodiment, the request checker 210 may receive a request (REQUEST) from the host 300. The request received from the host 300 may be a program request, a read request, or an erase request. The request received from the host 300 may be a request for any one of the first to fourth memory devices 100_1 to 100_4.

[0183] The request checker 210 can check which memory device among the first to fourth memory devices 100_1 to 100_4 the received request is for. That is, the request checker 210 can identify which memory device among the first to fourth memory devices 100_1 to 100_4 has started operating based on the request received from the host 300. Subsequently, the request checker 210 can generate device information DEVICE_INF including information identifying the memory device that has started operating, and provide the generated device information to the virtual manager 220.

[0184] In an embodiment, the request checker 210 may provide a preheat enable signal to the virtual manager 220 along with or in place of the device information DEVICE_INF. The preheat enable signal may indicate which channels and how many channels are connected to the memory device starting to operate among the first to fourth memory devices 100_1. In other words, the preheat enable signal may indicate the number of memory devices on which the operation is to be performed, the channels connected to the corresponding memory device, and the number of channels.

[0185] In an embodiment, the request checker 210 may identify a memory device that starts operating based on a request received from the host 300 and then output a preheat enable signal.

[0186] Therefore, in order to provide the virtual manager 220 with information about the memory device starting to operate, the request checker 210 may output a preheat enable signal together with or instead of the device information DEVICE_INF.

[0187] In an embodiment, the virtual manager 220 may output a virtual pulse generation request DPGE_REQ to the virtual pulse generator 230 based on the device information DEVICE_INF and / or the preheat enable signal received from the request checker 210. That is, the virtual manager 220 may control the current to be applied to the channel connected to the memory device that has started operating. The device information DEVICE_INF and the preheat enable signal may indicate two or more memory devices that have started operating.

[0188] Specifically, when the device information DEVICE_INF and / or the preheat enable signal indicate that only one memory device is operating, the virtual manager 220 may not operate to apply current control. However, when the device information DEVICE_INF and / or the preheat enable signal indicate that two or more memory devices are operating, the virtual manager 220 may control the current to be applied to the channels before the memory devices connected to these channels start operating.

[0189] In an example, information indicating that the first memory device 100_1 and the second memory device 100_2 connected to the channels CH1 and CH2, respectively, are about to start operating may be included in the device information DEVICE_INF or the preheat enable signal and may be output. The virtual manager 220 may output a dummy pulse generation request DPGE_REQ for requesting that dummy pulses be sequentially applied to the first channel CH1 and the second channel CH2 based on the device information DEVICE_INF or the preheat enable signal.

[0190] Based on the dummy pulse generation request DPGE_REQ, the dummy pulse generator 230 may generate a dummy pulse before the first memory device 100_1 and the second memory device 100_2 begin operating, and apply the dummy pulse to the first channel CH1 connected to the first memory device 100_1 or the second channel CH2 connected to the second memory device 100_2. That is, the dummy pulse generator 230 may first apply the dummy pulse to one of the two channels connected to the two memory devices that have begun operating. Subsequently, after a set time has passed since the dummy pulse was first applied to one channel, the dummy pulse generator 230 may apply the dummy pulse to another channel associated with the other memory device.

[0191] In another example, information indicating that the first to fourth memory devices 100_1 to 100_4, respectively coupled to the four channels CH1 to CH4, are about to start operating may be included in the device information DEVICE_INF or the preheat enable signal and may be output. The virtual manager 220 may output a dummy pulse generation request DPGE_REQ for requesting that dummy pulses be sequentially applied to the first to fourth channels CH1 to CH4 based on the device information DEVICE_INF or the preheat enable signal.

[0192] Based on the dummy pulse generation request DPGE_REQ, the dummy pulse generator 230 may generate a dummy pulse before the first to fourth memory devices 100_1 to 100_4 begin operation, and apply the dummy pulse to the first channel CH1, the second channel CH2, the third channel CH3, or the fourth channel CH4. That is, the dummy pulse generator 230 may apply the dummy pulse to one of the four channels connected to the memory device that begins operation. Subsequently, after a set time has passed since the previous application of the dummy pulse, the dummy pulse generator 230 may apply the dummy pulse to a channel connected to one of the remaining memory devices. Thus, the dummy pulses may be sequentially applied to the channels associated with the memory devices that are performing operations.

[0193] Sequentially applying the dummy pulses as described above prevents instantaneous changes in the total current consumption of the memory device and prevents noise from occurring in the system.

[0194] In another embodiment, the memory controller 200 does not receive the request REQUEST from the host 300. Instead, the memory controller 200 may autonomously generate a dummy pulse and apply the dummy pulse to the first to fourth channels CH1 to CH4. That is, before the first to fourth memory devices 100_1 to 100_4 begin operating, the memory controller 200 may autonomously generate a dummy pulse and apply the dummy pulse to each channel.

[0195] For example, when an operation of any of the first to fourth memory devices 100_1 to 100_4 is required based on an internal operation of the memory device 200, such as garbage collection (GC), the memory controller 200 may autonomously generate a dummy pulse and apply the dummy pulse to the channel. Therefore, the memory controller 200 may autonomously generate a dummy pulse even without receiving a request REQUEST from the host 300.

[0196] Figure 9 is a diagram illustrating a method for sequentially increasing and decreasing the total current consumption.

[0197] Reference Figure 8 and Figure 9 , Figure 9 FIG. 2 shows that after information indicating that the first to fourth memory devices 100_1 to 100_4 will start operating is included in the device information DEVICE_INF or the preheat enable signal, and based on the device information DEVICE_INF or the preheat enable signal, the virtual manager 220 outputs a virtual pulse generation request for requesting that virtual pulses be sequentially applied to the first to fourth channels CH1 to CH4 respectively connected to the first to fourth memory devices 100_1 to 100_4, according to ( Figure 8 ) channel currents I_CH1 to I_CH4 and a total current consumption I_TOT of the operation of the virtual pulse generator 230.

[0198] In an embodiment, when it is determined that the first to fourth memory devices are to begin operation, a dummy pulse may be applied to one channel connected to one of the memory devices at t11, which may be the first channel, the second channel, the third channel, or the fourth channel. Here, by way of example, the dummy pulse is first applied to the first channel.

[0199] At t11, when a dummy pulse is applied to the first channel, the first channel current I_CH1 may increase to the dummy current I_DUMMY. Therefore, the total current consumption I_TOT may also increase.

[0200] Subsequently, at t12, a dummy pulse may be applied to one of the remaining channels connected to the first to fourth memory devices 100_1 to 100_4. t12 may occur a set time after t11. Here, by way of example, the channel is the second channel.

[0201] At t12, when a dummy pulse is applied to the second channel, the second channel current I_CH2 may increase to the dummy current I_DUMMY. Therefore, the total current consumption I_TOT may also increase.

[0202] Subsequently, dummy pulses may be sequentially applied to the remaining channels. For example, at t13, a dummy pulse may be applied to the third channel, causing the third channel current I_CH3 to become the dummy current I_DUMMY. At t14, which may occur a set amount of time after t13, a dummy pulse may be applied to the fourth channel, causing the fourth channel current I_CH4 to become the dummy current I_DUMMY.

[0203] That is, the virtual manager ( Figure 8 As shown in 220), the total current consumption I_TOT can be sequentially increased by determining the set time and the channel to which the dummy pulse will be applied. In addition, the total current consumption I_TOT can be sequentially increased by adjusting the level of the dummy pulse or the duration of the dummy pulse.

[0204] Refer to the following Figure 10 A method of sequentially increasing the total current consumption I_TOT by adjusting the level of the dummy pulse is described.

[0205] Therefore, the total current consumption I_TOT can be sequentially increased from t11 to t14. When the sequentially increasing current reaches a certain level, the memory devices that are determined to perform an operation can perform their respective operations. That is, after t15, the memory devices can perform their respective operations. Here, after performing their respective operations, the virtual manager 220 can immediately determine to interrupt the application of the dummy pulse. In other words, since the memory devices have begun operating, there is no longer a need to generate dummy pulses to gradually increase the total current consumption.

[0206] Therefore, when the total current consumption I_TOT sequentially increases, noise may not occur in the voltage source Vsource. Therefore, the dummy pulse generator 230 sequentially applies dummy pulses to the channels so that reliability of operations performed by the memory device can be ensured.

[0207] It can be confirmed that after the first to fourth memory devices perform the operations, the first to fourth memory devices all end the operations.

[0208] When the first to fourth memory devices simultaneously terminate operations, the total current consumption I_TOT of the memory devices can be rapidly reduced. Therefore, dummy pulses can be applied to the first to fourth channels connected to the first to fourth memory devices, respectively. Subsequently, the dummy pulses applied to the respective channels can be sequentially interrupted. That is, after the application of the dummy pulses is interrupted, dummy pulses are applied to the respective channels connected to the first to fourth memory devices.

[0209] For example, at t16, when it is determined that the first to fourth memory devices do not operate, dummy pulses may be applied to the first to fourth channels. That is, at t16, the first to fourth channel currents I_CH1 to I_CH4 may become dummy currents I_DUMMY.

[0210] Subsequently, at t17, which may occur a set amount of time after t16, the dummy pulse generator 230 may interrupt the dummy pulse applied to one of the channels, which may be the first channel, the second channel, the third channel, or the fourth channel. Here, by way of example, the dummy pulse in the first channel is interrupted at t16.

[0211] At t17, when the application of the dummy pulse to the first channel ends, the first channel current I_CH1 may decrease. Therefore, the total current consumption I_TOT may also decrease.

[0212] Subsequently, at t18, the dummy pulse applied to the second channel coupled to the second memory device may be interrupted. t18 may occur a set amount of time after t17. More generally, at t18, the channel whose dummy pulse is interrupted may be any of the channels whose dummy pulse has not yet been interrupted.

[0213] At t18, when the dummy pulse of the second channel is interrupted, the second channel current I_CH2 may decrease. Therefore, the total current consumption I_TOT may also decrease.

[0214] Subsequently, the dummy pulses may be sequentially interrupted in the other channels. For example, at t19, which may occur a set amount of time after t18, the dummy pulses applied to the third channel may be interrupted. At t20, which may occur a set amount of time after t19, the dummy pulses applied to the fourth channel may be interrupted.

[0215] Therefore, the total current consumption I_TOT can be sequentially reduced from t17 to t20. Therefore, when the total current consumption I_TOT is sequentially reduced, noise may not occur in the voltage source Vsource. Therefore, the dummy pulses applied to the channels are sequentially interrupted, so that the reliability of the operation performed by the memory device can be ensured.

[0216] Figure 10 is a diagram illustrating another embodiment of sequentially increasing and decreasing the total current consumption.

[0217] Reference Figure 8 、 Figure 9 and Figure 10 , Figure 10 Shown from Figure 9 The illustrated embodiment of applying more subdivided dummy pulses is shown from t11 to t14. Figure 10 The first to fourth memory devices ( Figure 8 100_1 to 100_4 shown in the figure include information that the operation will start in the device information, and based on the device information, the virtual manager 220 outputs a virtual pulse generation request for requesting that virtual pulses be sequentially applied to the first channel CH1 to the fourth channel CH4 respectively connected to the first memory device 100_1 to the fourth memory device 100_4, and then the channel currents I_CH1 to I_CH4 and the total current consumption according to the operation of the virtual pulse generator 230.

[0218] In the description Figure 10 When omitting the combined Figure 9 The content of the description.

[0219] In an embodiment, the virtual manager 220 may determine that a virtual pulse is to be first applied to a first channel connected to a first memory device among the first to fourth memory devices. The virtual pulse generator 230 may generate the virtual pulses in a step-by-step manner. The virtual pulse generator 230 may generate the virtual pulses by adjusting the levels of the virtual pulses. Thus, the virtual pulse generator 230 may generate the virtual pulses such that the total current consumption gradually increases.

[0220] For example, at t11a, the dummy pulse generator 230 may generate a dummy pulse and apply the dummy pulse to the first channel, and the first channel current I_CH1 may become the step current I_STEP. Subsequently, at t11, the dummy pulse generator may generate a dummy pulse having a higher level than the previous dummy pulse and apply the dummy pulse to the first channel, and the first channel current I_CH1 may become the dummy current I_DUMMY.

[0221] and Figure 9 Similar to the arrangement in Figure 10 In the arrangement of , the dummy pulse generator 230 applies a dummy pulse through the first channel, and the first channel current I_CH1 becomes the dummy current I_DUMMY. However, in Figure 10 In the arrangement of FIG. 1 , the dummy pulse generator 230 applies pulses having different levels to the first channel so that a variation in total current consumption can be minimized.

[0222] The dummy pulses may also be applied stepwise to the second to fourth channels.

[0223] For example, after the reference time has passed, at t12a, by applying a dummy pulse to the second channel, the second channel current I_CH2 may become a step current I_STEP. At t12, by applying a dummy pulse having a higher level than the previous dummy pulse to the second channel, the second channel current I_CH2 may become a dummy current I_DUMMY.

[0224] In addition, after the reference time has passed, at t13a, by applying a dummy pulse to the third channel, the third channel current I_CH3 can become a step current I_STEP. At t13, by applying a dummy pulse having a higher level than the previous dummy pulse to the third channel, the third channel current I_CH3 can become a dummy current I_DUMMY.

[0225] Finally, at t14a, the fourth channel current I_CH4 may become a step current I_STEP by applying a dummy pulse to the fourth channel. At t14, the fourth channel current I_CH4 may become a dummy current I_DUMMY by applying a dummy pulse having a higher level than the previous dummy pulse to the fourth channel.

[0226] Therefore, the dummy pulses applied to the first to fourth channels are subdivided, so that the total current consumption can be increased more gradually. Therefore, noise is less likely to occur in the voltage source, thereby improving the reliability of operations performed by the memory device.

[0227] The above method can also be applied when the dummy pulses applied to each channel are sequentially interrupted. That is, the dummy pulses interrupted for each channel are subdivided to more gradually reduce the total current consumption. This reduces the likelihood of noise in the voltage source, ensuring the reliability of the memory device's operations.

[0228] Figure 11 is shown to sequentially reduce the total current consumption Figure 1 A diagram of the structure of the memory controller is shown.

[0229] Reference Figure 11 , Figure 11 The memory controller 200 shown may include a virtual manager 220, a virtual pulse generator 230, an enable signal generator 240, and a command queue group 250. The memory controller 200 may also include Figure 1 A request inspector 210 is shown, but such component is omitted here for clarity.

[0230] Figure 11 A method of interrupting a dummy pulse when it is determined that at least one memory device among the first to fourth memory devices 100_1 to 100_4 has ended or suspended execution of an operation is shown.

[0231] In an embodiment, each of the first to fourth channels CH1 to CH4 may include not only a channel for transmitting data received from the host 300 , but also a channel for applying or interrupting a virtual trigger.

[0232] In an embodiment, the enable signal generator 240 may generate a chip enable signal CE_SIG corresponding to the physical block address PBA and output the generated chip enable signal CE_SIG to the selected memory device and the virtual manager 220. The chip enable signal CE_SIG may be used to select a memory device on which an operation is to be performed or to release the selection. The chip enable signal CE_SIG may be in a high state or a low state. When the chip enable signal CE_SIG is in a high state, the selection of the memory device may be released. When the chip enable signal CE_SIG is in a low state, the memory device may be selected. In other words, the chip enable signal CE_SIG in a high state may be input to a memory device in a standby state, and the chip enable signal CE_SIG in a low state may be input to a memory device in operation.

[0233] For example, when the first memory device 100_1 is to end operation, the enable signal generator 240 may generate a high chip enable signal CE_SIG that releases selection of the first memory device 100_1 and provide the generated chip enable signal CE_SIG to the virtual manager 220 .

[0234] The virtual manager 220 may determine whether a high state chip enable signal CE_SIG corresponding to at least two memory devices has been received in response to the chip enable signal CE_SIG received from the enable signal generator 240 .

[0235] When the virtual manager 220 receives a high-state chip enable signal CE_SIG corresponding to two or more memory devices, the virtual manager 220 may output a command queue level request CMDQL_REQ to the command queue group 250 for checking the command queue level CMDQL of the corresponding memory device. The command queue level CMDQL may indicate the number of commands queued in the command queue. That is, when the number of queued commands is "0", the command queue level CMDQL may be "0". When the number of queued commands is "5", the command queue level CMDQL may be "5".

[0236] The command queue group 250 may output a command queue level CMDQL corresponding to a corresponding memory device to the virtual manager 220 in response to a command queue level request CMDQL_REQ received from the virtual manager 220 .

[0237] In an embodiment, the virtual manager 220 may determine a channel to which a virtual pulse is to be applied based on the chip enable signal CE_SIG in a high state and the command queue level CMDQL.

[0238] For example, when the command queue level CMDQL of all memory devices is "0", the virtual manager 220 may determine to apply virtual pulses to all memory devices and then sequentially interrupt the virtual pulses. As an example, the virtual manager 220 may output a virtual pulse input request DPIN_REQ to the virtual pulse generator 230. In response to the input request DPIN_REQ, the virtual pulse generator 230 may sequentially interrupt the application of virtual pulses.

[0239] However, when the command queue level (CMDQL) of some but not all memory devices is "0," the virtualization manager 220 may apply dummy pulses only to channels connected to memory devices whose command queue level (CMDQL) is not "0." In other words, dummy pulses are applied to memory devices predicted to resume operations within a short period of time, thereby preventing a rapid increase or decrease in total current consumption. In this case, the number of memory devices whose command queue level (CMDQL) is "0" may be one.

[0240] After applying the dummy pulse only to the remaining memory devices whose command queue levels CMDQL are not "0", the virtual manager 220 may again receive the high-state chip enable signal CE_SIG from the enable signal generator 240. When the virtual manager 220 receives the high-state chip enable signal CE_SIG corresponding to at least two memory devices, the virtual manager 220 may receive the command queue level CMDQL corresponding to the memory device with the high-state chip enable signal CE_SIG and then determine whether to apply or interrupt the dummy pulse.

[0241] Figure 12 is a diagram illustrating application or interruption of a virtual pulse determined based on a command queue.

[0242] Reference Figure 11 and Figure 12 , Figure 12 The first to fourth command queues CMD_QUEUE1 to CMD_QUEUE4 shown correspond to the first to fourth memory devices ( Figure 11 100_1 to 100_4 shown), Figure 12 Each column shown represents a sequence of commands to be executed by the corresponding memory device.

[0243] In an embodiment, the first to fifth commands CMD1 to CMD5 may be queued in a first command queue CMD_QUEUE1 corresponding to a first memory device, the sixth and seventh commands CMD6 and CMD7 may be queued in a second command queue CMD_QUEUE2 corresponding to a second memory device, the eighth to eleventh commands CMD8 to CMD11 may be queued in a third command queue CMD_QUEUE3 corresponding to a third memory device, and the twelfth to fourteenth commands CMD12 to CMD14 may be queued in a fourth command queue CMD_QUEUE4 corresponding to a fourth memory device.

[0244] Figure 12 An exemplary number and sequence of commands queued in each queue are shown. However, the number and sequence may vary.

[0245] In an embodiment, the first to fourth memory devices may perform operations simultaneously. That is, the first, second, third, and fourth memory devices may simultaneously perform operations corresponding to the first, sixth, eighth, and twelfth commands CMD1, CMD6, CMD8, and CMD12, respectively.

[0246] Reference Figure 9 Before the first to fourth memory devices execute operations corresponding to their respective commands, dummy pulses may be sequentially applied to the first to fourth channels connected to the first to fourth memory devices, respectively. When the dummy pulses are sequentially applied to the first to fourth channels, the total current consumption of the memory devices may sequentially increase. Therefore, when the total current consumption sequentially increases, voltage noise may not occur.

[0247] When the first to fourth channel currents become dummy currents as dummy pulses are applied to the first to fourth channels, the first to fourth memory devices may perform operations corresponding to the respective commands.

[0248] In an embodiment, the first to fourth memory devices may execute the next command. That is, the first memory device may execute an operation corresponding to the second command CMD2, the second memory device may execute an operation corresponding to the seventh command CMD7, the third memory device may execute an operation corresponding to the ninth command CMD9, and the fourth memory device may execute an operation corresponding to the thirteenth command CMD13.

[0249] Since none of the first to fourth memory devices have finished or suspended operations, the enable signal generator 240 can generate low-state chip enable signals corresponding to the first to fourth memory devices. Therefore, the virtualization manager 220 does not need to perform operations for sequentially reducing the total current consumption of the memory devices.

[0250] However, when it is determined that the second and third memory devices have completed their operations, for example, after the first to fourth memory devices have performed their respective operations, the enable signal generator 240 may generate a high chip enable signal corresponding to the second and third memory devices. After the second memory device performs the operation corresponding to the seventh command CMD7, the second memory device may complete the operation. After the third memory device performs the operation corresponding to the ninth command CMD9, the third memory device may complete the operation.

[0251] Since no current is consumed by the two memory devices, the total current consumption may decrease rapidly. Therefore, the virtual manager 220 may receive the high-state chip enable signal corresponding to the second and third memory devices, and then output a command queue level request for checking the command queue levels of the second and third memory devices to the command queue group 250.

[0252] In an embodiment, the command queue group 250 may output a command queue level in response to a command queue level request from the virtualization manager 220. Since the second memory device has executed operations corresponding to the sixth command CMD6 and the seventh command CMD7, the number of commands queued in the command queue corresponding to the second memory device may be "0." Furthermore, since the third memory device has executed operations corresponding to the eighth command CMD8 and the ninth command CMD9, the commands queued in the command queue corresponding to the third memory device may be the tenth command CMD10 and the eleventh command CMD11, and the number of commands may be "2."

[0253] Therefore, in response to the command queue level request from the virtual manager, the command queue group 250 may output a command queue level “0” corresponding to the second memory device and a command queue level “2” corresponding to the third memory device to the virtual manager 220 .

[0254] Since the command queue levels corresponding to the second and third memory devices are not both "0," the virtual manager may determine to apply a virtual pulse only to the third memory device whose command queue level is not "0." The virtual manager 220 may output a virtual pulse generation request to the virtual pulse generator 230 requesting that the virtual pulse be applied to the third memory device, and the virtual pulse generator 230 may apply the virtual pulse to the third channel coupled to the third memory device.

[0255] In an embodiment, although not shown in the figure, when the command queue levels corresponding to the second and third memory devices are both "0," a dummy pulse may be applied to the channels connected to the second and third memory devices, respectively. When a set time elapses after the dummy pulse is applied to the second and third channels, the dummy pulses applied to the second and third channels may be sequentially interrupted.

[0256] Subsequently, the first and fourth memory devices may be determined to have terminated their operations. That is, a high chip enable signal may be generated corresponding to the first and fourth memory devices. After the first memory device executes the operation corresponding to the third command CMD3, the first memory device may terminate its operation. After the fourth memory device executes the operation corresponding to the fourteenth command CMD14, the fourth memory device may terminate its operation.

[0257] Since no current is consumed in the two memory devices, the total current consumption may decrease rapidly. Therefore, the virtual manager 220 may receive the high-state chip enable signal corresponding to the first and fourth memory devices, and then output a command queue level request for checking the command queue levels of the first and fourth memory devices to the command queue group 250.

[0258] In an embodiment, command queue group 250 may output a command queue rank in response to a command queue rank request from virtual manager 220. Since the first memory device has executed operations corresponding to the first command CMD1, the second command CMD2, and the third command CMD3, the commands queued in the command queue corresponding to the first memory device may be the fourth command CMD4 and the fifth command CMD5, and the number of commands may be "2." Furthermore, since the fourth memory device has executed operations corresponding to the twelfth command CMD12 to the fourteenth command CMD14, the number of commands queued in the command queue corresponding to the fourth memory device may be "0."

[0259] Therefore, in response to the command queue level request from the virtual manager, the command queue group 250 may output a command queue level “2” corresponding to the first memory device and a command queue level “0” corresponding to the fourth memory device to the virtual manager 220 .

[0260] Since both command queue levels corresponding to the first and fourth memory devices are not "0," the virtual manager may determine to apply a virtual pulse only to the first memory device whose command queue level is not "0." The virtual manager 220 may output a virtual pulse generation request to the virtual pulse generator 230 requesting that a virtual pulse be applied to the first memory device, and the virtual pulse generator 230 may apply the virtual pulse to the first channel coupled to the first memory device.

[0261] Subsequently, the first memory device may perform an operation corresponding to the fourth command CMD4 , and the third memory device may perform an operation corresponding to the eleventh command CMD11 .

[0262] In an embodiment, it can be determined that after the third memory device performs the operation corresponding to the eleventh command CMD11, the third memory device ends the operation. That is, a high chip enable signal corresponding to the third memory device can be generated. After the third memory device performs the operation corresponding to the eleventh command CMD11, the third memory device can end the operation. However, since only the third memory device ends the operation among the multiple memory devices, the virtualization manager 220 does not need to perform operations for applying or interrupting virtual pulses.

[0263] Therefore, when the memory device starts operating, the total current consumption of the memory device can be sequentially increased. Then, when the memory device ends operating, the total current consumption of the memory device can be sequentially decreased. Therefore, through the above process, the total current consumption is prevented from rapidly increasing or decreasing, thereby preventing the occurrence of power noise.

[0264] Figure 13 is a diagram illustrating a virtual pulse output based on a chip enable signal.

[0265] Reference Figure 13 , Figure 13 The diagram shows a dummy toggle (Dummy toggle) and data (chunk) inputted through the input / output pin DQ based on the chip enable signal CE_SIG.

[0266] In an embodiment, when the memory device 100 is not operating, the chip enable signal CE_SIG corresponding to the corresponding memory device may be output in a high state. However, when the memory device 100 is operating (for example, when transmitting or receiving data through the input / output pin DQ), the chip enable signal CE_SIG corresponding to the corresponding memory device may be output in a low state.

[0267] In an embodiment, when data is transmitted or received via the input / output pin DQ, the total current consumption of the memory device 100 may increase or decrease instantaneously. Therefore, to prevent the total current consumption of the memory device 100 from increasing instantaneously, a virtual trigger may be applied to the memory device 100 via the input / output pin DQ. Here, the virtual trigger is a pulse of a specific amplitude applied to the memory device 100.

[0268] That is, when the chip enable signal CE_SIG is in a high state, a virtual trigger may be applied through the input / output pin DQ of the memory device 100, and the total current consumption of the memory device 100 may be gradually increased (preheated). The magnitude of the virtual trigger may increase sequentially (1, 2, 3, ...).

[0269] Therefore, before the memory device starts operating, a dummy trigger having a sequentially increasing magnitude is applied to the memory device 100 , thereby preventing an instantaneous increase in total current consumption.

[0270] When the total current consumption of the memory device 100 is instantaneously increased by a virtual trigger and then reaches a certain level, the memory device 100 may transmit or receive data.

[0271] Even if data transmission or reception is completed, that is, when it is predicted that the memory device 100 will transmit or receive a data block, a virtual trigger can be applied to the memory device 100. That is, since the memory device 100 immediately starts operating, a virtual trigger for maintaining the total current consumption at a certain level can be applied to the memory device 100. Subsequently, the memory device 100 can transmit or receive data again.

[0272] In an embodiment, even when the memory device 100 ends operation, a dummy trigger may be applied to the memory device 100 to prevent the total current consumption from being instantaneously reduced.

[0273] For example, when the chip enable signal CE_SIG is output in a high state due to the determination that the memory device 100 has terminated operation, a virtual trigger may be applied to the memory device 100 and then sequentially interrupted (warm-down). That is, after the virtual trigger is applied to the memory device 100 determined to have terminated operation, the magnitude of the virtual trigger may be sequentially reduced.

[0274] Therefore, before the memory device ends its operation, a dummy trigger whose magnitude sequentially decreases is applied to the memory device 100 , thereby making it possible to prevent the total current consumption from being instantaneously reduced.

[0275] Figure 14 is a diagram illustrating the operation of a memory controller according to an embodiment of the present disclosure.

[0276] Figure 14 A diagram showing a sequence of applying dummy pulses to a channel connecting a memory controller and a memory device when the memory device starts operating.

[0277] In step S1401, the memory controller may receive a request from a host. The request received from the host may be a program request, a read request, or an erase request for any one of the plurality of memory devices included in the storage device. In other words, the memory controller may determine which memory device among the plurality of memory devices to perform an operation on based on the request received from the host.

[0278] In step S1403, the memory controller may determine a memory device to execute the command based on the request received from the host. The number of memory devices to execute the command may be two or more.

[0279] In an embodiment, when multiple memory devices simultaneously execute operations corresponding to commands, the total current consumption of the memory devices may increase rapidly. Therefore, dummy pulses are sequentially applied to channels connecting the memory controller and the memory devices so that the total current consumption can be gradually increased.

[0280] That is, when memory devices performing an operation are determined in response to a request received from the host, dummy pulses may be sequentially applied to channels through which the memory controller is coupled to the memory devices ( S1405 ).

[0281] For example, when the memory devices that will execute the command corresponding to the request received from the host are determined to be the first memory device and the second memory device, dummy pulses can be sequentially applied to the first channel and the second channel through which the memory controller is connected to the first memory device and the second memory device. That is, the dummy pulse is first applied to the first channel or the second channel, and then after a set time has passed since the application of the dummy pulse, the dummy pulse can be applied to the other channel. Therefore, the total current consumption of the memory device can be prevented from increasing instantaneously. In addition, after performing the operation, the memory controller can immediately determine to interrupt the application of the dummy pulse. That is, since the memory device has started operating, it is no longer necessary to generate dummy pulses to gradually increase the total current consumption.

[0282] Figure 15 is a diagram illustrating the operation of a memory controller according to an embodiment of the present invention.

[0283] Reference Figure 15 , when the memory device ends an operation, a dummy pulse is applied to a channel connecting the memory controller and the memory device, or is interrupted in the channel.

[0284] In step S1501, the memory controller may determine a memory device to terminate an operation among a plurality of memory devices included in the storage device. The memory device to terminate an operation among the plurality of memory devices may be determined based on a chip enable signal. That is, when a high chip enable signal is generated, the memory controller may determine that the memory device corresponding to the chip enable signal will terminate an operation.

[0285] When the memory device to be terminated is determined, after the determined memory device terminates operation, a dummy pulse may be applied to all channels of the memory controller connected to the determined memory device (S1503). In other words, since the memory devices terminate operation simultaneously, the termination of operation of the memory devices can be delayed to prevent the total current consumption of the memory devices from being instantly reduced.

[0286] After applying the dummy pulses to the channels through which the memory controller is connected to the memory device whose operation is to be terminated, the dummy pulses applied to the channels may be sequentially interrupted (S1505). That is, after applying the dummy pulses to the channels, the memory controller may interrupt the dummy pulses applied to any one channel and sequentially interrupt the dummy pulses applied to the other channels after a set time has passed.

[0287] Therefore, it is possible to prevent the total current consumption of the memory device from being instantaneously reduced.

[0288] Figure 16 is a diagram illustrating the operation of a memory controller according to an embodiment of the present disclosure.

[0289] Reference Figure 15 and Figure 16 , steps S1601 to S1607 correspond to step S1501. That is, steps S1601 to S1607 may be steps of determining a memory device to end operation among a plurality of memory devices that are operating.

[0290] In step S1601, the memory controller may determine whether the generated chip enable signal is in a high state or a low state. The chip enable signal may correspond to a physical block address PBA. In addition, the chip enable signal may be generated for each memory device.

[0291] In an embodiment, the memory controller may determine the number of memory devices corresponding to the high-state chip enable signal among the chip enable signals corresponding to the plurality of memory devices (S1603). The memory device corresponding to the high-state chip enable signal may be the memory device to end the operation.

[0292] Subsequently, the memory controller may determine whether the number of memory devices corresponding to the chip enable signal in the high state is two or more (S1605). When the number of memory devices corresponding to the chip enable signal in the high state is not two or more (No at S1605), that is, when the number of memory devices corresponding to the chip enable signal in the high state is one, even when current does not flow in the corresponding memory device, the total current consumption of the memory devices does not decrease rapidly. Therefore, the memory controller does not need to perform an operation for sequentially reducing the total current consumption.

[0293] However, when the number of memory devices corresponding to the chip enable signal in the high state is two or more (Yes at S1605), when current does not flow simultaneously into the corresponding memory devices, the total current consumption of the memory devices may decrease rapidly. Therefore, the memory controller needs to perform an operation for sequentially reducing the total current consumption.

[0294] In an embodiment, in order to sequentially reduce the total current consumption, the memory controller may determine the command queue level of the memory device corresponding to the chip enable signal in the high state (S1607). In other words, the memory controller may determine whether a dummy pulse is applied to the channel through which the memory controller is connected to the corresponding memory device and is interrupted in the channel.

[0295] For example, the memory controller may determine whether to apply and interrupt the dummy pulse based on whether the command queue levels are all "0".

[0296] Figure 17 is a diagram illustrating the operation of a memory controller according to an embodiment of the present disclosure.

[0297] Reference Figure 15 and Figure 17 , steps S1701 to S1707 correspond to step S1503.

[0298] In step S1701 , the memory controller may determine whether the command queue levels are all “0.” That is, the channels to which the dummy pulses are applied may be determined based on the command queue levels.

[0299] In an embodiment, when the command queue level is not all "0" (No at S1701), the memory controller may determine whether the number of memory devices with a command queue level of "0" is two or more (S1703). When the number of memory devices with a command queue level of "0" is not two or more (No at S1703), that is, when the number of memory devices with a command queue level of "0" is 1, the memory controller may apply a dummy pulse to a channel connected to a memory device whose command queue level is not "0" (S1705). In other words, a dummy pulse may be applied to a channel connected to a memory device that has currently completed an operation but is about to immediately perform another operation again. Here, the dummy pulse is applied to the channel simultaneously or step by step.

[0300] Therefore, no current is consumed in the channel connected to the memory device that is about to end the operation. Since the number of the memory device that is about to end the operation is 1, the total current consumption of the memory device may not decrease rapidly.

[0301] As determined in step S1701, when the command queue levels are all "0" (yes), or as determined in step S1703, when the number of memory devices with a command queue level of "0" is two or more (yes), the memory controller may apply dummy pulses to all channels through which the memory controller is connected to the memory devices that are to terminate or suspend the operation (S1707). That is, since all memory devices are determined to terminate the operation, or since two or more memory devices are determined to terminate the operation, dummy pulses may be applied to all channels connected to the memory devices that are determined to terminate the operation. Here, the dummy pulses are applied to the channels simultaneously or step by step. Subsequently, the dummy pulses applied to the channels may be sequentially interrupted (S1505).

[0302] As determined in step S1703 , when the number of memory devices having a command queue level of “0” is two or more, in step S1505 , dummy pulses may be sequentially interrupted only in channels connected to memory devices having a command queue level of “0”.

[0303] Therefore, when the dummy pulses applied to the channels are sequentially interrupted, the total current consumption of the memory device may not decrease rapidly.

[0304] Figure 18 It shows Figure 1 A diagram of another embodiment of a memory controller is shown.

[0305] Reference Figure 18, the memory controller 1000 is connected to the host and the memory device. The memory controller 1000 is configured to access the memory device in response to a request received from the host. For example, the memory controller 1000 is configured to control read operations, program operations, erase operations, and background operations of the memory device. The memory controller 1000 is configured to provide an interface between the memory device and the host. The memory controller 1000 is configured to drive firmware for controlling the memory device.

[0306] The memory controller 1000 may include a processor 1010 , a memory buffer 1020 , an error correction code (ECC) circuit 1030 , a host interface 1040 , a buffer control circuit 1050 , a memory interface 1060 , and a bus 1070 .

[0307] The bus 1070 may be configured to provide a channel between the components of the memory controller 1000 .

[0308] The processor 1010 can control the overall operation of the memory controller 1000 and perform logical operations. The processor 1010 can communicate with an external host through the host interface 1040 and communicate with the memory device through the memory interface 1060. In addition, the processor 1010 can communicate with the memory buffer 1020 through the buffer control circuit 1050. The processor 1010 can use the memory buffer 1020 as a working memory, a cache memory, or a buffer memory to control the operation of the memory device.

[0309] The processor 1010 can perform the functions of the flash translation layer (FTL). The processor 1010 can convert the logical block address (LBA) provided by the host into a physical block address (PBA) through the FTL. The FTL can receive the LBA and convert it into the PBA using a mapping table. Depending on the mapping unit, there are several address mapping methods for the FTL. Representative address mapping methods include page mapping method, block mapping method and hybrid mapping method.

[0310] The processor 1010 is configured to randomize data received from the host. For example, the processor 1010 may use a randomization seed to randomize the data received from the host. The randomized data is provided as data to be stored to a memory device to be programmed in the memory cell array.

[0311] The processor 1010 may perform randomization and de-randomization through driving software or firmware.

[0312] In an embodiment, the processor 1010 may obtain the Figure 2100) receives a fuzzy programming completion response corresponding to the fuzzy programming command to record the fuzzy programming completion time, and sends a signal to the memory device ( Figure 2 100) shown as outputting fine programming commands.

[0313] Before the processor 1010 outputs a fine program command, the processor 1010 may send a program command to the memory device ( Figure 2 100) shown as outputting a virtual programming command.

[0314] The memory buffer 1020 may be used as a working memory, a cache memory, or a buffer memory of the processor 1010. The memory buffer 1020 may store codes and commands executed by the processor 1010. The memory buffer 1020 may include a static RAM (SRAM) or a dynamic RAM (DRAM).

[0315] The ECC circuit 1030 may perform ECC operations. The ECC circuit 1030 may perform ECC encoding on data to be written to the memory device via the memory interface 1060. The ECC-encoded data may be transmitted to the memory device via the memory interface 1060. The ECC circuit 1030 may perform ECC decoding on data received from the memory device via the memory interface 1060. In an example, the ECC circuit 1030 may be included in the memory interface 1060 as a component of the memory interface 1060.

[0316] The host interface 1040 may communicate with an external host under the control of the processor 1010. The host interface 1040 may communicate with the host using at least one of various communication methods such as a universal serial bus (USB), a serial AT attachment (SATA), a high-speed inter-chip (HSIC), a small computer system interface (SCSI), a FireWire, a peripheral component interconnect (PCI), PCI Express (PCIe), a high-speed non-volatile memory (NVMe), a universal flash memory (UFS), a secure digital (SD), a multimedia memory card (MMC), an embedded MMC (eMMC), a dual in-line memory module (DIMM), a registered DIMM (RDIMM), and / or a load-reduced DIMM (LRDIMM).

[0317] The buffer control circuit 1050 is configured to control the memory buffer 1020 under the control of the processor 1010 .

[0318] The memory interface 1060 is configured to communicate with the memory device under the control of the processor 1010. The memory interface 1060 may communicate commands, addresses, and data with the memory device through a channel.

[0319] In an example, the memory controller 1000 may not include the memory buffer 1020 and the buffer control circuit 1050. One or both of these components may be provided separately, or one or both of their functions may be distributed among other components of the memory controller 1000.

[0320] In an example, the processor 1010 may control the operation of the memory controller 1000 by using code. The processor 1010 may load code from a nonvolatile memory device (e.g., a read-only memory (ROM)) provided in the memory controller 1000. In another example, the processor 1010 may load code from a memory device through the memory interface 1060.

[0321] In this example, the bus 1070 of the memory controller 1000 can be divided into a control bus and a data bus. The data bus can transmit data within the memory controller 1000, and the control bus can transmit control information such as commands and addresses within the memory controller 1000. The data bus and the control bus are separated from each other so as not to interfere with or affect each other. The data bus can be connected to the host interface 1040, the buffer control circuit 1050, the ECC circuit 1030, and the memory interface 1060. The control bus can be connected to the host interface 1040, the processor 1010, the buffer control circuit 1050, the memory buffer 1020, and the memory interface 1060.

[0322] Figure 19 is a block diagram illustrating a solid-state drive (SSD) system to which a storage device is applied according to an embodiment of the present disclosure.

[0323] Reference Figure 19 , an SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals SIG with the host 3100 via a signal connector 3001 and receives power PWR via a power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0324] In an embodiment, the SSD controller 3210 may be used as a reference Figure 1 The memory controller 200 is described.

[0325] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. In an example, the signal SIG may be based on an interface between the host 3100 and the SSD 3200. For example, the signal SIG may be defined by at least one of the following interfaces: a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI Express (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), FireWire, a universal flash storage (UFS), Wi-Fi, Bluetooth, and / or NVMe.

[0326] In an embodiment, when a plurality of flash memories 3221 to 322n start or end operations at the same time, the SSD controller 3210 may apply a dummy pulse to or interrupt a dummy pulse from the first channel CH1 to the nth channel CHn, and the SSD controller 3210 is connected to the plurality of flash memories 3221 to 322n through CH1 to CHn.

[0327] In an embodiment, before the plurality of flash memories 3221 to 322n start operating simultaneously, the SSD controller 3210 may sequentially apply dummy pulses to the first to n-th channels CH1 to CHn. After applying the dummy pulses to the first to n-th channels CH1 to CHn, the plurality of flash memories 3221 to 322n may start operating simultaneously.

[0328] In addition, when multiple flash memories 3221 to 322n end operations at the same time, the SSD controller 3210 can apply dummy pulses to the first channel CH1 to the nth channel CHn after the multiple flash memories 3221 to 322n end operations, and sequentially interrupt the dummy pulses applied to the first channel CH1 to the nth channel CHn.

[0329] The auxiliary power supply 3230 is connected to the host 3100 through the power connector 3002. When the power supply from the host 3100 is not smooth, the auxiliary power supply 3230 can provide power to the SSD 3200. In an example, the auxiliary power supply 3230 can be located in the SSD 3200 or be provided outside the SSD 3200. For example, the auxiliary power supply 3230 can be located on the motherboard and provide auxiliary power to the SSD 3200.

[0330] The buffer memory 3240 operates as a buffer memory for the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 may include any of various types of volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and / or GRAM, or any of various types of non-volatile memories such as FRAM, ReRAM, STT-MRAM, and / or PRAM.

[0331] Figure 20 is a block diagram illustrating a user system of an application storage device according to an embodiment of the present disclosure.

[0332] Reference Figure 20 , the user system 4000 includes an application processor 4100 , a memory module 4200 , a network module 4300 , a storage module 4400 and a user interface 4500 .

[0333] The application processor 4100 may drive components, an operating system (OS), user programs, etc. included in the user system 4000. In an example, the application processor 4100 may include a controller, an interface, a graphic engine, etc. for controlling components included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

[0334] In an embodiment, when a plurality of memory devices included in memory module 4400 simultaneously start or end operations, application processor 4100 may apply a dummy pulse to or interrupt a channel through which application processor 4400 is coupled to the plurality of memory devices.

[0335] In an embodiment, the application processor 4100 may sequentially apply dummy pulses to the channels before the multiple memory devices included in the memory module 4400 simultaneously start operating. After applying the dummy pulses to all channels, the multiple memory devices in the memory module 4400 may simultaneously start operating.

[0336] In addition, when a plurality of memory devices in the memory module 4400 simultaneously end operations, the application processor 4100 may apply a dummy pulse to the channel after the plurality of memory devices end operations and sequentially interrupt the dummy pulse applied to the channel.

[0337] The memory module 4200 can operate as a main memory, working memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 can include any of various types of volatile random access memories such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and / or LPDDR3 SDRAM, or any of various types of non-volatile random access memories such as PRAM, ReRAM, MRAM, and / or FRAM. In an example, the application processor 4100 and the memory module 4200 can be packaged based on a stacked package (PoP) and provided as one semiconductor package.

[0338] The network module 4300 can communicate with external devices. In an example, the network module 4300 can support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), Wimax, WLAN, UWB, Bluetooth, and Wi-Fi. In an example, the network module 4300 can be included in the application processor 4100.

[0339] The storage module 4400 can store data. For example, the storage module 4400 can store data received from the application processor 4100. Alternatively, the storage module 4400 can transmit the data stored therein to the application processor 4100. In an example, the storage module 4400 can be implemented using a non-volatile semiconductor memory device, such as a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, or a NAND flash memory with a three-dimensional structure. In an example, the storage module 4400 can be configured as a removable drive, such as a memory card or an external drive of the user system 4000.

[0340] In an example, the storage module 4400 may include a plurality of non-volatile memory devices, each of which may be connected to a reference Figure 2 and Figure 3 The memory module 4400 can be used in conjunction with the memory device described in the reference Figure 1 The described storage device 50 operates identically.

[0341] The user interface 4500 may include an interface for inputting data or commands to the application processor 4100 or outputting data to an external device. In an example, the user interface 4500 may include a user input interface such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric element. The user interface 4500 may include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

[0342] According to an embodiment of the present disclosure, the number of channels connected to a memory device that is to start an operation is determined based on a request received from a host, the total current is sequentially increased based on the determined number of channels, the number of channels connected to a memory device that is to end an operation is determined based on a chip enable signal and a command queue, and the current can be sequentially decreased based on the determined number of channels.

[0343] Although the present disclosure has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents. Therefore, the scope of the present invention should not be limited to the above-described embodiments but should be determined by the appended claims including their equivalents.

[0344] In the above-described embodiments, steps may be selectively performed, or some steps or parts thereof may be omitted. In all embodiments, the steps do not necessarily need to be performed in the order described. The disclosed embodiments are provided to facilitate understanding of the present invention, rather than to limit the present invention. In other words, it should be clear to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0345] Although specific terms are used herein, they are only used to explain the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, as those skilled in the art will recognize that many variations can be made within the spirit and scope of the present disclosure. The present invention covers all modifications and variations of any disclosed embodiments that fall within the scope of the appended claims.

Claims

1. A memory controller for controlling a plurality of memory devices connected via a plurality of channels, the memory controller comprising: a request checker that identifies a memory device corresponding to a request received from a host among the plurality of memory devices and generates device information about the identified memory device to perform an operation corresponding to the request; a virtual manager that outputs a request for controlling a virtual pulse to be applied to a channel of a memory device selected according to the device information among the plurality of channels; as well as A dummy pulse generator sequentially applies the dummy pulse to channels coupled to the selected memory device based on a request to control the dummy pulse. 2 . The memory controller according to claim 1 , wherein the dummy pulse generator applies the dummy pulse by setting at least one of a level of the dummy pulse, a period of the dummy pulse, and a duration of the dummy pulse. 3 . The memory controller according to claim 1 , wherein the virtual manager outputs a virtual pulse generation request to request application of the virtual pulse to a channel connected to the selected memory device before the selected memory device starts operating according to the device information.

4. The memory controller according to claim 3, wherein the dummy pulse generator applies the dummy pulse to any one of the channels connected to any one of the memory devices selected according to the device information based on the dummy pulse generation request, and then applies the dummy pulse to another one of the channels after a set first time has passed.

5. The memory controller according to claim 1, further comprising: an enable signal generator, generating a chip enable signal for selecting the plurality of memory devices; as well as The command queue group includes command queues corresponding to the plurality of memory devices respectively.

6. The memory controller according to claim 5, wherein the virtual manager receives chip enable signals respectively corresponding to the memory devices selected according to the device information from the enable signal generator, and determines the memory device that will end the operation based on a high-state chip enable signal among the received chip enable signals.

7. The memory controller according to claim 6, wherein the virtual manager outputs a command queue level request to determine a command queue level of the memory device corresponding to the chip enable signal in the high state, The command queue group outputs the command queue level corresponding to the command queue level request.

8. The memory controller according to claim 7, wherein: When the command queue levels of the memory devices corresponding to the chip enable signals in the high state are all 0, the virtual manager determines to apply the virtual pulse to all channels connected to the memory devices corresponding to the chip enable signals in the high state.

9. The memory controller according to claim 8, wherein: When the dummy pulse is applied to all channels connected to the memory device corresponding to the chip enable signal in the high state, the dummy manager determines to interrupt the dummy pulse applied to any one of the channels, and interrupts the dummy pulse applied to another one of the channels after a set second time has passed.

10. The memory controller according to claim 7, wherein: When the command queue levels of the memory devices corresponding to the chip enable signals in the high state are not all 0, the virtual manager determines whether the number of memory devices having a command queue level of 0 is two or more.

11. The memory controller according to claim 10, wherein: When the number of memory devices having the command queue level 0 is 1, the virtual manager determines to apply the virtual pulse to a channel connected to a memory device corresponding to the chip enable signal in a high state except for the memory device having the command queue level 0.

12. The memory controller according to claim 10, wherein: When the number of memory devices whose command queue level is 0 is two or more, the virtual manager determines to apply the virtual pulse to all channels connected to the memory devices corresponding to the chip enable signal in the high state, and then interrupts the virtual pulse applied to the channels connected to the memory devices whose command queue level is 0 after a set third time has passed.

13. A method of operating a memory controller, the memory controller controlling a plurality of memory devices coupled via a plurality of channels, the method comprising: identifying, among the plurality of memory devices, a memory device corresponding to a request received from a host; generating device information of a memory device to perform an operation corresponding to the request; outputting a request for a dummy pulse to be applied to a channel of a memory device selected according to the device information among the plurality of channels; and The dummy pulses are sequentially applied to channels coupled to the selected memory device based on a request for controlling the dummy pulses.

14. The method according to claim 13, wherein: Outputting the request to control the dummy pulse includes outputting a dummy pulse generation request so that the dummy pulse is applied to a channel coupled to the selected memory device before the selected memory device starts operating according to the device information.

15. The method according to claim 14, wherein: Sequentially applying the dummy pulse includes: applying the dummy pulse to any one of the channels connected to the memory device selected according to the device information based on the dummy pulse generation request, and then applying the dummy pulse to another one of the channels after a set first time has passed.

16. The method of claim 13, wherein outputting a request to control the dummy pulse comprises: A memory device to end the operation is determined among the plurality of memory devices by checking whether a chip enable signal selecting the plurality of memory devices is in a high state.

17. The method of claim 16, wherein outputting a request to control the dummy pulse further comprises checking a command queue level of a memory device that is to end an operation.

18. The method of claim 17, wherein outputting a request to control the virtual pulse comprises: When the command queue levels of the memory devices to end the operation are all 0, a request to apply the dummy pulse to all channels connected to the memory devices corresponding to the chip enable signal in the high state is output.

19. The method according to claim 18, wherein: Sequentially applying the dummy pulses includes: when the dummy pulses are applied to all channels of the memory device connected to the chip enable signal corresponding to the high state, interrupting the dummy pulse applied to any one of the channels, and then interrupting the dummy pulse applied to another one of the channels after a set second time has passed.

20. The method according to claim 17, wherein: Sequentially applying the dummy pulses includes: when the command queue levels of the memory devices corresponding to the chip enable signals in the high state are not all 0, determining to apply the dummy pulses to channels connected to the memory devices having a command queue level of 0.

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