Memory devices, methods of operating memory devices, and memory modules

Abstract

Memory devices, methods of operating memory devices, and memory modules are provided. The memory devices include a built-in self-test (BIST) unit to test an array of memory cells during a power-up sequence. The BIST unit performs a test of the array of memory cells in response to a power good signal or in response to a impedance control (ZQ) calibration command. The BIST unit terminates a test being performed in response to a write equalization command or in response to an activate command.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0108457, filed September 2, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The inventive concept relates to a memory device, a memory module, and a memory test method, and more particularly, to securing operational stability of a memory device by testing and repairing memory cells during a power-up sequence. BACKGROUND

[0003] Upon starting a computing system, training and / or testing is performed on devices in the computing system, such as a memory module and a graphics card, as part of a power-on self-test (POST). In the POST, the training and / or testing of a memory module in which a dynamic random access memory (DRAM) is installed includes interface debugging tasks (such as clock training, write / read leveling, write / read de-skew, and write / read centering) for parameters related to an interface between a central processing unit (CPU) and the DRAM. After the interface debugging operation is completed, testing of the DRAM cells is performed in a data write / read operation. When a DRAM cell failure occurs, there can be a performance degradation of the memory module due to the DRAM cell failure.

[0004] Accordingly, there is a need to repair defective cells by testing DRAM cells during a power-up sequence. SUMMARY

[0005] According to some embodiments of the inventive concept, a memory device is provided, the memory device including: a memory core including an array of memory cells; a impedance control (ZQ) engine configured to, in response to a ZQ calibration command, perform a ZQ calibration operation by using a ZQ resistor connected to a ZQ terminal; and a built-in self-test (BIST) unit configured to generate a test enable signal in response to the ZQ calibration command and configured to initiate a first test based on the test enable signal, the first test including a test of the array of memory cells.

[0006] According to some embodiments of the inventive concept, a method of operating a memory device is provided, wherein a built-in self-test (BIST) unit is configured to test a memory core, the built-in self-test (BIST) unit being embedded in the memory device. The method includes: receiving an impedance control (ZQ) calibration command from outside of the memory device; performing a ZQ calibration operation in response to the ZQ calibration command; generating a test enable signal in response to the ZQ calibration command; and initiating a first test of the memory core by the BIST unit.

[0007] According to some embodiments of the inventive concept, a memory device is provided, the memory device comprising: a memory core including a memory cell array; an impedance control (ZQ) engine configured to: perform a ZQ calibration operation by using a ZQ resistor connected to a ZQ terminal in response to a ZQ calibration command; a built-in self-test (BIST) unit configured to: generate a test enable signal in response to a ZQ calibration command, and configured to initiate a first test based on the test enable signal, the first test including a test of the memory cell array. The BIST unit includes a fault cell table configured to store information related to fault cells with defective characteristics in the memory cell array as a result of the first test; a training unit configured to perform memory core parameter training related to the memory core and peripheral circuit parameter training of other peripheral circuits in the memory device excluding the memory core in response to a training command; and a built-in self-repair (BISR) unit configured to replace fault cells with redundant cells using redundant cells in the memory cell array.

[0008] According to some embodiments of the inventive concept, a memory module is provided, the memory module comprising: a printed circuit board; a plurality of memory devices connected to the printed circuit board; and a controller configured to control the plurality of memory devices. Each of the plurality of memory devices includes: a memory core including a memory cell array; an impedance control (ZQ) engine configured to: perform a ZQ calibration operation by using a ZQ resistor connected to a ZQ terminal in response to a ZQ calibration command; and a built-in self-test (BIST) unit configured to: generate a test enable signal in response to a ZQ calibration command. The BIST unit is configured to: initiate a first test based on the test enable signal, the first test including a test of the memory cell array. Attached Figure Description

[0009] The embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram illustrating a memory system according to an example embodiment of the inventive concept;

[0011] Figure 2 Examples of embodiments based on the inventive concept Figure 1 A flowchart of the power-on sequence of the memory system in the diagram;

[0012] Figure 3 Examples of embodiments based on the inventive concept Figure 2 The flowchart of memory training in the process;

[0013] Figure 4This illustrates an example embodiment based on the inventive concept. Figure 1 Block diagram of the memory device in the diagram;

[0014] Figures 5A to 5D It is based on Figure 4 Circuit diagram of an embodiment of the built-in self-test (BIST) signal generator;

[0015] Figure 6 Based on the exemplary embodiments of the inventive concept Figure 4 The operation timing diagram of the power-on sequence of the memory device;

[0016] Figure 7 This is a block diagram illustrating a processor-memory system with a register-equipped dual in-line memory module (DIMM) (RDIMM) for mounting memory devices, according to an embodiment of the inventive concept; and

[0017] Figure 8 This is a block diagram illustrating a processor-memory system for a low-load DIMM (LRDIMM) with a memory device mounted, according to an embodiment of the inventive concept. Detailed Implementation

[0018] Figure 1 This is a block diagram illustrating a memory system 100 according to an example embodiment of the inventive concept.

[0019] Reference Figure 1 The memory system 100 may include a memory controller 110 and a memory device 120. The memory device 120 may include, for example, dynamic random access memory (DRAM), and the memory controller 110 may control the operation of the DRAM. The memory controller 110 may operate as a register clock driver (RCD) that provides clock signals and command / address signals to the memory device 120. In some embodiments, the memory controller 110 may be labeled RCD 110. The memory system 100 may be implemented using any type of memory module. For example, the memory system 100 may be implemented as a dual in-line memory module (DIMM) (such as unbuffered dual in-line memory module (UDIMM), register-equipped DIMM (RDIMM), low-load DIMM (LRDIMM), fully buffered DIMM (FBDIMM), small outline DIMM (SODIMM), etc.).

[0020] The memory system 100 can be connected to and accessed by the host 105. The host 105 may include a computing system. For example, the host 105 may include a processor, microcontroller (MPU), and / or central processing unit (CPU) that performs various computing functions, such as specific calculations or tasks. The processor may include a single-core processor or multiple multi-core processors (such as dual-core, quad-core, and hexa-core processors). The processor may also include cache memory. According to some embodiments, the host 105 may include a server, server array or server farm, web server, network server, internet server, workstation, minicomputer, mainframe, network device, or a combination thereof. In some embodiments, one memory device 120 of the memory system 100 is described. However, the scope of the inventive concept is not limited thereto, and the memory system 100 may include a variety of numbers of memory devices 120. Furthermore, the memory system 100 may include different memory devices and / or memory modules.

[0021] Examples can be described using the terms “connected” and / or “combined” and their derivatives. These terms do not have to be synonyms of each other. For example, using the terms “connected” and / or “combined” can indicate that two or more elements are in direct physical or electrical contact with each other. Furthermore, the term “combined” can also indicate that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0022] The memory controller 110 may include a register control word (RCW) 112, which controls the initialization and / or operational characteristics of the memory controller 110 to match the memory device 120. The RCW 112 may include various algorithms for configuring the memory controller 110 to enable proper interoperability with the memory device 120. For example, code indicating the frequency, timing, drive, detailed operating parameters, etc., of the memory device 120 may be set in the RCW 112. Built-in self-test (BIST) and / or training of the memory device 120 may be performed via the RCW 112 code.

[0023] Memory controller 110 can be connected to memory device 120 via memory interface 130. For simplicity, memory interface 130 is shown as a single signal line connecting memory controller 110 to memory device 120, but memory interface 130 may actually connect memory controller 110 to memory device 120 via multiple signal lines. Memory interface 130 may include connectors for connecting memory controller 110 to memory device 120. The connectors may be implemented as pins, balls, signal lines, and / or other hardware components. For example, clock signals, commands, addresses, data, etc., can be sent and / or received between memory controller 110 and memory device 120 via memory interface 130.

[0024] The memory device 120 may include a memory core 122, a mode register set (MRS) 124, an impedance control (ZQ) engine 126, and a test control unit 128.

[0025] Memory core 122 may include a memory cell array (122a, Figure 4 ), line decoder (122b, Figure 4 ), column decoder (122c, Figure 4 ) and sensing amplifier unit (122d, Figure 4 The memory cell array 122a may include multiple word lines (WL) and multiple bit lines (BL), and multiple memory cells (MC) formed at the intersections of the word lines (WL) and bit lines (BL). The row decoder 122b can enable the word line (WL) corresponding to the row address. The sense amplifier unit (122d) can sense and amplify the data of the memory cells (MC) connected to the enabled word lines, and send the amplified data of the memory cells (MC) to the bit lines (BL). The column decoder 122c can progressively increase the received column address in burst mode and select the bit line (BL) corresponding to the progressively increasing column address. In response to the BIST enable signal (BIST_EN), Figure 4 The memory core 122 can be selectively controlled in a normal operating mode for performing write / read operations or in a test operating mode for performing BIST. When the BIST enable signal BIST_EN is activated, BIST of the memory core 122 can be executed. The BIST enable signal BIST_EN can be controlled by the BIST unit (128a, ...) in the test control unit 128. Figure 4 )generate.

[0026] MRS 124 can be programmed to set multiple operating options, various functions, characteristics, and / or modes of memory device 120. When an MRS command is issued by memory controller 110, MRS 124 can be programmed using appropriate bit values ​​provided on the address bus of memory interface 130.

[0027] As an example, the MRS 124 can be used to control burst length (BL), column access strobe (CAS) delay (CL), write leveling enable / disable, data terminal reference voltage (VrefDQ) training, etc. BL can be provided to set the maximum number of column positions that can be accessed for read and / or write commands. CL can be provided to define the clock cycle delay between a read command and the first bit of valid output data. Write leveling can be provided to enable or disable skew compensation between the clock signal and the data strobe signal during a write operation. VrefDQ training can be provided to set the reference voltage used to read data input to or output from the data (DQ) terminal. VrefDQ training can be performed based on the supply voltage (VDDQ) driving the input / output buffer connected to the DQ terminal.

[0028] In addition, the MRS 124 can be used to control delay phase-locked loop (DLL) reset, DLL enable / disable, output drive strength, additional delay, termination data strobe (TDQS) enable / disable, input / output buffer enable, CAS write delay, dynamic termination, write cyclic redundancy check (CRC), multifunction register (MPR) positioning function, MPR operation function, deceleration mode, MPR read format, power saving mode, reference voltage (Vref) monitoring, read preamble training mode, read preamble function, write preamble function, command and address (C / A) parity function, CRC error status, C / A parity error status, die-on termination (ODT) function, data masking function, write data bus inversion (DBI) function, read DBI function, error detection code (EDC) holding mode, etc., related to the general functions, characteristics, and modes of DRAM.

[0029] ZQ engine 126 controls the impedance matching of signal lines transmitting commands, addresses, and / or data via memory interface 130. To reduce the transmission time of signals transmitted via memory interface 130, the signal swing width can be reduced. The swing width can be the difference between the lowest and highest amplitude of the signal. As the signal swing width decreases, the impact of external noise on memory device 120 can increase, and signal reflections caused by impedance mismatch in memory interface 130 can become more severe or require more consideration. To address impedance mismatch, memory device 120 may include a ZQ terminal 125 that receives a ZQ calibration command from memory controller 110 and controls impedance matching by performing a ZQ calibration operation. A resistor RZQ can be connected between ZQ terminal 125 and ground voltage VSS. The value of resistor RZQ can be, for example, approximately 240Ω.

[0030] The test control unit 128 may include a BIST unit 128a, a built-in self-healing (BISR) unit 128b, and a training unit 128c. The BIST unit 128a may initiate a first test to perform a full-cell test on the memory core 122 in response to a ZQ calibration command. The BIST unit 128a may initiate a second test to perform a test on the memory core 122 in response to a power stabilization signal PVCCH from the memory device 120. The BIST unit 128a may test the memory core 122 by selecting one of the first and second tests. The BIST unit 128a may store information about defective cells with defective characteristics in the memory core 122 as the result of the first and / or second tests.

[0031] The BISR unit 128b can replace defective cells with redundant cells by using redundant cells included in the memory core 122. The BISR unit 128b can store information about defective cells that have been repaired with redundant cells, as well as information about the defective cells themselves.

[0032] In response to a training command, training unit 128c can perform memory core parameter training related to memory core 122 in memory device 120 and / or peripheral circuit parameter training for other peripheral circuits besides memory core 122. Training unit 128c can serve as a training object to determine optimal parameters for memory core parameters and / or peripheral circuit parameters. In some embodiments, training unit 128c is described as being included in memory device 120. However, training unit 128c can be included in memory controller 110, and memory controller 110 can serve as a training object to perform memory training.

[0033] Figure 2 yes Figure 1 A flowchart of the power-on sequence of the memory system 100.

[0034] Reference Figure 2 Power can be supplied to the memory system 100, enabling the memory system 100 to be powered on (S100). When the memory system 100 is powered on, it drives the power supply voltage (VDD) of the memory device 120. Figure 4 When the power level remains stable, the memory device 120 can supply a power stabilization signal (PVCCH). Figure 4 The memory device 120 can be controlled to be in an operable state by using the power stabilization signal PVCCH. In this case, the memory device 120 can start the BIST by using the BIST unit 128a in response to the power stabilization signal PVCCH as the first option for starting the BIST (S100a).

[0035] After the memory system 100 is powered on, the memory controller 110 can set RCW 112, which is used to control the memory device 120 to match the initialization and / or operating characteristics of the memory device 120 (S200). RCW 112 can store codes indicating the frequency, timing, drive, detailed operating parameters, etc. of the memory device 120, so that the memory controller 110 can interact with the memory device 120 in a normal manner.

[0036] The memory device 120 can configure the MRS 124 with multiple operating options, various functions, features, and modes (S300). In the MRS 124, codes for setting BL, CL, MPR operating functions, MPR read format, write equalization, VrefDQ training, read / write DBI functions, etc., can be set.

[0037] The memory device 120 may receive a ZQ calibration command from the memory controller 110 and perform a ZQ calibration operation using the ZQ engine 126 (S400). In this case, the memory device 120 may, as a second option, start the BIST using the BIST unit 128a in response to the ZQ calibration command (S400a). In this case, the BIST unit 128a of the memory device 120 may need to be configured so that the BIST is not started in response to the power stabilization signal PVCCH in operation S100a.

[0038] The ZQ engine 126 can generate pull-up calibration codes by performing pull-up calibration on the resistor RZQ connected to the ZQ terminal 125 and on the pull-up resistors in the ZQ engine 126, or by performing pull-down calibration on the pull-up and pull-down resistors in the ZQ engine 126. The pull-up calibration codes and / or pull-down calibration codes can be provided to the input / output buffers. The input / output buffers can adjust the terminating resistor values ​​based on the pull-up calibration codes and / or pull-down calibration codes.

[0039] The ZQ calibration operation performed after the memory system 100 is powered on may need to be completed within a time period specified by the standard associated with the ZQ calibration command. For example, the ZQ calibration operation may be completed in approximately 512 clock cycles.

[0040] After the ZQ calibration operation is performed, the memory device 120 can perform memory training using the training unit 128c as an interface debugging operation in the memory interface 130 (S500). The memory device 120 can perform, for example, clock training, address training, write / read balancing, write / read re-centering training, etc.

[0041] Figure 3 yes Figure 2The flowchart of the memory training operation S500 in the process.

[0042] Reference Figure 3 The memory device 120 can perform clock training (S501) on the control signal CTL received via the memory interface 130. The control signal CTL may include a chip select signal CS, a clock enable signal CKE, a row address strobe signal RAS, CAS, a write enable signal WE, etc. Clock training can be performed so that the control signal CTL sent from the memory controller 110 is received by the memory device 120 synchronously with the clock signal CLK.

[0043] The memory device 120 can perform clock training (S502) on commands CMD received via the memory interface 130. Commands CMD may include precharge commands, activation commands, read commands, write commands, etc. Clock training can be performed such that commands CMD sent from the memory controller 110 are received by the memory device 120 synchronously with the clock signal CLK.

[0044] The memory device 120 can be trained to recognize a receive enable signal received via the memory interface 130 (S503). The memory device 120 can provide a receive enable signal for recognizing a signal sent from the memory controller 110 to the training unit 128c. The training unit 128c may include buffer circuitry and timing circuitry for aligning the assertion of the receive enable signal with the transmission of the signal from the memory controller 110. In the training unit 128c, the timing assertion of the receive enable signal can be determined during the receive enable training process.

[0045] The memory device 120 can perform basic data strobe signal DQS training (S504) on the data DQ output via the memory interface 130. When the data strobe signal DQS and the data DQ are output together to the memory controller 110, the memory device 120 can perform read recentering training so that the edge of the data strobe signal DQS is centered in the window of the data DQ.

[0046] The clock training for the control signal CTL in operation S501, the clock training for the command CMD in operation S502, the receive enable training in operation S503, and / or the training for the data strobe signal DSQ in operation S504 can be performed using the MPR operation function and MPR read format of MRS 124. Clock training for the control signal CTL, the clock training for the command CMD, and the receive enable training can be performed by reading the preset timing calibration bit sequence in the MPR. Furthermore, training for the data strobe signal DQS of the data DQ can be performed by reading the preset data mode in the MPR.

[0047] The training for operations S501 to S504 can be performed using the MPR instead of the peripheral circuit parameters of memory core 122. When the peripheral circuit parameter training is complete, training unit 128c can determine that training using the MPR will no longer be performed. In this case, training unit 128c can generate an MPR disable signal MPR_DISEN indicating that the MPR is not used. The MPR disable signal MPR_DISEN can be used as a basic signal to terminate the BIST operation being performed by BIST unit 128a.

[0048] The memory device 120 can receive a write equalization command related to a write operation from the memory controller 110 via the memory interface 130, and perform write equalization to compensate for the skew between the received clock signal CLK and the data strobe signal DQS (S505). The write equalization can be a function that samples the data strobe signal DQS output from the memory controller 110 as the clock signal CLK, detects the phase relationship between the data strobe signal DQS and the clock signal CLK, and adjusts the delay time of the data strobe signal DQS.

[0049] The memory device 120 may terminate the BIST executed by the BIST unit 128a based on the MPR disable signal MPR_DISEN and in response to the write equalization command, as a first option to terminate the BIST (S505a).

[0050] Based on the write operation related to write balancing, activation and write commands can be sequentially issued from memory controller 110 to memory device 120. Memory device 120 can access memory core 122 in response to the activation command. In this case, memory device 120 can terminate BIST executed by BIST unit 128a based on the MPR disable signal MPR_DISEN and in response to the activation command, as a second option to terminate BIST (S505b). In this case, BIST unit 128a of memory device 120 may need to be configured such that BIST is not terminated in response to the write balancing command in operation S505a.

[0051] When memory system 100 uses DIMM (720, Figure 7 In implementation, multiple memory devices 120 may be mounted on the memory system 100. In the memory interface 130, a multi-drop connection may be used, in which the clock signal CLK line and C / A signal line are routed to the multiple memory devices 120 in a fly-through topology, and the data DQ line and data strobe signal DQS line are routed to each of the multiple memory devices 120.

[0052] In the fly-through topology, during a write operation, when the clock signal CLK is input to each of the plurality of memory devices 120 via the clock signal CLK line through the data link wiring, the data DQ and data strobe signal DQS can be input to each of the plurality of memory devices 120. The data DQ and data strobe signal DQS input to the memory device 120 that is last input to the clock signal CLK are significantly delayed compared to the data DQ and data strobe signal DQS input to the memory device 120 that was first input to the clock signal CLK. Therefore, each of the plurality of memory devices 120 can perform a write fly-through operation such that the arrival time of the data strobe signal DQS during the write operation satisfies the time point defined in the standard (S506).

[0053] The memory device 120 can perform data strobe signal DQS training (S507) on the data DQ input via the memory interface 130. When the data strobe signal DQS and the data DQ are input together into the memory controller 110, the memory device 120 can perform write recentering training so that the edge of the data strobe signal DQS is centered in the window of the data DQ.

[0054] The memory device 120 can perform a write / read data deskipation operation to reduce the time difference between data input / output times between data DQ inputs or outputs via the memory interface 130 (S508). Since the effective data window decreases when the skew between written data DQ increases in write mode, the memory device 120 can perform a write data deskipation operation to compensate for data skew and ensure effective data margin. Since the effective data window decreases when the skew between read data DQ increases in read mode, the memory device 120 can perform a read data deskipation operation to compensate for data skew and ensure effective data margin or improved data margin.

[0055] The memory device 120 can perform VrefDQ training to set the level of the reference voltage VrefDQ for reading data DQ input or output via the memory interface 130 (e.g., write / read VrefDQ training) (S509). The memory device 120 can perform training on the training value of the reference voltage VrefDQ, the training range of VrefDQ, etc.

[0056] As an example, VrefDQ training values ​​can be provided by dividing the training values ​​of VrefDQ into a first range (Range 1) and a second range (Range 2) based on VDDQ. In the first range (Range 1), the minimum operating voltage of VrefDQ can be set to approximately 60% of VDDQ, and the maximum operating voltage of VrefDQ can be set to approximately 92% of VDDQ. In the second range (Range 2), the minimum operating voltage of VrefDQ can be set to approximately 45% of VDDQ, and the maximum operating voltage of VrefDQ can be set to approximately 77% of VDDQ. The memory device 120 can perform VrefDQ training such that the VrefDQ level enters the middle of the data DQ eye diagram, which is considered as a superposition of multiple transitions of the data DQ.

[0057] It may be important to determine the validity period of the read data DQ so that the memory controller 110 correctly recognizes the data DQ read from the memory device 120. It may also be important to determine the validity period of the written data DQ so that the memory device 120 correctly recognizes the data DQ received from the memory controller 110. For this purpose, a specific lead time indicating whether the data DQ is valid before its input or output can be set as a data strobe signal DQS. The memory device 120 may perform high-level data strobe signal DQS training (e.g., transmit / receive DQ / DQS advanced training) on ​​the data DQ input or output via the memory interface 130 (S510).

[0058] The memory device 120 may perform enable training before inputting data DQ according to a write command or outputting data DQ according to a read command, such that the data strobe signal DQS has a one-clock-cycle lead time or a two-clock-cycle lead time. Enable training of the data strobe signal DQS may perform an operation to adjust the delay of the DLL until the assertion of the enable signal matches the lead indication in the data strobe signal DQS.

[0059] The training in operations S507 to S510 can be performed using the core parameters of memory core 122. Training unit 128c can perform peripheral circuit parameter training and core parameter training, and then store the optimized peripheral circuit parameters and improved or optimized core parameters in a parameter storage area. The parameter storage area can be, for example, an Extended Mode Register Set (EMRS) or a separate parameter register, or non-volatile memory (such as flash memory, erasable programmable read-only memory (EPROM), and / or electrical EPROM (EEPROM)). Memory device 120 can write and / or read data using the optimized or improved peripheral circuit parameters and core parameter settings stored in the parameter storage area.

[0060] Figure 4 It is shownFigure 1 Block diagram of memory device 120.

[0061] Reference Figure 4 The memory device 120 may include a memory core 122, an MRS 124, a BIST unit 128a, a BISR unit 128b, a training unit 128c, a power detector 410, and a CMD decoder 420. The BIST unit 128a may include a BIST signal generator 430 and a BIST engine 432. The BISR unit 128b may include a row repair unit 440 and a column repair unit 442. For simplicity, refer to... Figure 1 The description of the given memory device 120 is omitted here, but it can be applied to... Figure 4 .

[0062] The power detector 410 generates a power stabilization signal PVCCH by detecting whether the power supply voltage level is stably maintained at the power supply voltage VDD level after the memory device 120 is powered on. The memory device 120 can enter an operable state in response to the power stabilization signal PVCCH. The power stabilization signal PVCCH can be provided to the BIST signal generator 430 of the BIST unit 128a.

[0063] The command decoder 420 can receive commands (CMD) via the memory interface 130 and store the commands (CMD) in the command sequencer 422. The command sequencer 422 can then... Figure 2 The power-on sequence of the memory system 100 shown queues the commands (CMDs) issued to the memory device 120. The command sequencer 422 can be configured to sequentially store commands (such as MRS commands including instructions for setting MRS 124 in S300, ZQ calibration commands including instructions for ZQ calibration operations in S400, training commands including instructions for memory training in S500, write equalization commands, activation commands, write commands, read commands, etc.). The memory device can be configured to sequentially store write commands, read commands, etc., and operate in a first-in-first-out (FIFO) manner, where commands stored in FIFO are output from the command decoder 420 in the order they are stored.

[0064] Command decoder 420 can generate control signals corresponding to the associated commands CMD according to the output sequence from command sequencer 422, and provide the control signals to BIST signal generator 430 and / or training unit 128c. Command decoder 420 can be based on ZQ calibration command (ZQCL, Figure 6The system generates a ZQ calibration enable signal ZQ_EN, a write equalization enable signal WRLVL_EN based on the write equalization command WRLVL, and an activation signal ACTIVE based on the activation command ACT. The ZQ calibration enable signal ZQ_EN, the write equalization enable signal WRLVL_EN, and the activation signal ACTIVE can be provided to the BIST signal generator 430 of the BIST unit 128a.

[0065] The BIST signal generator 430 can receive the power stabilization signal PVCCH, the ZQ calibration enable signal ZQ_EN, the write equalization enable signal WRLVL_EN, the activation signal ACTIVE, and / or the MPR disable signal MPR_DISEN provided by the training unit 128c. Based on these signals, the BIST signal generator 430 can generate the BIST enable signal BIST_EN and the BIST disable signal BIST_DISEN. (Refer to...) Figures 5A to 5D A conceptual embodiment of the BIST signal generator 430 is described.

[0066] Reference Figure 5A The BIST signal generator 430a can generate a BIST enable signal BIST_EN in response to the power stabilization signal PVCCH, instructing the BIST engine 432 to start BIST. The BIST engine 432 can perform a full memory cell test in response to the BIST enable signal BIST_EN to confirm that all or substantially all memory cells of the memory cell array 122a are operating normally.

[0067] Reference Figure 5B The BIST signal generator 430b can generate a BIST enable signal BIST_EN in response to the ZQ calibration enable signal ZQ_EN. In this case, Figure 5A BIST signal generator 430a and Figure 5B Only one of the BIST signal generators 430b can be selectively controlled to generate the BIST enable signal BIST_EN.

[0068] Reference Figure 5C The BIST signal generator 430c generates the BIST disable signal BIST_DISEN by performing an AND operation on the MPR disable signal MPR_DISEN and the write equalization enable signal WRLVL_EN. The BIST engine 432 can terminate the full-cell memory test of the memory cell array 122a in response to the BIST disable signal BIST_DISEN.

[0069] Reference Figure 5DThe BIST signal generator 430d can generate the BIST disabling signal BIST_DISEN by performing a bitwise AND operation on the MPR disabling signal MPR_DISEN and the ACTIVE signal. In this case... Figure 5C BIST signal generator 430c and Figure 5D One of the BIST signal generators 430d can be selectively controlled to generate the BIST disable signal BIST_DISEN.

[0070] Refer again Figure 4 The BIST enable signal BIST_EN and the BIST disable signal BIST_DISEN generated by the BIST signal generator 430 can be provided to the BIST engine 432.

[0071] The BIST engine 432 provides various test algorithms to test the functionality and reliability of the memory core 122. The BIST engine 432 can interpret and execute the test algorithms to control the sequence of test modes and application timing. The BIST engine 432 can write various test mode data to the memory core 122 and read the written test mode data from the memory core 122 to detect any potential memory defects. By comparing the test mode data with the data read from the memory core 122, the BIST engine 432 can determine whether any memory cell in the memory core 122 is defective.

[0072] The BIST engine 432 can be configured to change DC and / or AC parameters during BIST and programmer user-defined test sequences. DC parameters may include the operating voltage VINTA of the memory cell array 122a, bit line voltage VBL, etc. AC parameters may include the row command delay time tRCD, write recovery time tWR, write latency, etc.

[0073] The BIST engine 432 provides flexibility to test various test sequences. For example, it may be necessary to ensure that the data retention time of the memory cells (MC) of the memory cell array 122a is greater than the refresh interval defined in the standard. Data retention testing can be performed by turning on the memory cell transistor (CT) to charge the memory cell capacitor (CC) with a logic "1" voltage. After the memory cell transistor (CT) is turned off, the BIST engine 432 allows the memory cell capacitor (CC) to remain charged with a logic "1" voltage (this state is called pause), and the logic "1" or "0" in the sense amplifier of the memory core 122 can be determined by reading the potential of the memory cell capacitor (CC). During pause, leakage current may occur due to reverse bias at the PN junction between the memory node of the memory cell capacitor and the semiconductor substrate. Because the charge stored in the memory cell capacitor (CC) is lost due to leakage current, data refresh (repeated read / write operations) may need to be performed at regular intervals for data retention. The refresh characteristics of the memory cells can degrade at high temperatures. Therefore, when screening refresh fault units, the BIST engine 432 can use a temperature sensor in the memory device 120 to screen for hold faults while adjusting the pause time according to the temperature of the memory device 120. In other words, the pause time can be modified when the temperature sensor indicates a temperature change. Subsequently, a refresh fault test of the memory device 120 can be performed to screen for changes in characteristics caused by temperature changes.

[0074] BIST engine 432 can perform a full-cell memory test on memory cell array 122a in response to the BIST enable signal BIST_EN, and terminate the full-cell memory test in response to the BIST disable signal BIST_DISEN. As a result of the full-cell memory test, faulty cells with degraded component characteristics may appear (e.g., cells with short refresh times, cells with degraded cell write characteristics, and / or cells exhibiting variable hold times). BIST engine 432 can store information about faulty cells with such defective characteristics in faulty cell table 434. Faulty cell table 434 can use a fuse array or an antifuse array. The faulty cell information stored in faulty cell table 434 can be provided to BISR unit 128b to assist in repair processing.

[0075] The BISR unit 128b can repair faulty cells by using redundant cells included in the memory cell array 122a for repairing faulty cells. The BISR unit 128b can replace faulty cells with redundant cells by using row repair unit 440 and column repair unit 442. For example, the BISR unit 128b can replace a memory cell group in which a faulty cell exists with a redundant memory cell group. When a faulty cell is generated from a memory cell connected to a bit line, the BISR unit 128b can replace a memory cell connected to that bit line with a memory cell connected to the redundant bit line. The BISR unit 128b can replace a memory cell connected to a portion (bit segment) of a bit line where a faulty cell has been generated with a memory cell connected to a portion of the redundant bit line. In some embodiments, the BISR unit 128b can replace faulty cells with redundant cells. The row repair unit 440 and column repair unit 442 can generate row and column addresses by replacing the addresses indicating the redundant cells used to repair the faulty cells.

[0076] In BISR unit 128b, information that a faulty unit has been repaired by a redundant unit can be stored together with an indication representing the corresponding faulty unit information stored in the faulty unit table 434 of the BIST engine 432. The information stored in the faulty unit table 434 can be controlled by the memory controller (110, ...). Figure 1 ) or host (105, Figure 1 The memory controller 110 or host 105 can control the memory device 120 to interact normally with the memory device 120 by using information stored in the fault cell table 434 and / or information about the repair of redundant cells in the BISR cell 128b.

[0077] Figure 6 It is based on Figure 4 The operation timing diagram of the power-on sequence of the memory device 120. Figure 6 A timing diagram is shown illustrating the operation of memory device 120 based on clock signal CLK according to a communication protocol or standard. Note that the timing diagrams described in the inventive concept are not necessarily drawn to scale.

[0078] Reference Figure 2 , Figure 3 , Figure 4 and Figure 6 At time point T0, a power supply voltage VDD can be applied to the memory device 120 upon power-up. After the power supply voltage VDD stabilizes and the reset signal RESETn remains at a logic low level for a specific period to allow power stabilization, the reset signal RESETn can be triggered. The reset signal RESETn may include a signal that initializes the memory device 120 for proper operation.

[0079] Following the reset operation of memory device 120, according to the power-on sequence of memory system 100 ( Figure 2 and Figure 3 Commands CMD issued to memory device 120 can be sequentially stored in command sequencer 422. Command sequencer 422 can sequentially store MRS commands for instructing MRS 124 settings, ZQ calibration commands ZQCL for instructing ZQ calibration operations, write equalization commands WRLVL, activation commands ACT, write commands WR, read commands RD (not shown), etc. Command sequencer 422 can sequentially output the corresponding commands according to the storage order.

[0080] At time T1, the power detector 410 can detect that the power supply voltage VDD level is stably maintained at the target voltage level, and can trigger the power stabilization signal PVCCH to a logic high level. BIST signal generator (430a, Figure 5A In response to the triggering of the power stabilization signal PVCCH, the BIST enable signal BIST_EN, which instructs the BIST engine 432 to start the BIST, is changed to a logic high level. The BIST enable signal BIST_EN generated based on the power stabilization signal PVCCH can be used as a first option signal for starting the BIST. The BIST engine 432 can start the BIST of the memory core 122 in response to the first option BIST enable signal BIST_EN. The BIST engine 432 can execute a programmed test sequence and then store information about faulty cells exhibiting defective characteristics in the memory cell array 122a in a faulty cell table 434. The BISR cell 128b can repair faulty cells by using redundant cells based on the faulty cell information stored in the faulty cell table 434.

[0081] At time T2, the MRS command stored in the command sequencer 422 can be output. In response to the MRS command, the MRS 124 can be programmed using the appropriate bit values ​​provided on the address bus of the memory interface 130. The MRS 124 can set the operating options of the memory device 120 (such as burst length BL, CAS delay CL, MPR operation function, MPR read format, write equalization, VrefDQ training, read / write DBI function, various functions, features and / or modes).

[0082] At time T3, the ZQ calibration command ZQCL stored in command sequencer 422 can be output. ZQ engine 126 can generate a pull-up calibration code / pull-down calibration code in response to the ZQ calibration command ZQCL by using a resistor RZQ connected to the ZQ terminal 125 and performing pull-up / pull-down calibration. The pull-up / pull-down calibration code can be provided to the input / output buffer to adjust the terminal stored value of the input / output buffer connected to the DQ terminal. Command decoder 420 can generate a ZQ calibration enable signal ZQ_EN based on the ZQ calibration command ZQCL. BIST signal generator (430b, Figure 5B The BIST enable signal BIST_EN can be switched to a logic high level in response to the ZQ calibration enable signal ZQ_EN, causing the BIST engine 432 to start BIST. The BIST enable signal BIST_EN generated based on the ZQ calibration enable signal ZQ_EN can be used as a second option signal for starting BIST. The BIST engine 432 can start the BIST of memory core 122 in response to the second option BIST enable signal BIST_EN. The BIST engine 432 can execute a programmed test sequence and store information about faulty cells with defective characteristics in memory cell array 122a in fault cell table 434. Then, the BISR unit 128b can repair the faulty cells by using redundant units according to the information about the faulty cells stored in the fault cell table 434.

[0083] After the ZQ calibration operation is performed, the memory device 120 can perform memory training using the training unit 128c. The training unit 128c can perform, for example, clock training, address training, write / read equalization, write / read recentering training, etc. When performing memory training, the training unit 128c can perform memory training by reading a preset data pattern in the MPR of the MRS 124. For example, peripheral circuit parameter training (such as data DQ receive enable training (S503) or data strobe signal DQS training (S504)) can be performed by reading a preset timing calibration bit sequence in the MPR.

[0084] At time T4, when the peripheral circuit parameter training is complete, the training unit 128c can trigger the MPR disable signal MPR_DISEN, indicating that training will no longer be performed using MPR. In other words, by setting MPR_DISEN to a logic high level, MPR is in an unused state. The MPR disable signal MPR_DISEN can be provided to the BIST signal generator ( Figure 5C 430c and Figure 5D (430d).

[0085] At time T5, the write equalization command WRLVL, stored in the command sequencer 422, can be output by the command decoder 420. The training unit 128c can respond to the write equalization command WRLVL and perform write equalization to compensate for the skew between the clock signal CLK and the data strobe signal DQS.

[0086] Command decoder 420 can generate a write equalization enable signal WRLVL_EN based on the write equalization command WRLVL. BIST signal generator ( Figure 5C 430c) can generate a logic high BIST disable signal BIST_DISEN by performing a bitwise AND operation on the MPR disable signal MPR_DISEN and the write equalization enable signal WRLVL_EN. The BIST disable signal BIST_DISEN generated based on the write equalization enable signal WRLVL_EN can be used as a first option signal for terminating BIST. BIST engine 432 can terminate the BIST of memory core 122 in response to the first option BIST disable signal BIST_DISEN.

[0087] At time points T6 and T7, the activation command ACT and the write command WR, respectively, based on the write equalization command stored in the command sequencer 422, can be output. The command decoder 420 can generate the activation signal ACTIVE based on the activation command ACT. (BIST signal generator) Figure 5D 430d) can generate a BIST disable signal BIST_DISEN at a logic high level by performing a AND operation on the MPR disable signal MPR_DISEN and the ACTIVE activation signal. The BIST disable signal BIST_DISEN generated based on the ACTIVE activation signal can be used as a second option signal for terminating BIST. BIST engine 432 can terminate the BIST of memory core 122 in response to the second option BIST disable signal BIST_DISEN.

[0088] Subsequently, training unit 128c can perform training of the data strobe signal DQS for data DQ, deskew operation of data DQ, VrefDQ training, and training of the data strobe signal DQS for setting the lead time. Memory device 120 can be configured to write or read data using the training result values ​​of training unit 128c under optimized operating parameter settings.

[0089] Figure 7 This is a block diagram illustrating a processor-memory system 700 for mounting an RDIMM 720 with a memory device 120, according to an embodiment of the inventive concept.

[0090] Reference Figure 7The processor-memory system 700 may include a board 701 on which one or more RDIMMs 720 and a processor 705 are connected via one or more memory channels 702. A bidirectional data bus 703, through which data DQ is transferred, may be connected to the host interface 710 of the memory device 120 and the processor 705, respectively. The processor 705 may include a single-core processor or a multi-core processor.

[0091] Clock signal line CLK 704 and C / A signal line 706 can be provided from host interface 710 to register clock driver RCD 110. RCD 110 can provide the clock signal CLK received via clock signal line CLK 704 to each of the plurality of memory devices 120, and provide control signals / command signals / address signals received via C / A signal line 706 to each of the plurality of memory devices 120. RCD 110 can be connected to the plurality of memory devices 120 in a fly-through manner, and a module terminating resistor can be connected to C / A signal line 706.

[0092] Memory device 120 can be referenced Figures 1 to 6 The memory device 120 described is the same as or similar to the memory device 120. The memory device 120 may include a BIST cell 128a, a BISR cell 128b, and a training cell 128c for testing the memory cell array 122a during a power-on sequence. The BIST cell 128a may perform tests on the memory cell array 122a in response to a power stabilization signal PVCCH or in response to a ZQ calibration command ZQCL. The BIST cell 128a may terminate the ongoing test in response to a write equalization command WRLVL or in response to an activation command ACT. The BIST cell 128a may store information about faulty cells with defective characteristics in the memory core 122 as test results of the memory cell array 122a. The BISR cell 128b may replace defective cells with redundant cells included in the memory core 122. The BISR cell 128b may store information about defective cells that have been repaired with redundant cells, along with information about the defective cells themselves. In response to a training command, training unit 128c can perform memory core parameter training related to memory core 122 and / or peripheral circuit parameter training for other peripheral circuits in memory device 120 excluding memory core 122. Training unit 128c can determine improved or optimal parameters for memory core parameters and / or peripheral circuit parameters as a training object.

[0093] Figure 8 This is a block diagram illustrating a processor-memory system 800 for an LRDIMM 820 with a memory device 120 mounted, according to an embodiment of the inventive concept.

[0094] Reference Figure 8 The processor-memory system 800 may include a board 801 on which one or more LRDIMMs 820 and a processor 805 are connected via one or more memory channels 802. The LRDIMM 820 and... Figure 7 The difference between RDIMM 720 and RDIMM 820 is that RDIMM 820 also includes a data buffer (DB) 120D connected to each of the multiple memory devices 120 in a one-to-one correspondence. For Figure 7 The description of LRDIMM 820 given in RDIMM 720 is omitted. Memory device 120 may include, for example, DRAM.

[0095] The bidirectional data bus 807, through which data DQ is transmitted, can be connected to each DB 120D. On-Die Termination (ODT) can be provided to each DB 120D connected to the data bus 807. When data DQ is bidirectionally transmitted to the data bus 807, the data strobe signal DQS can also be transmitted.

[0096] Figure 8 The memory device 120 can be referenced Figures 1 to 6 The memory device 120 described is the same as or similar to the memory device 120. The memory device 120 may include a BIST cell 128a, a BISR cell 128b, and / or a training cell 128c for testing the memory cell array 122a during a power-on sequence. The BIST cell 128a may perform tests on the memory cell array 122a in response to a power stabilization signal PVCCH or in response to a ZQ calibration command ZQCL. The BIST cell 128a may terminate an ongoing test in response to a write equalization command WRLVL or in response to an activation command ACT. The BIST cell 128a may store information about faulty cells with defective characteristics in the memory core 122 as test results of the memory cell array 122a. The BISR cell 128b may replace defective cells with redundant cells included in the memory core 122. The BISR cell 128b may store information about defective cells that have been repaired with redundant cells, along with information about the defective cells themselves. In response to a training command, training unit 128c can perform training on memory core parameters related to memory core 122 and / or training on peripheral circuit parameters of other peripheral circuits in memory device 120 excluding memory core 122. Training unit 128c can serve as a training object to determine the optimal parameters for memory core parameters and / or peripheral circuit parameters.

[0097] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A memory device, the memory device comprising: Memory core, including memory cell array; The impedance control engine is configured to perform impedance control calibration operations by using an impedance control resistor connected to the impedance control terminal in response to an impedance control calibration command. as well as The built-in self-test unit is configured to generate a test enable signal in response to an impedance control calibration command, and is configured to initiate a first test based on the test enable signal generated in response to the impedance control calibration command, the first test including a test of the memory cell array.

2. The memory device according to claim 1, further comprising: A power detector is configured to generate a power stabilization signal based on whether the level of the power supply voltage applied to the memory device is stably maintained at a target voltage level when the memory device is powered on. The second test responds to a power stabilization signal and includes performing a test on the memory cell array. The built-in self-test unit is configured to test the memory cell array by selecting one of the first test and the second test.

3. The memory device according to claim 1, further comprising: The training unit is configured to perform memory core parameter training related to the memory core in response to training commands.

4. The memory device according to claim 3, in, The training unit is also configured to compensate for the skew between the clock signal and the data strobe signal in response to a write equalization command, and The built-in self-test unit is also configured to: in response to a write balancer command, terminate the first test performed by the built-in self-test unit.

5. The memory device according to claim 4, in, The training unit is also configured to receive activation commands to access the memory cell array during memory core training. The built-in self-test unit is also configured to: in response to an activation command, terminate the second test on the first test being executed by the built-in self-test unit, and The built-in self-test unit is also configured to terminate the test of the memory cell array by selecting one of the first test termination and the second test termination.

6. The memory device according to claim 5, in, The training unit is also configured to perform peripheral circuit parameter training on other peripheral circuits in the memory device, excluding the memory core. The training unit is further configured to generate a disable signal after the peripheral circuit parameter training is performed. This disable signal indicates that a preset data mode in the mode register of the memory device is not used. The built-in self-test unit is also configured to selectively execute either a first test termination or a second test termination based on a disable signal.

7. The memory device according to claim 1, further comprising: The fault cell table is configured to store information related to fault cells with defective characteristics in the memory cell array as the result of the first test. as well as The built-in self-healing unit is configured to replace faulty cells with redundant cells from the memory cell array. The built-in self-repair unit is configured to store information related to repairing faulty units with redundant units in a faulty unit table.

8. A method of operating a memory device, wherein, A built-in self-test unit is configured to test a memory core, wherein the built-in self-test unit is embedded in a memory device, the method comprising: Receive impedance control calibration commands from outside the memory device; Perform impedance control calibration operation in response to impedance control calibration command; Generate a test enable signal in response to an impedance control calibration command; and The first test of the memory core is initiated via the built-in self-test unit based on the test enable signal generated in response to the impedance control calibration command. The first test includes testing the memory cell array.

9. The method according to claim 8, further comprising: When the memory device is powered on, a power supply voltage is applied to the memory device; A power supply stability signal is generated by detecting whether the power supply voltage level is stably maintained at the target voltage level. as well as In response to a power stabilization signal, a second test of the memory core is initiated via the built-in self-test unit. This second test includes performing a test on the memory cell array. The built-in self-test unit is configured to test the memory core by selecting one of the first test and the second test.

10. The method according to claim 8, further comprising: Perform memory core parameter training related to the memory core.

11. The method according to claim 10, further comprising: During memory core training, a write equalization command is received, which compensates for the skew between the clock signal and the data strobe signal from outside the memory device. as well as In response to the write balancer command, execute the first test termination to terminate the first test executed by the built-in self-test unit.

12. The method according to claim 11, further comprising: During memory core training, an activation command is received, which enables access to the memory core. as well as In response to the activation command, a second test termination is executed to terminate the first test being performed by the built-in self-test unit. The built-in self-test unit is configured to terminate the test of the memory core by selecting one of the first test termination and the second test termination.

13. The method according to claim 12, further comprising: Training of peripheral circuit parameters for the memory device, excluding the memory core; as well as After performing peripheral circuit parameter training, a disable signal is generated. The disable signal indicates that the preset data mode in the mode register of the memory device is not used. The built-in self-test unit is configured to selectively execute either a first test termination or a second test termination based on a disable signal.

14. The method according to claim 8, further comprising: Information related to faulty cells with defective characteristics in the memory cells of the memory core is used as the result of the first test; Repair faulty cells using redundant cells in the memory core; as well as Information related to repairing faulty cells using redundant units is stored in the faulty cell table.

15. A memory module, the memory module comprising: Printed circuit boards; as well as Multiple memory devices are connected to a printed circuit board. Each of the plurality of memory devices includes: Memory core, including memory cell array; The impedance control engine is configured to: perform an impedance control calibration operation by using an impedance control resistor connected to the impedance control terminal in response to an impedance control calibration command; and The built-in self-test unit is configured to generate a test enable signal in response to an impedance control calibration command, and is configured to initiate a first test based on the test enable signal generated in response to the impedance control calibration command, the first test including a test of the memory cell array.

16. The memory module according to claim 15, in, Each of the plurality of memory devices further includes a power detector configured to generate a power stabilization signal based on whether the level of the power supply voltage applied to each of the plurality of memory devices is stably maintained at a target voltage level when the memory module is powered on. The second test responds to a power stabilization signal and includes performing a test on the memory cell array. The built-in self-test unit is also configured to test the memory cell array by selecting one of the first test and the second test.

17. The memory module according to claim 15, in, Each of the plurality of memory devices further includes: a fault cell table, configured to store information relating to fault cells in the memory cells that have defective characteristics as the result of a first test. The built-in self-healing unit is also configured to replace faulty units with redundant units in the memory cell array, and The built-in self-repair unit is also configured to store information related to repairing faulty units with redundant units in a faulty unit table.

18. The memory module according to claim 15, further comprising: The controller is connected to the printed circuit board. The controller is configured to control the plurality of memory devices.

19. The memory module according to claim 18, in, The controller includes a register clock driver configured to provide clock signals and command / address signals to each of the plurality of memory devices. Each of the plurality of memory devices further includes a command sequencer, which is used to queue command signals provided by the controller according to the power-on sequence of the memory modules. The command sequencer is configured to sequentially store stored commands including the following commands: impedance control calibration command, training command for instructing memory training, write equalization command, activation command, and / or write command. The command sequencer is also configured to output stored commands in the order they are stored.

20. The memory module according to claim 15, in, The memory module includes any one of the following: unbuffered dual in-line memory module (DIMM), register-equipped DIMM, low-load DIMM, fully buffered DIMM, and small outline DIMM.

Images