Semiconductor device packages

Abstract

The present invention relates to semiconductor device packages. In general, a semiconductor device may include a substrate and a positive power terminal electrically coupled to the substrate, the positive power terminal being arranged in a first plane. The device may also include a first negative power terminal, the first negative power terminal being laterally disposed from the positive power terminal and arranged in the first plane. The device may also include a second negative power terminal, the second negative power terminal being laterally disposed from the positive power terminal and arranged in the first plane. The positive power terminal may be disposed between the first negative power terminal and the second negative power terminal. The device may also include a conductive clip electrically coupling the first negative power terminal to the second negative power terminal via a conductive bridge. A portion of the conductive bridge may be arranged in a second plane, the second plane being parallel to and non-coplanar with the first plane.

Description

Technical Field

[0001] The present invention relates to semiconductor device packages (packaged devices), and more particularly, to packaged devices that implement parallel current paths to reduce stray inductance. Background Art

[0002] Semiconductor devices may be included in a package assembly, wherein such a package assembly may include one or more semiconductor devices (semiconductor dies). The performance of semiconductor devices in such a package assembly may be adversely affected by parasitic impedances, such as parasitic (stray) inductances. For example, the performance of power semiconductor devices in an associated package assembly may be affected by stray inductances caused by magnetic fields associated with the high currents conducted by those power semiconductor devices. Current package assemblies are limited in the measures that can be implemented to reduce such stray inductances (e.g., due to design rules, etc.). Therefore, alternative methods for reducing stray (parasitic) inductances would be beneficial in order to improve the performance of power semiconductor devices included in the package assembly. Summary of the Invention

[0003] In general, a packaged semiconductor device may include a substrate and a positive power terminal electrically coupled to the substrate, the positive power terminal being arranged in a first plane. The packaged device may also include a first negative power terminal disposed laterally from the positive power terminal and disposed in the first plane. The packaged device may also include a second negative power terminal disposed laterally from the positive power terminal and disposed in the first plane. The positive power terminal may be disposed between the first negative power terminal and the second negative power terminal. The packaged device may also include a conductive clip electrically coupling the first negative power terminal to the second negative power terminal via a conductive bridge. A portion of the conductive bridge may be disposed in a second plane that is parallel to and non-coplanar with the first plane. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a schematic diagram illustrating a power semiconductor circuit that may be included in a packaged semiconductor device according to one embodiment.

[0005] Figures 2A to 2E is a schematic diagram showing various views of a packaged semiconductor device according to one embodiment.

[0006] Figure 3 is a diagram showing a method for Figures 2A to 2E Schematic diagram of the current path of a packaged semiconductor device.

[0007] Figure 4A and Figure 4B It is shown that according to one embodiment, Figures 2A to 2E and Figure 3 Schematic diagram of a semiconductor device in a packaged semiconductor device.

[0008] Figures 5A to 5G is a schematic diagram generally illustrating a manufacturing flow that can be used to produce the packaged semiconductor devices described herein.

[0009] Figure 6 is a flow chart illustrating a method for producing a packaged semiconductor device, which can be implemented Figures 5A to 5G manufacturing process.

[0010] The same reference numerals in the various drawings indicate the same elements. Reference numerals for some similar elements may not be repeated for all such elements. In some cases, different reference numerals may be used for identical or similar elements. Some reference numerals for certain elements of a given embodiment may not be repeated in each drawing corresponding to that embodiment. Some reference numerals for certain elements of a given embodiment may be repeated in other drawings corresponding to that embodiment, but may not be discussed in detail with reference to each corresponding drawing. DETAILED DESCRIPTION

[0011] The present disclosure relates to packaged semiconductor device apparatus and associated manufacturing methods. The methods described and illustrated herein can be used to produce packaged semiconductor devices that operate with reduced stray inductance, compared to current implementations in which stray inductance can be measured as a series inductance between power supply terminals. As indicated above, such stray inductance (e.g., during operation of a given device) is caused by magnetic fields generated by current flowing into and out of the power supply terminals, where the magnetic field lines caused by current associated with one power supply terminal are incident on the current path associated with another (e.g., coplanar) power supply terminal (and vice versa).

[0012] In the methods described herein, stray inductance may be reduced due to the implementation of power terminals (e.g., DC+ and DC- terminals) and the internal routing of currents associated with the respective power terminals using a plurality of conductive clips such that the respective current paths of these currents are substantially parallel to one another. That is, in the disclosed embodiments, the current paths may be configured such that the general direction of current flow associated with one power terminal is parallel to the general direction of current flow associated with another power terminal. Such an arrangement may reduce the stray inductance of a power semiconductor device or module. For example, such a reduction in stray inductance may be achieved due to the overlap (e.g., increased overlap) between the respective magnetic fields corresponding to the current associated with each power terminal, causing these magnetic fields to cancel each other rather than impinging on the opposing power terminals in the absence of a parallel arrangement.

[0013] Figure 1FIG2 is a schematic diagram illustrating a power semiconductor circuit 100 that may be included in a packaged semiconductor device according to one embodiment. Circuit 100 (a power transistor pair) is provided by way of example and for illustrative purposes. In other embodiments, the methods described herein may be used in conjunction with other semiconductor devices, other power semiconductor circuits, other semiconductor device modules, and the like. Although certain elements of circuit 100 are referenced with respect to other figures, other arrangements and / or methods are possible in other embodiments.

[0014] like Figure 1 As shown, circuit 100 may include a first power semiconductor device, an insulated gate bipolar transistor (IGBT) 110, and a second power semiconductor device, an IGBT 120. IGBTs 110 and 120 may be implemented in one or more semiconductor dies. In other embodiments, other power semiconductor devices, such as power metal oxide semiconductor field effect transistors (power FETs), may be used, or circuits having other arrangements may be implemented. In some embodiments, IGBT 110 and IGBT 120 may each include a plurality of IGBTs coupled in parallel to one another. For example, IGBT 110 may include two or more IGBTs coupled in parallel to one another, and IGBT 120 may include two or more IGBTs coupled in parallel to one another.

[0015] In circuit 100, IGBT 110 includes a collector 112, an emitter 114, and a gate 116. Similarly, IGBT 120 includes a collector 122, an emitter 124, and a gate 126. Emitter 114 of IGBT 110 and collector 122 of IGBT 120 are electrically coupled to a common node of circuit 100, at which an output signal (e.g., a regulated voltage) may be generated by circuit 100.

[0016] In circuit 100, a positive power supply terminal 140 (e.g., a DC+ terminal, a Vdd terminal, etc.) can be coupled to the collector 112 of IGBT 110. A negative power supply terminal 150 (e.g., a DC- terminal, an electrical ground terminal, etc.) can be coupled to the emitter 124 of IGBT 120. In some embodiments, such as those described herein, the negative power supply terminal 150 can use multiple negative power supply terminals (e.g., Figures 2A to 2E Terminals 150a and 150b in FIG) and a conductive clip 210 (e.g., such as Figures 2A to 2E The conductive clip 210 shown in FIG2 is implemented to provide a positive power current I in the power terminal. P and negative supply current I N Provide parallel current paths, as indicated in the figure. Additionally, as described with respect to the embodiments disclosed herein, the components of the packaged semiconductor device may be arranged such that the positive supply current I Pand negative supply current I N The corresponding internal current paths are also parallel (generally parallel, substantially parallel, etc.).

[0017] Additionally, an output terminal 160 of circuit 100 can be coupled to a common node of emitter 114 of IGBT 110 and collector 122 of IGBT 120. As further described below, positive power supply terminal 140, one or more negative power supply terminals 150, and output terminal 160 can be implemented using metal terminals (copper terminals, metal leads) included in a packaged semiconductor device. For example, in some embodiments, positive power supply terminal 140 and output terminal 160 can be electrically and physically coupled to a substrate on which IGBT 110 and IGBT 120 are implemented. One or more negative power supply terminals 150 can be electrically and physically coupled to a conductive clip included in the packaged semiconductor. For example, terminals 140 and 160 can be directly bonded (using direct lead attachment (DLA)) to the substrate, while one or more terminals 150 can be directly bonded (using DLA) to the conductive clip, such as in the exemplary embodiments described below.

[0018] like Figure 1 As further shown, the circuit 100 may also include a plurality of signal leads 170 electrically coupled to the respective gate terminals of the IGBT 110 and the IGBT 120. For example, Figure 1 As shown, the first signal lead 170 can be electrically coupled to the gate terminal 116 of the IGBT 110, and the second signal lead 170 can be electrically coupled to the gate terminal 126 of the IGBT 120. In other embodiments, the signal leads 170 can be electrically coupled (or operatively coupled) to other components included in the circuit 100, such as a control circuit (not shown). The specific signal leads 170 (and the connections to / from the signal leads 170) implemented in the circuit 100 will depend on the specific embodiment and the specific configuration of the circuit. As some examples, the signal leads 170 can include gate control signal leads (e.g., Figure 1 As shown), temperature sensing signal leads, voltage sensing signal leads, etc.

[0019] Figures 2A to 2E is a schematic diagram showing various views of a packaged semiconductor device (device) 200 according to one embodiment. In some embodiments, device 200 may implement circuit 100, may implement a similar circuit (e.g., including additional components such as passive devices, control circuits, etc.), or may implement a different circuit. However, for illustrative purposes, further reference is made to Figure 1 , the exemplary device implementations shown herein will be described as implementing circuit 100 .

[0020] Figure 2A A plan view of the device 200 is shown, and Figure 2B An isometric view of the device 200 is shown. Figure 2A and Figure 2B As shown, the device 200 may include a plurality of negative power supply terminals 150a and 150b, an output terminal 160, and a signal lead 170 of the circuit 100. The device 200 may also include a conductive clip (first conductive clip) 210 and a molding compound 200 (e.g., gel molding compound, epoxy molding compound, etc.) that encapsulates the components of the device 200, such as in the exemplary embodiments shown in the drawings and described herein. The device 200 may also include the positive power supply terminal 140 of the circuit 100, Figure 2A and Figure 2B In the view shown in FIG. 2 , the positive power terminal is blocked by the conductive clip 210 .

[0021] In the device 200, the conductive clip 210 includes a first portion 210a that is coupled (e.g., physically and electrically) to the negative power supply terminal 150a, such as using solder. The conductive clip 210 also includes a second portion 210b that is coupled (e.g., physically and electrically) to the negative power supply terminal 150b, such as using solder. Figure 2A and Figure 2B As shown, the conductive clip 210 further includes a third portion including a conductive bridge 210c that electrically couples the first portion 210a and the first negative power supply terminal 150a with the second portion 210b and the second negative power supply terminal 150b. The conductive clip 210 of the device 200 further includes a plurality of conductive contact fingers 210d that can be coupled to another conductive clip (e.g., a conductive bridge 210c) at least partially encapsulated in the molding compound 220. Figure 2D For example, in some embodiments, the contact points for coupling the second conductive clip to the conductive contact fingers 210d can be exposed through the molding compound 210d.

[0022] refer to Figure 2A , showing direction lines 2C, 2D and 2E, wherein the direction lines are respectively Figure 2C 、 Figure 2D and Figure 2E The side view of the device 200 shown corresponds to the viewing direction. Figure 2C For device 200 along Figure 2A A side view of the direction line 2C, Figure 2D For device 200 along Figure 2A The direction lines in the 2D side view, and Figure 2E For device 200 along Figure 2A Side view of the direction line 2E. Figure 2D The side view of is an x-ray view showing the internal structure of the device 200. Figure 2A and Figure 2BThe view shown Figure 1 Sample, Figure 2C and Figure 2D The positive power supply terminal 140 in the first negative power supply terminal 150a (in Figure 2C ) is blocked or blocked by the second negative power supply terminal 150b (in Figure 2D (in the middle) plane, because the positive power terminal 140, the first negative power terminal 150a and the second negative power terminal 150b are all arranged in the same (first) plane.

[0023] refer to Figure 2C , shows the arrangement of the output terminals 160 and the signal leads 170 along respective sides of the device 200. Figure 2C As shown, the output terminal 160 and the signal leads 170 may extend out of the molding compound 220 , with a portion of the output terminal 160 and a corresponding portion of each of the signal leads 170 disposed within (encapsulated in) the molding compound 220 .

[0024] Figure 2C The arrangement of the first negative power terminal 150a and the conductive clip 210 is further shown. Figure 2C As shown, the first portion 210a of the conductive clip 210 is disposed on (coupled to, welded to, etc.) the first negative power terminal 150a. In addition, the conductive bridge 210c of the conductive clip 210 is spaced apart from the first negative power terminal 150a and is also spaced apart from the positive power terminal ( Figure 2C The conductive bridge 210c of the conductive clip 210 can be arranged in a plane (a second plane) that is parallel to but not coplanar with the first plane (in which the positive and negative power terminals 150a and 150b are arranged).

[0025] refer to Figure 2D , shows a side (x-ray) view of the device 200, which illustrates the internal structure of the device 200 and its relationship to other elements of the device 200 (such as the internal structure discussed further below). Figure 2C The arrangement of the first negative power terminal 150a and the conductive clip 210 is similar, Figure 2D Also shown is the arrangement of the second negative power terminal 150b and the conductive clip 210. For example, Figure 2D As shown, the second portion 210b of the conductive clip 210 is disposed on (coupled to, welded to, etc.) the second negative power terminal 150b. In addition, the conductive bridge 210c of the conductive clip 210 is spaced apart (in different parallel planes) from the second negative power terminal 150b and is also spaced apart from the positive power terminal. Figure 2C similar, Figure 2DThe positive power terminal in the embodiment is shielded by the second negative power terminal 150b (behind the second negative power terminal). However, the conductive contact finger of the positive power terminal 140 (which may be disposed within the molding compound 220) is located in the mold. Figure 2D Shown in.

[0026] exist Figure 2D In the exemplary device 200, the conductive contact fingers 210d of the conductive clip 210 can be coupled (electrically coupled, welded, etc.) to a second conductive clip 240 (at least partially) disposed within the molding compound 220. For example, as noted above, contact points on the conductive clip 240 for attaching the conductive contact fingers 210d of the conductive clip 210 can be exposed through the molding compound (e.g., by etching, grinding, using a molding jig, etc.).

[0027] like Figure 2D As shown, the device 200 further includes a substrate 230, the IGBTs 110 and 120 of the circuit 100 (which are implemented as a first semiconductor die and a second semiconductor die), and a further (third) conductive clip 250. The substrate 230 includes a first metal layer 230a and a second metal layer 230b electrically isolated from the first metal layer 230a. Figure 2D As shown, IGBT 110 (in the form of a first semiconductor die) can be disposed on first metal layer 230a. For example, referring to circuit 100, in this example, the collector terminal 112 (e.g., a backside collector contact) of the semiconductor die implementing IGBT 110 (e.g., the high-side transistor of a power transistor pair) can be coupled to first metal layer 230a. Additionally, one (or more) conductive contact fingers of positive power terminal 140 are coupled to metal layer 230a of substrate 230 (e.g., electrically coupled using a DLA). Thus, in device 200 of reference circuit 100, positive power terminal 140 is coupled to collector terminal 112 of IGBT 110 via metal layer 230a.

[0028] exist Figure 2D In the exemplary embodiment of the present invention, in addition to the conductive clip 210, the second negative power terminal 150b (and the first negative power terminal 150a, which is Figure 2D ) is also coupled (e.g., electrically coupled using DLA) to the conductive clip 240. Figure 2D In the example shown, the conductive clip 240 is coupled (electrically coupled) to the IGBT 120. For example, referring to the circuit 100, the conductive clip 240 can be coupled (soldered) to the emitter terminal 124 of the IGBT 120 (e.g., the low-side transistor of the circuit 100 implemented in the second semiconductor die). Therefore, in the device 200, the first negative power supply terminal 150a, the second negative power supply terminal 150b, and the conductive clip 210 are electrically coupled to the emitter terminal 124 of the IGBT 120 via the conductive clip 240.

[0029] Also like Figure 2D As shown, the semiconductor die implementing the IGBT 120 can be disposed on the second metal layer 230b of the substrate 230. For example, referring to the circuit 100, in this example, the collector terminal 122 (e.g., the backside collector contact) of the semiconductor die implementing the IGBT 120 (e.g., the low-side transistor of the power transistor pair) can be coupled to the second metal layer 230b. In the device 200, the metal layer 230b corresponds to (is electrically coupled to) the output terminal 160 of the circuit 100. For example, as Figure 2D As shown, one (or more) conductive contact fingers) of the output terminal 160 are coupled (electrically coupled) to the metal layer 230b.

[0030] In the device 200, as Figure 2D As shown, the third conductive clip 250 electrically couples the emitter terminal 114 of the semiconductor die implementing the (high-side) IGBT 110 with the second metal layer 230b of the substrate (eg, the output terminal 160 and the collector terminal 122 of the IGBT 120). Figure 2D 2 , the second conductive clip 240 and the third conductive clip 250 are arranged in a non-coplanar arrangement parallel to each other. In this example, as the conductive clip 240 conducts current associated with the negative power supply terminal 150 of the circuit 100 and the conductive clip 250 conducts current associated with the positive power supply terminal 140 of the circuit 100, their parallel arrangement can cause the magnetic fields associated with their respective currents to (at least partially) cancel each other, thereby resulting in a reduction in stray inductance in the device 200 compared to current devices (e.g., implemented with coplanar current conduction).

[0031] like Figures 2A to 2D (as well as Figure 2E ), in device 200, molding compound 220 partially encapsulates substrate 230, wherein a surface (e.g., the bottom surface) of substrate 230 is exposed through molding compound 220. This surface of substrate 230 can be used to attach a heat transfer mechanism, such as a heat sink, a water jacket, etc. In device 200, as noted above, molding compound 220 also partially encapsulates conductive clip 240, wherein one or more portions of conductive clip 240 (e.g., the contact points of conductive clip 210) are exposed through molding compound 220.

[0032] Additionally, in device 200, molding compound 220 may encapsulate (completely encapsulate) conductive clip 250 and the semiconductor die implementing IGBTs 110 and 120. As previously noted, in device 200, first negative power terminal 150a, second negative power terminal 150b, and conductive clip 210 are at least partially disposed outside molding compound 220. For example, first negative power terminal 150a and second negative power terminal 150b may extend out of molding compound 220 (with respective portions disposed within molding compound 220), while conductive clip 210 may be disposed completely outside molding compound 220.

[0033] As pointed out above, Figure 2E The device 200 is shown along Figure 2A Schematic diagram of a view of direction line 2E shown. Figure 2E The view in FIG. 1 shows the arrangement of the negative power terminals 150 a and 150 b , the conductive clip 210 , and the positive power terminal 140 of the device 200 . Figure 2E Also shown is the arrangement of the signal leads 170 in the device 200 when viewed along direction line 2E. Figure 2C ) and signal leads 170 (e.g., as Figure 2C and Figure 2E As shown in FIG, the positive power terminal 140 and the negative power terminals 150a and 150b may extend out of the molding compound 220, wherein a portion of the positive power terminal 140 and a corresponding portion of each of the negative power terminals 150a and 150b are disposed within (encapsulated in) the molding compound 220.

[0034] like Figure 2E As shown, the positive power terminal 140 and the negative power terminals 150a and 150b of the device 200 are arranged in a first plane P1 (e.g., are coplanar). The negative power terminals 150a and 150b are laterally arranged from the respective sides (edges, etc.) of the positive power terminal 140 in the plane P1. That is, in the device 200, the positive power terminal 140 is arranged between the negative power terminals 150a and 150b. Figure 2E As shown, a first portion 210a of the conductive clip 210 is coupled to the negative power terminal 150a, and a second portion 210b of the conductive clip 210 is coupled to the negative power terminal 150b.

[0035] In the device 200, as Figure 2E As shown, the conductive bridge 210c of the conductive clip 210 is arranged in a second plane P2, wherein the plane P2 is parallel to the plane P1 but not coplanar. In other words, the conductive bridge 210c is parallel to and spaced apart from the positive power terminal 140. For example, Figure 2E As shown (see also at least Figure 2D), the line L1 orthogonal to the first plane and the second plane may be due to the parallel arrangement (and vertical alignment, such as Figure 2E shown) and intersects with both.

[0036] Because the conductive clip 210 in the device 210 is configured to conduct current associated with the negative power supply terminals 150a and 150b, this parallel arrangement with the positive power supply terminal 140 allows for the cancellation of magnetic fields generated by the corresponding currents conducted by the positive power supply terminal 140 and the conductive clip 210. Such magnetic field cancellation allows for a reduction in stray inductance in the device 200 (during operation) compared to current semiconductor device packages implementing circuits similar to the circuit 100. Furthermore, because the negative power supply terminals 150a and 150b are disposed on either side of the positive power supply terminal 140, respectively, an additional reduction in stray inductance can be achieved, as such an arrangement allows for additional cancellation of the corresponding magnetic fields.

[0037] Figure 3 is a diagram showing a method for Figures 2A to 2E Schematic diagram of a current path of a packaged semiconductor device 200 . Figure 3 The device 200 in FIG. Figure 2D The device 200 is shown rotated 90 degrees clockwise. Figure 3 , only a portion of the output terminal 160 outside the molding compound 220 is shown (as indicated by the cutting line). Figure 3 The reference numbers of the elements of device 200 are included for use with at least Figures 2A to 2E However, for the sake of brevity, no longer relative to Figure 3 Each of these elements is described in detail.

[0038] exist Figure 3 For further reference Figure 1 1 , lines 310a, 310b, and 310c (which may be collectively referred to as lines 310) schematically illustrate currents associated with the negative power supply terminal 140 of the circuit 100. For example, line 310a schematically illustrates current associated with the negative power supply terminal 150 of the circuit 100 flowing through the conductive clip 210 in the device 200. Similarly, line 310b schematically illustrates current associated with the negative power supply terminal 150 of the circuit 100 flowing through the negative power supply terminals 150a and 150b of the device 200. Figure 3Line 310c in FIG2 schematically illustrates the combination of the currents indicated by lines 310a and 310b in conductive clip 240 (e.g., continuing to emitter terminal 124 of the semiconductor die implementing IGBT 120). Current 310c can be conducted between conductive clip 240 and output terminal 160 through IGBT 120 (when turned on) and second metal layer 230b of substrate 230. Thus, in the embodiment of circuit 100 in device 200, the current path between output terminal 160 and first negative power supply terminal 150a, and between second negative power supply terminal 150b and conductive clip 210 (hereinafter referred to as the first current path) sequentially from output terminal 160 includes metal layer 230b of substrate 230, semiconductor die implementing IGBT 220, and conductive clip 240.

[0039] like Figure 3 As shown, substrate 230 may further include a third metal layer 230c disposed on a side of substrate 230 opposite first metal layer 230a and second metal layer 230b. In this exemplary embodiment, third metal layer 230c may be electrically isolated from first metal layers 230a and 230b by insulating layer 230d of substrate 230. In some embodiments, insulating layer 230d may be a ceramic layer or other electrically insulating material. In some embodiments, a surface of third metal layer 230c may be exposed through molding compound 220, and a heat dissipation mechanism (not shown) (such as a heat sink) may be coupled to third metal layer 230c to dissipate heat energy generated during operation of device 200 (e.g., by IGBTs 110 and 120).

[0040] like Figure 3 As shown, line 320 indicates the power supply from the positive power supply terminal 140 (at Figure 3 The current path (hereinafter referred to as the second current path) to the output terminal 160 is blocked. Figure 3 As shown, the current path, starting from positive power supply terminal 240, may include metal layer 230a of substrate 230, the semiconductor die implementing IGBT 110, conductive clip 250, and metal layer 230b of substrate 230. It will be understood that turning IGBT 110 on and off will regulate the conduction of current along the second current path indicated by line 320.

[0041] like Figure 3 As shown, the first current path and the second current path are generally arranged along line C1, wherein the current flow direction changes due to the structure of the components of device 200 and the transition of the current path between the various components of device 200. For example, clips 240 and 250 can have changes in direction, wherein those changes in direction can have different radii of curvature in order to maintain the first current path (e.g., with respect to the negative supply current I N Correspondingly, for example, Figure 1 shown) and a second current path (e.g., with the positive supply current I P Correspondingly, for example, Figure 1 That is, the parallel current paths may follow changes in their directions due to deflections caused by the arrangement of the various elements of the device 200. For example, Figure 3 As shown, the first current path and the second current path can generally be arranged along line C1, parallel to each other (substantially parallel, generally parallel, etc.) along their respective lengths, wherein the first current path and the second current path both terminate at metal layer 230b (e.g., at output terminal 160).

[0042] In addition to the stray inductance reduction achieved by the arrangement of conductive bridge 210c and positive power supply terminal 140, this parallel arrangement of the respective current paths indicated by lines 310 and 320 allows for the cancellation of magnetic fields induced by the respective currents conducted along those paths. This magnetic field cancellation can result in a further reduction in the stray inductance of device 200 compared to a packaged semiconductor device implementing a similar circuit without such a parallel arrangement (e.g., with coplanar current conduction). For example, in some embodiments, the stray inductance of exemplary device 200 can be one-fifth or less (e.g., one-tenth) of the stray inductance of current packaged embodiments.

[0043] Figure 4A and Figure 4B It is shown that according to one embodiment, Figures 2A to 2E and Figure 3 FIG. 4 is a schematic diagram of a semiconductor device 400 in a packaged semiconductor device. For example, the semiconductor device 400 can be used to implement the IGBTs 110 and 120 of the circuit 100. In some embodiments, the device 400 can be a fan-out wafer-level package device.

[0044] Figure 4A A first side (eg, top side) of the device 400 is shown, while Figure 4B A second side (eg, bottom side) of the device 400 is shown. Figure 4A As shown, the device 400 may include an emitter terminal contact 412 for an IGBT implemented in the device 400. Figure 4A As shown, the device 400 may include a gate terminal contact 416 for an IGBT of the device 400. Figure 4B As shown, the device 400 may include a (backside) collector terminal contact 414 for the device 400 .

[0045] Figures 5A to 5G is a schematic diagram generally illustrating a manufacturing process that can be used to produce the packaged semiconductor devices described herein. For example, Figures 5A to 5GThe manufacturing process can be used, for example, according to the following discussion Figure 6 600 to produce the exemplary device 200. Therefore, for the purpose of illustration, further reference will be made to Figures 2A to 2E as well as Figure 1 The circuit 100 (which may be implemented in the device 200) is discussed. Figures 5A to 5G However, it should be understood that Figures 5A to 5G The fabrication flow may be used to produce packaged semiconductor devices having configurations different from device 200 and / or to implement circuits different from circuit 100. Figure 5G In the example of , the circuit 100 is implemented using a plurality (two) high-side IGBTs 510a and 510b coupled in parallel to each other (eg, having a common collector node, a common emitter node, and a common gate node). Figures 5A to 5G In the example of FIG. 1 , the circuit 100 is implemented using a plurality of (two) low-side IGBTs 520a and 520b coupled in parallel to each other (e.g., having a common collector node, a common emitter node, and a common gate node). In this example, the IBGTs 510a, 510b, 520a, and 520c may each use Figure 4A and Figure 4B The semiconductor device 400 shown is implemented.

[0046] like Figure 5A As shown, an exemplary manufacturing flow (process, etc.) may include attaching high-side IGBTs 510a and 510b to metal layer 230a of substrate 230 (e.g., to establish a common collector node for the high-side IGBTs); and attaching low-side IGBTs to metal layer 230b of substrate 230 (e.g., to establish a common collector node for the low-side IGBTs). In some embodiments, attaching IGBTs 510a, 510b, 520a, and 520b to substrate 230 may include performing a solder screen printing operation and a solder reflow operation. As discussed above, the backside collector contacts of IGBTs 510a, 510b, 520a, and 520b may be coupled (soldered) to the corresponding metal layers 230a and 230b of substrate 230. In some embodiments, substrate 230 may be a direct-bonded metal substrate, an insulated metal substrate, or any suitable substrate.

[0047] Also like Figure 5A As shown, substrate 230 may include, for example, contact 540 for DLA attachment of positive power terminal 140 , contact 550 for DLA attachment of output terminal 160 , and contact 570 for DLA of signal lead 170 of device 200 . Figure 5A Also shown by way of reference is an overlap of contact points 560 showing the locations of contact points for the conductive clip 240 coupled to the conductive clip 210 (where the conductive clip 240 will be as shown in FIG. Figure 5D Attach as shown). That is, Figure 5A (as well as Figure 5B and Figure 5C ) is shown in order to illustrate the location of the contact point of the conductive contact finger 210d of the conductive clip 210 by way of reference only (to be attached using, for example, a DLA, as shown in FIG. Figure 5F and Figure 5G As shown). Figure 2D and Figure 3 As shown, conductive clips 210 and 240 do not contact (are not coupled to) metal layer 230a of substrate 230, which, if such a connection were made, would result in an electrical short between positive and negative power terminals 140 and 150 of circuit 100.

[0048] like Figure 5B As shown, wire bonds 575 may be formed to electrically couple the corresponding contact points 570 (and the signal leads 170 to be attached) to the corresponding gate terminals of the IGBTs 510a, 510b, 520a, and 520b (such as the gate terminal 516 of the high-side IGBT 510a and the gate terminal 526 of the low-side IGBT 520a). Figure 5C As shown, the conductive clip 250 may be attached to the emitter terminals of the high-side IGBTs 510a and 510b and the metal layer 230b of the substrate 230, such as in Figure 2D In some embodiments, solder spot welding and / or solder screen printing may be used to attach the conductive clip 250 .

[0049] refer to Figure 5D , the conductive clip 240, the power terminals 140, 150a and 150b; the output terminal 160; and the signal lead 170 may be attached to Figure 5C Components such as Figure 5D as well as Figures 2A to 2E In the arrangement shown. Figure 5C As with the attachment of the conductive clip 250 shown, the attachment of the conductive clip 240, the power terminals 140, 150a, and 150b; the output terminal 160; and the signal lead 170 may include performing solder spot welding and / or solder screen printing operations. Additionally, after the attachment of the conductive clip 240, the power terminals 140, 150a, and 150b; the output terminal 160; and the signal lead 170, a solder reflow operation may be performed to reflow and couple (solder) the conductive clip 250, the conductive clip 240, the power terminals 140, 150a, and 150b; the output terminal 160; and the signal lead 170 in place within the assembly.

[0050] Figure 5DAlso shown are contact points 550 on the conductive clip 240 (eg, DLA for the conductive contact fingers 210d of the clip 210) that are connected to the conductive clip 240. Figures 5A to 5C The overlap shown corresponds to the contact points 550. In some embodiments, the conductive clip 250, the conductive clip 240, the power terminals 140, 150a, and 150b; the output terminal 160; and the signal lead 170 can comprise copper, plated copper, copper alloys, other conductive metals, etc., wherein the specific material or materials used will depend on the specific embodiment.

[0051] like Figure 5E As shown, a molding operation (e.g., gel molding or transfer molding operation) may be performed to Figure 5D The components of the device are encapsulated in the molding compound 220. Figure 5E As shown, contact points 550 on the conductive clip 240 are exposed through openings 555 in the molding compound 220. In some embodiments, the openings 555 can be defined using an etching operation, a grinding operation, a molding jig, or the like.

[0052] like Figure 5F and Figure 5G As shown, the conductive clip 210 can be coupled to the negative power supply terminals 150a and 150b and the conductive clip 240 (eg, using a DLA), such as in Figure 5G as well as Figures 2A to 2E For example, Figure 5F and Figure 5G As shown, the first portion 210a of the conductive clip 210 can be coupled to the first negative power terminal 150a, and the second portion 210b of the conductive clip 210 can be coupled to the second negative power terminal 150b. Additionally, the conductive contact finger 210d of the conductive clip 210 can be coupled to the contact point 550 of the conductive clip 240. In this example, the conductive contact finger 210d of the clip 210 is at least partially disposed in the opening 555 in the molding compound 220.

[0053] Figure 6 is a flow chart illustrating a method 600 for producing a packaged semiconductor device, which may be implemented Figures 5A to 5G 5A to 5B are further referenced for purposes of illustration. Figure 5G as well as Figures 1 to 2E , circuit 100, and device 200. However, it should be understood that method 600 may be used to implement variations of or in conjunction with Figures 5A to 5G Additionally, method 600 may be used to produce a packaged semiconductor device having a configuration different from device 200 , and / or implement a circuit different from circuit 100 .

[0054] At block 610, method 600 includes attaching (coupling) a semiconductor die to a substrate, such as attaching high-side IGBTs 510a and 510b and low-side IGBTs 520a and 520b to respective metal layers 230a and 230b of substrate 230, such as Figure 5A In some embodiments, at block 610, the semiconductor die may be attached (coupled) to the substrate using a solder screen printing operation and a solder reflow operation. At block 620, the method 600 includes forming wire bonds (such as Figure 5B ) that electrically couple the respective signal leads 170 (e.g., to be attached using a DLA) to the respective gate terminals (e.g., 516 and 526) of the IGBT devices 510a, 510b, 520a, and 520b. In some embodiments, additional wire bonds 570 may be formed at block 620 to electrically couple to other elements of the circuit being implemented (such as those described above with respect to Figure 1 The electrical connector and components are electrically connected.

[0055] At block 630, method 600 includes mounting (attaching, coupling) a first conductive clip to the components of block 620, such as conductive clip 250 to a Figure 5B Component coupling, such as Figure 5C As shown. The clip installation at block 630 may include solder spot welding or solder printing the emitter terminal contacts of the high-side IGBTs 510a and 510b and the metal layer 230b of the substrate 230. At block 640, the method 600 includes installing (e.g., using solder spot welding and / or solder screen printing): a second conductive clip such as conductive clip 240; power terminals (e.g., power terminals 140, 150a, and 150b); output terminals such as output terminal 160; and signal leads such as signal lead 170, such as in Figure 5D as well as Figures 2A to 2E At block 650 , a solder reflow operation may be performed to reflow the solder applied at blocks 630 and 640 and electrically couple the conductive clips, power terminals, output terminals, and signal leads of blocks 630 and 640 to their respective locations in device 200 .

[0056] At block 660 , method 600 includes molding (eg, using transfer molding, gel molding, etc.) the solder paste after the solder reflow of block 650 and / or Figure 5D and performing trimming and finishing operations (e.g., to expose contact points on the conductive clip, separate the individual package devices from each other, etc.). The molding and trimming operations of block 660 may result in an assembly having a Figure 5EAt block 670, method 600 may include mounting and soldering (e.g., using another solder reflow operation) a third conductive clip to the package assembly, such as attaching and soldering clip 210 to negative power supply terminals 150a and 150b and contact point 550 of conductive clip 240, e.g., as shown. Figure 5F and 5G shown.

[0057] It should be understood that in the foregoing description, when an element such as a layer, region or substrate is mentioned as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element may be directly on another element, connected or coupled to another element, or one or more intermediate elements may be present. In contrast, when an element is mentioned as being directly on another element or layer, directly connected to another element or layer, or directly coupled to another element or layer, there are no intermediate elements or layers. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the specific embodiments, elements shown as being directly on, directly connected to, or directly coupled to an element can be referred to in this manner. The claims of this application may be revised to describe the exemplary relationships described in the specification or shown in the drawings.

[0058] As used in this specification, singular forms may include plural forms unless the context clearly indicates otherwise. Spatially relative terms (e.g., above, above, above, below, below, below, below, on top of, below, etc.) are intended to encompass different orientations of the device in use or operation, in addition to the orientations shown in the drawings. In some embodiments, the relative terms above and below may include vertically above and vertically below, respectively. In some embodiments, the term adjacent can include lateral adjacent or horizontal adjacent.

[0059] Some embodiments may be implemented using various semiconductor processing and / or packaging technologies. Some embodiments may be implemented using various types of semiconductor device processing technologies associated with semiconductor substrates including, but not limited to, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc.

[0060] Although certain features of the described embodiments have been described as described herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of a specific implementation. It should be understood that these modifications and variations are presented by way of example only and not limitation, and that various changes in form and detail may be made. Except for mutually exclusive combinations, any portion of the apparatus and / or method described herein may be combined in any combination. The embodiments described herein can include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A semiconductor device package, comprising: substrate; a positive power terminal electrically coupled to the substrate, the positive power terminal being arranged in a first plane; a first negative power terminal disposed laterally from the positive power terminal, the first negative power terminal being arranged in the first plane; a second negative power terminal disposed laterally from the positive power terminal, the second negative power terminal being arranged in the first plane, the positive power terminal being disposed between the first negative power terminal and the second negative power terminal; and A conductive clip electrically couples the first negative power terminal with the second negative power terminal via a conductive bridge, a portion of the conductive bridge being arranged in a second plane that is parallel to and non-coplanar with the first plane. 2 . The semiconductor device package of claim 1 , wherein a line orthogonal to the first plane and the second plane intersects the positive power terminal and the portion of the conductive bridge arranged in the second plane.

3. The semiconductor device package according to claim 1 , wherein the conductive clip is a first conductive clip, and the semiconductor device package further comprises a second conductive clip. The first negative power terminal, the second negative power terminal, and the first conductive clip are electrically coupled to the second conductive clip.

4. The semiconductor device package according to claim 3, further comprising: a semiconductor die disposed on the substrate; and A third conductive clip electrically couples the semiconductor die to the substrate, and the third conductive clip is arranged in parallel with the second conductive clip.

5. The semiconductor device package of claim 4, wherein the semiconductor die is a first semiconductor die, the semiconductor device package further comprising: a second semiconductor die disposed on the substrate, the second conductive clip electrically coupling the second semiconductor die to the first conductive clip, the first negative power terminal, and the second negative power terminal; and Molding compound, the molding compound: partially encapsulating the substrate, with a surface of the substrate exposed through the molding compound; partially encapsulating the second conductive clip, a portion of the second conductive clip being exposed through the molding compound, the first conductive clip being electrically coupled to the portion of the second conductive clip exposed through the molding compound, and encapsulating the first semiconductor die, the second semiconductor die, and the third conductive clip, The first negative power terminal, the second negative power terminal, and the first conductive clip are at least partially disposed outside of the molding compound.

6. The semiconductor device package of claim 4, wherein the semiconductor die is a first semiconductor die, the semiconductor device package further comprising: a second semiconductor die disposed on the substrate, the second conductive clip electrically coupling the second semiconductor die to the first conductive clip, the first negative power terminal, and the second negative power terminal; and an output terminal electrically coupled to the substrate, a first current path between the positive power supply terminal and the output terminal, the first current path including the substrate, the first semiconductor die, and the third conductive clip, and a second current path between the output terminal and the first negative power terminal and between the second negative power terminal and the first conductive clip, the second current path including the substrate, the second semiconductor die, and the second conductive clip, the second current path being parallel to the first current path.

7. The semiconductor device package according to claim 1, wherein the conductive clip is a first conductive clip, and the semiconductor device package further comprises: a second conductive clip; a semiconductor die disposed on the substrate; and a third conductive clip electrically coupling the semiconductor die to the substrate, The third conductive clip is arranged in parallel with the second conductive clip, The first negative power terminal, the second negative power terminal, and the first conductive clip are electrically coupled with the second conductive clip using direct wire attachment.

8. The semiconductor device package according to claim 1, further comprising: An output terminal is electrically coupled to the substrate, wherein the positive power terminal and the output terminal are electrically coupled to the substrate using direct wire attachment.

9. A semiconductor device package, comprising: substrate; a positive power terminal electrically coupled to the substrate, the positive power terminal being arranged in a plane; a first negative power terminal disposed laterally from the positive power terminal, the first negative power terminal being arranged in the plane; a second negative power terminal disposed laterally from the positive power terminal, the second negative power terminal being arranged in the plane, the positive power terminal being disposed between the first negative power terminal and the second negative power terminal; a first semiconductor die disposed on the substrate; a second semiconductor die disposed on the substrate; a first conductive clip electrically coupling the first negative power terminal and the second negative power terminal to the first semiconductor die; and A second conductive clip electrically couples the second semiconductor die to the substrate, the second conductive clip being arranged in parallel with the first conductive clip.

10. The semiconductor device package according to claim 9, wherein the plane is a first plane, the semiconductor device package further comprising: a third conductive clip electrically coupling the first negative power terminal and the second negative power terminal via a conductive bridge, a portion of the conductive bridge being arranged in a second plane that is parallel to and non-coplanar with the first plane; and an output terminal electrically coupled to the substrate, The first conductive clip also electrically couples the first semiconductor die to the third conductive clip, a first current path between the positive power supply terminal and the output terminal, the first current path including the substrate, the second semiconductor die, and the second conductive clip, and a second current path between the output terminal and the first negative power terminal and between the second negative power terminal and the third conductive clip, the second current path including the substrate, the first semiconductor die, and the first conductive clip, the second current path being parallel to the first current path.

11. The semiconductor device package according to claim 9, wherein: The first semiconductor die includes a first low-side transistor of a power transistor pair; and the second semiconductor die comprising a first high-side transistor of the power transistor pair, The semiconductor device package further includes: a third semiconductor die comprising a second low-side transistor coupled in parallel with the first low-side transistor; and A fourth semiconductor die includes a second high-side transistor coupled in parallel with the first high-side transistor.

12. A semiconductor device package, comprising: substrate; a positive power terminal electrically coupled to the substrate, the positive power terminal being arranged in a first plane; a first negative power terminal disposed laterally from the positive power terminal, the first negative power terminal being arranged in the first plane; a second negative power terminal disposed laterally from the positive power terminal, the second negative power terminal being arranged in the first plane, the positive power terminal being disposed between the first negative power terminal and the second negative power terminal; a first semiconductor die disposed on the substrate, the first semiconductor die comprising a low-side transistor of a power transistor pair; a second semiconductor die disposed on the substrate, the second semiconductor die comprising a high-side transistor of the power transistor pair; a first conductive clip electrically coupling the first negative power terminal and the second negative power terminal to the low-side transistor; a second conductive clip, the second conductive clip electrically coupling the high-side transistor to the substrate, the second conductive clip being arranged in parallel with the first conductive clip; a third conductive clip electrically coupling the first negative power terminal and the second negative power terminal via a conductive bridge, wherein a portion of the conductive bridge is arranged in a second plane, the second plane being parallel to and non-coplanar with the first plane, and the third conductive clip, the first negative power terminal, and the second negative power terminal are electrically coupled to the first conductive clip; and An output terminal is electrically coupled to the substrate.

13. The semiconductor device package according to claim 12, wherein: The low-side transistor includes a first insulated gate bipolar transistor, the first conductive clip is coupled to an emitter terminal of the first insulated gate bipolar transistor, and a collector terminal of the first insulated gate bipolar transistor is electrically coupled to the output terminal via the substrate; and The high-side transistor includes a second insulated gate bipolar transistor, the second conductive clip is coupled to an emitter terminal of the second insulated gate bipolar transistor, and a collector terminal of the second insulated gate bipolar transistor is electrically coupled to the positive power supply terminal via the substrate, The semiconductor device package further includes: a first signal lead electrically coupled to a gate terminal of the first insulated gate bipolar transistor; and A second signal lead is electrically coupled to a gate terminal of the second insulated gate bipolar transistor.

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