Encapsulation Structure and Method of Manufacturing the Same

Abstract

An encapsulation structure includes a circuit substrate, a semiconductor package, a cover structure, passive devices, and a barrier structure. The semiconductor package is disposed on the circuit substrate and electrically connected to the circuit substrate. The cover structure is disposed on the circuit substrate and covers the semiconductor package. The cover structure is adhered to the circuit substrate by an adhesive material. The passive devices are disposed on the circuit substrate between the semiconductor package and the cover structure. The barrier structure separates the passive devices from the cover structure and the adhesive material and the barrier structure contacts the adhesive material.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a packaging structure, and more particularly to a packaging structure including a barrier structure and a method of manufacturing the same. Background Art

[0002] Semiconductor devices and integrated circuits used in various electronic applications (e.g., mobile phones and other mobile electronic devices) are typically fabricated on a single semiconductor wafer. The die of the wafer can be processed and packaged together with other semiconductor devices or die at the wafer level, and various techniques have been developed for wafer-level packaging. Summary of the Invention

[0003] Embodiments of the present disclosure provide a packaging structure, including a wiring substrate, a semiconductor package, a lid structure, passive devices, and a barrier structure. The semiconductor package is disposed on the wiring substrate and electrically connected to the wiring substrate. The lid structure is disposed on the wiring substrate and covers the semiconductor package, wherein the lid structure is attached to the wiring substrate by an adhesive material. The passive devices are disposed on the wiring substrate and between the semiconductor package and the lid structure. The barrier structure separates the passive devices from the lid structure and the adhesive material, wherein the barrier structure contacts the adhesive material.

[0004] Embodiments of the present disclosure provide a packaging structure, including a wiring substrate, an interposer structure, a plurality of semiconductor dies, a lid structure, a plurality of passive devices, and a plurality of barrier structures. The interposer structure is disposed on the wiring substrate and electrically connected to the wiring substrate. The plurality of semiconductor dies are disposed on the interposer structure and electrically connected to the interposer structure. The lid structure is disposed on the wiring substrate and surrounds the interposer structure and the plurality of semiconductor dies, wherein the lid structure is attached to the wiring substrate by an adhesive material. The plurality of passive devices are disposed on the wiring substrate and between the interposer structure and the lid structure, wherein the plurality of passive devices have a first surface facing the lid structure and a second surface opposite to the first surface and facing the interposer structure. The plurality of barrier structures are disposed on the wiring substrate and between the interposer structure and the lid structure, wherein the plurality of barrier structures separate the first surfaces of the plurality of passive devices from the lid structure and the adhesive material.

[0005] An embodiment of the present disclosure provides a method for manufacturing a packaging structure, including the following steps: disposing a semiconductor package on a circuit substrate; disposing passive devices on the circuit substrate adjacent to the semiconductor package; forming a barrier structure on the circuit substrate adjacent to the passive devices by applying a polymer ink material on the circuit substrate and curing the polymer ink material to form the barrier structure; and attaching a cover structure to the circuit substrate through an adhesive material, wherein the barrier structure separates the passive devices from the cover structure and the adhesive material, and the adhesive material contacts the barrier structure. Description of the Drawings

[0006] Various aspects of the present disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, according to standard practices in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the key dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figures 1A to 1G is a schematic cross-sectional view of various stages in a method for manufacturing a semiconductor package according to some exemplary embodiments of the present disclosure.

[0008] Figures 2A to 2C is a schematic cross-sectional view of various stages in a method for manufacturing a packaging structure according to some exemplary embodiments of the present disclosure.

[0009] Figure 3 is an enlarged cross-sectional view of a packaging structure according to some exemplary embodiments of the present disclosure.

[0010] Figure 4 is an enlarged cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure.

[0011] Figure 5 is an enlarged cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure.

[0012] Figure 6 is an enlarged cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure.

[0013] Figure 7 is an enlarged cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure.

[0014] Figure 8 is a top view of a packaging structure according to some exemplary embodiments of the present disclosure.

[0015] Figure 9 is a top view of a packaging structure according to some other exemplary embodiments of the present disclosure.

[0016] Figure 10It is a top view of a packaging structure according to some other exemplary embodiments of the present disclosure.

[0017] Figure 11 It is a top view of a packaging structure according to some other exemplary embodiments of the present disclosure.

[0018] Figure 12 It is a top view of a packaging structure according to some other exemplary embodiments of the present disclosure.

[0019] Figure 13 It is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure.

[0020] [Description of symbols]

[0021] 21, 602: Semiconductor die

[0022] 21S, 22S, 114b: Back surface

[0023] 22: Semiconductor die / die

[0024] 100, 100’: Interposer structure

[0025] 102: Core part

[0026] 102a, SD1: First surface

[0027] 102b, SD2: Second surface

[0028] 104: Through hole

[0029] 106, 602B, 610: Conductive pad

[0030] 110: Electrical connector

[0031] 112, 350: Underfill structure

[0032] 114, 606: Insulating seal

[0033] 114a, 116s: Top surface

[0034] 116: Redistribution structure

[0035] 116a, 604, 608B: Dielectric layer

[0036] 116b: Metallization pattern

[0037] 118: Conductive terminal

[0038] 210, 220: Body

[0039] 211, 221: Active surface

[0040] 212, 222: Connection pads

[0041] 300: Circuit substrate / substrate

[0042] 310, 320: Contact pads

[0043] 330, 608A: Metallization layer

[0044] 340, 612: Conductive balls

[0045] 410: Thermal interface metal

[0046] 510: Cover structure

[0047] 520: Adhesive material

[0048] 602A: Semiconductor substrate

[0049] 602C: Passivation layer

[0050] 602D: Post - passivation layer

[0051] 602E: Via hole / conductive rod

[0052] 602F: Protective layer

[0053] 608: Redistribution layer

[0054] BS: Barrier structure

[0055] CP1: Covering part

[0056] Cx: Carrier

[0057] DL: Saw street

[0058] DP1: First dam part / dam part

[0059] DP2: Second dam part / dam part

[0060] DP - Bs: Bottom section

[0061] DP - Ms: Middle section

[0062] DP - Ts: Top section

[0063] H1, H2, H3: Height

[0064] LX1, LX2: Length

[0065] IM: Polymer ink material

[0066] PDx: Passive device

[0067] PDx1: First passive device / passive device

[0068] PDx2: Second passive device / Passive device

[0069] PDx3: Third passive device / Passive device

[0070] PDx4: Fourth passive device / Passive device

[0071] PD-Ts: Top surface

[0072] PKR: Package area

[0073] PS, PS1, PS2, PS3, PS4, PS5, PS6: Package structure

[0074] S1: First side wall

[0075] S2: Second side wall

[0076] SD3: Third surface

[0077] SD4: Fourth surface

[0078] SM, SM2: Semiconductor package

[0079] Tx, Ty: Thickness

[0080] W1, W1A, W1B, WX1, WX2: Width

[0081] W1C: Maximum width Detailed implementation manners

[0082] The following disclosure provides numerous different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a second feature above or on a first feature may include embodiments in which the second feature and the first feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the second feature and the first feature such that the second feature and the first feature may not be in direct contact. Additionally, the present disclosure may reuse reference numerals and / or letters in various examples. Such reuse is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0083] In addition, for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "on", "over", "overlying", "above", "upper", etc. may be used herein to describe the relationship between one element or feature illustrated in the figures and another (other) element or feature. In addition to the orientation depicted in the figures, these spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0084] Other features and processes may also be included. For example, test structures may be included to assist in verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3DIC) devices. The test structures may include, for example, test pads formed in the redistribution layer or on the substrate, which allow testing of the 3D package or 3DIC, allow the use of probes and / or probe cards, etc. Verification testing may be performed on the intermediate structure as well as the final structure. Additionally, the structures and methods disclosed herein may be used in combination with test methods that include verifying known good dies during intermediate steps to increase yield and reduce cost.

[0085] As the size of semiconductor packages (e.g., chip-on-wafer (CoW) structures) on a circuit substrate gradually increases, the enclosure width between the passive device and the adhesive material of the lid structure is limited. In other words, the space between the passive device and the adhesive material decreases, and there is a risk that the adhesive material may contact the passive device. Therefore, functional failures of the passive device may occur. Additionally, tin whiskers on the passive device may also contact the lid structure, resulting in electrical failures. In the packaging structure according to an exemplary embodiment of the present disclosure, the packaging structure includes at least one barrier structure that separates the passive device from the lid structure and the adhesive material. Thus, the seepage or spread of the adhesive material towards the passive device can be avoided, and therefore electrical failures and / or functional failures of the passive device can be prevented.

[0086] Figures 1A to 1G are schematic cross-sectional views of various stages in a method of fabricating a semiconductor package according to some exemplary embodiments of the present disclosure. Referring to Figure 1A, an interposer structure 100 is provided. In some embodiments, the interposer structure 100 includes a core portion 102 and a plurality of vias 104 and conductive pads 106 formed in the core portion 102. In some embodiments, the core portion 102 is a substrate, such as a bulk semiconductor substrate, a silicon on insulator (SOI) substrate, or a multi-layer semiconductor material substrate. The semiconductor material of the substrate (core portion 102) may be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof. In some embodiments, the core portion 102 is doped or undoped.

[0087] In some embodiments, the conductive pads 106 are formed on the first surface 102a of the core portion 102. In some embodiments, the vias 104 are formed in the core portion 102 and are connected to the conductive pads 106. In some embodiments, the vias 104 extend into the core portion 102 to a specific depth. In some embodiments, the vias 104 are substrate vias. In some embodiments, when the core portion 102 is a silicon substrate, the vias 104 are silicon vias. In some embodiments, the vias 104 can be formed by forming holes or grooves in the core portion 102 and then filling the grooves with a conductive material. In some embodiments, the grooves can be formed by, for example, etching, milling, laser drilling, etc. In some embodiments, the conductive material can be formed by an electroplating process, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the conductive material may include copper, tungsten, aluminum, silver, gold, or a combination thereof. In some embodiments, the conductive pads 106 connected to the vias 104 can be formed as conductive portions of a redistribution layer formed on the interposer structure 100. In some embodiments, the conductive pads 106 include under bump metallurgies (UBM). In certain embodiments, the interposer structure 100 may further include active or passive devices formed in the core portion 102, such as transistors, capacitors, resistors, or diode passive devices.

[0088] As Figure 1AAs shown, the die body portion 102 has a plurality of package regions PKR and scribe lanes DL separating each of the plurality of package regions PKR. Through holes 104 and conductive pads 106 are formed in the die body portion 102 within the package regions PKR. In some embodiments, semiconductor dies 21 and semiconductor dies 22 are disposed on the interposer structure 100 or on the die body portion 102 within the package regions PKR. The semiconductor dies 21 and the semiconductor dies 22 are individual dies singulated from a wafer. In some embodiments, the semiconductor dies 21 include the same circuitry, such as devices and metallization patterns, or the semiconductor dies 21 are dies of the same type. In some embodiments, the semiconductor dies 22 include the same circuitry, or the semiconductor dies 22 are dies of the same type. In certain embodiments, the semiconductor dies 21 and the semiconductor dies 22 have different circuitry or are dies of different types. In alternative embodiments, the semiconductor dies 21 and the semiconductor dies 22 may have the same circuitry.

[0089] In some embodiments, the semiconductor die 21 may be a main die, and the semiconductor die 22 is a subsidiary die. In some embodiments, the main die is arranged on the die body portion 102 at the center position of each package region PKR, and the subsidiary dies are arranged side by side and spaced apart from the main die. In some embodiments, the subsidiary dies are arranged beside the main die and surround or encircle the main die. In one embodiment, in each package region PKR, four or six subsidiary dies are arranged around one main die.

[0090] In some embodiments, the surface area of semiconductor die 21 is greater than the surface area of semiconductor die 22. Additionally, in some embodiments, semiconductor die 21 and semiconductor die 22 may have different sizes, including different surface areas and / or different thicknesses. In some embodiments, semiconductor die 21 may be a logic die, including a central processing unit (CPU) die, a graphics processing unit (GPU) die, a system-on-a-chip (SoC) die, a microcontroller, etc. In some embodiments, semiconductor die 21 is a power management die, such as a power management integrated circuit (PMIC) die. In some embodiments, semiconductor die 22 may be a memory die, including a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, or a high bandwidth memory (HBM) die. The present disclosure is not limited thereto, and the number, size, and type of semiconductor dies disposed on the die body portion 102 may be appropriately adjusted based on product requirements.

[0091] As Figure 1A illustrated, semiconductor die 21 includes a body 210 and connection pads 212 formed on an active surface 211 of the body 210. In certain embodiments, the connection pads 212 may further include pillar structures for bonding the semiconductor die 21 to other structures. In some embodiments, semiconductor die 22 includes a body 220 and connection pads 222 formed on an active surface 221 of the body 220. In other embodiments, the connection pads 222 may further include pillar structures for bonding the die 22 to other structures.

[0092] In some embodiments, for example, semiconductor dies 21 and 22 are bonded to the first surface 102a of the core portion 102 by means of electrical connectors 110 through flip-chip bonding. The electrical connectors 110 are formed between the connection pads 212, 222 and the conductive pads 106 through a reflow soldering process, thereby electrically and physically connecting the semiconductor dies 21, 22 to the core portion 102 of the interposer structure 100. In some embodiments, the electrical connectors 110 are located between the semiconductor dies 21, 22 and the interposer structure 100. In certain embodiments, the semiconductor dies 21, 22 are electrically connected to the vias 104 and the conductive pads 106 through the electrical connectors 110. In one embodiment, the electrical connector 110 is a microbump, such as a microbump having a copper metal column. In another embodiment, the electrical connector 110 is a solder bump, a lead-free solder bump or a microbump, such as a controlled collapse chip connection (C4) bump or a microbump including a copper column. In some embodiments, the bonding between the semiconductor dies 21, 22 and the core portion 102 may be a solder bond. In some embodiments, the bonding between the semiconductor dies 21, 22 and the core portion 102 may be a direct metal-to-metal bond, such as a copper-to-copper bond.

[0093] Referring Figure 1B , in the next step, a underfill structure 112 may be formed to cover the plurality of electrical connectors 110 and fill the space between the semiconductor dies 21, 22 and the interposer structure 100. In some embodiments, the underfill structure 112 further covers the sidewalls of the semiconductor dies 21, 22 and is located within the package region PKR. Thereafter, an insulating seal 114 may be formed over the interposer structure 100 (or over the core portion 102) to cover the underfill structure 112 and surround the semiconductor dies 21 and 22.

[0094] In some embodiments, the insulating seal 114 is formed on the first surface 102a of the core portion 102 in the package region PKR and is formed over the dicing lane DL. In some embodiments, the insulating seal 114 is formed by, for example, a compression molding process or a transfer molding. In one embodiment, a curing process is performed to cure the insulating seal 114. In some embodiments, the semiconductor dies 21, 22 and the electrical connectors 110 are encapsulated by the insulating seal 114. In some embodiments, a planarization process (including grinding or polishing) may be performed to locally remove the insulating seal 114, thereby exposing the backside surfaces 21S, 22S of the semiconductor dies 21, 22. Thus, the backside surfaces 21S, 22S of the semiconductor dies 21, 22 are flush with the top surface 114a of the insulating seal 114. The top surface 114a is opposite to the backside surface 114b of the insulating seal 114, wherein the backside surface 114b contacts the core portion 102.

[0095] In some embodiments, the material of the insulating seal 114 includes polymers (e.g., epoxy resin, phenolic resin, silicone resin, or other suitable resins), dielectric materials having low dielectric constant (Dk) and low dissipation factor (Df) properties, or other suitable materials. In alternative embodiments, the insulating seal 114 may comprise an acceptable encapsulating material. In some embodiments, the insulating seal 114 may further comprise inorganic fillers or inorganic compounds (such as silica, clay, etc.) that can be added to the insulating seal 114 to optimize the coefficient of thermal expansion (CTE) of the insulating seal 114. The present disclosure is not limited thereto.

[0096] Refer to Figure 1C , invert or flip the structure of Figure 1B and place it on the carrier Cx such that the carrier Cx is in direct contact with the back surfaces 21S, 22S of the semiconductor dies 21, 22 and the top surface 114a of the insulating seal 114. As shown in Figure 1C , at this processing stage, the interposer structure 100 has not been thinned and has a thickness Tx. In other words, the vias 104 are not exposed and are embedded in the core portion 102 of the interposer structure 100.

[0097] Refer to Figure 1D , perform a thinning process on the interposer 100 to locally remove or thin the core portion 102 of the interposer structure 100 until the vias 104 are exposed and a second surface 102b of the core portion 102 is formed. In some embodiments, the thinning process may include a back grinding process, a polishing process, or an etching process. In some embodiments, after the thinning process, the interposer structure 100 is thinned to a thickness Ty. In some embodiments, the ratio of the thickness Ty to the thickness Tx ranges from about 0.1 to about 0.5.

[0098] Refer to Figure 1E, a redistribution structure 116 is formed on the second surface 102b of the die part 102 in the encapsulation area PKR and above the scribe lane DL. The second surface 102b of the die part 102 is opposite to the first surface 102a of the die part 102. In some embodiments, the redistribution structure 116, the die part 102, the vias 104, and the conductive pads 106 constitute an interposer structure 100'. In some embodiments, the redistribution structure 116 electrically connects the vias 104 and / or connects the vias 104 to external devices. In certain embodiments, the redistribution structure 116 includes at least one dielectric layer 116a and a metallization pattern 116b located in the dielectric layer 116a. In some embodiments, the metallization pattern 116b may include pads, vias, and / or traces to perform internal connection of the vias 104 and further connect the vias 104 to one or more external devices. Although Figure 1E shows one layer of dielectric layer 116a and one layer of metallization pattern 116b, it should be noted that the number of layers of the dielectric layer 116a and the metallization pattern 116b is not limited thereto and can be adjusted based on needs.

[0099] In some embodiments, the material of the dielectric layer 116a includes silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or a low dielectric constant dielectric material (e.g., phosphosilicate glass material, fluorosilicate glass material, borophosphosilicate glass material, SiOC, spin-on glass material, spin-on polymer, or silicon carbon material). In some embodiments, the dielectric layer 116a can be formed by spin coating or deposition (including chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), high density plasma-CVD (HDP-CVD), etc.). In some embodiments, the metallization pattern 116b includes under bump metal (UBM). In some embodiments, the formation of the metallization pattern 116b may include using lithography techniques and one or more etching processes to pattern the dielectric layer and filling the openings of the patterned dielectric layer with a metal material. Any excess conductive material on the dielectric layer can be removed, for example, by using a chemical mechanical polishing process. In some embodiments, the material of the metallization pattern 116b includes copper, aluminum, tungsten, silver, and combinations thereof.

[0100] As Figure 1EAs described, a plurality of conductive terminals 118 are provided on the metallization pattern 116b and the plurality of conductive terminals 118 are electrically coupled to the vias 104. In some embodiments, the conductive terminals 118 are placed on the top surface 116s of the redistribution structure 116 and are electrically connected to the vias 104 through the metallization pattern 116b within the encapsulation region PKR. In certain embodiments, the conductive terminals 118 are located on the metallization pattern 116b and are physically adhered to the metallization pattern 116b. In some embodiments, the conductive terminals 118 include lead-free solder balls, solder balls, ball grid array (BGA) balls, bumps, C4 bumps, or micro-bumps. In some embodiments, the conductive terminals 118 may comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or a combination thereof. In some embodiments, the conductive terminals 118 are formed by forming a solder paste on the redistribution structure 116 by, for example, evaporation plating, electroplating, printing, or solder transfer and then reflowing into a desired bump shape. In some embodiments, the conductive terminals 118 are placed on the redistribution structure 116 by ball placement or the like. In other embodiments, the conductive terminals 118 are formed by forming solderless metal pillars (such as copper pillars) by sputtering, printing, electroless plating, electroplating, or CVD, and then forming a lead-free top layer by plating on the metal pillars. The conductive terminals 118 can be used for bonding to external devices or additional electrical components. In some embodiments, the conductive terminals 118 are used for bonding to a circuit substrate, a semiconductor substrate, or a package substrate.

[0101] Referring to Figure 1F , in the next step, the structure shown in Figure 1E is cut or singulated along the dicing street DL to form a plurality of semiconductor packages SM. For example, a dicing process is performed to cut through the redistribution structure 116, the core portion 102, and the insulating seal 114 along the dicing street DL to remove portions of the redistribution structure 116, portions of the core portion 102, and portions of the insulating seal 114. In some embodiments, the dicing process or singulation process generally involves using a rotating blade or a laser beam for cutting. In other words, the dicing process or singulation process is, for example, a laser scribing process, a mechanical sawing process, or other suitable processes. In some embodiments, the dicing process or singulation process can be performed on a tape (e.g., a dicing tape) supported by a frame (not shown). In other words, the carrier Cx can be peeled off and the structure can be transferred to the dicing tape to perform the dicing process. After peeling off the carrier Cx and performing the dicing process, the singulated semiconductor packages SM as described in Figure 1G can be obtained.

[0102] Figures 2A to 2C are schematic cross-sectional views of the respective stages in a method of fabricating a package structure according to some exemplary embodiments of the present disclosure. Referring to Figure 2A, in an exemplary embodiment, the semiconductor package SM obtained in Figure 1G is mounted or attached to the circuit substrate 300 through the conductive terminal 118. In some embodiments, the circuit substrate 300 includes contact pads 310, contact pads 320, a metallization layer 330, and vias (not shown). In some embodiments, the contact pads 310 and the contact pads 320 are respectively distributed on two opposite sides of the circuit substrate 300 and are exposed for electrical connection to elements / features to be formed later. In some embodiments, the metallization layer 330 and the vias are embedded in the circuit substrate 300 and together provide a wiring function for the circuit substrate 300, wherein the metallization layer 330 and the vias are electrically connected to the contact pads 310 and the contact pads 320. In other words, at least some of the contact pads 310 in the contact pads 310 are electrically connected to some of the contact pads 320 in the contact pads 320 through the metallization layer 330 and the vias. In some embodiments, the contact pads 310 and the contact pads 320 may include metal pads or metal alloy pads. In some embodiments, the material of the metallization layer 330 and the material of the vias may be substantially the same as or similar to the material of the contact pads 310 and the contact pads 320.

[0103] In addition, in some embodiments, the semiconductor package SM is bonded to the circuit substrate 300 by physically connecting the conductive terminal 118 to the contact pad 310 to form a stacked structure. In certain embodiments, the semiconductor package SM is electrically connected to the circuit substrate 300. In some embodiments, the circuit substrate 300 is, for example, an organic flexible substrate or a printed circuit board. In these embodiments, the conductive terminal 118 is, for example, a chip connector. In some embodiments, a plurality of conductive balls 340 are respectively formed on the substrate 300. As Figure 2A illustrated, for example, the conductive balls 340 are connected to the contact pads 320 of the circuit substrate 300. In other words, the conductive balls 340 are electrically connected to the circuit substrate 300 through the contact pads 320. Through the contact pads 310 and the contact pads 320, some of the conductive balls 340 are electrically connected to the semiconductor package SM (for example, the semiconductor dies 21 and 22 included in the semiconductor package SM). In some embodiments, the conductive balls 340 are, for example, solder balls or BGA balls. In some embodiments, the semiconductor package SM is bonded to the circuit substrate 300 by physically connecting the conductive terminal 118 to the contact pad 310 of the circuit substrate 300 through a chip on wafer on substrate (CoWoS) packaging process. Additionally, as Figure 2AAs described, the passive device PDx (integrated passive device or surface mount device) can be mounted on the circuit substrate 300. For example, the passive device PDx can be mounted on the contact pads 310 of the circuit substrate 300 by a soldering process. The present disclosure is not limited thereto. In some embodiments, the passive device PDx can be mounted on the circuit substrate so as to surround the semiconductor package SM.

[0104] As Figure 2A As further described, in some embodiments, a underfill structure 350 is formed to fill the space between the circuit substrate 300 and the semiconductor package SM. In some embodiments, the underfill structure 350 fills the space between adjacent conductive terminals 118 and covers the conductive terminals 118. For example, the underfill structure 350 surrounds the plurality of conductive terminals 118. In some embodiments, the passive device PDx is exposed by the underfill structure 350 and is spaced apart from the underfill structure 350. In other words, the underfill structure 350 does not cover the passive device PDx.

[0105] Generally, the semiconductor package SM will be further protected by a lid structure that is adhered to the circuit substrate 300 by an adhesive. It is desirable to avoid contact between the adhesive and the passive device PDx. Figures 2B to 13 Described is a dam or barrier structure for blocking the intrusion of the adhesive towards the passive device PDx. An additional benefit is that some of the barrier structures in the barrier structure are also used to mitigate the growth of tin whiskers from the passive device PDx, which may contact the lid structure and cause device failure due to short circuit. For example, such a structure is shown in Figure 7 、 Figure 10 and Figure 12 This structure is shown.

[0106] Referring to Figure 2B, in the next step, a barrier structure BS (or a first dam portion DP1) is formed on the circuit substrate 300 by inkjet printing or other suitable deposition processes. For example, in some embodiments, a polymer ink material IM is dispensed on the circuit substrate 300, and then the polymer ink material IM is cured to form the barrier structure BS (the first dam portion DP1). In certain embodiments, after dispensing the polymer ink material IM, the polymer ink material is cured by radiation of ultraviolet light. In some embodiments, the polymer ink material IM is dispensed in the region on the circuit substrate 300 between the passive device PDx and the cover structure 510 (provided in a subsequent step), and is spaced apart from the passive device PDx and the cover structure 510. In some embodiments, the polymer ink material IM is a polyimide-based polymer material, an epoxy-based polymer material, or any other polymer-based material. However, the present disclosure is not limited thereto, and any other suitable material can be used to form the barrier structure BS as long as it provides sufficient barrier function without affecting the performance of the passive device PDx.

[0107] Referring to Figure 2C , in some embodiments, the cover structure 510 is bonded to the circuit substrate 300 by an adhesive material 520. For example, the cover structure 510 is disposed on the circuit substrate 300 and surrounds the semiconductor package SM and the passive device PDx. In some embodiments, the adhesive material 520 is a conductive adhesive, but the present disclosure is not limited thereto. In alternative embodiments, the adhesive material 520 can be any other suitable adhesive material as long as it can achieve bonding the cover structure 510 to the circuit substrate 300.

[0108] In some embodiments, the cover structure 510 can be a heat sink for heat dissipation. In some embodiments, the thermal interface metal 410 is attached to the back side of the semiconductor package SM and sandwiched between the cover structure 510 and the semiconductor package SM. In certain embodiments, the thermal interface metal 410 fills the space between the semiconductor package SM and the cover structure 510 to further enhance heat dissipation.

[0109] In an exemplary embodiment, when the lid structure 510 is bonded to the circuit substrate 300 by the bonding material 520, seepage of the bonding material 520 may occur. The bonding material 520 may spread in the direction where the passive device PDx and the semiconductor package SM are located. In some embodiments, since a barrier structure BS (first dam portion DP1) is provided between the passive device PDx and the lid structure 510, the spread or seepage of the bonding material 520 is blocked by the barrier structure BS (first dam portion DP1). That is, the barrier structure BS (first dam portion DP1) separates the passive device PDx from the lid structure 510 and the bonding material 520, while being in contact with the bonding material 520. In certain embodiments, the barrier structure BS (first dam portion DP1) is spaced apart from the passive device PDx and the lid structure 510 by a specific distance to prevent excessive spread of the bonding material 520. By using the barrier structure BS to prevent the bonding material 520 from spreading towards the passive device PDx, electrical failure and / or functional failure of the passive device PDx can be prevented. According to some embodiments of the present disclosure, Figure 2C the structure shown in can be regarded as the package structure PS.

[0110] In the above embodiment, the barrier structure BS is described as a dam-shaped portion (first dam portion DP1). Various other designs of the barrier structure BS are set forth in the following sections.

[0111] Figure 3 is an enlarged cross-sectional view of a package structure according to some exemplary embodiments of the present disclosure. For example, Figure 3 is Figure 2C an enlarged view of the package structure PS shown in, so the same reference numerals are used to refer to the same or similar components, and they will not be described in detail herein. Referring to Figure 3 , the barrier structure BS includes a first dam portion DP1 located between the passive device PDx and the lid structure 510. In some embodiments, the first dam portion DP1 has a first sidewall S1 facing the lid structure 510 and a second sidewall S2 opposite to the first sidewall S1 and facing the passive device PDx. For example, the first sidewall S1 of the first dam portion contacts the bonding material 520 to block the bonding material 520. In addition, in some embodiments, the passive device PDx has a first surface SD1 facing the lid structure 510 and a second surface SD2 opposite to the first surface SD1 and facing the interposer structure 100' (as Figure 2C illustrated in).

[0112] In an exemplary embodiment, the width W1 of the first dam part DP1 remains substantially constant from the bottom to the top of the first dam part DP1. In certain embodiments, the width W1 is in the range of 5 μm to 3000 μm, and the width can be adjusted based on design requirements. In some embodiments, when the width W1 is less than 5 μm, it may introduce undesirable process non-uniformity or insufficient adhesion strength to the circuit substrate 300, resulting in the fracture of the first dam part DP1 under the stress from the adhesive material 520. In some embodiments, the height H1 of the first dam part DP1 is greater than the height H2 of the passive device PDx. Similar to the above embodiments, since the first dam part DP1 prevents the adhesive material 520 from spreading towards the passive device PDx, electrical failure and / or functional failure of the passive device PDx can be prevented.

[0113] Figure 4 is an enlarged cross-sectional view of a package structure according to some other exemplary embodiments of the present disclosure. Figure 4 The embodiment shown in Figure 3 is similar to the embodiment shown in Figure 3 In the configuration shown in Figure 4 the height H1 of the first dam part DP1 is shown as greater than the height H2 of the passive device PDx. However, the present disclosure is not limited thereto. As Figure 4 illustrates, the height H1 of the first dam part DP1 is less than the height H2 of the passive device PDx. In some embodiments, when the distance between the first dam part DP1 and the lid structure 510 increases, the height of the first dam part DP1 can be reduced. When the first dam part DP1 is arranged further away from the lid structure 510, the spreading of the adhesive material 520 towards the first dam part DP1 can become less obvious. In other words, since the distance between the first dam part DP1 and the lid structure 510 becomes larger, the adhesive material 520 spreads further, which results in a lower height of the spreading adhesive material 520. Thus, due to the limited spreading of the adhesive material 520, the height of the first dam part DP1 can be reduced. In some alternative embodiments, the height of the first dam part DP1 can be substantially equal to the height of the passive device PDx. In certain embodiments, the height of the barrier structure BS (or the first dam part DP1) can be in the range of 10 μm to 2000 μm, and the height can be adjusted based on design requirements. Similar to the above embodiments, since the first dam part DP1 prevents the adhesive material 520 from spreading towards the passive device PDx, electrical failure and / or functional failure of the passive device PDx can be prevented.

[0114] Figure 5 is an enlarged cross-sectional view of a package structure according to some other exemplary embodiments of the present disclosure. Figure 5 The embodiment shown inFigure 3 the embodiments shown in, and thus the same reference numerals are used to refer to the same or similar components, and they will not be described in detail herein. As Figure 5 illustrated in, the first dam portion DP1 may include a bottom section DP-Bs and a top section DP-Ts joined to the bottom section DP-Bs. In the illustrated embodiment, the width of the first dam portion DP1 decreases from the bottom section DP-Bs to the top section DP-Ts. For example, in some embodiments, the bottom of the bottom section DP-Bs may have a width W1A, while the top of the top section DP-Ts may have a width W1B, and the width of the first dam portion DP1 decreases from W1A to W1B. In some embodiments, the shape or size of the first dam portion DP1 can be adjusted by controlling the amount of the polymer ink material and the time period for dispensing and curing the polymer ink material. Similar to the above embodiments, since the first dam portion DP1 prevents the adhesive material 520 from spreading toward the passive device PDx, electrical failures and / or functional failures of the passive device PDx can be prevented.

[0115] Figure 6 is an enlarged cross-sectional view of a package structure according to some other exemplary embodiments of the present disclosure. Figure 6 the embodiments shown in Figure 3 the embodiments shown in, and thus the same reference numerals are used to refer to the same or similar components, and they will not be described in detail herein. As Figure 6 illustrated in, the first dam portion DP1 may include a bottom section DP-Bs, an intermediate section DP-Ms, and a top section DP-Ts joined in sequence, and the bottom section DP-Bs, the intermediate section DP-Ms, and the top section DP-Ts are manufactured together in a single process. In the illustrated embodiment, the width of the first dam portion DP1 increases from the bottom section DP-Bs to the intermediate section DP-Ms, and the width decreases from the intermediate section DP-Ms to the top section DP-Ts. For example, in some embodiments, the bottom of the bottom section DP-Bs may have a width W1A, the intermediate section DP-Ms may have a maximum width W1C, and the top of the top section DP-Ts may have a width W1B. In certain embodiments, the width of the first dam portion DP1 increases from W1A to W1C and decreases from W1C to W1B. Similar to the above embodiments, since the first dam portion DP1 prevents the adhesive material 520 from spreading toward the passive device PDx, electrical failures and / or functional failures of the passive device PDx can be prevented.

[0116] Figure 7 is an enlarged cross-sectional view of a package structure according to some other exemplary embodiments of the present disclosure. Figure 7 the embodiments shown in Figure 3The embodiments shown herein, so the same reference numerals are used to refer to the same or similar components, and will not be described herein again. As Figure 7 As described in Figure 7 , the barrier structure BS may include a covering portion CP1 that covers the side surfaces (the first surface SD1 and the second surface SD2) and the top surface PD-Ts of the passive device PDx. In some embodiments, the passive device PDx is covered and enclosed by the covering portion CP1 while being in contact with the covering portion CP1. In some embodiments, the covering portion CP1 may be formed in a manner similar to that of forming the dam portion DP1. For example, a polymer ink material IM (such as Figure 2B shown in Figure 2B ) may be dispensed on the circuit substrate 300 to surround the passive device PDx, and the polymer ink material IM may be cured to form the covering portion CP1. In some embodiments, the height H3 of the covering portion CP1 may be greater than the height H2 of the passive device PDx. In alternative embodiments, the height H3 of the covering portion CP1 may be substantially equal to the height H2 of the passive device PDx. In addition, in some embodiments, the width of the covering portion CP1 may be greater than or substantially equal to the width of the passive device PDx to enclose the passive device PDx. Similar to the above embodiments, since the covering portion CP1 also prevents the adhesive material 520 from spreading toward the passive device PDx, electrical failure and / or functional failure of the passive device PDx can be prevented. In addition, by using the covering portion CP1 to protect the top surface PD-Ts of the passive device PDx, this can be used to mitigate the growth of tin whiskers from the passive device PDx, thus preventing device failure due to short circuits.

[0117] Figure 8 is a top view of a packaging structure according to some exemplary embodiments of the present disclosure. Figure 8 The packaging structure PS1 described in Figure 8 is similar to Figure 2C the packaging structure PS described in Figure 2C , so the same reference numerals are used to refer to the same or similar components, and will not be described herein again. As Figure 8As described, the encapsulation structure PS1 includes a first passive device PDx1 and a second passive device PDx2 located beside the semiconductor package SM, and a barrier structure BS (first dam portion DP1) is provided between the first passive device PDx1 and the lid structure 510 and between the second passive device PDx2 and the lid structure 510. In some embodiments, the first dam portion DP1 located beside the first passive device PDx1 has a width WX2 and a length LX2, and the first dam portion DP1 located beside the second passive device PDx2 has a width WX1 and a length LX1. In an exemplary embodiment, the width WX1 is greater than the width WX2, and the length LX2 is greater than the length LX1. It can be seen from the embodiments of the present disclosure that the length and width of the first dam portion DP1 can be appropriately adjusted based on design requirements. In some embodiments, the design of the first dam portion DP1 can be appropriately adjusted as long as the first dam portion DP1 successfully separates the passive devices (PDx1, PDx2) from the adhesive material 520. In an exemplary embodiment, the first dam portion DP1 is located at a side surface (first surface SD1) of the passive devices (PDx1, PDx2) to prevent the adhesive material 520 from spreading towards the passive devices (PDx1, PDx2). In certain embodiments, the first dam portion DP1 is located at the surface of the passive devices (PDx1, PDx2) closest to the lid structure 510.

[0118] Figure 9 is a top view of an encapsulation structure according to some other exemplary embodiments of the present disclosure. Figure 9 The encapsulation structure PS2 described in Figure 8 is similar to the encapsulation structure PS1 described in Figure 8 and thus the same reference numerals are used to refer to the same or similar components and will not be described herein again. In the configuration shown in Figure 9As described, in some embodiments, a first dam portion DP1 located next to a first passive device PDx1 is formed to surround all side surfaces of the first passive device PDx1. In certain embodiments, the first passive device PDx1 is confined to the area surrounded by the first dam portion DP1. Further, in certain embodiments, the first dam portion DP1 located next to a second passive device PDx2 is formed to surround a first surface SD1, a third surface SD3, and a fourth surface SD4 of the second passive device PDx2 while leaving a second surface SD2 exposed. Additionally, in the above embodiments, the adhesive material 520 is shown in contact with a side wall (e.g., a first side wall S1) of the first dam portion DP1. However, the present disclosure is not limited thereto. For example, in some embodiments, when the first dam portion DP1 is maintained at a specific distance from the lid structure 510, then in some cases, the adhesive material 520 may not spread to contact the first dam portion DP1. As Figure 9 described, the first side wall S1 of the first dam portion DP1 located next to the first passive device PDx1 does not contact the adhesive material 520.

[0119] Figure 10 is a top view of a package structure according to some other exemplary embodiments of the present disclosure. Figure 10 The package structure PS3 described in Figure 9 is similar to the package structure PS2 described in

[0120] Thus, the same reference numerals are used to refer to the same or similar components, and a detailed description thereof will not be repeated herein. In the above embodiments, the barrier structure BS includes the first dam portion DP1 or the cover portion CP1. However, the present disclosure is not limited thereto, and the barrier structure BS in a single package may include both the first dam portion DP1 and the cover portion CP1. Figure 10As described, the encapsulation structure PS3 includes a first passive device PDx1, a second passive device PDx2, a third passive device PDx3, and a fourth passive device PDx4 located beside the semiconductor package SM. In some embodiments, a barrier structure BS (a first dam portion DP1 or a covering portion CP1) is disposed between the passive devices (PDx1, PDx2, PDx3, PDx4) and the lid structure 510 to separate the passive devices (PDx1, PDx2, PDx3, PDx4) from the lid structure 510 and the adhesive material 520. In some embodiments, the first dam portion DP1 surrounds all the sidewalls of the first passive device PDx1. In some embodiments, the covering portion CP1 covers all the side surfaces and the top surface of the third passive device PDx3. Additionally, in certain embodiments, another first dam portion DP1 may surround the sidewalls of both the second passive device PDx2 and the fourth passive device PDx4. In some embodiments, the underfill structure 350 contacts the first dam portion DP1 (barrier structure BS) located beside the second passive device PDx2 and the fourth passive device PDx4. That is, the barrier structure BS can also prevent the underfill structure 350 from spreading towards the passive devices (PDx1, PDx2, PDx3, PDx4).

[0121] In an exemplary embodiment, four passive devices (PDx1, PDx2, PDx3, PDx4) are illustrated. However, the present disclosure is not limited thereto, and the number of passive devices located in the encapsulation structure can be adjusted based on product requirements. Further, it should be noted that each of the passive devices is protected from the spread of the adhesive material 520 by using any one or a combination of the various designs of the above-described barrier structure BS.

[0122] Figure 11 is a top view of an encapsulation structure according to some other exemplary embodiments of the present disclosure. Figure 11 The encapsulation structure PS4 described in Figure 10 is similar to the encapsulation structure PS3 described in Figure 11As described, a single first dam portion DP1 is provided to surround all passive devices (PDx1, PDx2, PDx3, PDx4). In some embodiments, the first dam portion DP1 surrounds and encapsulates all passive devices (PDx1, PDx2, PDx3, PDx4) and the semiconductor package SM. In certain embodiments, the first dam portion DP1 has a first sidewall S1 (outer sidewall) facing the lid structure 510 and a second sidewall S2 (inner sidewall) opposite the first sidewall S1 and facing the passive devices (PDx1, PDx2, PDx3, PDx4). In some embodiments, the adhesive material 520 contacts the first sidewall S1 (outer sidewall). In other words, the spread or seepage of the adhesive material 520 is blocked by the first sidewall S1 of the first dam portion DP1.

[0123] Figure 12 is a top view of a package structure according to some other exemplary embodiments of the present disclosure. Figure 12 The package structure PS5 described in Figure 10 is similar to the package structure PS3 described in Figure 12 and thus the same reference numerals are used to denote the same or similar components and will not be described herein again. As described in Figure 12 the first dam portion DP1 located on one side of the first passive device PDx1 and the third passive device PDx3 contacts the adhesive material 520 to block the adhesive material 520. In some embodiments, a second dam portion DP2 surrounds the first passive device PDx1 to further protect the first passive device PDx1. In certain embodiments, a cover portion CP1 is located next to the first dam portion DP1 to further protect and cover the third passive device PDx3. Similarly, the first dam portion DP1 and the second dam portion DP2 located next to the second passive device PDx2 and the fourth passive device PDx4 are formed to surround three sides of the passive devices (PDx2, PDx4). In certain embodiments, the second dam portion DP2 is located between the first dam portion DP1 and the passive device PDx1 and is spaced apart from the passive devices (PDx2, PDx4) and the first dam portion DP1. In some embodiments, the second dam portion DP2 is formed after the first dam portion DP1 is formed.

[0124] In an exemplary embodiment, similar to the method of forming the first dam portion DP1 and the cover portion CP1 described previously, a polymer ink material IM (such as Figure 2Bas described in [reference] to form the second dam portion DP2. In some embodiments, after curing the polymer ink material IM, a barrier structure BS including the first dam portion DP1, the second dam portion DP2, and the cover portion CP1 is formed. In some embodiments, the second dam portion DP2 is spaced apart from the first dam portion DP1 and the cover portion CP1. In certain embodiments, the height of the second dam portion DP2 is different from the height of the first dam portion DP1. However, the present disclosure is not limited thereto, and the length, width, height, and design of the dam portions (DP1, DP2) can be adjusted according to the foregoing embodiments. The use of the second dam portion DP2 further ensures the protection of the passive devices (PDx1, PDx2, PDx3, PDx4). For example, in addition to the first dam portion DP1, the second dam portion DP2 can be used as an additional barrier layer to increase the spreading path of the adhesive material 520 and prevent the adhesive material 520 from spreading towards the passive devices (PDx1, PDx2, PDx3, PDx4).

[0125] Figure 13 is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure. Figure 13 The packaging structure PS6 described in [reference] is similar to Figure 2C the packaging structure PS described in [reference], so the same reference numerals are used to refer to the same or similar components, and they will not be described in detail herein. As Figure 2C described in [reference], the semiconductor package SM refers to a chip-on-wafer (CoW) package. However, the present disclosure is not limited thereto. For example, referring to Figure 13 [reference], a semiconductor package SM2 is provided to replace Figure 2C the semiconductor package SM shown in [reference].

[0126] As Figure 13 shown in [reference], the semiconductor package SM2 includes a semiconductor die 602, a dielectric layer 604, an insulating sealant 606, a redistribution layer 608, a conductive pad 610, and a conductive ball 612. The semiconductor die 602 is located on the dielectric layer 604. The insulating sealant 606 is located on the dielectric layer 604 and surrounds the semiconductor die 602. In some embodiments, the semiconductor die 602 includes a semiconductor substrate 602A, a plurality of conductive pads 602B, a passivation layer 602C, a post-passivation layer 602D, a plurality of conductive rods or vias 602E, and a protective layer 602F. As Figure 13As described, the plurality of conductive pads 602B are disposed on the semiconductor substrate 602A. A passivation layer 602C is formed over the semiconductor substrate 602A and has openings that locally expose the conductive pads 602B on the semiconductor substrate 602A. The semiconductor substrate 602A can be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate, and further includes active components (e.g., transistors, etc.) formed in the semiconductor substrate 602A and optionally includes passive components (e.g., resistors, capacitors, inductors, etc.). The conductive pads 602B can be aluminum pads, copper pads, or other suitable metal pads. The passivation layer 602C can be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of any suitable dielectric material.

[0127] In addition, in some embodiments, a post-passivation layer 602D is optionally formed over the passivation layer 602C. The post-passivation layer 602D covers the passivation layer 602C and has a plurality of contact openings. The conductive pads 602B are locally exposed through the contact openings of the post-passivation layer 602D. The post-passivation layer 602D can be a benzocyclobutene (BCB) layer, a polyimide layer, a polybenzoxazole (PBO) layer, or a dielectric layer formed of other suitable polymers. In some embodiments, a conductive post or via 602E is formed on the conductive pad 602B by plating. In some embodiments, a protective layer 602F is formed over the post-passivation layer 602D to cover the conductive post or via 602E to protect the conductive post or via 602E. Although only one semiconductor die 602 is illustrated herein, it should be noted that the present disclosure is not limited thereto, and the number of semiconductor dies 602 in the semiconductor package SM2 can be more than one.

[0128] In addition, as Figure 13 described, a redistribution layer 608 is formed on the insulating seal 606 and is electrically connected to the semiconductor die 602. In some embodiments, the formation of the redistribution layer 608 includes sequentially and alternately forming one or more dielectric layers 608B and one or more metallization layers 608A. In certain embodiments, the metallization layers 608A are sandwiched between the dielectric layers 608B. Although only three metallization layers 608A and four dielectric layers 608B are illustrated herein, the scope of the present disclosure is not limited to the embodiments of the present disclosure. In other embodiments, the number of metallization layers 608A and dielectric layers 608B can be adjusted based on product requirements. In some embodiments, the metallization layer 608A is electrically connected to the conductive post 602E of the semiconductor die 602.

[0129] In some embodiments, a plurality of conductive pads 610 are disposed on the exposed top surface of the topmost layer of the metallization layer 608A for electrical connection to conductive balls. In certain embodiments, the conductive pads 610 are, for example, under-ball metallurgy (UBM) patterns for ball mounting. As Figure 13 shown, the conductive pads 610 are formed on the redistribution layer 608 and electrically connected to the redistribution layer 608. In some embodiments, the material of the conductive pads 610 may include copper, nickel, titanium, tungsten, or alloys thereof, etc., and may be formed by, for example, an electroplating process. In the present disclosure, the number of the conductive pads 610 is not limited and may be selected based on the design layout. In some alternative embodiments, the conductive pads 610 may be omitted. In other words, the conductive balls 612 formed in subsequent steps may be directly disposed on the redistribution layer 608.

[0130] As Figure 13 illustrated, a plurality of conductive balls 612 are disposed on the conductive pads 610 and above the redistribution layer 608. In some embodiments, the conductive balls 612 may be disposed on the conductive pads 610 by a ball placement process or a reflow soldering process. In some embodiments, the conductive balls 612 are, for example, solder balls or ball grid array (BGA) balls. In some embodiments, the conductive balls 612 are connected to the redistribution layer 608 through the conductive pads 610. In certain embodiments, some of the conductive balls 612 among the conductive balls 612 may be electrically connected to the semiconductor die 602 through the redistribution layer 608. The number of the conductive balls 612 is not limited to the present disclosure and may be specified and selected based on the number of the conductive pads 610.

[0131] In an exemplary embodiment, the semiconductor package SM2 is disposed on the circuit substrate 300 by flip chip bonding. In some embodiments, the semiconductor package SM2 is electrically connected to the contact pads 310 of the circuit substrate 300 through the conductive balls 612. In certain embodiments, the conductive balls 612 are further protected by an underfill structure 350. Similar to the above embodiments, since the barrier structure BS is disposed on the circuit substrate 300 to prevent the adhesive material 520 from spreading toward the passive device PDx, electrical failure and / or functional failure of the passive device PDx can be prevented.

[0132] The package structure includes at least one barrier structure that separates the passive device from the cover structure and the adhesive material. Thus, the adhesive material can be prevented from oozing or spreading toward the passive device, and thus electrical failure and / or functional failure of the passive device can be prevented. In addition, the barrier structure can be used to protect the passive device and prevent tin (Sn) whiskers of the passive device from touching the cover structure. Additionally, by using the barrier structure, the enclosure width between the passive device and the cover structure can be reduced, and thus a larger semiconductor package can be mounted on the circuit substrate. Generally speaking, a package structure with better reliability and performance can be obtained.

[0133] In some embodiments of the present disclosure, a packaging structure is provided. The packaging structure includes a wiring substrate, a semiconductor package, a cover structure, passive devices, and a barrier structure. The semiconductor package is disposed on the wiring substrate and electrically connected to the wiring substrate. The cover structure is disposed on the wiring substrate and covers the semiconductor package, wherein the cover structure is adhered to the wiring substrate by an adhesive material. The passive devices are disposed on the wiring substrate between the semiconductor package and the cover structure. The barrier structure separates the passive devices from the cover structure and the adhesive material, wherein the barrier structure contacts the adhesive material.

[0134] In some embodiments, the first dam portion includes a bottom segment and a top segment, and the width of the first dam portion decreases from the bottom segment to the top segment. In some embodiments, the first dam portion includes a bottom segment, a middle segment, and a top segment, and the width of the first dam portion increases from the bottom segment to the middle segment and decreases from the middle segment to the top segment. In some embodiments, the barrier structure includes a covering portion that covers the side surface and the top surface of the passive device. In some embodiments, the covering portion contacts the passive device.

[0135] In some other embodiments of the present disclosure, a packaging structure is provided. The packaging structure includes a wiring substrate, an interposer structure, a plurality of semiconductor dies, a cover structure, a plurality of passive devices, and a plurality of barrier structures. The interposer structure is disposed on the wiring substrate and electrically connected to the wiring substrate. The plurality of semiconductor dies are disposed on the interposer structure and electrically connected to the interposer structure. The cover structure is disposed on the wiring substrate and surrounds the interposer structure and the plurality of semiconductor dies, wherein the cover structure is adhered to the wiring substrate by an adhesive material. The plurality of passive devices are disposed on the wiring substrate between the interposer structure and the cover structure, wherein the plurality of passive devices have a first surface facing the cover structure and a second surface opposite to the first surface and facing the interposer structure. The plurality of barrier structures are disposed on the wiring substrate between the interposer structure and the cover structure, wherein the plurality of barrier structures separate the first surface of the plurality of passive devices from the cover structure and the adhesive material.

[0136] In some embodiments, the plurality of passive devices are located in an area surrounded by the first dam portion. In some embodiments, the first dam portion includes a bottom segment and a top segment, and the width of the first dam portion decreases from the bottom segment to the top segment. In some embodiments, the plurality of barrier structures include a covering portion that covers the first surface, the second surface, and the top surface of the plurality of passive devices.

[0137] In yet another embodiment of the present disclosure, a method of fabricating an encapsulation structure is described. The method includes the following steps. A semiconductor package is disposed on a circuit substrate. A passive device is disposed on the circuit substrate adjacent to the semiconductor package. A barrier structure is formed around the passive device on the circuit substrate by dispensing a polymer ink material on the circuit substrate and curing the polymer ink material to form the barrier structure. A cover structure is attached to the circuit substrate by an adhesive material, wherein the barrier structure separates the passive device from the cover structure and the adhesive material, and the cover structure is attached to the circuit substrate in such a manner that the adhesive material contacts the barrier structure.

[0138] In some embodiments, the polymer ink material is dispensed on the circuit substrate to surround the passive device. In some embodiments, after forming the first dam portion, the polymer ink material is further dispensed in the region on the circuit substrate between the first dam portion and the passive device, and after curing the polymer ink material, a barrier structure including a second dam portion is formed, and the second dam portion is separated from the first dam portion. In some embodiments, the polymer ink material is dispensed in the region on the circuit substrate overlapping with the passive device to cover the passive device, and after curing the polymer ink material, a barrier structure including a covering portion is formed, and the covering portion covers the side surface and the top surface of the passive device.

[0139] The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that these equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. An encapsulation structure, comprising: a circuit substrate; a semiconductor package disposed on the circuit substrate and electrically connected to the circuit substrate; a underfill structure disposed between the circuit substrate and the semiconductor package; a lid structure disposed on the circuit substrate and covering the semiconductor package, wherein the lid structure is adhered to the circuit substrate by an adhesive material; a first passive device disposed on the circuit substrate and between a first side of the semiconductor package and the lid structure; a second passive device disposed on the circuit substrate and between a second side of the semiconductor package and the lid structure, wherein the second side is opposite to the first side; a barrier structure, comprising: a first dam portion that extends in a first direction and is located between the first passive device and the lid structure, and the first passive device is spaced apart from the lid structure and the adhesive material, wherein the first dam portion is in physical contact with the adhesive material; and an auxiliary first dam portion that spaces the second passive device from the lid structure and the adhesive material, wherein the auxiliary first dam portion is physically separated from the first dam portion, does not overlap with the first dam portion in the first direction, and is in physical contact with the adhesive material, wherein the auxiliary first dam portion includes a first section, a second section, and a third section, the first section and the second section surround two opposite side surfaces of the second passive device, the third section physically connects the first section and the second section and surrounds a third side surface of the second passive device, the auxiliary first dam portion does not cover a fourth side surface of the second passive device facing the second side of the semiconductor package, wherein, the open ends of the first section and the second section include end surfaces that face the underfill structure.

2. The encapsulation structure according to claim 1, wherein the first dam portion further includes a first sidewall facing the lid structure and a second sidewall opposite to the first sidewall and facing the first passive device, wherein the first sidewall of the first dam portion is in physical contact with the adhesive material.

3. The encapsulation structure according to claim 1, wherein the barrier structure further includes a second dam portion located between the first dam portion and the first passive device and spaced apart from the first passive device and the first dam portion.

4. The encapsulation structure according to claim 1, wherein the barrier structure further includes a covering portion that covers a side surface and a top surface of a third passive device.

5. The encapsulation structure according to claim 4, wherein the covering portion contacts the third passive device.

6. An encapsulation structure, comprising: a circuit substrate; an interposer structure disposed on the circuit substrate and electrically connected to the circuit substrate; a plurality of semiconductor dies disposed on the interposer structure and electrically connected to the interposer structure; A lid structure is disposed on the circuit substrate and surrounds the interposer structure and the plurality of semiconductor dies, wherein the lid structure is bonded to the circuit substrate by an adhesive material; A first passive device and a second passive device are respectively disposed on the circuit substrate and between the interposer structure and the lid structure, wherein the first passive device and the second passive device respectively have a first surface facing the lid structure, a second surface opposite to the first surface and facing the interposer structure, a third surface connecting the first surface to the second surface, and a fourth surface opposite to the third surface and connecting the first surface to the second surface; And A plurality of barrier structures are disposed on the circuit substrate and between the interposer structure and the lid structure, wherein the plurality of barrier structures include: A first dam portion is disposed between the first surface of the first passive device and the lid structure and between the first surface of the second passive device and the lid structure, and An annular second dam portion is located between the first dam portion and the interposer structure, wherein the annular second dam portion only surrounds the first passive device and is physically isolated from the first passive device.

7. The package structure according to claim 6, wherein the interposer structure is electrically connected to the circuit substrate through a plurality of conductive terminals, and the package structure further includes an underfill structure surrounding the plurality of conductive terminals, and the plurality of barrier structures contact the underfill structure.

8. The package structure according to claim 6, Wherein, The first dam portion has a first sidewall facing the lid structure and a second sidewall opposite to the first sidewall and facing the first passive device and the second passive device, and the first sidewall of the first dam portion contacts the adhesive material.

9. The package structure according to claim 8, wherein the first dam portion includes a bottom section and a top section, and the width of the first dam portion decreases from the bottom section to the top section.

10. The package structure according to claim 8, Wherein, The height of the annular second dam portion is different from the height of the first dam portion.

11. The package structure according to claim 6, wherein the plurality of barrier structures further include a covering portion covering the first surface, the second surface, the third surface, the fourth surface and the top surface of the second passive device.

12. A method of fabricating a package structure, Comprising: Placing a semiconductor package on a circuit substrate; Forming an underfill structure disposed between the circuit substrate and the semiconductor package; Disposing a first passive device on the circuit substrate adjacent to a first side of the semiconductor package; Disposing a second passive device on the circuit substrate adjacent to a second side of the semiconductor package, wherein the second side is opposite to the first side; Forming a barrier structure, including: Applying a polymer ink material on the circuit substrate adjacent to the first passive device and curing the polymer ink material to form a first dam portion extending in a first direction; By dispensing the polymer ink material on the circuit substrate adjacent to the second passive device and curing the polymer ink material to form an auxiliary first dam portion physically separated from the first dam portion, wherein the auxiliary first dam portion does not overlap with the first dam portion in the first direction, and the auxiliary first dam portion includes a first segment, a second segment, and a third segment, the first segment and the second segment surround two opposite sides of the second passive device, the third segment physically connects the first segment and the second segment and surrounds a third side of the second passive device, the auxiliary first dam portion does not cover a fourth side of the second passive device facing the second side of the semiconductor package, wherein the open ends of the first segment and the second segment include end surfaces facing the underfill structure; and By attaching a cover structure to the circuit substrate with an adhesive material, wherein the first passive device is disposed between the first side of the semiconductor package and the cover structure, and the second passive device is disposed between the second side of the semiconductor package and the cover structure, wherein the first dam portion spaces the first passive device from the cover structure and the adhesive material and is in physical contact with the adhesive material, and the auxiliary first dam portion spaces the second passive device from the cover structure and the adhesive material and is in physical contact with the adhesive material.

13. The method according to claim 12, wherein the first dam portion is formed to have a first sidewall facing the cover structure and a second sidewall opposite to the first sidewall and facing the first passive device, and the cover structure is attached to the circuit substrate such that the adhesive material contacts the first sidewall.

14. The method according to claim 13, wherein the polymer ink material is dispensed on the circuit substrate to surround the first passive device.

15. The method according to claim 13, wherein after forming the auxiliary first dam portion, the polymer ink material is further dispensed in a region on the circuit substrate between the auxiliary first dam portion and the second passive device, and after curing the polymer ink material, a barrier structure including a second dam portion is formed, and the second dam portion is separated from the auxiliary first dam portion.

16. The method according to claim 12, wherein the polymer ink material is dispensed in a region on the circuit substrate overlapping with a third passive device to cover the third passive device, and after curing the polymer ink material, a barrier structure including a covering portion is formed, and the covering portion covers side surfaces and a top surface of the third passive device.

Images