Method for manufacturing semiconductor device and semiconductor device

Abstract

A semiconductor device includes: an isolation insulating layer disposed on a substrate; a semiconductor fin disposed on the substrate; an upper portion of the semiconductor fin protruding from the isolation insulating layer; a lower portion of the semiconductor fin embedded in the isolation insulating layer; a gate structure disposed above the upper portion of the semiconductor fin and including a gate dielectric layer and a gate electrode layer; a gate sidewall spacer disposed above opposite sides of the gate structure; and a source / drain epitaxial layer. The upper portion of the semiconductor fin includes a first epitaxial growth enhancement layer made of a semiconductor material different from that of the rest of the semiconductor fin. The first epitaxial growth enhancement layer contacts the source / drain epitaxial layer. The gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer. Embodiments of the present invention also relate to a method for manufacturing a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method of manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] As the semiconductor industry moves into nanotechnology process nodes in pursuit of higher device density, higher performance and lower cost, the development of three-dimensional designs of multi-gate field effect transistors (FETs), such as fin-type FETs (FinFETs) and gate-all-around (GAA) FETs, has led to challenges from manufacturing and design issues. As transistor dimensions continue to shrink to technology nodes below 10nm-15nm, further improvements to FinFETs are needed. Summary of the invention

[0003] An embodiment of the present invention provides a semiconductor device, comprising: an isolation insulating layer, arranged above a substrate; a semiconductor fin, arranged above the substrate, an upper portion of the semiconductor fin protruding from the isolation insulating layer and a lower portion of the semiconductor fin embedded in the isolation insulating layer; a gate structure, arranged above the upper portion of the semiconductor fin and comprising a gate dielectric layer and a gate electrode layer; a gate sidewall spacer, arranged on opposite sides of the gate structure; and a source / drain epitaxial layer, wherein: the upper portion of the semiconductor fin comprises a first epitaxial growth enhancement layer made of a semiconductor material different from that of the rest of the semiconductor fin, the first epitaxial growth enhancement layer is in contact with the source / drain epitaxial layer, and the gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer.

[0004] Another embodiment of the present invention provides a semiconductor device, comprising: an isolation insulating layer, disposed on a substrate; a semiconductor fin, disposed on the substrate and comprising a bottom fin layer, one or more body layers and one or more epitaxial growth enhancement layers made of a material different from the one or more body layers; a gate structure, disposed above a channel region of the semiconductor fin and comprising a gate dielectric layer and a gate electrode layer; a gate sidewall spacer, disposed on opposite sides of the gate structure; a source / drain epitaxial layer; and a fin liner layer, partially covering the semiconductor fin, wherein: at least one of the one or more epitaxial growth enhancement layers is in contact with the source / drain epitaxial layer, and the fin liner layer is disposed on the semiconductor fin at least below the gate sidewall spacer, and the top of the fin liner layer is higher than the top of the uppermost layer of the one or more epitaxial growth enhancement layers and lower than the top of the channel region.

[0005] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, the method comprising: forming a fin structure above a substrate, the fin structure comprising a bottom fin layer, one or more main layers, and one or more epitaxial growth enhancement layers made of a material different from the one or more main layers; forming an isolation insulating layer on the substrate so that the upper portion of the fin structure protrudes from the isolation insulating layer; forming a sacrificial gate structure above a channel region of the fin structure; forming a source / drain space by recessing the source / drain region of the fin structure so that at least one of the one or more epitaxial growth enhancement layers is exposed in the source / drain space; and forming a source / drain epitaxial layer in the source / drain recess, wherein at least one of the one or more epitaxial growth enhancement layers is in contact with the source / drain epitaxial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0008] Figure 1B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0009] Figure 2A A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0010] Figure 2B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0011] Figure 3 A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0012] Figure 4 A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0013] Figure 5A and Figure 5B A diagram illustrating one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure. Figure 5C and Figure 5D A diagram illustrating one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure. Figure 5B and Figure 5D is a top (plan) view, and Figure 5A and Figure 5C A cross-sectional view is shown.

[0014] Fig. 6A and Figure 6B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0015] Fig. 7A and Figure 7B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0016] Fig. 8A and Figure 8B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0017] Fig.9A and 9B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown. Fig. 9C and Fig.9D A cross-sectional view of a stage in a sequential process for fabricating a FinFET device according to another embodiment of the present disclosure is shown.

[0018] Fig. 10A and Fig. 10B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown. Fig. 10C and Fig. 10D A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0019] Fig.11 A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0020] Fig.12 A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0021] Fig.13 A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0022] Fig.14A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0023] Fig.15A and Fig. 15B A diagram illustrating one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure. Fig. 15B It is a top view (plan view), Fig.15A It is a cross-sectional view.

[0024] Fig.16A and Fig. 16B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0025] Fig.17A and Fig. 17B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown. Fig. 17C and Fig.17D A cross-sectional view of a stage in a sequential process for fabricating a FinFET device according to another embodiment of the present disclosure is shown.

[0026] Fig.18A and Fig.18B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown. Fig. 18C and Fig.18D A cross-sectional view of a stage in a sequential process for fabricating a FinFET device according to another embodiment of the present disclosure is shown.

[0027] Fig.19A and Fig.19B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown. Fig.19C and Fig.19D A cross-sectional view of a stage in a sequential process for fabricating a FinFET device according to another embodiment of the present disclosure is shown.

[0028] Fig. 20A and Fig. 20B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown. Fig. 20C and Fig.20D A cross-sectional view of a stage in a sequential process for fabricating a FinFET device according to another embodiment of the present disclosure is shown.

[0029] Fig.21A and Fig. 21B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown. Fig. 21C and Fig.21D A cross-sectional view of a stage in a sequential process for fabricating a FinFET device according to another embodiment of the present disclosure is shown.

[0030] Fig.22A and Fig. 22B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown. Fig. 22C and Fig.22D A cross-sectional view of a stage in a sequential process for fabricating a FinFET device according to another embodiment of the present disclosure is shown.

[0031] Fig.23 A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0032] Fig.24 A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0033] Fig.25 A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0034] Fig.26 A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0035] Fig.27A and Fig.27B A diagram illustrating one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure.

[0036] Fig.28A and Fig.28B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0037] Fig.29A and Fig.29B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown. Fig.29C and Fig.29D A cross-sectional view of a stage in a sequential process for fabricating a FinFET device according to another embodiment of the present disclosure is shown.

[0038] Fig. 30A and Fig. 30B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0039] Fig.31A and Fig.31B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown. Fig.31C A cross-sectional view of a stage in a sequential process for fabricating a FinFET device according to another embodiment of the present disclosure is shown.

[0040] Fig.32A and Fig.32B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0041] Fig.33A and Fig.33B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0042] Fig.34A and Fig.34B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0043] Fig.35A and Fig.35B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0044] Fig.36A and Fig.36B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0045] Fig.37A and Fig.37B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0046] Fig.38A and Fig.38B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0047] Fig.39A and Fig.39B A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0048] Fig.40 A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown. Specific embodiments

[0049] It should be understood that the following disclosure provides many different embodiments or examples for implementing different components of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which additional components may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. For the sake of simplicity and clarity, various components may be arbitrarily drawn in different proportions.

[0050] In addition, for ease of description, spatial relationship terms such as "below...", "below...", "lower", "above...", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figure. In addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the device in use or operation process. The device can be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used in this article can be interpreted accordingly. In addition, the term "made of..." can mean "including" or "consisting of...". In the present disclosure, unless otherwise stated, the phrase "one of A, B and C" means "A, B and / or C" (A, B, C, A and B, A and C, B and C or A, B and C), otherwise it does not mean an element from A, an element from B and an element from C. Throughout the disclosure, source and drain are used interchangeably, and source / drain refers to one or both of the source and drain. In the following embodiments, materials, configurations, dimensions, processes, and / or operations described with respect to one embodiment (eg, one or more figures) may be adopted in other embodiments, and a detailed description thereof may be omitted.

[0051] Figures 1A to 10B An exemplary sequential process for manufacturing a FET device according to an embodiment of the present disclosure is shown. It should be understood that Figures 1A to 4 Additional operations are provided before, during, and after the process shown. For further embodiments of the method, reference may be made to Figures 1A to 10B Some operations described below may be replaced or eliminated. The order of operations / processes may be interchanged.

[0052] like Figure 1AAs shown, a portion of a substrate 10, in which one or more p-type FETs are subsequently formed, is etched to form a recess 8 by one or more photolithography and etching operations. In one embodiment, the substrate 10 includes a single crystalline semiconductor layer at least on a surface portion thereof. The substrate 10 may include a single crystalline semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In this embodiment, the substrate 10 is made of Si. The substrate 10 may include a variety of regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity). For example, the dopant for n-type Fin FETs is boron (BF2), and the dopant for p-type Fin FETs is phosphorus.

[0053] like Figure 1B As shown, an epitaxial layer 11 is formed in the recess 8. In some embodiments, the epitaxial layer 11 is made of SiGe. In some embodiments, the germanium concentration of the SiGe layer is in the range of about 5 atomic % to about 30 atomic %. In some embodiments, one or more buffer layers having a lower Ge concentration than the epitaxial layer 11 are formed between the epitaxial layer 11 and the substrate 10.

[0054] Furthermore, if Figure 1B As shown, epitaxial growth enhancement layers 20N and 20P are formed over the substrate 10 (n-type region) for one or more n-type FETs and over the epitaxial layer (p-type region) for one or more p-type FETs. In some embodiments, the n-type epitaxial growth enhancement layer 20N includes one or more of SiP, SiCP, SiGe, and SiGeB. In some embodiments, SiP and / or SiCP are used as the n-type epitaxial growth enhancement layer 20N for n-type FETs. In some embodiments, the amount of phosphorus in the n-type epitaxial growth enhancement layer 20N is in the range of about 3 atomic % to about 30 atomic %. If the amount of phosphorus is too large, the n-type epitaxial growth layer 20N may include defects caused by lattice mismatch, and if the amount of phosphorus is too small, the epitaxial enhancement effect may not be obtained. For the p-type epitaxial growth enhancement layer 20P, one or more of SiGe and SiGeB are used for the p-type FET. In some embodiments, the amount of Ge in the p-type epitaxial growth enhancement layer 20P is higher than the amount of Ge in the epitaxial layer 11 and is in the range of about 10 atomic % to about 40 atomic %. If the amount of Ge is too large, the p-type epitaxial growth layer 20P may include defects caused by lattice mismatch, and if the amount of Ge is too small, the epitaxial enhancement effect may not be obtained. When the epitaxial growth enhancement layers 20N and 20P are semiconductor materials, the epitaxial growth enhancement layers can be epitaxially formed on the semiconductor substrate 10 and the epitaxial layer 11, respectively.

[0055] In some embodiments, the epitaxial growth enhancement layer includes an oxide of one or more of Si, SiP, and SiGe. The oxide of Si, SiP, and / or SiGe can be formed by chemical vapor deposition (CVD), such as low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0056] In some embodiments, the epitaxial growth enhancement layer is formed by one or more ion implantation operations. In some embodiments, the dopant is P and / or Ge.

[0057] In some embodiments, the thickness of the epitaxial growth enhancement layer 20N, 20P is in the range of about 1 nm to about 50 nm, and in other embodiments, in the range of 5 nm to 30 nm. When the thickness is greater than these ranges, the channel performance may be reduced, and when the thickness is less than these ranges, the function of serving as an epitaxial growth enhancement layer becomes insufficient.

[0058] In other embodiments, any one of the n-type epitaxial growth enhancement layer 20N or the p-type epitaxial growth enhancement layer 20P is formed.

[0059] In some embodiments, a mask layer 15 is further formed on the epitaxial growth enhancement layers 20N and 20P. In some embodiments, the mask layer 15 includes a first mask layer 15A and a second mask layer 15B. The first mask layer 15A is a pad oxide layer made of silicon oxide that can be formed by thermal oxidation. The second mask layer 15B is made of silicon nitride (SiN), which is formed by CVD, PVD, ALD or other suitable processes.

[0060] In other embodiments, the recess 8 is not formed and the epitaxial layer 11 is not formed, so that Figure 2A and Figure 2B An n-type FET and a p-type FET are formed on the Si substrate 10 shown. In this case, an epitaxial growth enhancement layer 20 is formed on both the n-type region and the p-type region. In other embodiments, the epitaxial growth enhancement layer 20 is formed on either the n-type region or the p-type region. In other embodiments, the n-type region of the substrate 10 is also etched to form a recess, and a silicon layer is epitaxially formed in the recess. An embodiment of forming an epitaxial layer 11 (e.g., a SiGe layer) is shown below. However, the following embodiments are applicable to the case where the epitaxial layer 11 is not formed. In this case, the p-type FET and the n-type FET have substantially the same fin channel structure except for the epitaxial growth layer.

[0061] Next, if Figure 3As shown, the mask layer 15 in the p-type region, the substrate 10, and the epitaxial layer 11 are patterned by using a patterned mask layer to form fin structures 12N and 12P (collectively referred to as fin structures 12) extending in the Y direction. In some embodiments, the fin structure 12N is used for an n-type FET, and the fin structure 12P is used for a p-type FET. Figure 3 In the embodiment, two fin structures are arranged in the X direction for n-type FET and p-type FET, respectively. However, the number of fin structures is not limited to two, and may be one or three or more. In some embodiments, one or more dummy fin structures are formed on both sides of the fin structure 12 to improve pattern fidelity in the patterning operation.

[0062] The fin structure 12 may be patterned by any suitable method. For example, the fin structure may be patterned using one or more lithography processes including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines lithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a pitch that is smaller than that obtainable using a single direct lithography method. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may be used to pattern the fin structure. The multiple patterning process combining lithography and self-alignment processes typically results in the formation of a pair of fin structures.

[0063] After forming the fin structure, an insulating material layer including one or more insulating materials is formed over the substrate so that the fin structure 12 is completely embedded in the insulating layer. The insulating material used for the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-K dielectric material formed by LPCVD (low pressure chemical vapor deposition), plasma CVD, or flowable CVD. An annealing operation may be performed after forming the insulating layer. Then, a planarization operation such as a chemical mechanical polishing (CMP) method and / or an etch-back method is performed so that the upper surface of the epitaxial growth enhancement layer 20N, 20P is exposed from the insulating material layer. Then, as Figure 4 As shown, the insulating material layer is recessed to form an isolation insulating layer 30, thereby exposing the upper portion of the fin structure 12. With this operation, the fin structures 12 are electrically isolated from each other by the isolation insulating layer 30, which is also called shallow trench isolation (STI).

[0064] After forming the isolation insulating layer 30, a sacrificial gate structure 40 is formed above the fin structure. Figure 5A and Figure 5B shown. Figure 5B It is a top view (plan view), Figure 5A is corresponding to Figure 5B. In some embodiments, the sacrificial gate structure includes a sacrificial gate dielectric layer 42, a sacrificial gate electrode layer 44 and a hard mask layer 46. The sacrificial gate dielectric layer 42 includes one or more layers of insulating material, such as a silicon oxide-based material. In one embodiment, silicon oxide formed by CVD is used. In some embodiments, the thickness of the sacrificial gate dielectric layer 42 is in the range of about 1 nm to about 5 nm. The sacrificial gate electrode layer 44 includes silicon such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate electrode layer is in the range of about 100 nm to about 200 nm. In some embodiments, the sacrificial gate electrode layer is subjected to a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD including LPCVD and PECVD, PVD, ALD or other suitable processes. The hard mask layer 46 is used to form the sacrificial gate electrode layer 44 and includes one or more layers of silicon nitride and silicon. In some embodiments, the sacrificial gate dielectric layer 42 also covers the source / drain region of the fin structure 12 having the epitaxial growth enhancement layer 20N, 20P. To keep it simple, Figure 5B The sacrificial gate dielectric layer 42 is not shown.

[0065] After forming the sacrificial gate structure, a capping layer of insulating material for sidewall spacers 48 is conformally formed by using CVD or other suitable methods. The capping layer is deposited in a conformal manner so that it is formed to have substantially equal thickness on vertical surfaces, such as the sidewalls, horizontal surfaces, and top of the sacrificial gate structure. In some embodiments, the capping layer is deposited to a thickness in the range of about 2 nm to about 10 nm. In one embodiment, the insulating material of the capping layer is a silicon nitride-based material, such as SiN, SiON, SiOCN, or SiCN, and combinations thereof. Sidewall spacers 48 are formed on opposite sidewalls of the sacrificial gate structure 40, such as Figure 5A and Figure 5B shown.

[0066] exist Figure 5A and Figure 5B In the embodiment of the present invention, the sacrificial gate structure 40 is disposed above the n-type fin structure 12N and the p-type fin structure. In other embodiments, separate sacrificial gate structures are formed above the n-type fin structure 12N and the p-type fin structure, respectively, such as Figure 5C and Figure 5D shown.

[0067] Subsequently, the fin structure of the source / drain region is recessed downward below the upper surface of the isolation insulating layer 30 by using dry etching and / or wet etching. Fig. 6A and Figure 6B shown. Fig. 6A is corresponding to Figure 5B A cross-sectional view of the line X2-X2, Figure 6B is corresponding to Figure 5A A cross-sectional view along line Y1-Y1.

[0068] like Figure 6B As shown, the side surfaces of the epitaxial growth enhancement layers 20N and 20P are exposed in the source / drain recesses 25N and 25P, respectively.

[0069] In some embodiments, a capping layer of dielectric material for the fin sidewalls is formed prior to the recess etch, and an anisotropic etch is performed on the capping layer using, for example, reactive ion etching (RIE). In some embodiments, the fin sidewall spacers 49 remain around the source / drain recesses, such as Fig. 6A shown.

[0070] After forming the source / drain recesses, source / drain (S / D) epitaxial layers 50N and 50P are formed, as shown in FIG. Fig. 7A and Figure 7B shown. Fig. 7A is corresponding to Figure 5B A cross-sectional view of the line X2-X2, Figure 7B is corresponding to Figure 5B sectional view of line Y1-Y1 of the n-type FET. The S / D epitaxial layer 50N of the n-type FET includes one or more layers of SiP and SiCP. In at least one embodiment, the epitaxial layer is epitaxially grown by an LPCVD process, molecular beam epitaxy, atomic layer deposition, or any other suitable method. The LPCVD process is performed using a silicon source gas (such as SiH4, Si2H6, or Si3H8), a germanium source gas (such as GeH4 or G2H6), a carbon source gas (such as CH4 or SiH3CH3), a phosphorus source gas (such as PH3), and a boron source gas (such as B2H6) at a temperature of about 400 to about 850° C. and a pressure of about 1 Torr to about 200 Torr. In some embodiments, two or more layers with different compositions (e.g., different P, C, Ge, and / or B concentrations) are formed as source / drain epitaxial layers 50N and 50P, respectively.

[0071] Because the n-type epitaxial growth enhancement layer 20N includes P, the n-type epitaxial growth enhancement layer 20N is used as an additional source of P in addition to the epitaxially grown P source gas. Therefore, the size (volume) of the source / drain epitaxial layer 50N can be larger than the case where the epitaxial growth enhancement layer 20N is not formed. Similarly, the S / D epitaxial layer 50P for the p-type FET includes SiGe, Ge, and SiGeB. Because the p-type epitaxial growth enhancement layer 20P includes Ge, the p-type epitaxial growth enhancement layer 20P is used as an additional source of Ge in addition to the epitaxially grown Ge source gas. Therefore, the size (volume) of the source / drain epitaxial layer 50P can be larger than the case where the epitaxial growth enhancement layer 20P is not formed.

[0072] Subsequently, a first interlayer dielectric (ILD) layer 60 is formed over the source / drain epitaxial layers 50N and 50P and the sacrificial gate structure 40. Then, a planarization operation such as CMP is performed so that the top of the sacrificial gate electrode layer 44 is exposed, as shown in FIG. Fig. 8A and Figure 8B shown. Fig. 8A is corresponding to Figure 5B A cross-sectional view of the line X2-X2, Figure 8B is corresponding to Figure 5B 2 . A material for the first ILD layer 60 includes a compound containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. An organic material such as a polymer may be used for the first ILD layer 60 .

[0073] Next, the sacrificial gate electrode layer 44 and the sacrificial gate dielectric layer 42 are removed to expose the fin structure. The first ILD layer 60 protects the S / D structures 50N, 50P during the removal of the sacrificial gate structure. The sacrificial gate structure 40 can be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode layer 44 is polysilicon and the first ILD layer 60 is silicon oxide, a wet etchant such as a TMAH solution can be used to selectively remove the sacrificial gate electrode layer 44. Thereafter, the sacrificial gate dielectric layer 42 is removed using plasma dry etching and / or wet etching.

[0074] After removing the sacrificial gate structure, a gate dielectric layer 102 is formed over the channel region (the upper portion of the fin structure over the isolation insulating layer 30), and a gate electrode layer 104 is formed over the gate dielectric layer 102. Fig.9A and Fig. 9B shown. Fig.9A is corresponding to Figure 5B A cross-sectional view of the line X1-X1, Fig. 9B is corresponding to Figure 5B A cross-sectional view along line Y1-Y1.

[0075] In some embodiments, the gate dielectric layer 102 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride or high-k dielectric materials, other suitable dielectric materials and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-k dielectric materials and / or combinations thereof. In some embodiments, the gate dielectric layer 102 includes an interface layer formed between the channel layer and the dielectric material.

[0076] The gate dielectric layer 102 may be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer 102 is formed using a highly conformal deposition process such as ALD to ensure that a gate dielectric layer having a uniform thickness is formed on each channel layer. In one embodiment, the thickness of the gate dielectric layer 102 is in a range of about 1 nm to about 6 nm.

[0077] The gate electrode layer 104 is formed on the gate dielectric layer 102. The gate electrode 104 includes one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof.

[0078] The gate electrode layer 104 can be formed by CVD, ALD, electroplating or other suitable methods. The gate electrode layer is also deposited on the upper surface of the first ILD layer 60. The gate dielectric layer and the gate electrode layer formed above the first ILD layer 60 are then planarized by using, for example, CMP until the top surface of the first ILD layer 60 is exposed. In some embodiments, after the planarization operation, the gate electrode layer 104 is recessed and a cap insulating layer is formed above the recessed gate electrode 104. The cap insulating layer includes one or more layers of silicon nitride-based materials, such as SiN. The cap insulating layer can be formed by depositing an insulating material and then performing a planarization operation.

[0079] In certain embodiments of the present disclosure, one or more work function adjustment layers (not shown) are inserted between the gate dielectric layer 102 and the gate electrode 104. The work function adjustment layer is made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. For n-channel FETs, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi are used as work function adjustment layers, and for p-channel FETs, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co are used as work function adjustment layers. The work function adjustment layer can be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes. In addition, the work function adjustment layer can be formed separately for n-channel FETs and p-channel FETs that can use different metal layers.

[0080] It should be understood that Fig.9A and Fig. 9B The semiconductor device shown is subjected to further CMOS processing to form various features, such as contacts / vias, interconnect metal layers, dielectric layers, passivation layers, and the like.

[0081] Fig. 9C and Fig.9D A semiconductor device according to another embodiment is shown in which the epitaxial layer 11 is not formed. An epitaxial growth enhancement layer 20P is formed on the Si fin structure.

[0082] In other embodiments, before forming the gate dielectric layer 102, at least one of the epitaxial growth enhancement layers 20N and 20P is removed by a suitable etching operation, and then the gate dielectric layer 102 and the gate electrode layer 104 are formed. Fig. 10A and Fig. 10B shown. Fig. 10A is corresponding to Figure 5B A cross-sectional view of the line X1-X1, Fig. 10B is corresponding to Figure 5B When the epitaxial growth enhancement layers 20N and 20P are made of an oxide material (eg, SiP oxide, SiGe oxide), the epitaxial growth enhancement layers 20N and 20P are removed. Fig. 10B As shown, in some embodiments, portions of the epitaxial growth enhancement layers 20N and / or 20P remain beneath the sidewall spacers 48 .

[0083] Fig. 10C and Fig. 10D A semiconductor device according to another embodiment is shown in which the epitaxial layer 11 is not formed. An epitaxial growth enhancement layer 20P is formed on the Si fin structure.

[0084] Figures 11 to 17B An exemplary sequential process for manufacturing a FET device according to an embodiment of the present disclosure is shown. It should be understood that additional embodiments of the method may be Figures 11 to 17B Additional operations are provided before, during, and after the processes shown, and some operations described below may be replaced or eliminated. The order of operations / processes may be interchangeable. The materials, configurations, dimensions, processes, and / or operations described in the preceding embodiments may be adopted in the following embodiments, and their detailed descriptions may be omitted.

[0085] exist Figures 1A to 10B In the embodiment of the present invention, the epitaxial growth enhancement layer is formed at the top of the fin structure. In the following embodiment, the epitaxial growth enhancement layer is formed in the middle of the fin structure.

[0086] like Fig.11As shown, an n-type epitaxial growth enhancement layer 22N is formed over the substrate 10, and a first semiconductor layer 23N is formed over the n-type epitaxial growth enhancement layer 22N. Then, by using one or more photolithography and etching operations, a recess 8 is formed at the p-type region. In some embodiments, the first epitaxial layer 23N is made of the same material as the substrate 10, such as Si. In other embodiments, the first epitaxial layer 23N is made of a different material from the substrate 10 or a material having a different composition.

[0087] Then, if Fig.12 As shown, in the recess 8 of the p-type region, the second epitaxial layer 11, the p-type epitaxial growth enhancement layer 22P, and the third epitaxial layer 23P are sequentially formed in the recess 8. In some embodiments, the third epitaxial layer 23P is made of the same material as the second epitaxial layer 11. In other embodiments, the third epitaxial layer 23P is made of a different material from the second epitaxial layer 11 or a material having a different composition.

[0088] The thickness of the n-type and p-type epitaxial growth enhancement layers 22N and 22P ranges from about 1 nm to about 50 nm in some embodiments, and from 5 nm to 30 nm in other embodiments. The heights (levels) of the n-type and p-type epitaxial growth enhancement layers 22N and 22P may be the same or different from each other.

[0089] In addition, if Fig.12 As shown, a mask layer 15 including a first mask layer 15A and a second mask layer 15B is further formed on the first epitaxial layer 23N and the third epitaxial layer 23P. In some embodiments, the first mask layer 15A is a pad oxide layer made of silicon oxide, which can be formed by thermal oxidation. The second mask layer 15B is made of silicon nitride (SiN), which is formed by chemical vapor deposition (CVD), including low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable processes. In other embodiments, the mask layer 15 is a single layer.

[0090] In other embodiments, the recess 8 is not formed and the second epitaxial layer 11 is not formed. In this case, an epitaxial growth enhancement layer is formed on the n-type region and the p-type region over the substrate 10, and an epitaxial layer is formed on the epitaxial growth enhancement layer.

[0091] Similar to Figure 3 , patterning the mask layer 15, and patterning the first, second and third epitaxial layers, the p-type and n-type epitaxial growth enhancement layers and the substrate 10 by using the patterned mask layer, so that the stacked layers are formed in the fin structures 12N and 12P (collectively referred to as the fin structure 12) extending in the Y direction, as shown in Fig.12 shown.

[0092] After forming the fin structure 12, similar to Figure 4 , forming an isolation insulating layer 30, such as Fig.14 In some embodiments, n-type and p-type epitaxial growth enhancement layers 22N and 22P are located above the upper surface of the isolation insulating layer 30 .

[0093] After forming the isolation insulating layer 30, similar to FIG. 5A to FIG. 5D , forming a sacrificial gate structure 40 over the fin structure and forming a gate sidewall spacer 48, as shown in Fig.15A and Fig. 15B shown. Fig. 15B It is a top view (plan view), Fig.15A is corresponding to Fig. 15B A cross-sectional view along line X1-X1.

[0094] Then, similar to FIG. 6A to FIG. 7B , the fin structure of the source / drain region is recessed downward below the upper surface of the isolation insulating layer 30 by using dry etching and / or wet etching, and source / drain epitaxial layers 50N and 50P are formed, as shown in FIG. Fig.16A and Fig. 16B shown. Fig.16A is corresponding to Fig. 15B A cross-sectional view of the line X2-X2, Fig. 16B is corresponding to Fig. 15B A cross-sectional view along line Y1-Y1.

[0095] like Fig. 16B As shown, the side of the epitaxial growth enhancement layer 22N (and 22P) is exposed in the source / drain recess and serves as an additional source of the epitaxial layer 50N (and 50P). Since the n-type epitaxial growth enhancement layer 22N includes P, the n-type epitaxial growth enhancement layer 22N serves as an additional source of P in addition to the epitaxially grown P source gas. Therefore, the size of the source / drain epitaxial layer 50N can be larger than that in the case where the epitaxial growth enhancement layer 20N is not formed. Similarly, the S / D epitaxial layer 50P of the p-type FET includes SiGe, Ge, and SiGeB. Since the p-type epitaxial growth enhancement layer 22P includes Ge, the p-type epitaxial growth enhancement layer 22P serves as an additional source of Ge in addition to the epitaxially grown Ge source gas. Therefore, the size of the source / drain epitaxial layer 50P can be larger than that in the case where the epitaxial growth enhancement layer 22P is not formed.

[0096] Then, similar to FIG. 8A to FIG. 9B, a first interlayer dielectric (ILD) layer 60 is formed over the source / drain epitaxial layers 50N and 50P and the sacrificial gate structure 40. Then, a planarization operation such as CMP is performed so that the top of the sacrificial gate electrode layer 44 is exposed. Then, the sacrificial gate electrode layer 44 and the sacrificial gate dielectric layer 42 are removed, thereby exposing the fin structure. After removing the sacrificial gate structure, a gate dielectric layer 102 is formed over the channel region and a gate electrode layer 104 is formed on the gate dielectric layer 102, as shown in FIG. Fig.17A and Fig. 17B shown. Fig.17A is corresponding to Fig. 15B A cross-sectional view of the line X1-X1, Fig. 17B is corresponding to Fig. 15B In some embodiments, when the epitaxial growth enhancement layer is made of a semiconductor material, the epitaxial growth enhancement layer is not removed, and the gate dielectric layer 102 covers the side surfaces of the epitaxial growth enhancement layer.

[0097] It should be understood that Fig.17A and Fig. 17B The semiconductor device shown undergoes further CMOS processing to form various features, such as contacts / vias, interconnect metal layers, dielectric layers, passivation layers, and the like.

[0098] Fig. 17C and Fig.17D A semiconductor device according to another embodiment is shown in which no epitaxial layer 11 is formed. An epitaxial growth enhancement layer 22P is formed in the Si fin structure.

[0099] Fig.18A and Fig.18B A cross-sectional view of one stage of a sequential process for manufacturing a FinFET device according to an embodiment of the present disclosure is shown. The materials, configurations, dimensions, processes and / or operations described with respect to the previous embodiments may be adopted in the following embodiments, and their detailed description may be omitted. Fig.18A is corresponding to Fig. 15B A cross-sectional view of the line X1-X1, Fig.18B is corresponding to Fig. 15B A cross-sectional view along line Y1-Y1.

[0100] like Fig.18A and Fig.18BAs shown, two epitaxial growth enhancement layers are provided in a fin structure for at least one of an n-type FET and a p-type FET. In some embodiments, the fin structure of the n-type FET includes a first n-type epitaxial growth enhancement layer 122N, a first epitaxial layer 123N, a second n-type epitaxial growth enhancement layer 124N, and a second epitaxial layer 125N stacked sequentially. The fin structure of the n-type FET can be formed by stacking semiconductor materials corresponding to the respective layers and patterning by one or more photolithography and etching operations. The first and second n-type epitaxial growth enhancement layers are made of the same material (e.g., SiP) in some embodiments, or of different materials or materials having different compositions from each other in other embodiments. In other embodiments, the first epitaxial layer 123N and the second epitaxial layer 125N are made of the same material (e.g., Si), or of different materials or materials having different compositions from each other. Similarly, in some embodiments, the fin structure of the p-type FET includes a first p-type epitaxial growth enhancement layer 122P, a third epitaxial layer 123P, a second p-type epitaxial growth enhancement layer 124P, and a fourth epitaxial layer 125P stacked sequentially. The fin structure of a p-type FET can be formed by stacking semiconductor materials corresponding to the respective layers and patterning by one or more photolithography and etching operations. The first and second p-type epitaxial growth enhancement layers are made of the same material (e.g., SiGe) in some embodiments, or are made of different materials or materials having different compositions from each other in other embodiments. In other embodiments, the third and fourth epitaxial layers 123P and 125P are made of the same material (e.g., SiGe), or are made of different materials or materials having different compositions from each other. In some embodiments, before and / or after forming the source / drain epitaxial layer 50P, the Ge concentration of the first and second p-type epitaxial growth enhancement layers is greater than the Ge concentration of the epitaxial layer 11 and the third and fourth epitaxial layers.

[0101] In some embodiments, the first n-type and first p-type epitaxial growth enhancement layers 122N and 122P are located below the upper surface of the isolation insulating layer 30, and the second n-type and second p-type epitaxial growth enhancement layers 124N and 124P are located above the upper surface of the isolation insulating layer 30, such as Fig.18A shown.

[0102] like Fig.18BAs shown, the side surfaces of the first and second n-type epitaxial growth enhancement layers 122N and 124N are exposed in the source / drain recess and serve as an additional source of the epitaxial layer 50N. Therefore, the size of the source / drain epitaxial layer 50N can be larger than that in the case where the epitaxial growth enhancement layer is not formed. Similarly, since the first and second p-type epitaxial growth enhancement layers 122P and 124P include Ge, the p-type epitaxial growth enhancement layer serves as an additional source of Ge in addition to the epitaxially grown Ge source gas. Therefore, the size of the source / drain epitaxial layer 50P can be larger than that in the case where the epitaxial growth enhancement layer is not formed.

[0103] Fig. 18C and Fig.18D A semiconductor device according to another embodiment is shown in which the epitaxial layer 11 is not formed. Epitaxial growth enhancement layers 122P and 124P are formed in the Si fin structure.

[0104] Fig.19A and Fig.19B A cross-sectional view of one stage of a sequential process for manufacturing a FinFET device according to an embodiment of the present disclosure is shown. The materials, configurations, dimensions, processes and / or operations described with respect to the previous embodiments may be adopted in the following embodiments, and their detailed description may be omitted. Fig.19A is corresponding to Fig. 15B A cross-sectional view of the line X1-X1, Fig.19B is corresponding to Fig. 15B A cross-sectional view along line Y1-Y1.

[0105] like Fig.19A and Fig.19BAs shown, three epitaxial growth enhancement layers are provided in the fin structure of at least one of the n-type FET and the p-type FET. In some embodiments, the fin structure of the n-type FET includes a first n-type epitaxial growth enhancement layer 222N, a first epitaxial layer 223N, a second n-type epitaxial growth enhancement layer 224N, a second epitaxial layer 225N, a third n-type epitaxial growth enhancement layer 226N and a third epitaxial layer 227N stacked sequentially. The fin structure of the n-type FET can be formed by stacking semiconductor materials corresponding to the respective layers and patterning by one or more photolithography and etching operations. The first, second and third n-type epitaxial growth enhancement layers are made of the same material (e.g., SiP) in some embodiments, or are made of different materials or materials having different compositions from each other in other embodiments. In other embodiments, the first, second and third epitaxial layers 223N, 225N and 227N are made of the same material (e.g., Si), or are made of different materials or materials having different compositions from each other. Similarly, in some embodiments, the fin structure of the p-type FET includes a first p-type epitaxial growth enhancement layer 222P, a fourth epitaxial layer 223P, a second p-type epitaxial growth enhancement layer 224P, a fifth epitaxial layer 225P, a third p-type epitaxial growth enhancement layer 226P, and a sixth epitaxial layer 227P stacked in sequence. The fin structure of the p-type FET can be formed by stacking semiconductor materials corresponding to the respective layers and patterning by one or more photolithography and etching operations. The first, second, and third p-type epitaxial growth enhancement layers are made of the same material (e.g., SiGe) in some embodiments, or are made of different materials or materials having different compositions from each other in other embodiments. In other embodiments, the fourth, fifth, and sixth epitaxial layers 223P, 225P, and 227P are made of the same material (e.g., SiGe), or are made of different materials or materials having different compositions from each other. In some embodiments, before and / or after forming the source / drain epitaxial layer 50P, the Ge concentration of the first, second and third p-type epitaxial growth enhancement layers is greater than the Ge concentration of the epitaxial layer 11 and the fourth, fifth and sixth epitaxial layers.

[0106] In some embodiments, the first n-type and first p-type epitaxial growth enhancement layers 222N and 222P are located below the upper surface of the isolation insulating layer 30, and the second and third n-type and second and third p-type epitaxial growth enhancement layers 224N, 226N, 224P, and 226P are located above the upper surface of the isolation insulating layer 30, as shown in FIG. Fig.19A shown.

[0107] Fig.19C and Fig.19D A semiconductor device according to another embodiment is shown in which the epitaxial layer 11 is not formed. Epitaxial growth enhancement layers 222P, 224P, and 226P are formed in the Si fin structure.

[0108] Fig. 20A and Fig. 20B A cross-sectional view of one stage of a sequential process for manufacturing a FinFET device according to an embodiment of the present disclosure is shown. The materials, configurations, dimensions, processes and / or operations described with respect to the previous embodiments may be adopted in the following embodiments, and their detailed description may be omitted. Fig. 20A is corresponding to Fig. 15B A cross-sectional view of the line X1-X1, Fig. 20B is corresponding to Fig. 15B A cross-sectional view along line Y1-Y1.

[0109] like Fig. 20A and Fig. 20B As shown, two epitaxial growth enhancement layers are provided in the fin structure of at least one of the n-type FET and the p-type FET. In some embodiments, the fin structure of the n-type FET includes a first n-type epitaxial growth enhancement layer 322N, a first epitaxial layer 323N, and a second n-type epitaxial growth enhancement layer 324N stacked sequentially. The fin structure of the n-type FET can be formed by stacking semiconductor materials corresponding to the respective layers and patterning by one or more photolithography and etching operations. The first and second n-type epitaxial growth enhancement layers are made of the same material (e.g., SiP) in some embodiments, or made of different materials or materials having different compositions from each other in other embodiments. In some embodiments, the first epitaxial layer 323N is made of the same material as the substrate 10 (e.g., Si). Similarly, in some embodiments, the fin structure of the p-type FET includes a first p-type epitaxial growth enhancement layer 322P, a second epitaxial layer 323P, and a second p-type epitaxial growth enhancement layer 324P stacked sequentially. The fin structure of the p-type FET can be formed by stacking semiconductor materials corresponding to the respective layers and patterning by one or more photolithography and etching operations. The first and second p-type epitaxial growth enhancement layers are made of the same material (e.g., SiGe) in some embodiments, or made of different materials or materials with different compositions from each other in other embodiments. In other embodiments, the second epitaxial layer 323P is made of the same material (e.g., SiGe) as the epitaxial layer 11, or made of different materials or materials with different compositions from each other. In some embodiments, before and / or after forming the source / drain epitaxial layer 50P, the Ge concentration of the first and second p-type epitaxial growth enhancement layers is greater than the Ge concentration of the epitaxial layer 11 and the third epitaxial layer.

[0110] In some embodiments, the first n-type and first p-type epitaxial growth enhancement layers 322N and 322P are located below the upper surface of the isolation insulating layer 30, and the second n-type and second p-type epitaxial growth enhancement layers 324N and 324P are located above the upper surface of the isolation insulating layer 30, such as Fig. 20A shown.

[0111] Fig. 20C and 20D A semiconductor device according to another embodiment is shown in which the epitaxial layer 11 is not formed. An epitaxial growth enhancement layer 322P is formed in the Si fin structure, and an epitaxial growth enhancement layer 324P is formed on the Si fin structure.

[0112] Fig.21A and Fig. 21B A cross-sectional view of one stage of a sequential process for manufacturing a FinFET device according to an embodiment of the present disclosure is shown. The materials, configurations, dimensions, processes and / or operations described with respect to the previous embodiments may be adopted in the following embodiments, and their detailed description may be omitted. Fig.21A is corresponding to Fig. 15B A cross-sectional view of the line X1-X1, Fig. 21B is corresponding to Fig. 15B A cross-sectional view along line Y1-Y1.

[0113] like Fig.21A and Fig. 21BAs shown, three epitaxial growth enhancement layers are provided in the fin structure of at least one of the n-type FET and the p-type FET. In some embodiments, the fin structure of the n-type FET includes a first n-type epitaxial growth enhancement layer 422N, a first epitaxial layer 423N, a second n-type epitaxial growth enhancement layer 424N, a second epitaxial layer 425N, and a third n-type epitaxial growth enhancement layer 426N stacked in sequence. The fin structure of the n-type FET can be formed by stacking semiconductor materials corresponding to the respective layers and patterning by one or more photolithography and etching operations. The first, second, and third n-type epitaxial growth enhancement layers are made of the same material (e.g., SiP) in some embodiments, or are made of different materials or materials having different compositions from each other in other embodiments. In other embodiments, the first and second epitaxial layers 423N, 425N are made of the same material (e.g., Si) as the substrate 10, or are made of different materials or materials having different compositions from each other. Similarly, in some embodiments, the fin structure of the p-type FET includes a first p-type epitaxial growth enhancement layer 422P, a third epitaxial layer 423P, a second p-type epitaxial growth enhancement layer 424P, a fourth epitaxial layer 425P, and a third p-type epitaxial growth enhancement layer 426P stacked in sequence. The fin structure of the p-type FET can be formed by stacking semiconductor materials corresponding to the respective layers and patterning by one or more photolithography and etching operations. The first, second, and third p-type epitaxial growth enhancement layers are made of the same material (e.g., SiGe) in some embodiments, or are made of different materials or materials having different compositions from each other in other embodiments. In other embodiments, the third and fourth epitaxial layers 423P and 425P are made of the same material (e.g., SiGe), or are made of different materials or materials having different compositions from each other. In some embodiments, before and / or after forming the source / drain epitaxial layer 50P, the Ge concentration of the first, second, and third p-type epitaxial growth enhancement layers is greater than the Ge concentration of the epitaxial layer 11 and the third and fourth epitaxial layers.

[0114] In some embodiments, the first n-type and first p-type epitaxial growth enhancement layers 422N and 422P are located below the upper surface of the isolation insulating layer 30, and the second and third n-type and second and third p-type epitaxial growth enhancement layers 424N, 426N, 424P, and 426P are located above the upper surface of the isolation insulating layer 30, as shown in FIG. Fig.21A shown.

[0115] Fig. 21C and Fig.21D A semiconductor device according to another embodiment is shown, in which the epitaxial layer 11 is not formed. Epitaxial growth enhancement layers 422P, 424P are formed in the Si fin structure, and an epitaxial growth enhancement layer 426P is formed on the Si fin structure.

[0116] Fig.22A and Fig. 22B A cross-sectional view of one stage of a sequential process for manufacturing a FinFET device according to an embodiment of the present disclosure is shown. The materials, configurations, dimensions, processes and / or operations described with respect to the previous embodiments may be adopted in the following embodiments, and their detailed description may be omitted. Fig.22A is corresponding to Fig. 15B A cross-sectional view of the line X1-X1, Fig. 22B is corresponding to Fig. 15B A cross-sectional view along line Y1-Y1.

[0117] like Fig.22A and Fig. 22B As shown, an epitaxial growth enhancement layer is provided in the fin structure of at least one of the n-type FET and the p-type FET. In some embodiments, the fin structure of the n-type FET includes an n-type epitaxial growth enhancement layer 522N and a first epitaxial layer 523N stacked in sequence. The fin structure of the n-type FET can be formed by stacking semiconductor materials corresponding to the respective layers and patterning by one or more photolithography and etching operations. In other embodiments, the first epitaxial layer 523N is made of the same material as the substrate 10 (e.g., Si), or is made of a different material or a material having a different composition from each other. Similarly, in some embodiments, the fin structure of the p-type FET includes a p-type epitaxial growth enhancement layer 522P and a second epitaxial layer 523P stacked in sequence. The fin structure of the p-type FET can be formed by stacking semiconductor materials corresponding to the respective layers and patterning by one or more photolithography and etching operations. In other embodiments, the second epitaxial layer 523P is made of the same material as the epitaxial layer 11 (e.g., SiGe), or is made of a different material or a material having a different composition from each other. In some embodiments, before and / or after forming the source / drain epitaxial layer 50P, the Ge concentration of the p-type epitaxial growth enhancement layer is greater than the Ge concentrations of the epitaxial layer 11 and the second epitaxial layer.

[0118] In some embodiments, the n-type and p-type epitaxial growth enhancement layers 522N and 522P are located below the upper surface of the isolation insulating layer 30, such as Fig.22A shown.

[0119] Fig. 22C and Fig.22D A semiconductor device according to another embodiment is shown, in which the epitaxial layer 11 is not formed. An epitaxial growth enhancement layer 522P is formed in the Si fin structure.

[0120] In some embodiments, the number of n-type and / or p-type epitaxial growth enhancement layers is greater than three and up to twenty.

[0121] Figures 23 to 29BAn exemplary sequential process for manufacturing a FET device according to an embodiment of the present disclosure is shown. It should be understood that additional embodiments of the method may be Figures 23 to 29B Additional operations are provided before, during, and after the processes shown, and some operations described below may be replaced or eliminated. The order of operations / processes may be interchangeable. The materials, configurations, dimensions, processes, and / or operations described in the preceding embodiments may be employed in the following embodiments, and their detailed descriptions may be omitted.

[0122] After forming the fin structures 12N and 12P, as shown in FIG. Fig.13 As shown, a liner 70 is formed to cover the fin structure. Fig.23 As shown. The liner 70 includes one or more of silicon nitride, SiON, SiCN, SiOCN, SiOC and other suitable materials. In some embodiments, silicon nitride is used. In some embodiments, the thickness of the liner layer 70 is in the range of about 0.5nm to about 20nm. The liner 70 prevents the outward diffusion of P or Ge in the epitaxial growth enhancement layer before the source / drain epitaxial layer is formed. The liner 70 can be formed by CVD, PVD, ALD or other suitable film formation processes.

[0123] After forming the liner layer 70, an insulating material layer 30 including one or more insulating materials is formed over the substrate so that the fin structure 12 is completely embedded in the insulating layer. The insulating material used for the insulating layer 30 may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-K dielectric material formed by LPCVD (low pressure chemical vapor deposition), plasma CVD, or flowable CVD. An annealing operation may be performed after forming the insulating layer. Then, a planarization operation such as a chemical mechanical polishing (CMP) method and / or an etch-back method is performed so that the upper surface of the fin structure 12N, 12P is exposed from the insulating material layer, such as Fig.24 shown.

[0124] Then, if Fig.25 As shown, the insulating material layer 30 is recessed to a level above the upper surfaces of the n-type and p-type epitaxial growth enhancement layers 22N and 22P, and the exposed liner layer 70 is further removed by the recessing process, as shown in FIG. Fig.25 Then, the insulating material layer 30 is further recessed to form an isolation insulating layer 30 so that the upper portion of the fin structure 12 including the n-type and p-type epitaxial growth enhancement layers 22N and 22P is covered by the exposed liner layer 70, as shown in FIG. Fig.26As shown. In some embodiments, one or more plasma dry etching operations are used to recess the insulating material layer 30 and the liner layer 70. In other embodiments, wet etching is used. In some embodiments, when the insulating material layer 30 is silicon oxide and the liner layer 70 is silicon nitride, buffered HF or dilute HF is used to recess the insulating material layer 30 and H3PO4 is used to remove the liner layer.

[0125] After forming the isolation insulating layer 30, similar to FIG. 5A to FIG. 5D , forming a sacrificial gate structure 40 over the fin structure and forming a gate sidewall spacer 48, as shown in Fig.27A and Fig.27B shown. Fig.27B It is a top view (plan view), Fig.27A is corresponding to Fig.27B A cross-sectional view along line X1-X1.

[0126] Then, similar to 6A to 7B , the fin structure of the source / drain region is recessed downward below the upper surface of the isolation insulating layer 30 by using dry etching and / or wet etching, and source / drain epitaxial layers 50N and 50P are formed, as shown in FIG. Fig.28A shown. Fig.28A is corresponding to Fig.27B Cross-sectional view along line X2-X2.

[0127] Then, similar to FIG. 8A to FIG. 9B , a first interlayer dielectric (ILD) layer 60 is formed over the source / drain epitaxial layers 50N and 50P and the sacrificial gate structure 40. Then, a planarization operation such as CMP is performed so that the top of the sacrificial gate electrode layer 44 is exposed. Then, the sacrificial gate electrode layer 44 and the sacrificial gate dielectric layer 42 are removed to form a gate space, thereby exposing the fin structure in the gate space, such as Fig.28B shown. Fig.28B is corresponding to Fig.27B The cross-sectional view of the line X1-X1. Fig.28B As shown, the liner layer 70 is further removed from the upper portion of the fin structure in the gate space.

[0128] After removing the sacrificial gate structure, a gate dielectric layer 102 is formed above the channel region, and a gate electrode layer 104 is formed on the gate dielectric layer 102. Fig.29A and Fig.29B shown. Fig.29A is corresponding to Fig.27B A cross-sectional view of the line X1-X1, Fig.29B is corresponding to Fig.27B The cross-sectional view of the line X3-X3. Fig.29B As shown, below the sidewall spacers 48, the liner layer 70 remains and maintains the original height.

[0129] Since the epitaxial growth enhancement layer is covered by the liner layer 70 , it is possible to prevent P or Ge from diffusing from the epitaxial growth enhancement layer to a region other than the source / drain epitaxial layer 50N or 50P.

[0130] Fig.29C and Fig.29D A semiconductor device according to another embodiment is shown in which no epitaxial layer 11 is formed. An epitaxial growth enhancement layer 20P is formed in the Si fin structure.

[0131] Fig. 30A and Fig. 30B A cross-sectional view of one stage of a sequential process for manufacturing a FinFET device according to an embodiment of the present disclosure is shown. The materials, configurations, dimensions, processes and / or operations described with respect to the previous embodiments may be adopted in the following embodiments, and their detailed description may be omitted.

[0132] Similar to Fig.18A and Fig.18B and Fig.26 , the fin structure with two epitaxial growth enhancement layers is covered by a liner layer 70, such as Fig. 30A The top of the liner layer 70 is located above the top (highest) parts of the second epitaxial growth enhancement layers 124N and 124P. Fig. 30B The structure formed after the gate dielectric layer 102 and the gate electrode layer 104 are shown.

[0133] Fig.31A and Fig.31B A cross-sectional view of one stage of a sequential process for manufacturing a FinFET device according to an embodiment of the present disclosure is shown. The materials, configurations, dimensions, processes and / or operations described with respect to the previous embodiments may be adopted in the following embodiments, and their detailed description may be omitted.

[0134] Similar to Fig.19A and Fig.19B as well as Fig.26 , a fin structure having three epitaxial growth enhancement layers is provided and covered by a liner 70 , as shown in FIG. Fig.31A The top of the liner layer 70 is located above the top (highest) parts of the third epitaxial growth enhancement layers 226N and 226P. Fig.31B The structure is shown after the gate dielectric layer 102 and the gate electrode layer 104 are formed.

[0135] The liner layer 70 may be applied to fin structures of other configurations. In some embodiments, the top of the liner layer 70 is located above the highest point of the epitaxial growth enhancement layer.

[0136] Fig.31CA semiconductor device according to another embodiment is shown in which the epitaxial layer 11 is not formed. Epitaxial growth enhancement layers 222P, 224P, and 226P are formed in the Si fin structure.

[0137] FIG. 32A to FIG. 39B A cross-sectional view of a stage of a sequential process for manufacturing a FinFET device according to an embodiment of the present disclosure is shown. The materials, configurations, dimensions, processes and / or operations described in the previous embodiments may be adopted in the following embodiments, and their detailed descriptions may be omitted. Fig.32A , Fig.33A , ...) shows the corresponding Figure 5B , Fig. 15B or Fig.27B A cross-sectional view of the line X2-X2, and Figure "B" ( Fig.32B , Fig.33B , ...) shows the corresponding Figure 5B , Fig. 15B or Fig.27B A cross-sectional view of the line Y1-Y1. Fig. 6A and Figure 6B In the process, the source / drain region of the fin structure is deeply recessed below the isolation insulating layer 30 .

[0138] exist Fig.32A and Fig.32B In the embodiment of FIG. 5 , recess etching is not performed, and source / drain epitaxial layers 50N and 50P are formed over the epitaxial growth enhancement layers 20N and 20P, respectively.

[0139] exist Fig.33A and Fig.33B In the embodiment of the present invention, the recess etching stops at the substrate 10 in the n-type region and at the epitaxial layer 11 in the p-type region. In other words, the recess etching stops after the epitaxial growth enhancement layer is removed. In other embodiments, a thin layer of the epitaxial growth enhancement layer is retained. Source / drain epitaxial layers 50N and 50P are formed over the sides of the epitaxial growth enhancement layers 20N and 20P and on the substrate 10 and the epitaxial layer 11, respectively.

[0140] Fig.34A and Fig.34B The embodiment in has Fig.14 and Fig.26 Similar to the fin structure, recess etching is not performed, and source / drain epitaxial layers 50N and 50P are formed on the sides of the epitaxial growth enhancement layers 22N and 22P, respectively.

[0141] Fig.35A and Fig.35B The embodiment in has Fig.14 and Fig.26Similar to the fin structure, the recess etching stops at the epitaxial growth enhancement layer. Source / drain epitaxial layers 50N and 50P are formed on the epitaxial growth enhancement layers 22N and 22P, respectively.

[0142] Fig.36A and Fig.36B The embodiment in has Fig.14 and Fig.26 Similar to the fin structure, the recessed etch stops below the epitaxial growth enhancement layer, similar to Figure 16. Source / drain epitaxial layers 50N and 50P are formed on the sides of the epitaxial growth enhancement layers 22N and 22P, respectively.

[0143] Fig.37A and Fig.37B The embodiment in has Fig.18A and Fig. 30A Similar to the fin structure, the recess etching stops at the second epitaxial growth enhancement layers 124N and 124P. Source / drain epitaxial layers 50N and 50P are formed on the second epitaxial growth enhancement layers 124N and 124P, respectively.

[0144] Fig.38A and Fig.38B The embodiment in has Fig.18A and Fig. 30A Similar to the fin structure, the recess etching stops at the middle of the first epitaxial layer 123N and the third epitaxial layer 123P. Source / drain epitaxial layers 50N and 50P are formed on the side surfaces of the second epitaxial growth enhancement layers 124N and 124P, respectively.

[0145] Fig.39A and Fig.39B The embodiment in has Fig.18A and Fig. 30A Similar to the fin structure, the recess etching stops at the first epitaxial growth enhancement layers 122N and 122P. Source / drain epitaxial layers 50N and 50P are formed on the first epitaxial growth enhancement layers 122N and 122P, respectively.

[0146] In addition to the aforementioned embodiments, other combinations of stacked structures of fin structures, liner layers, and / or source / drain recess etching are possible.

[0147] Fig.40 A cross-sectional view of one stage of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure is shown.

[0148] As described above, the epitaxial growth enhancement layer can be used as a source of P or Ge for the source / drain epitaxial layer. In some embodiments, after forming the source / drain epitaxial layers 50N, 50P, the concentration of P or Ge in the epitaxial growth enhancement layer is non-uniform because the outward diffusion of P or Ge occurs from a region closer to the source / drain epitaxial layer. In some embodiments, the concentration of P or Ge in the epitaxial growth enhancement layer decreases toward the source / drain epitaxial layers 50N and 50P, as shown in FIG. Fig.40 shown.

[0149] In some embodiments, the concentration of P and / or Ge in the epitaxial growth enhancement layer formed (before the source / drain epitaxial layer is formed) has a gradient. In some embodiments, in the fin extension direction (Y), the concentration of P and / or Ge in the fin structure at the side of the fin structure is higher than that in the middle of the fin structure. In some embodiments, in the fin extension direction (Y), the concentration of P and / or Ge in the fin structure at one side of the fin structure is higher than that at the other side of the fin structure. In other embodiments, in the fin width direction (X), the concentration of P and / or Ge in the fin structure at the side of the fin structure is higher than that in the middle of the fin structure.

[0150] Various embodiments or examples described herein provide several benefits over the prior art. For example, in the present disclosure, due to the insertion of one or more epitaxial growth enhancement layers in the fin structure, the source / drain epitaxial layers can be made larger, which improves device performance.

[0151] It will be understood that not all benefits are necessarily discussed herein, that no particular benefit is necessary for all embodiments or examples, and that other embodiments or examples may provide different benefits.

[0152] According to one aspect of the present disclosure, a semiconductor device includes: an isolation insulating layer disposed above a substrate; a semiconductor fin disposed above the substrate, an upper portion of the semiconductor fin protruding from the isolation insulating layer and a lower portion of the semiconductor fin embedded in the isolation insulating layer; a gate structure disposed above the upper portion of the semiconductor fin and including a gate dielectric layer and a gate electrode layer; a gate sidewall spacer disposed on opposite sides of the gate structure; and a source / drain epitaxial layer. The upper portion of the semiconductor fin includes a first epitaxial growth enhancement layer made of a semiconductor material different from that of the rest of the semiconductor fin. The first epitaxial growth enhancement layer contacts the source / drain epitaxial layer. The gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer. In one or more of the foregoing and following embodiments, the first epitaxial growth enhancement layer includes one of SiP, SiCP, SiGe, and SiGeB. In one or more of the foregoing and following embodiments, the first epitaxial growth enhancement layer is located on top of the semiconductor fin. In one or more of the foregoing and following embodiments, the first epitaxial growth enhancement layer includes an oxide of one of Si, SiP and SiGe. In one or more of the foregoing and following embodiments, the lower portion of the semiconductor fin includes a second epitaxial growth enhancement layer, and the second epitaxial growth enhancement layer is made of a semiconductor material different from the first epitaxial growth enhancement layer and the remaining portion of the semiconductor fin. In one or more of the foregoing and following embodiments, the composition of the first epitaxial growth enhancement layer is different from the composition of the second epitaxial growth enhancement layer. In one or more of the foregoing and following embodiments, the upper portion of the semiconductor fin also includes a third epitaxial growth enhancement layer, and the third epitaxial growth enhancement layer is made of a semiconductor material different from the first epitaxial growth enhancement layer and the second epitaxial growth enhancement layer and the remaining portion of the semiconductor fin. In one or more of the foregoing and following embodiments, the composition of the third epitaxial growth enhancement layer is different from the composition of the first epitaxial growth enhancement layer and the second epitaxial growth enhancement layer.

[0153] According to another aspect of the present disclosure, a semiconductor device includes: an isolation insulating layer disposed on a substrate; a semiconductor fin disposed on the substrate and including a bottom fin layer, one or more body layers, and one or more epitaxial growth enhancement layers made of a material different from the one or more body layers; a gate structure disposed above a channel region of the semiconductor fin and including a gate dielectric layer and a gate electrode layer; a gate sidewall spacer disposed on opposite sides of the gate structure; a source / drain epitaxial layer; and a fin liner layer partially covering the semiconductor fin. At least one of the one or more epitaxial growth enhancement layers is in contact with the source / drain epitaxial layer. The fin liner layer is disposed on the semiconductor fin at least below the gate sidewall spacer. The top of the fin liner layer is higher than the top of the uppermost layer of the one or more epitaxial growth enhancement layers and lower than the top of the channel region. In one or more of the foregoing and following embodiments, each of the one or more epitaxial growth enhancement layers is made of one of SiP, SiGe, SiGeB, and SiCP. In one or more of the foregoing and following embodiments, each of the one or more epitaxial growth enhancement layers is made of an oxide of one of Si, SiGe, and SiP. In one or more of the foregoing and following embodiments, the semiconductor fin includes two or more epitaxial growth enhancement layers, and at least one of the two or more epitaxial growth enhancement layers is in contact with the source / drain epitaxial layer, and at least one of the two or more epitaxial growth enhancement layers is not in contact with the source / drain epitaxial layer. In one or more of the foregoing and following embodiments, the semiconductor fin includes two or more epitaxial growth enhancement layers, and at least one of the two or more epitaxial growth enhancement layers is located above the upper surface of the isolation insulating layer, and at least one of the two or more epitaxial growth enhancement layers is located below the upper surface of the isolation insulating layer. In one or more of the foregoing and following embodiments, the gate dielectric layer covers at least one of the two or more epitaxial growth enhancement layers located above the upper surface of the isolation insulating layer. In one or more of the foregoing and following embodiments, at least one of the one or more epitaxial growth enhancement layers in contact with the source / drain epitaxial layer has a non-uniform composition. In one or more of the foregoing and following embodiments, at least one of the one or more epitaxial growth enhancement layers in contact with the source / drain epitaxial layer extends laterally below the source / drain epitaxial layer. In one or more of the foregoing and following embodiments, the fin liner layer is not present between the gate electrode and the channel region.

[0154] According to one aspect of the present disclosure, in a method for manufacturing a semiconductor device, a fin structure is formed above a substrate. The fin structure includes a bottom fin layer, one or more main layers, and one or more epitaxial growth enhancement layers made of a material different from the one or more main layers. An isolation insulating layer is formed on the substrate so that the upper portion of the fin structure protrudes from the isolation insulating layer. A sacrificial gate structure is formed above the channel region of the fin structure. A source / drain space is formed by recessing the source / drain region of the fin structure so that at least one of the one or more epitaxial growth enhancement layers is exposed in the source / drain space. A source / drain epitaxial layer is formed in the source / drain recess. At least one of the one or more epitaxial growth enhancement layers is in contact with the source / drain epitaxial layer. In one or more of the foregoing and following embodiments, each of the one or more main layers is made of Si, and one or more epitaxial growth enhancement layers are made of one of SiP, SiGe, SiGeB, and SiCP. In one or more of the foregoing and following embodiments, each of the one or more main layers is made of Si, and one or more epitaxial growth enhancement layers are made of an oxide of one of SiGe, Si, and SiP. In one or more of the foregoing and following embodiments, each of the one or more main layers is made of Si, and each of the one or more epitaxial growth enhancement layers is made of a semiconductor material containing P. In one or more of the foregoing and following embodiments, each of the one or more main layers is made of SiGe, and each of the one or more epitaxial growth enhancement layers is made of a semiconductor material containing Ge. In one or more of the foregoing and following embodiments, the fin structure includes two epitaxial growth enhancement layers separated by a main layer. An isolation insulating layer is formed so that one of the two epitaxial growth enhancement layers is located above the upper surface of the isolation insulating layer and the other of the two epitaxial growth enhancement layers is located below the upper surface of the isolation insulating layer. In one or more of the foregoing and following embodiments, the source / drain region of the fin structure is recessed so that the two epitaxial growth enhancement layers are exposed in the source / drain space. In one or more of the foregoing and following embodiments, the source / drain region of the fin structure is recessed so that one of the two epitaxial growth enhancement layers located above the upper surface of the isolation insulating layer is exposed in the source / drain space, and the other of the two epitaxial growth enhancement layers located below the upper surface of the isolation insulating layer is not exposed. In one or more of the foregoing and following embodiments, the fin structure includes three epitaxial growth enhancement layers separated by the subject layer and forming an isolation insulating layer, so that two of the three epitaxial growth enhancement layers are located above the upper surface of the isolation insulating layer and one of the three epitaxial growth enhancement layers is located below the upper surface of the isolation insulating layer. In one or more of the foregoing and following embodiments, at least one of the three epitaxial growth enhancement layers located above the upper surface of the isolation insulating layer does not contact the source / drain epitaxial layer.

[0155] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a substrate to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that this equivalent construction does not deviate from the spirit and scope of the present invention, and that they can make multiple changes, substitutions and changes herein without deviating from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: An isolation insulating layer is disposed above the substrate; A semiconductor fin is disposed above the substrate, wherein an upper portion of the semiconductor fin protruding from the isolation insulating layer and a lower portion of the semiconductor fin are embedded in the isolation insulating layer; a gate structure disposed over the upper portion of the semiconductor fin and comprising a gate dielectric layer and a gate electrode layer; gate sidewall spacers disposed on opposite sides of the gate structure; as well as Source / drain epitaxial layer, the epitaxial growth material of the source / drain epitaxial layer includes silicon element, wherein: The upper portion of the semiconductor fin includes a first epitaxial growth enhancement layer made of a semiconductor material different from a remaining portion of the semiconductor fin, The first epitaxial growth enhancement layer contacts the source / drain epitaxial layer, and the first epitaxial growth enhancement layer includes an element that combines with the silicon element of the epitaxial growth material of the source / drain epitaxial layer to form an element having the same conductivity type as the epitaxial growth material of the source / drain epitaxial layer and diffuses toward the source / drain epitaxial layer; and The gate dielectric layer covers the upper portion of the semiconductor fin including the first epitaxial growth enhancement layer.

2. The semiconductor device according to claim 1, wherein The first epitaxial growth enhancement layer includes one of SiP, SiCP, SiGe and SiGeB.

3. The semiconductor device according to claim 1, wherein The first epitaxial growth enhancement layer is located on top of the semiconductor fin.

4. The semiconductor device according to claim 3, wherein: The first epitaxial growth enhancement layer includes an oxide of one of SiP and SiGe.

5. The semiconductor device according to claim 1, wherein The lower portion of the semiconductor fin includes a second epitaxial growth enhancement layer made of a semiconductor material different from the remaining portion of the semiconductor fin than the first epitaxial growth enhancement layer.

6. The semiconductor device according to claim 5, wherein: A composition of the first epitaxial growth enhancement layer is different from a composition of the second epitaxial growth enhancement layer.

7. The semiconductor device according to claim 5, wherein: The upper portion of the semiconductor fin further includes a third epitaxial growth enhancement layer made of a semiconductor material different from the first and second epitaxial growth enhancement layers and the remaining portion of the semiconductor fin.

8. The semiconductor device according to claim 7, wherein: The composition of the third epitaxial growth enhancement layer is different from compositions of the first epitaxial growth enhancement layer and the second epitaxial growth enhancement layer.

9. A semiconductor device comprising: An isolation insulating layer is disposed on the substrate; a semiconductor fin disposed on the substrate and comprising a bottom fin layer, one or more bulk layers, and a plurality of epitaxial growth enhancement layers made of a material different from the one or more bulk layers; a gate structure disposed above the channel region of the semiconductor fin and comprising a gate dielectric layer and a gate electrode layer; gate sidewall spacers disposed on opposite sides of the gate structure; A source / drain epitaxial layer, wherein the epitaxial growth material of the source / drain epitaxial layer includes silicon; and a fin liner layer partially covering the semiconductor fin, wherein: At least one of the plurality of epitaxial growth enhancement layers is in contact with the source / drain epitaxial layer, and the at least one of the plurality of epitaxial growth enhancement layers includes an element that combines with the silicon element of the epitaxial growth material of the source / drain epitaxial layer to form an element having the same conductivity type as the epitaxial growth material of the source / drain epitaxial layer and diffuses toward the source / drain epitaxial layer; as well as The fin liner layer is disposed on the semiconductor fin at least below the gate sidewall spacer, and A top of the fin liner layer is higher than a top of an uppermost layer of the plurality of epitaxial growth enhancement layers and lower than a top of the channel region.

10. The semiconductor device according to claim 9, wherein Each of the plurality of epitaxial growth enhancement layers is made of one of SiP, SiGe, SiGeB, and SiCP.

11. The semiconductor device according to claim 9, wherein: Each of the plurality of epitaxial growth enhancement layers is made of an oxide of one of SiGe and SiP.

12. The semiconductor device according to claim 9, wherein: At least one of the plurality of epitaxial growth enhancement layers contacts the source / drain epitaxial layer, and at least one of the plurality of epitaxial growth enhancement layers does not contact the source / drain epitaxial layer.

13. The semiconductor device according to claim 9, wherein: At least one of the plurality of epitaxial growth enhancement layers is located above an upper surface of the isolation insulating layer, and at least one of the plurality of epitaxial growth enhancement layers is located below the upper surface of the isolation insulating layer.

14. The semiconductor device according to claim 13, wherein: The gate dielectric layer covers at least one of the plurality of epitaxial growth enhancement layers located above an upper surface of the isolation insulating layer.

15. The semiconductor device according to claim 9, wherein: The at least one of the plurality of epitaxial growth enhancement layers contacting the source / drain epitaxial layer has a non-uniform composition.

16. The semiconductor device according to claim 9, wherein: The at least one of the plurality of epitaxial growth enhancement layers in contact with the source / drain epitaxial layer extends laterally below the source / drain epitaxial layer.

17. The semiconductor device according to claim 9, wherein: The fin liner layer does not exist between the gate electrode layer and the channel region.

18. A method for manufacturing a semiconductor device, the method comprising: forming a fin structure over a substrate, the fin structure comprising a bottom fin layer, a plurality of body layers, and a plurality of epitaxial growth enhancement layers made of a material different from the plurality of body layers; forming an isolation insulating layer on the substrate so that an upper portion of the fin structure protrudes from the isolation insulating layer; forming a sacrificial gate structure above a channel region of the fin structure; forming a source / drain space by recessing the source / drain region of the fin structure so that at least one of the plurality of epitaxial growth enhancement layers is exposed in the source / drain space; as well as A source / drain epitaxial layer is formed in the source / drain recess, wherein the epitaxial growth material of the source / drain epitaxial layer includes silicon element, Wherein, at least one of the multiple epitaxial growth enhancement layers is in contact with the source / drain epitaxial layer, and at least one of the multiple epitaxial growth enhancement layers includes an element that is combined with the silicon element of the epitaxial growth material of the source / drain epitaxial layer to form an element with the same conductivity type as the epitaxial growth material of the source / drain epitaxial layer and diffuses into the source / drain epitaxial layer.

19. The method of claim 18, wherein: Each of the plurality of body layers is made of Si, and Each of the plurality of epitaxial growth enhancement layers is made of a P-containing semiconductor material.

20. The method of claim 18, wherein: Each of the plurality of body layers is made of SiGe, and Each of the plurality of epitaxial growth enhancement layers is made of a semiconductor material containing Ge.

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