Vertical transistor array and method of forming a vertical transistor array

Abstract

The present application relates to a vertical transistor array, and a method for forming a vertical transistor array. A vertical transistor array includes spaced apart conductive pillars, each of which includes a channel region of an individual vertical transistor. A horizontally elongated conductor line electrically couples together individual channel regions of the conductive pillars of a plurality of the vertical transistors directly. An upper source / drain region is above the individual channel region of the conductive pillar, a lower source / drain region is below the individual channel region of the conductive pillar, and a conductive gate line is operatively adjacent to the individual channel region of the conductive pillar and interconnects a plurality of the vertical transistors. A method is disclosed.

Description

Technical Field

[0001] Embodiments disclosed herein relate to vertical transistor arrays and methods of forming vertical transistor arrays. Background Art

[0002] A memory is an integrated circuit and is used in computer systems to store data. The memory may be fabricated in one or more arrays of individual memory cells. The memory cells may be written to or read from using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). The digit lines may interconnect the memory cells in a conductive manner along the columns of the array, and the access lines may interconnect the memory cells in a conductive manner along the rows of the array. Each memory cell may be uniquely addressed by a combination of digit lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for a long period of time without power. Conventionally, non-volatile memory is designated as memory with a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory may have a retention time of a few milliseconds or less. In any case, the memory cell is configured to retain or store storage content in at least two different selectable states. In a binary system, the states are considered to be "0" or "1". In other systems, at least some individual memory cells may be configured to store more than two levels or information states.

[0004] Field effect transistors are electronic components that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconductive channel region between them. A conductive gate is adjacent to the channel region and is separated from the channel region by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current is greatly prevented from flowing through the channel region. The gate insulator may be able to be programmed to be between at least two capacitive states, whereby the transistor is non-volatile. Alternatively, the gate insulator may not have this capability, whereby the transistor is volatile. In any case, the field effect transistor may also include additional structures, such as a charge storage region that can be reversibly programmed as part of the gate structure between the gate insulator and the conductive gate.

[0005] Capacitors are another type of electronic component that can be used in memory cells. A capacitor has two electrical conductors separated by an electrically insulating material. Energy, such as an electric field, can be stored in such a material in an electrostatic manner. Depending on the composition of the insulator material, the stored field will be volatile or non-volatile. For example, a capacitor insulator material that only contains SiO2 will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor, which has a ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarization states, and thus can include programmable materials for capacitors and / or memory cells. The polarization state of a ferroelectric material can be changed by applying a suitable programming voltage and maintained (at least for a certain period of time) after the programming voltage is removed. Each polarization state has a different charge storage capacitance from each other, and the charge storage capacitance is ideally used to write (i.e., store) and read the memory state without reversing the polarization state until such reversal is desired. Less desirable is that in a memory having a ferroelectric capacitor, the act of reading the memory state can reverse the polarization. Thus, upon determining the polarization state, the memory cell is rewritten to place the memory cell in the pre-read state immediately following its determination. In any case, memory cells incorporating ferroelectric capacitors are ideally non-volatile due to the bistable nature of the ferroelectric material that forms part of the capacitor. Other programmable materials can be used as capacitor insulators to render the capacitor non-volatile.

[0006] The capacitors and transistors may of course be used in integrated circuits other than memory circuits, and fabricated into arrays that may or may not be at least part of a memory array. Summary of the invention

[0007] In some embodiments, a method of forming a vertical transistor array includes forming laterally separated and horizontally elongated lines including transistor material, and horizontally elongated conductor lines located between immediately laterally adjacent transistor-material lines. The transistor material includes a channel region, which will become an individual vertical transistor. The conductor line is directly electrically coupled to the channel region of the transistor-material line on both sides of the conductor line. The transistor-material line is cut to form separated conductive pillars that individually include the channel region of individual vertical transistors. The conductor line directly electrically couples the individual channel regions of the conductive pillars of multiple vertical transistors together. The upper source / drain region is formed above the individual channel region of the conductive pillar, the lower source / drain region is formed below the individual channel region of the conductive pillar, and the conductive gate line is formed in an operational manner next to the individual channel region of the conductive pillar and interconnects multiple vertical transistors.

[0008] In some embodiments, a method of forming a vertical transistor array includes forming laterally spaced and horizontally elongated transistor-material lines in the column direction. The transistor material includes an upper source / drain region, a lower source / drain region, and a channel region vertically therebetween, which will be an individual vertical transistor. After forming the transistor-material lines, horizontally elongated conductor lines are formed in the column direction between the immediately laterally adjacent transistor-material lines. After forming the conductor lines, a conductive material is formed that electrically couples the conductor lines directly to the channel regions of the transistor-material lines on both sides of the conductor lines. In a single masking step, the following are cut: (a) transistor-material lines to form separated first conductive pillars that individually include channel regions of individual vertical transistors, wherein the conductor lines are electrically coupled directly together in the channel regions of the first conductive pillars of multiple vertical transistors in the column direction; and (b) conductor lines to form separated conductive second conductive pillars that protrude upward from a continuous line of conductive material of the conductor lines. Conductive gate lines are formed in an operational manner next to the individual channel regions of the first conductive pillars and interconnect multiple vertical transistors in the row direction.

[0009] In some embodiments, a method of forming a vertical transistor array includes forming laterally separated and horizontally elongated lines including transistor material. The transistor material includes a channel region that will become an individual vertical transistor. The sides of the trenches between the transistor-material lines are lined with insulating material. Horizontally elongated conductor lines are formed in individual trenches of the insulating material-lined trenches immediately adjacent to the laterally adjacent transistor-material lines. The insulating material is vertically recessed to have a top lower than the top of the conductor line therebetween, thereby forming a vertical recessed portion that is laterally located between the conductor line and the channel region of the immediately laterally adjacent transistor-material line on each side of the conductor line. Conductive material is formed in the vertical recessed portion on each of the sides of the conductor line, and the conductive material electrically couples the conductor line directly to the channel region of the immediately laterally adjacent transistor-material line on each side of the conductor line. The transistor-material line is cut to form separated conductive pillars that individually include the channel region of individual vertical transistors. The conductor line electrically couples the individual channel regions in the channel regions of the conductive pillars of multiple vertical transistors directly together. Upper source / drain regions are formed above the respective channel regions of the conductive pillars, lower source / drain regions are formed below the respective channel regions of the conductive pillars, and conductive gate lines are operatively formed beside the respective channel regions of the conductive pillars and interconnect multiple vertical transistors.

[0010] In some embodiments, a vertical transistor array includes spaced apart conductive pillars, each of which includes a channel region of an individual vertical transistor. A horizontally elongated conductor line electrically couples the individual channel regions of the conductive pillars of the plurality of vertical transistors directly together. An upper source / drain region is above the individual channel region of the conductive pillar, a lower source / drain region is below the individual channel region of the conductive pillar, and a conductive gate line is operatively adjacent to the individual channel region of the conductive pillar and interconnects the plurality of vertical transistors.

[0011] In some embodiments, a vertical transistor array includes separated first conductive pillars, which individually include channel regions of individual vertical transistors, and upper source / drain regions directly above the channel regions. Conductor lines elongated horizontally in the column direction directly electrically couple individual channel regions of the first conductive pillars of multiple vertical transistors together. The conductor lines include separated conductive second conductive pillars protruding upward from a continuous line of conductive material of the conductor lines. The lower source / drain regions are below the individual channel regions of the first conductive pillars. Conductive gate lines are operatively adjacent to the individual channel regions of the first conductive pillars and interconnect multiple vertical transistors in the row direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagrammatic cross-sectional view of a portion of a substrate under processing according to an embodiment of the present invention and passes through Figure 2 Intercepted by line 1-1.

[0013] Figure 2 It passes through Figure 1 A diagrammatic cross-sectional view taken along line 2-2 in FIG.

[0014] Figures 3 to 27 According to some embodiments of the present invention, Figure 1 and 2 Diagrammatical sequential cross-sectional and / or enlarged views of the structure or parts thereof.

[0015] Fig.28 is a diagrammatic cross-sectional view of a portion of a substrate according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] Embodiments of the present invention include methods for forming transistor arrays that can be used, for example, in memory or other integrated circuits. Embodiments of the present invention also include transistor arrays that are independent of the manufacturing method. Figures 1 to 27 Example embodiments of methods of forming transistor arrays are described.

[0017] See also Figures 1 to 3, shows an example substrate construction 8, which includes an array or array region 10 that has been fabricated relative to a base substrate 11. The substrate 11 may include any of a conductive / conductor / conductive, a semiconductive / semiconducting / semiconductive, and an insulating / insulator / isolating (i.e., electrically herein) material. Various materials are above the base substrate 11. The materials may be Figure 1-3 To the side, vertically inwardly, or vertically outwardly of the depicted material. For example, other partially fabricated or fully fabricated components of the integrated circuit may be provided somewhere above, around, or within the base substrate 11. Control circuits and / or other peripheral circuits for operating components within the memory array may also be fabricated, and may or may not be completely or partially within the memory array or sub-array. In addition, multiple sub-arrays may also be fabricated and operated independently of each other, sequentially, or otherwise. As used in this document, a "sub-array" may also be considered an array.

[0018] An example material 12 (e.g., an insulator material, an undoped or lightly doped semiconducting material, a circuit component, etc.) is over base substrate 11. In one embodiment, laterally spaced metal-material lines 14 with insulator material 16 therebetween are over material 12. In one such embodiment, metal-material lines 14 may comprise digit lines of a memory circuit. Example insulator material 16 comprises a combination of silicon dioxide and silicon nitride, such as deposited as a liner layer (not shown) between previously formed metal-material lines 14, and may be planarized back to provide an uppermost planar surface thereof.

[0019] Transistor material 18 is above material 12, and in one embodiment, directly against and thereby directly electrically coupled to metal-material line 14. Transistor material 18, as a minimal body, may be considered to include a channel region that will be an individual vertical transistor at the end of fabrication. In the depicted example, and in one embodiment, transistor material 18 may be considered to include an upper source / drain region 19, a lower source / drain region 21, and a channel region 20 vertically located therebetween, which will be the individual vertical transistor being fabricated. At this point in the process, regions 19, 20, and 21 may or may not be inherently at the desired conductivity / semiconductivity. Regardless, and by way of example only, transistor material 18 may alternatively include only a channel region (not shown), a combination of a channel region and only a lower source / drain region (not shown), or a combination of an upper source / drain region and only a channel region (not shown). Example transistor material 18 includes any existing or future developed and ultimately appropriately doped semiconductive material, and it may include LDD, halide, etc. regions (not shown).

[0020] See also Figure 4 and 5, transistor material 18 has been formed into laterally spaced and horizontally elongated lines 25 with trenches 24 therebetween. For simplicity herein, all trenches are shown as having vertical sidewalls, but the sidewalls may taper laterally inwardly and / or outwardly. Lines 25 may be formed by any existing or future developed technology, including, for example, photolithographic patterning and etching with or without pitch multiplication. In one embodiment, transistor-material lines 25 may be considered to extend in a column direction 26. In one embodiment and as shown, transistor-material lines 25 have been formed directly above, directly against, and horizontally along individual metal-material lines 14. Lines 25 (and lines 14) are shown as being linear, but curves, combinations of different straight segments at angles relative to each other, combinations of straight and curved segments, etc. may be used.

[0021] See also Figure 6 and 7 , the sides of the trenches 24 between the transistor-material lines 25 have been lined with insulating material 28 (e.g., silicon dioxide or other low-k [no greater than 3.9] material). A hard mask material (e.g., silicon nitride and not shown) may remain over the transistor-material lines 25, with insulating material 28 (not shown) deposited thereon.

[0022] See also Figure 8 and 9 , a conductor material 30 has been deposited and overfills trench 24. Example conductor material 30 is a conductively doped semiconductive material, such as heavily conductively doped polysilicon. A thin metal-material liner (not shown) may first be deposited as part of conductor material 30. Alternatively, and by way of example only, conductor material 30 may at least primarily comprise a metallic material.

[0023] See also Fig.10 , the conductor material 30 has been vertically recessed to form horizontally elongated conductor lines 32 between immediately laterally adjacent transistor-material lines 25 in the respective insulating material lined trenches 24. In one embodiment, the conductor lines 32 are formed in the column direction 26.

[0024] The above process is merely one example method of forming laterally spaced and horizontally elongated transistor-material lines 25 with horizontally elongated conductor lines 32 between immediately laterally adjacent transistor-material lines 25, and in one embodiment, conductor lines 32 are formed after forming transistor-material lines 25. Alternative existing or future developed techniques may be used. Regardless, and in one embodiment, transistor-material lines 25 are formed taller than conductor lines 32. In one embodiment, conductor lines 32 are shown with respective tops 33 that are lower than tops 34 of channel regions 20 of transistor-material lines 25 on both sides of individual conductor lines 32. Alternatively, as an example, conductor lines may be formed with tops that are vertically consistent with the tops of channel regions of transistor-material lines on both sides of the conductor lines (not shown).

[0025] See also Fig.11 and 12 , insulating material 28 has been vertically recessed (e.g., by selective wet etching relative to materials 18 and 30) to have a top 36 that is lower than a corresponding top 33 of a conductor line 32 therebetween. This forms a vertical recessed portion 38 that is laterally between conductor line 32 and the channel region 20 of the immediately laterally adjacent transistor-material line 25 on each side of conductor line 32.

[0026] See also Fig.13 and 14 , conductive material 40 has been formed in vertical recesses 38 on each side of conductor line 32, and electrically couples conductor line 32 directly to channel regions 20 of immediately laterally adjacent transistor-material lines 25 on each side of individual conductor line 32. Any suitable conductive material may be used. The composition of this material may be the same or different from that of material 30, with examples of the same composition shown. In one embodiment, material 44 is deposited, which includes an undoped semiconductive material (e.g., undoped polysilicon) that is conductively doped by outdiffusion of conductivity-increasing dopants in conductor line 32, thereby forming conductive material 40. This may occur during or after deposition of material 44. Sufficient outdiffusion of dopants may render some of material 40 above vertical recesses 38 conductive, as shown, but this should not extend sufficiently high to short to upper source / drain regions 19. As an alternative example, a metallic material may be deposited into vertical recesses 38.

[0027] See also Fig.15 , conductive material 40 has optionally been removed from top portions 33 of conductor lines 32 (eg by a short isotropic or by anisotropic etching). Fig.16 and 17 The subsequent formation of an insulator material 46 (eg, silicon dioxide) between the example materials 44 applied to the sides of the transistor-material line 25 is shown.

[0028] The above process is only one example method of forming a conductor line 32 that will be electrically coupled to the channel region 20 of the transistor-material line 25 on both sides of the conductor line 32. Any alternative existing or future developed technology may be used. The above is also only one example embodiment in which the conductor line 32 is initially formed not to be directly electrically coupled to the channel region 20, wherein the conductor line 32 is subsequently directly electrically coupled to the channel region 20 by forming a conductive material 40 directly against and across the conductor line 32 and the channel region 20 on both sides thereof.

[0029] See also Figures 18 to 22 , the transistor-material line 25 (numerically unspecified) has been cut (e.g., by photolithographic patterning, and etching with or without distance multiplication) to form separated guide pillars 48 that individually include channel regions 20. In some embodiments, the guide pillars 48 are referred to as first guide pillars 48 to distinguish them from second guide pillars identified below. In any case, the conductor line 32 directly electrically couples together the individual channel regions 20 of the guide pillars 48 of multiple vertical transistors being formed (e.g., in the column direction 26). In one embodiment and as shown, the cut is not completely through the transistor material 18 of the transistor-material line 25, thereby leaving a continuous line 52 of the transistor material 18 (the lower source / drain region 21) horizontally laid below the guide pillars 48, and the guide pillars 48 protruding upward therefrom.

[0030] In one embodiment and as shown, the conductor line 32 has also been cut to form spaced apart conductive pillars 50 (referred to as second conductive pillars 50 in some embodiments) that protrude upwardly from the continuous line 54 of conductor material 30 of the conductor line 32. In one such embodiment and as shown, the actions of cutting the transistor-material line 25 and cutting the conductor line 32 use a single / common masking step for both. For instance and as an example, a patterned masking material (not shown) may be provided atop the transistor-material line 25 and the insulator material 46 in the row direction 65 , wherein the cutting actions as described above with respect to the transistor-material line 25 and the conductor line 32 occur substantially at the same time or at least in the same single common masking step, and the illustrated trenches 55 are formed.

[0031] Finally, an upper source / drain region above the individual channel region of the guide pillar and a lower source / drain region below the individual channel region of the guide pillar are formed. In the depicted example embodiment, the upper source / drain region 19 and the lower source / drain region 21 have been formed in the individual guide pillars 48. The lower source / drain region 19 is shown as a portion of the individual guide pillars 48 and the continuous line 52. Alternatively, as an example, the lower source / drain region may be formed entirely below the guide pillars 48 (not shown), and / or the upper source / drain region may be at least partially formed above the guide pillars 48 (not shown).

[0032] Figures 23 to 27 Subsequent processing is shown whereby conductive gate lines 60 (both shown) have been operatively formed alongside individual channel regions 20 of guide pillars 48, thereby forming vertical transistors 75 (only a few outlines 75 are shown for clarity of drawing). Gate lines 60 interconnect multiple vertical transistors 75 (e.g., in a row direction 65). Gate insulator 61 is located between conductive gate lines 60 and channel regions 20. In one embodiment and as shown, conductor lines 32 and conductive gate lines 60 are angled (i.e., other than at a straight angle) relative to each other, wherein in one such embodiment, conductive gate lines 60 are formed in the row direction 65. Any suitable existing or future developed method may be used to form the conductive gate lines 60. Figures 23 to 27 As an example, after forming the gate insulator 61, an insulator or sacrificial material will be formed in the trench 55 to have a top surface that will become the bottom surface of the conductive gate line 60. A layer of conductive material for the conductive gate line will then be deposited to the linear trench 55, which will then be anisotropically etched back in a manner similar to the formation of the spacer to substantially remove it from the horizontal surface and form the conductive gate line 60 depicted. If a sacrificial material is used, it can now be removed. In any case, an insulator material 76 (such as silicon dioxide and / or silicon nitride) will be deposited to fill the remaining volume of the trench 55.

[0033] Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used with respect to the above-described embodiments.

[0034] The embodiment described and shown above forms a side edge 45 ( Fig.14 , 15 , 17, 22, 27) of conductive material 40. Fig. 22 and 27 Also shown is an example embodiment in which the conductive material 40 directly against the conductor line 32 is formed to only directly against the sides of the conductor line 32 in the finished construction (the example conductive pillars 50 are inherently part of the conductor line 32). Alternatively and by way of example only, the conductive material may be formed to directly against the top of the conductor line in the finished construction, and in one such embodiment, only directly against the top of the conductor line in the finished construction. For example, and by way of example only, if no Fig.14 Production Fig.15 Example of the construction of etching, then Fig.14 The materials 30 and 40 of the construction will be in the finished construction whereby the conductive material 40 directly abuts against the conductor line top 33. Fig.28An alternative example of configuration 8a is described. The same reference numerals from the embodiments described above have been used where appropriate, with certain configuration differences indicated by the suffix "a" or by different reference numerals. The example conductive material 40a, which is directly against the conductor line 32, is shown as being directly against only the top 33 of the conductor line 32 in the finished configuration (the example conductive post 50 is inherently a part of the conductor line 32). Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0035] The above is merely an example method of forming a transistor array. This may or may not include a portion of a memory circuit, where the individual transistors may or may not include a portion of a memory cell of an array of memory cells. Thus and regardless, the processing and formation of integrated circuit structures may occur in further fabrication of an integrated circuit incorporating the example transistor 75, either before or after the processing as shown and described above.

[0036] The array 10 of vertical transistors 75 may inherently include a memory cell, wherein, for example, the gate insulator 61 includes a programmable material, such as a ferroelectric material, and / or wherein the vertical transistor includes a programmable charge storage structure as part of its respective gate structure (not shown). Alternatively and by way of example only, a storage device, such as a charge storage device, such as a capacitor 85 (shown schematically) may be individually coupled to an individual upper source / drain region 19, thereby forming a memory cell 90 that individually includes a capacitor 85 and a transistor 75 (for clarity, Fig.24 , 27 28). Alternatively and by way of example only, a cross-point memory cell (not shown) may be formed above the upper source / drain region 19, with transistor 75 acting as a select device. Further alternatively and by way of example only, a storage device may be formed below the depicted structure (not shown) and electrically coupled directly to the lower source / drain region 21 and the upper source / drain region 19, which are coupled to a digit line (not shown).

[0037] Embodiments of the present invention include transistor arrays that are independent of the manufacturing method. However, such an array may have any of the properties described in the method embodiments herein. Likewise, the method embodiments described above may incorporate and form any of the properties described with respect to the device embodiments.

[0038] Embodiments of the present invention include an array (e.g., 10) of vertical transistors (e.g., 75) comprising spaced apart conductive pillars (e.g., 48) that individually comprise channel regions (e.g., 20) of individual vertical transistors. Horizontally elongated conductor lines (e.g., 32 / 54 / 50) electrically couple the individual channel regions of the conductive pillars of a plurality of vertical transistors directly together. The upper source / drain regions (e.g., 19) are above the individual channel regions of the conductive pillars, and the lower source / drain regions (e.g., 21) are below the individual channel regions of the conductive pillars. The conductive gate lines (e.g., 60) are operatively adjacent to the individual channel regions of the conductive pillars and interconnect the plurality of vertical transistors. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0039] Embodiments of the present invention include an array (e.g., 10) of vertical transistors (e.g., 75) comprising separated first conductive pillars (e.g., 48) that individually include channel regions (e.g., 20) of individual vertical transistors and upper source / drain regions (e.g., 19) directly above the channel regions. Conductor lines (e.g., 32 / 54 / 50) are horizontally elongated in the column direction (e.g., 26) and directly electrically couple individual channel regions of the first conductive pillars of a plurality of vertical transistors together. The conductor line comprises separated conductive second conductive pillars (e.g., 50) that protrude upward from a continuous line (e.g., 54) of the conductor material (e.g., 30) of the conductor line. The lower source / drain region (e.g., 21) is below the individual channel regions of the first conductive pillars. Conductive gate lines (e.g., 60) are operatively adjacent to the individual channel regions of the first conductive pillars and interconnect the plurality of vertical transistors in the row direction (e.g., 65). Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0040] The above-described processing or construction may be considered to be associated with an array of components formed as a single stack or single stack of such components above or as part of the underlying base substrate or within the single stack or single stack (although the single stack / stack may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array may also be formed at any location as part of the finished construction, and in some embodiments may be below the array (e.g., CMOS under the array). In any case, one or more additional such stacks / stacks may be provided or manufactured above and / or below the stacks / stacks shown in the figures or described above. In addition, the arrays of components may be the same or different in different stacks / stacks relative to each other, and different stacks / stacks may have the same thickness or different thicknesses relative to each other. Intervening structures may be provided between vertically adjacent stacks / stacks (e.g., additional circuits and / or dielectric layers). Furthermore, different stacks / stacks may be electrically coupled relative to each other. Multiple stacks / stacks may be manufactured individually and sequentially (e.g., one on top of another), or two or more stacks / stacks may be manufactured substantially simultaneously.

[0041] The assemblies and structures discussed above can be used in integrated circuits / circuitry systems and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0042] In this document, unless otherwise indicated, "vertical", "higher", "upper", "lower", "top", "top", "bottom", "above", "below", "under", "under", "up", and "down" generally refer to the vertical direction. "Horizontal" refers to the general direction along the surface of the main substrate (i.e., within 10 degrees), and can be relative to the substrate processed during manufacturing, and vertical is a direction generally orthogonal thereto. Reference to "just horizontal" refers to the direction along the surface of the main substrate (i.e., not forming a degree with the surface), and the substrate can be relative to the direction of processing during manufacturing. In addition, "vertical" and "horizontal" as used herein are generally vertical directions relative to each other and have nothing to do with the orientation of the substrate in three-dimensional space. In addition, "vertically extending" and "vertically extending" refer to a direction that deviates from just horizontal by at least 45°. In addition, "vertically extending", "vertically extending", "horizontally extending", "horizontally extending", and the like relative to a field effect transistor are reference to the orientation of the channel length of the transistor, and in operation, the current flows between the source / drain regions along the orientation. For bipolar junction transistors, "vertically extending," "vertically extending," "horizontally extending," "horizontally extending," and the like are referenced to the orientation of the substrate length along which, in operation, current flows between the emitter and the collector. In some embodiments, any component, feature, and / or region extending vertically extends vertically or within 10° of vertical.

[0043] In addition, "directly above," "directly below," and "directly below" require at least some lateral overlap (i.e., horizontally) of the two stated areas / materials / components relative to each other. Moreover, the use of "above" without a preceding "directly" requires only that some portion of the stated area / material / component that is above another stated area / material / component is vertically outward of the other stated area / material / component (i.e., regardless of whether there is any lateral overlap of the two stated areas / materials / components). Similarly, the use of "below" and "beneath" without a preceding "directly" requires only that some portion of the stated area / material / component that is below / beneath another stated area / material / component is vertically inward of the other stated area / material / component (i.e., regardless of whether there is any lateral overlap of the two stated areas / materials / components).

[0044] Any of the materials, regions, and structures described herein may be uniform or non-uniform, and in any case may be continuous or discontinuous over any material overlying it. When one or more example components are provided for any material, the material may include, consist essentially of, or consist of the one or more components. Furthermore, unless otherwise stated, each material may be formed using any suitable present or future developed technology, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0045] In addition, "thickness" (without a directional adjective in front) used alone is defined as the average straight-line distance perpendicularly passing through a given material or region from the closest surface of an adjacent material or adjacent region with different compositions. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If there is a variable thickness, then unless otherwise indicated, the thickness refers to the average thickness, and such materials or regions will have a certain minimum thickness and a certain maximum thickness due to the variable thickness. As used herein, "different compositions" only require that those parts of the two stated materials or regions that can directly abut against each other are chemically and / or physically different, such as when such materials or regions are not uniform. If the two stated materials or regions do not directly abut against each other, then in the case of such materials or regions being not uniform, "different compositions" only require that those parts of the two stated materials or regions that are closest to each other are chemically and / or physically different. In this article, when the stated materials, regions or structures are in at least some physical contact relative to each other, the material, region or structure "directly abuts" another material, region or structure. In contrast, "over," "on," "adjacent," "along," and "against" without being preceded by "directly" encompass "directly against" as well as configurations in which intervening materials, regions, or structures are such that the stated materials, regions, or structures are not in physical contact with each other.

[0046] As used herein, regions / materials / components are "electrically coupled" relative to one another if, in normal operation, electrical current can flow continuously from one region / material / component to another region / material / component, and flow occurs primarily through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component may be between and electrically coupled to the region-material-components. In contrast, when region-material-components are referred to as being "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

[0047] "Rows" and "columns" are used herein for convenience in distinguishing one series or orientation of features from another series or orientation of features, and components have been or may be formed along the "rows" and "columns". "Rows" and "columns" are used synonymously with respect to any series of regions, components and / or features, regardless of function. Regardless, rows can be straight and / or curved and / or parallel and / or non-parallel relative to each other, and columns can be the same. In addition, rows and columns can intersect at 90° or at one or more other angles (i.e., other than straight angles) relative to each other.

[0048] The components of any of the conductive / conductor / conductive materials herein may be metallic materials and / or conductively doped semiconductive / semiconductive / semiconductive materials. "Metallic material" is any one or combination of elemental metals, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0049] As used herein, any use of "selective" with respect to etching, etching, removal, deposition, forming, and / or formation is such action performed on one stated material relative to another stated material acted upon at a volume ratio of at least 2:1. Additionally, any use of selectively depositing, selectively growing, or selectively forming is deposition, growth, or formation of one material relative to another stated material or materials at a volume ratio of at least 2:1 for at least the first 75 angstroms.

[0050] Unless otherwise indicated, the use of "or" herein includes either or both.

[0051] in conclusion

[0052] As specified, the subject matter disclosed herein has been described in language more or less specific in terms of structural and methodological features. However, it should be understood that the appended claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes example embodiments. Therefore, the appended claims are to be given the full scope as written and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A method for forming a vertical transistor array, comprising: forming laterally spaced and horizontally elongated transistor-material lines comprising transistor material, and horizontally elongated conductor lines located between immediately laterally adjacent said transistor-material lines, said transistor material including channel regions which will become individual vertical transistors, said conductor lines being directly electrically coupled to said channel regions of said transistor-material lines on both sides of said conductor lines; cutting the transistor-material line to form separated conductive pillars individually including the channel regions of the individual vertical transistors, the conductive line directly electrically coupling individual channel regions of the conductive pillars of a plurality of the vertical transistors together; and An upper source / drain region is formed above the individual channel region of the conductive pillar, a lower source / drain region is formed below the individual channel region of the conductive pillar, and a conductive gate line is formed, the conductive gate line is operatively adjacent to the individual channel region of the conductive pillar and interconnects a plurality of the vertical transistors, wherein: initially forming the conductor line to be not directly electrically coupled to the channel region of the transistor-material line on both sides of the conductor line; and After forming the transistor-material line and the conductor line, the conductor line is directly electrically coupled to the channel region of the transistor-material line on two sides of the conductor line by forming a conductive material that directly abuts against and spans between the conductor line and the channel region of the transistor-material line on two sides of the conductor line. 2 . The method of claim 1 , comprising forming the conductor line after forming the transistor-material line. 3 . The method of claim 1 , comprising forming the transistor-material line to be taller than the conductor line. 4 . The method according to claim 1 , forming the conductor line to have a top portion lower than a top portion of the channel region of the transistor-material line on both sides of the conductor line. 5 . The method according to claim 1 , forming the conductor line to have a top portion vertically coincident with a top portion of the channel region of the transistor-material line on both sides of the conductor line.

6. The method of claim 1 including forming the conductive material directly against sides of the conductor line in a finished configuration.

7. The method of claim 6 including forming the conductive material to directly abut the conductor line that will directly abut only the side edge of the conductor line in the finished configuration.

8. The method of claim 1 including forming the conductive material directly against the top of the conductor line in a finished construction.

9. The method of claim 8 including forming the conductive material to directly abut the conductor line that will only directly abut the top portion of the conductor line in the finished configuration.

10. The method of claim 1, wherein the cutting does not completely pass through the transistor material of the transistor-material line, thereby leaving a continuous line of the transistor material that runs horizontally beneath the conductive pillar and from which the conductive pillar protrudes upwardly.

11. The method of claim 1, comprising forming the transistor-material lines directly above, directly against, and horizontally along individual metal-material lines.

12. The method of claim 1, comprising forming the conductor line and the conductive gate line to be angled relative to each other.

13. The method of claim 1, comprising forming the upper source / drain regions in individual ones of the pillars.

14. The method of claim 1, comprising forming the lower source / drain regions in individual ones of the pillars.

15. The method of claim 1, comprising forming the upper and lower source / drain regions in individual ones of the pillars.

16. The method of claim 1 including forming the vertical transistors as individual memory cells comprising a memory array.

17. A method of forming a vertical transistor array, comprising: forming laterally spaced and horizontally elongated transistor-material lines comprising transistor material, and horizontally elongated conductor lines located between immediately laterally adjacent said transistor-material lines, said transistor material including channel regions which will become individual vertical transistors, said conductor lines being directly electrically coupled to said channel regions of said transistor-material lines on both sides of said conductor lines; cutting the transistor-material line to form separated conductive pillars individually including the channel regions of the individual vertical transistors, the conductive line directly electrically coupling individual channel regions of the conductive pillars of a plurality of the vertical transistors together; forming an upper source / drain region above the individual channel region of the guide pillar, forming a lower source / drain region below the individual channel region of the guide pillar, and forming a conductive gate line operatively adjacent to the individual channel region of the guide pillar and interconnecting a plurality of the vertical transistors; as well as The conductor line is cut to form spaced apart conductive posts projecting upwardly from a continuous line of conductive material of the conductor line.

18. The method of claim 17, wherein said cutting of said transistor-material lines and said cutting of said conductor lines use a single common masking step for both.

19. A method of forming a vertical transistor array, comprising: forming laterally spaced and horizontally elongated transistor-material lines comprising transistor material in a column direction; The transistor material includes an upper source / drain region, a lower source / drain region, and a channel region vertically therebetween, which will be a respective vertical transistor; After forming the transistor-material lines, forming horizontally elongated conductor lines in the column direction between immediately laterally adjacent transistor-material lines; After forming the conductor line, forming a conductive material that electrically couples the conductor line directly to the channel regions of the transistor-material line on both sides of the conductor line; In a single masking step, cut: (a) the transistor-material line to form separated first conductive pillars, each of which includes the channel region of the individual vertical transistor, the conductor line directly electrically couples the individual channel regions of the first conductive pillars of a plurality of the vertical transistors together in the column direction; as well as (b) said conductor line to form spaced apart electrically conductive second conductive pillars projecting upwardly from a continuous line of conductive material of said conductor line; as well as A conductive gate line is formed operatively next to the individual channel regions of the first conductive pillars and interconnects a plurality of the vertical transistors in a row direction. 20 . The method of claim 19 , forming the conductor line to have a top portion lower than a top portion of the channel region of the transistor-material line on both sides of the conductor line. 21 . The method of claim 19 , forming the conductor line to have a top portion vertically coincident with a top portion of the channel region of the transistor-material line on both sides of the conductor line.

22. A method according to claim 19, wherein the cutting does not completely pass through the transistor material of the transistor-material line, thereby leaving a continuous line of the transistor material that is horizontally laid below the first conductive pillar and the first conductive pillar protrudes upward from it, and the continuous line includes the lower source / drain region of the individual vertical transistor.

23. The method of claim 19, comprising forming the conductive material directly against sides of the conductor line in a finished configuration.

24. The method of claim 19, comprising forming the conductive material directly against the top of the conductor line in a finished configuration.

25. A method of forming a vertical transistor array, comprising: forming laterally spaced and horizontally elongated transistor-material lines comprising transistor material including channel regions that will become individual vertical transistors; lining the sides of the trench between the transistor-material lines with insulating material; forming horizontally elongated conductor lines in individual ones of said insulating material-lined trenches immediately adjacent said transistor-material lines; vertically recessing the insulating material to have a top lower than a top of the conductor line therebetween, thereby forming a vertically recessed portion laterally between the conductor line and the channel region of the immediately laterally adjacent transistor-material line on each side of the conductor line; forming a conductive material in the vertical recessed portion on each of the sides of the conductor line, the conductive material electrically coupling the conductor line directly to the channel region of the immediately laterally adjacent transistor-material line on each side of the conductor line; cutting the transistor-material line to form separated conductive pillars individually including the channel regions of the individual vertical transistors, the conductive line directly electrically coupling individual channel regions of the conductive pillars of a plurality of the vertical transistors together; and An upper source / drain region is formed above the individual channel region of the conductive pillar, a lower source / drain region is formed below the individual channel region of the conductive pillar, and a conductive gate line is formed, which is operatively adjacent to the individual channel region of the conductive pillar and interconnects multiple vertical transistors.

26. The method of claim 25, wherein the cutting does not completely pass through the transistor material of the transistor-material line, thereby leaving a continuous line of the transistor material that runs horizontally beneath the conductive pillar and from which the conductive pillar protrudes upwardly.

27. The method of claim 25, comprising cutting the conductor line to form spaced apart conductive posts projecting upwardly from a continuous line of conductive material of the conductor line.

28. The method of claim 25, comprising forming the conductor line and the conductive gate line to be angled relative to each other.

29. A vertical transistor array comprising: spaced apart conductive pillars, each of which individually comprises a channel region of a respective vertical transistor; a horizontally elongated conductor line that directly electrically couples together individual ones of the channel regions of the conductive pillars of a plurality of vertical transistors; and An upper source / drain region above the individual channel region of the guide pillar, a lower source / drain region below the individual channel region of the guide pillar, and a conductive gate line, which is operatively adjacent to the individual channel region of the guide pillar and interconnects a plurality of the vertical transistors, the horizontally elongated conductor line having a top portion that is lower than a top portion of the conductive gate line.

30. The array of claim 29 including conductive material between the individual channel regions and the horizontally elongated conductor lines, the conductive material directly against sides of the horizontally elongated conductor lines.

31. The array of claim 30 wherein the conductive material directly against the conductor lines only directly against the sides of the horizontally elongated conductor lines.

32. The array of claim 29, wherein the horizontally elongated conductor lines and the conductive gate lines are angled relative to each other.

33. The array of claim 29, wherein the upper source / drain regions are located in individual ones of the pillars.

34. The array of claim 29, wherein the lower source / drain regions are located in individual ones of the pillars.

35. The array of claim 29, wherein the upper and lower source / drain regions are located in individual ones of the pillars.

36. The array of claim 29 wherein the vertical transistors comprise individual memory cells of a memory array.

37. A vertical transistor array comprising: spaced apart conductive pillars, each of which individually comprises a channel region of a respective vertical transistor; a horizontally elongated conductor line that directly electrically couples together individual ones of the channel regions of the conductive pillars of a plurality of vertical transistors; an upper source / drain region above the individual channel region of the guide pillar, a lower source / drain region below the individual channel region of the guide pillar, and a conductive gate line operatively adjacent to the individual channel region of the guide pillar and interconnecting a plurality of the vertical transistors; as well as A conductive material is located between the individual channel regions and the horizontally elongated conductor lines, the conductive material directly against the top of the horizontally elongated conductor lines.

38. The array of claim 37 wherein the conductive material directly against the horizontally elongated conductor lines only directly against the tops of the horizontally elongated conductor lines.

39. A vertical transistor array comprising: spaced first pillars, each of which individually includes a channel region of a respective vertical transistor and an upper source / drain region directly above the channel region; a conductor line horizontally elongated in a column direction, said conductor line directly electrically coupling together individual channel regions of said first conductive pillars of a plurality of said vertical transistors, said conductor line comprising spaced apart conductive second conductive pillars protruding upwardly from a continuous line of conductive material of said conductor line; a lower source / drain region below the respective channel region of the first pillar; and A conductive gate line is operatively adjacent to the individual channel regions of the first conductive pillars and interconnects a plurality of the vertical transistors in a row direction.

40. The array of claim 39, wherein the conductor lines and the spaced apart conductive second conductive pillars comprise conductively doped semiconductive material.

41. The array of claim 39, wherein the conductor lines and the spaced apart conductive second conductive posts comprise a metallic material.

42. The array of claim 39, wherein the conductor lines and the spaced apart conductive second conductive posts at least primarily comprise a metallic material.

43. The array of claim 39 wherein the spaced apart conductive second pillars individually have a top portion located between a top portion and a bottom portion of the channel region.

44. The array of claim 39, wherein the spaced apart conductive second conductive posts are taller than a vertical thickness of the conductor lines between the spaced apart conductive second conductive posts.

45. The array of claim 39, wherein individual ones of the spaced apart conductive second conductive posts and individual ones of the conductor lines have the same maximum lateral thickness relative to each other in the column direction.

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