Semiconductor structure and method for forming a semiconductor structure

Abstract

Various embodiments of the present invention relate to semiconductor structures including a contact pad disposed within a semiconductor substrate and methods for forming semiconductor structures. The semiconductor substrate has a backside surface and a frontside surface opposite the backside surface. An upper surface of the semiconductor substrate is lower than the backside surface in a vertical direction. The contact pad extends through the semiconductor substrate. The contact pad includes a conductive body located above the upper surface of the semiconductor substrate and a conductive protrusion extending from above the upper surface of the semiconductor substrate below the frontside surface. A vertical distance between a top surface of the contact pad and the backside surface of the semiconductor substrate is less than a height of the conductive protrusion. A first contact pad isolation structure extends through the semiconductor substrate and laterally surrounds the conductive protrusion.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention relate to a semiconductor structure and a method for forming a semiconductor structure. BACKGROUND

[0002] Integrated circuits (ICs) with image sensors are used in a wide variety of modern electronic devices such as cameras and cellular telephones. Complementary metal-oxide semiconductor (CMOS) devices have become popular IC image sensors. CMOS image sensors are increasingly popular compared to charge-coupled devices (CCDs) due to low power consumption, small size, fast data processing, direct data output, and low manufacturing cost. Some types of CMOS image sensors include front-side illuminated (FSI) image sensors and back-side illuminated (BSI) image sensors. SUMMARY

[0003] A semiconductor structure of an embodiment of the present invention includes a semiconductor substrate having a backside surface and a frontside surface opposite the backside surface, wherein an upper surface of the semiconductor substrate is lower than the backside surface in a vertical direction; a contact pad extending through the semiconductor substrate, wherein the contact pad includes a conductive body above the upper surface of the semiconductor substrate and a conductive protrusion extending from above the upper surface of the semiconductor substrate to below the frontside surface, and wherein a vertical distance between a top surface of the contact pad and the backside surface of the semiconductor substrate is less than a height of the conductive protrusion; and a first contact pad isolation structure extending through the semiconductor substrate and laterally surrounding the conductive protrusion.

[0004] An embodiment of the present invention provides a semiconductor structure comprising: a first substrate, covering a second substrate and including a top surface that is vertically higher than the upper surface, wherein a photodetector is disposed in the first substrate; an interconnect structure disposed between the first substrate and the second substrate, wherein an upper conductive wiring layer is disposed within the interconnect structure; a pad, covering the upper surface of the first substrate and extending through the first substrate to the interconnect structure, wherein the pad contacts the upper conductive wiring layer and is laterally offset from the photodetector, and wherein the vertical distance between the top surface of the first substrate and the top surface of the pad is less than the height of the pad covering the upper surface of the first substrate; a first pad isolation structure disposed within the first substrate and laterally surrounding the outer sidewall of the pad; and a second pad isolation structure disposed within the first substrate, wherein the second pad isolation structure directly contacts the sidewall of the pad extending through the first substrate.

[0005] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising: forming a shallow trench isolation (STI) structure on a front surface of a substrate; forming an interconnect structure on the front surface of the substrate, wherein the interconnect structure includes a conductive wiring layer; patterning the substrate to define an upper surface of the substrate that is lower in a vertical direction than a rear surface of the substrate, wherein the rear surface is opposite to the front surface; forming a first passivation layer on the rear surface of the substrate; patterning the first passivation layer and the substrate to define a pad isolation opening and a pad protrusion opening, wherein patterning the first passivation layer and the substrate exposes the upper surface of the shallow trench isolation structure; depositing a pad isolation layer on the substrate, wherein the pad isolation layer fills the pad isolation opening and backs the pad protrusion opening; etching the pad isolation layer and the shallow trench isolation structure to expose the upper surface of the conductive wiring layer and define a first pad isolation structure and a second pad isolation structure; and forming pads on the conductive wiring layer. Attached Figure Description

[0006] The most thorough understanding of all aspects of the invention will be achieved by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 The illustration shows cross-sectional views of some embodiments of an integrated chip (IC), which includes pads extending through a semiconductor substrate.

[0008] Figures 2A-2B Explain the intercept along line A-A' Figure 1Top view of some alternative embodiments of the IC shown.

[0009] Figure 3 Cross-sectional view illustrating some embodiments of an image sensor including pads laterally offset from a plurality of photodetectors.

[0010] Figure 4 Top view illustrating some embodiments of a semiconductor structure including a plurality of pads laterally surrounding a device region.

[0011] Figure 5 Block diagram illustrating some embodiments of a method according to Figure 1 Cross-sectional view of some alternative embodiments of the IC.

[0012] Figures 6-16 Series of cross-sectional views illustrating some embodiments of a method for forming a pad and a pad isolation structure surrounding the pad with reduced step height.

[0013] Figure 17 Block diagram illustrating some embodiments of a method according to Figures 6-16 DETAILED DESCRIPTION

[0014] The present disclosure provides a number of different embodiments or examples to implement different features of the present disclosure. Specific examples of components and arrangements are described below to provide a thorough description of embodiments of the present disclosure. Of course, these are simply examples, and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numbers and / or letters can be repeated in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations described.

[0015] Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0016] ​Some complementary metal-oxide-semiconductor (CMOS) image sensors include an array of pixel sensors arranged within a pixel array region of an integrated circuit (IC) substrate. The pixel sensors each include a plurality of photodetectors arranged within the substrate proximate to a backside of the substrate to enable the photodetectors to receive light along the backside of the substrate. A color filter array is arranged over the array of pixel sensors and is buried within a dielectric layer overlying the backside of the substrate. Burying the color filter array within the dielectric layer facilitates increasing a quantum efficiency (QE) of the image sensor. A landing pad is disposed within a landing pad region that is a peripheral region of the substrate laterally offset from the pixel array region. The landing pad is formed prior to performing a buried color filter array (BCFA) process. For example, the landing pad is formed within a landing pad opening and is vertically offset from the backside of the substrate by a step height. Forming the landing pad opening can include removing an entire thickness of the substrate over a shallow trench isolation structure (STI) such that the landing pad does not extend through the substrate. The buried color filter array (BCFA) process is implemented after the landing pad is formed. For example, a dielectric layer is formed over the backside of the substrate and the dielectric layer fills a remaining portion of the landing pad opening. Subsequently, a color filter array can be formed in and / or over the dielectric layer in a region laterally offset from the landing pad.

[0017] In some embodiments, the foregoing structure can face some challenges as the thickness of the substrate increases. As the thickness of the substrate increases (e.g., to a range of about 3.5 microns to 6 microns), the intrinsic absorption coefficient of the substrate material (e.g., silicon) increases, thus increasing the quantum efficiency (QE) of the image sensor. However, as the substrate thickness increases, the step height between the landing pad and the backside of the substrate increases (e.g., from about 2.75 microns to about 5.75 microns). As the step height increases, the dielectric layer within the landing pad opening can not uniformly fill the gap around and / or over the landing pad (e.g., due to limitations on the tool used to form the dielectric layer). This can cause delamination and / or cracking of the layers adjacent to the landing pad. Additional processing steps (e.g., additional dielectric deposition and / or patterning processes) can be implemented to fill the gap, however this can increase the time and cost associated with fabricating the IC. Furthermore, by disposing the landing pad over a shallow trench isolation (STI) structure such that the landing pad does not extend through the substrate, noise in the image sensor can be reduced, but this can cause the step height to increase.

[0018] Accordingly, in some embodiments, the present disclosure is directed to a landing pad having a reduced step height and an associated method of forming the same that simplifies the process of filling the landing pad opening. In some embodiments, a passivation layer is formed over a backside of a substrate. The passivation layer and substrate are patterned to form a landing pad opening. The patterning process defines an upper surface of the substrate to be lower than the backside in a vertical direction. The landing pad opening includes a landing pad protrusion opening that extends through an entire thickness of the substrate and exposes an upper surface of a metal line located within an underlying interconnect structure. A first landing pad isolation structure is formed in the substrate around the landing pad protrusion opening and a second landing pad isolation structure is formed along a sidewall of the substrate that defines the landing pad protrusion opening. Subsequently, a landing pad is formed in the landing pad opening such that the landing pad has an upper conductive body overlying the upper surface of the substrate and a conductive protrusion extending from the conductive body to the metal line. Subsequently, a dielectric layer is formed over the passivation layer and the dielectric layer fills a remaining portion of the landing pad opening. The step height is reduced (e.g., to about 0 microns to 1.80 microns) and the thickness of the dielectric layer in the landing pad opening is reduced by forming the landing pad over the upper surface of the substrate. This can partially mitigate and / or eliminate cracking and / or delamination of layers adjacent to the landing pad. Further, the first and second landing pad isolation structures separate the landing pad from the substrate, thereby reducing and / or eliminating "leakage" between the landing pad and a photodetector. This can reduce noise present in an image sensor.

[0019] Figure 1 A cross-sectional view illustrating some embodiments of an integrated chip 100 having a landing pad 116 disposed within a landing pad region 101b is shown.

[0020] The integrated chip 100 includes an interconnect structure 104 disposed along a front side 110f of a semiconductor substrate 110 (e.g., a silicon substrate). The interconnect structure 104 overlies a carrier substrate 102 (e.g., a silicon substrate), with the interconnect structure 104 disposed between the semiconductor substrate 110 and the carrier substrate 102. The interconnect structure 104 includes a plurality of interconnect layers arranged within an interconnect dielectric structure 103. The plurality of interconnect layers alternate between conductive wiring 108 and conductive vias 106. The conductive wiring 108 is configured to provide lateral connections (i.e., connections parallel to an upper surface of the carrier substrate 102), while the conductive vias 106 are configured to provide vertical connections between adjacent conductive wiring 108. The conductive wiring 108 includes an upper conductive wiring layer 108a. A passivation structure 118 overlies a backside 110b of the semiconductor substrate 110. A first dielectric layer 120 overlies the passivation structure 118. A shallow trench isolation (STI) structure 112 is disposed within the semiconductor substrate 110 and extends along an upper surface of the interconnect dielectric structure 103.

[0021] The contact pad region 101b extends through the semiconductor substrate 110 at a location laterally offset from the device region 101a to the upper conductive wiring layer 108a. In some embodiments, the device region 101a includes one or more semiconductor devices 126 (e.g., transistors, resistors, varactor diodes, etc.) and / or photodetectors (not shown) disposed within and / or on the semiconductor substrate 110. The contact pad 116, the first contact pad isolation structure 114, and the second contact pad isolation structure 115 are disposed within the contact pad region 101b. The contact pad 116 includes an upper conductive body 116a and a conductive protrusion 116b below the upper conductive body 116a.

[0022] The upper conductive body 116a and the conductive protrusion 116b comprise the same material (e.g., aluminum copper). The upper conductive body 116a overlies the upper surface 110us of the semiconductor substrate and is separated from the upper surface 110us by the passivation structure 118. Further, the conductive protrusion 116b continuously extends through the semiconductor substrate 110, the shallow trench isolation structure 112, and the interconnect dielectric structure 103. Further, the upper conductive body 116a has sidewalls that define contact pad openings 116o overlying the conductive protrusion 116b. The electrical connection pads 122 are laterally disposed between the contact pad openings 116o and provide wiring junction locations for the conductive wires 124. In some embodiments, the conductive wires 124 are bonded to another integrated chip (not shown) in which the interconnect structure 104 is electrically coupled to the other integrated chip via the contact pad 116. The conductive ring structure 113 is disposed over the upper surface 110us of the semiconductor substrate 110 and laterally surrounds the upper conductive body 116a.

[0023] The first contact pad isolation structure 114 laterally offsets and surrounds the outer sidewalls of the contact pad 116. In some embodiments, the first contact pad isolation structure 114 comprises a different material (e.g., silicon dioxide) than the semiconductor substrate 110. Accordingly, the first contact pad isolation structure 114 is configured to increase electrical isolation between the contact pad 116 and other devices (e.g., semiconductor devices 126) disposed on and / or within the semiconductor substrate 110. Further, the second contact pad isolation structure 115 respectively surrounds and / or directly contacts the adjacent conductive protrusions 116b. The second contact pad isolation structure 115 each extend from the upper conductive body 116a to the shallow trench isolation structure 112. This further increases electrical isolation between the contact pad 116 and other devices disposed on and / or within the semiconductor substrate 110. With the first contact pad isolation structure 114 and / or the second contact pad isolation structure 115 surrounding the contact pad 116, “leakage” (i.e., current) between the contact pad 116 and other devices and / or doped regions disposed within and / or on the semiconductor substrate 110 can be mitigated and / or eliminated. This can in part increase the reliability and / or durability of the integrated chip 100.

[0024] A top surface of the landing pad 116 is offset from the backside 110b of the semiconductor substrate 110 by a step height hi in the vertical direction. In some embodiments, the step height hi is in a range from 0 microns to 1.80 microns. In some embodiments, if the step height hi is greater than 0 microns, a thickness of the first dielectric layer 120 overlying the landing pad 116 can be reduced so that the first dielectric layer 120 can uniformly fill gaps around and / or over the landing pad 116 during fabrication of the integrated chip 100. This can improve reliability and / or durability of the integrated chip 100. In other embodiments, if the step height hi is less than 0 microns, the landing pad 116 can negatively interact with (e.g., reflect) electromagnetic radiation disposed on the backside 110b of the semiconductor substrate 110. For example, this can reduce sensitivity of photodetectors disposed within the device region 101a of the semiconductor substrate 110 and / or increase noise present in the integrated chip 100. In further embodiments, if the step height hi is greater than 1.80 microns, the first dielectric layer 120 cannot uniformly fill gaps around and / or over the landing pad 116, so the unfilled gaps can cause delamination and / or cracking of layers adjacent to the landing pad 116.

[0025] In some embodiments, a lower surface of the upper conductive body 116a has a second height h2, measured from the backside 110b of the semiconductor substrate 110. The second height h2 is greater than the step height hi. An upper surface 110us of the semiconductor substrate 110 has a third height h3, measured from the backside 110b of the semiconductor substrate 110. The third height h3 is greater than the step height hi. Further, a lower surface of the conductive protrusion 116b has a fourth height h4, measured from the backside 110b of the semiconductor substrate 110. The fourth height h4 is greater than the step height hi and greater than a thickness Ts of the semiconductor substrate 110. In other embodiments, a top surface of the landing pad 116 can be aligned with the backside 110b of the semiconductor substrate 110 (e.g., the step height hi can be zero). In further embodiments, a top surface of the landing pad 116 can not be disposed above the backside 110b of the semiconductor substrate 110 (e.g., the step height hi can not be negative). In some embodiments, a thickness Tcb of the upper conductive body 116a is approximately 1.2 microns.

[0026] Figure 2A A top view of some alternative embodiments of the integrated chip 100 taken along line A-A’ of FIG. 1 is illustrated. For ease of illustration, the first dielectric layer 120 of FIG. 1 has been omitted from the top view of FIG. 2. Figure 1 Figure 2A Figure 1

[0027] ​​​The first pad isolation structure 114 has an annular shape, wherein the sidewalls of the first pad isolation structure 114 completely surround the outer sidewalls of the pad 116. When viewed from above, the first pad isolation structure 114 has a rectangular / square shape with rounded edges; however, the first pad isolation structure 114 may have other shapes, such as circular / elliptical shapes. When viewed from above, the pad 116 has a rectangular / square shape formed by rounding etching; however, the pad 116 may have other shapes, such as circular / elliptical shapes. In some embodiments, solder bumps (not shown) may be laterally disposed between the pad openings 116o.

[0028] When viewed from above, the pad opening 116o may, for example, have a square / rectangular shape. The second pad isolation structure 115 completely surrounds the conductive protrusion of the pad 116. Figure 1 The outer periphery of the conductive protrusion 116b is shown. In these embodiments, the second pad isolation structure 115 may each have a shape corresponding to the adjacent pad opening 116o. Therefore, the second pad isolation structure 115 separates the pad 116 from the semiconductor substrate 110, thereby electrically isolating the pad 116 from other semiconductor devices and / or doped regions disposed within and / or on the semiconductor substrate 110. However, in some embodiments, the thickness of the second pad isolation structure 115 may be substantially insufficient, thus "leakage" may occur between the pad 116 and the semiconductor substrate 110. In these embodiments, the first pad isolation structure 114 further increases the electrical isolation between the pad 116 and the semiconductor substrate 110. This partially mitigates and / or eliminates "leakage" between the pad 116 and other semiconductor devices and / or doped regions disposed within and / or on the semiconductor substrate 110. Figure 1 As shown in the cross-sectional view, the shallow groove isolation structure 112 is located directly below the pad isolation structure 114. In some embodiments, the outer walls of the pad 116 and / or the outer walls of the first pad isolation structure 114 are each laterally spaced between the outer walls of the shallow groove isolation structure 112. In other embodiments, the first pad isolation structure 114 is disposed around the center of the pad 116.

[0029] In some embodiments, the pad 116 may have a length L1 and a width W1. The length L1 may be, for example, in the range of about 75 micrometers to 85 micrometers. The width W1 may be, for example, in the range of about 85 micrometers to 95 micrometers. In some embodiments, the width W1 is greater than the length L1. In some embodiments, the pad opening 116o may each have a length L2 and a width W2. The length L2 may be, for example, in the range of about 15 micrometers to 25 micrometers. The width W2 may be, for example, in the range of about 2 micrometers to 8 micrometers. In some embodiments, the length L2 is greater than the width W2.

[0030] Figure 2B This diagram illustrates a top view of some alternative embodiments of the integrated chip 100, taken along line A-A' of Figure 1. For ease of explanation, Figure 2B The top view has been omitted Figure 1 The first dielectric layer is 120.

[0031] like Figure 2B As described above, the inner wall of the first pad isolation structure 114 directly contacts the conductive protrusion of the pad 116. Figure 1 The sidewall of at least one of the conductive protrusions 116b shown. In addition, the outer sidewall of the first pad isolation structure 114 is laterally spaced between the outer sidewalls of the pads 116.

[0032] Figure 3 A cross-sectional view illustrating some embodiments of an image sensor 300, which includes pads 116 laterally offset from a plurality of photodetectors 328.

[0033] A semiconductor substrate 110 is overlaid on an application-specific integrated circuit (ASIC) substrate 301. In some embodiments, the semiconductor substrate 110 and / or the ASIC substrate 301 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, a silicon-germanium (SiGe) substrate, or some other suitable substrate. A plurality of transistors 302 are disposed on the ASIC substrate 301. Each transistor 302 includes a gate electrode 310, a gate dielectric 306, a sidewall spacer structure 308, and a source / drain region 304. An interconnect structure 104 and an ASIC interconnect structure 312 are disposed between the semiconductor substrate 110 and the ASIC substrate 301. Each interconnect structure 104 and the ASIC interconnect structure 312 includes an interconnect dielectric structure 103, a plurality of conductive wirings 108, and a plurality of conductive vias 106. Interconnect structure 104 and ASIC interconnect structure 312 are configured to electrically couple transistor 302 to photodetector 328 and / or transfer transistor 320 disposed in semiconductor substrate 110. In some embodiments, each transfer transistor 320 includes a dielectric transfer layer 324 overlying a transfer electrode 322. Semiconductor substrate 110 is bonded to ASIC substrate 301 via interconnect structure 104 and ASIC interconnect structure 312. In some embodiments, conductive wiring 108 and / or conductive via 106 may be, for example, aluminum, copper, aluminum-copper, tungsten, etc. In some embodiments, interconnect dielectric structure 103 may include, for example, one or more dielectric layers (e.g., silicon dioxide). In other embodiments, ASIC substrate 301 may be configured to Figure 1of the carrier substrate 102. In these embodiments, the ASIC interconnect structure 312 can be omitted.

[0034] The plurality of photodetectors 328 are disposed within the semiconductor substrate 110. In some embodiments, the photodetectors 328, the transistors 302, and the transfer transistor 320 are laterally spaced within the device region 101a. The semiconductor substrate 110 can have a first doping type (e.g., p-type) and the photodetectors 328 can each have a second doping type (e.g., n-type) opposite the first doping type. In some embodiments, the photodetectors 328 each extend from the backside 110b of the semiconductor substrate 110 to a point below the backside 110b. In other embodiments, the point is at the frontside 110f of the semiconductor substrate 110, which is opposite the backside 110bs of the semiconductor substrate 110. In some embodiments, isolation structures 325, 326 can be disposed within the semiconductor substrate 110 laterally between adjacent photodetectors 328. For example, a shallow trench isolation (STI) structure 326 can be disposed in the frontside 110f of the semiconductor substrate 110 to a point above the transfer transistor 320. The isolation structure 326 can be configured as a shallow trench isolation structure and can be or include silicon dioxide, silicon nitride, etc. Further, an elongated isolation structure 325 can extend from the isolation structure 326 to the backside 110b of the semiconductor substrate 110. The elongated isolation structure 325 can be configured as a deep trench isolation (DTI) structure and / or can be a doped region of the semiconductor substrate 110 configured to electrically isolate the photodetectors 328 from one another.

[0035] The photodetectors 328 are each configured to convert electromagnetic radiation (e.g., photons) into an electrical signal (e.g., to generate electron-hole pairs from electromagnetic radiation). In some embodiments, the photodetectors 328 may, for example, each be configured to generate an electrical signal from near infrared radiation (NIR) electromagnetic radiation (e.g., wavelengths of about 0.7 microns to 5 microns). In these embodiments, the material of the semiconductor substrate 110 and / or the thickness Ts is configured to ensure that the photodetectors 328 have a high quantum efficiency (QE) in near infrared radiation applications. For example, the thickness Ts of the semiconductor substrate 110 can be in a range of about 3.5 microns to 6 microns. In some embodiments, if the thickness Ts is greater than about 3.5 microns, then the photodetectors 328 will each have a high near infrared radiation light quantum efficiency, and this can improve the ability for phase detection and / or depth detection. In other embodiments, if the thickness Ts is less than about 6 microns, then the photodetectors 328 will each have a high near infrared radiation light quantum efficiency while reducing the complexity, cost, and time associated with fabricating the image sensor 300. In further embodiments, the photodetectors 328 may, for example, each be configured to generate an electrical signal from visible light (e.g., wavelengths of about 0.38 microns to 0.75 microns).

[0036] The passivation structure 118 overlies the backside 110b of the semiconductor substrate 110 and includes a first passivation layer 118a, a second passivation layer 118b, and a third passivation layer 118c. The first passivation layer 118a may, for example, be or include an oxide such as silicon dioxide, a low-k dielectric material, or the like. The first passivation layer 118a can directly contact the contact pads 116. The second passivation layer 118b may, for example, be or include an oxide such as silicon dioxide, a low-k dielectric material, or the like. The third passivation layer 118c may, for example, be or include a high-k dielectric material or some other suitable dielectric material. The passivation structure 118 can be configured to protect the backside 110b of the semiconductor substrate 110.

[0037] A mesh structure 329 overlies the passivation structure 118. The mesh structure 329 includes a first mesh layer 330 and a second mesh layer 332 overlying the first mesh layer 330. The mesh structure 329 laterally surrounds the photodetectors 328 and is located between the photodetectors 328 to define a plurality of color filter openings. A dielectric protective layer 334 can be disposed along the upper surface and sidewalls of the mesh structure 329. In some embodiments, the dielectric protective layer 334 can be configured as a sidewall protection structure that prevents damage to the mesh structure 329. The dielectric protective layer 334, for example, can be or include an oxide such as silicon dioxide or another suitable dielectric material. A plurality of filters 336 are arranged within the plurality of color filter openings and overlie the plurality of photodetectors 328. The mesh structure 329 can include a dielectric material having a lower refractive index than the refractive index of the filters 336. Due to the lower refractive index, the mesh structure 329 acts as a radiation guide to direct incident electromagnetic radiation (e.g., near-infrared radiation light) to the corresponding photodetectors 328. Further, the filters 336 are each configured to block a first frequency range of incident electromagnetic radiation while passing a second frequency range of incident electromagnetic radiation (different from the first frequency range) to the underlying photodetectors 328. In some embodiments, the second frequency range can be near-infrared radiation light. In further embodiments, the plurality of color filters can be configured as a backside color filter array (BCFA) such that the second frequency range can be visible light. Further, a plurality of microlenses 338 can be disposed over the plurality of filters 336.

[0038] The device region 101a is laterally offset from the pad region 101b of the image sensor 300. The pads 116 and the first pad isolation structures 114 are laterally arranged within the pad region 101b of the image sensor 300. Thus, in some embodiments, the pads 116 and the first pad isolation structures 114 are laterally offset from the photodetectors 328 and / or the transfer transistors 320 by a non-zero distance.

[0039] The landing pad 116 is configured to electrically couple the transfer transistor 320, the transistor 302, and / or the photodetector 328 to another integrated chip (not shown) via the interconnect structure 104 and / or the ASIC interconnect structure 312. In some embodiments, the landing pad 116 is separated from an upper surface of the semiconductor substrate 110 via the first passivation layer 118a and has a protrusion that extends through the semiconductor substrate 110 to the upper conductive wiring layer 108a. In these embodiments, the protrusion is separated from a sidewall of the semiconductor substrate 110 via the second landing pad isolation structure 115. The protrusion extends through the shallow trench isolation (STI) structure 112 and the interconnect dielectric structure 103. Further, the landing pad 116 has a sidewall that defines a landing pad opening 116o overlying the protrusion of the landing pad 116. In some embodiments, a height of the landing pad 116 is greater than a thickness Ts of the semiconductor substrate 110. Further, the first dielectric layer 120 is disposed over an upper surface of the landing pad 116 and can have a substantially planar upper surface that is aligned with an upper surface of the first passivation 118a. The first landing pad isolation structure 114 and the second landing pad isolation structure 115 are configured to electrically isolate the landing pad 116 from the photodetector 328 and / or the transfer transistor 320, thereby preventing “leakage” (i.e., current) between the landing pad 116 and the photodetector 328 and / or the transfer transistor 320. This can improve performance, stability, and reliability of the image sensor 300. The first landing pad isolation structure 114 and / or the second landing pad isolation structure 115 may, for example, be or include a dielectric material, such as silicon dioxide, silicon nitride, silicon oxynitride, etc.

[0040] Figure 4 A top view of some embodiments of a semiconductor structure 400 including a plurality of landing pads 116 laterally surrounding a device region 101a is illustrated.

[0041] As Figure 4 As illustrated in FIG. 4B, the semiconductor structure 400 includes a plurality of integrated chip die regions 402, 404, 406, 408 that are spaced immediately adjacent to one another along a first substantially straight line 410 and a second substantially straight line 412. When viewed in cross-section, the plurality of integrated chip die regions 402-408 can be along a single semiconductor substrate (e.g., a silicon substrate, such as a silicon-on-insulator (SOI) substrate, etc.). Figure 1semiconductor substrate 110) are provided such that each contact pad 116 extends through the single semiconductor substrate. A first substantially straight line 410 extends along a first direction (e.g., along an x-axis), and a second substantially straight line 412 extends along a second direction perpendicular to the first direction (e.g., along a y-axis). Each integrated chip die region 402-408 includes a device region 101a surrounded by a contact pad region 101b. In some embodiments, the device region 101a can include a plurality of photodetectors and / or transistors, and the contact pad region 101b includes a plurality of contact pads 116. The contact pads 116 can each be configured to Figure 1 a reduced step height (e.g., the step height h1) of the contact pads 116 such that the contact pads 116 each have a reduced step height (e.g., the step height h1) in a range of about 0 microns to 1.80 microns. Figure 1

[0042] In some embodiments, during fabrication of the semiconductor structure 400, a dicing process (e.g., performed via mechanical sawing and / or performed via a dicing laser) can be performed along the first substantially straight line 410 and / or the second substantially straight line 412. Accordingly, the first substantially straight line 410 and the second substantially straight line 412 can be configured as dicing streets during the dicing process. The dicing process is configured to singulate each integrated chip die region 402-408 into individual semiconductor dies, which can then be bonded to another semiconductor structure (not shown) via the contact pads 116. In some embodiments, during the dicing process, the conductive layers and / or the dielectric layers and structures adjacent to each contact pad 116 can be susceptible to cracking and / or delamination. This can be due to stress induced by the dicing process. However, the reduced step height (e.g., the step height h1) of each contact pad 116 can mitigate and / or eliminate the cracking and / or delamination of the layers adjacent to the contact pads 116. This is because the reduced step height (e.g., the step height h1) of each contact pad 116 facilitates performing a contact pad opening fill process such that the dielectric layers (e.g., the dielectric layer 120) can uniformly fill the space and / or cracks around the contact pads 116, thereby enhancing the performance and durability of each semiconductor die. Figure 1 Figure 1 Figure 1

[0043] Figure 5 A cross-sectional view of some embodiments of an integrated chip 500 illustrating an alternative embodiment of the integrated chip 100 according to Figure 1 A second dielectric layer 502 is provided around the sidewalls of the contact pads 116. The second dielectric layer 502 is located between the first dielectric layer 120 and the first passivation layer 118a. In some embodiments, the second dielectric layer 502 and the second contact pad isolation structure 115 can comprise the same material. ​​​​

[0044] Figures 6-16 Cross-sectional views 600 to 1600 illustrate some embodiments of a method for forming a pad with a reduced step height according to the present invention and a pad isolation structure surrounding the pad. Although the reference method is described... Figures 6-16 The sectional views shown are from 600 to 1600, but it should be understood that... Figures 6-16 The structure shown is not limited to the method described, but can exist independently of the method. Furthermore, although... Figures 6-16 The actions described are a series of actions, but it should be understood that these actions are not limiting; the order of the actions can be changed in other embodiments, and the disclosed methods are also applicable to other structures. In other embodiments, some of the described and / or illustrated actions may be omitted in whole or in part.

[0045] like Figure 6 As shown in the cross-sectional view 600, a semiconductor substrate 110 is provided, and a shallow trench isolation (STI) structure 112 is formed on the front side 102f of the semiconductor substrate 110. In some embodiments, the semiconductor substrate 110 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate. In some embodiments, the process for forming the shallow trench isolation structure 112 may include: selectively etching the semiconductor substrate 110 according to a masking layer (not shown) to form trenches extending into the front side 102f; and filling the trenches (e.g., via chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, etc.) with a dielectric material (e.g., silicon dioxide, silicon carbide, etc.). In some embodiments, the material and / or thickness Ts of the semiconductor substrate 110 are configured to ensure high quantum efficiency (QE) of the photodetector in near-infrared radiation applications. For example, the thickness Ts of the semiconductor substrate 110 can be in the range of about 3.5 micrometers to 6 micrometers.

[0046] like Figure 7As shown in the cross-sectional view 700, an interconnect structure 104 is formed on the front side 110f of the semiconductor substrate 110. The interconnect structure 104 includes an interconnect dielectric structure 103, a plurality of conductive wirings 108, and a plurality of conductive vias 106. In some embodiments, the interconnect dielectric structure 103 may be or include one or more inter-level dielectric (ILD) layers. The one or more inter-level dielectric layers may be, for example, an oxide such as silicon dioxide or another suitable oxide. In some embodiments, the process for forming the interconnect structure 104 includes forming the conductive vias 106 and conductive wirings 108 via a single damascene process or a dual damascene process. For example, the first layer of the conductive vias 106 and the first layer of the conductive wirings 108 may each be formed by a single damascene process. Furthermore, in these embodiments, the process includes forming the remaining layers of the conductive wirings 108 and the conductive vias 106 by repeatedly performing a dual damascene process. In some embodiments, the conductive wiring 108 and / or the conductive via 106 may be, for example, aluminum, copper, aluminum-copper, tungsten, etc.

[0047] like Figure 8 As shown in the cross-sectional view 800, Figure 7 The structure is rotated 180 degrees and the interconnect structure 104 is bonded to the carrier substrate 102. In some embodiments, the bonding process may include a fusion bonding process. In some embodiments, the carrier substrate 102 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate. Furthermore, passivation layers 118b to 118c are formed on the rear side 110b of the semiconductor substrate 110. In some embodiments, passivation layers 118b to 118c may be deposited or grown via, for example, CVD, PVD, ALD, or another suitable growth or deposition process.

[0048] like Figure 9 As shown in the cross-sectional view 900, Figure 8 The structure is patterned to form openings in the passivation layers 118b to 118c and the semiconductor substrate 110, defining the upper surface 110us of the semiconductor substrate 110. The upper surface 110us is separated from the rear side 110b of the semiconductor substrate 110 by a distance ds. In some embodiments, the distance ds is in the range of about 1.2 micrometers to 3 micrometers. In some embodiments, the structure is patterned to form openings in the passivation layers 118b to 118c and the semiconductor substrate 110, defining the upper surface 110us of the semiconductor substrate 110. Figure 8The structural patterning may include: forming a masking layer (not shown) over passivation layers 118b to 118c; exposing passivation layers 118b to 118c and unmasked areas of the semiconductor substrate 110 to one or more etchants; and performing a removal process to remove the masking layer. After performing the patterning process, a first passivation layer 118a is formed over the semiconductor substrate 110, thereby defining the passivation structure 118. The first passivation layer 118a may be deposited or grown, for example, via CVD, PVD, ALD, or another suitable deposition or growth process. The first passivation layer 118a liner the sidewalls and upper surface 110µs of the semiconductor substrate 110. The passivation structure 118 is overlaid on the semiconductor substrate 110 and includes the first passivation layer 118a, the second passivation layer 118b, and the third passivation layer 118c. The first passivation layer 118a may be, for example, an oxide such as silicon dioxide, a low-k dielectric material, etc. The first passivation layer 118a can directly contact the pad 116. The second passivation layer 118b can be, for example, an oxide such as silicon dioxide, a low-k dielectric material, etc. The third passivation layer 118c can be, for example, a high-k dielectric material or some other suitable dielectric material.

[0049] like Figure 10 As shown in the cross-sectional view 1000, Figure 9 The structure is patterned to define the pad isolation opening 1002 and the pad protrusion opening 1004. In some embodiments, the patterning process includes: forming a masking layer (not shown) over a first passivation layer 118a; exposing the first passivation layer 118a and an unmasked area of ​​the semiconductor substrate 110 to one or more etchants to define the pad isolation opening 1002 and the pad protrusion opening 1004; and performing a removal process to remove the masking layer. In some embodiments, the patterning process may over-etch and remove at least a portion of the shallow trench isolation structure 112. In other embodiments, the patterning process may stop at the top surface of the shallow trench isolation structure 112, wherein the patterning process does not remove a portion of the shallow trench isolation structure 112 (not shown).

[0050] like Figure 11 As shown in the cross-sectional view 1100, a pad isolation layer 1102 is formed over the passivation structure 118 and the semiconductor substrate 110. In some embodiments, the pad isolation layer 1102 may be deposited or grown, for example, via PVD, CVD, ALD, thermal oxidation, or some other suitable growth or deposition process. The pad isolation layer 1102 may be, for example, a dielectric material, such as silicon dioxide, silicon nitride, silicon oxynitride, etc. In some embodiments, the pad isolation layer 1102 may completely fill the pad isolation opening ( Figure 10 The shown pad isolation opening 1002) and each of the pad protrusion openings 1004 can be lined.

[0051] like Figure 12 As shown in the cross-sectional view 1200, the mating pad isolation layer ( Figure 11 The pad isolation layer 1102 shown is patterned to define the first pad isolation structure 114, the second pad isolation structure 115, the second dielectric layer 502, and the pad opening 1202. The patterning process further removes a portion of the shallow trench isolation structure 112 and a portion of the interconnect dielectric structure 103, exposing the upper surface of the upper conductive wiring layer 108a. In some embodiments, the patterning process includes performing blanket dry etching and / or wet etching.

[0052] like Figure 13 As shown in the cross-sectional view 1300, in Figure 12 A pad layer 1302 is formed on the structure, and the pad layer 1302 fills the pad opening. Figure 12 At least a portion of the pad opening 1202 shown. In some embodiments, the pad layer 1302 may be deposited and / or grown, for example, via electroless plating, electroplating, sputtering, or some other suitable deposition process. In some embodiments, the pad layer 1302 may be, for example, aluminum, copper, aluminum-copper, etc. The pad layer 1302 may, for example, contain the same material as the conductive via 106 and / or conductive wiring 108.

[0053] like Figure 14 As shown in the cross-sectional view 1400, the pad layer ( Figure 13 The pad layer 1302 shown is patterned to define the pad 116 and the conductive ring structure 113. The top surface of the pad 116 and / or the top surface of the conductive ring structure 113 may be vertically separated from the rear side 110b of the semiconductor substrate 110 by a step height h1. The pad 116 and / or the conductive ring structure 113 may each be, for example, aluminum, copper, aluminum-copper, etc. In some embodiments, the pad 116 is laterally offset from the conductive ring structure 113 by a non-zero distance. In other embodiments, the pad layer ( Figure 13 The patterning of the pad layer 1302 shown includes: in the pad layer ( Figure 13 A masking layer (not shown) is formed on top of the padding layer 1302 shown; the padding layer ( Figure 13 The unmasked area of ​​the pad layer 1302 shown is exposed to one or more etchants, thereby defining the pad 116 and the conductive ring structure 113; and a removal process is performed to remove the masking layer.

[0054] like Figure 15As shown in the cross-sectional view 1500, a first dielectric layer 120 is formed over the pad 116. The first dielectric layer 120 may be, for example, silicon dioxide, some other suitable dielectric, etc. In some embodiments, the first dielectric layer 120 may be deposited or grown, for example, via CVD, PVD, ALD, or some other suitable growth or deposition process. In some embodiments, the first dielectric layer 120 is formed with an initial thickness Ti. Subsequently, a planarization process (e.g., chemical mechanical planarization (CMP)) may be performed on the first dielectric layer 120 until the upper surface of the first passivation layer 118a is reached. In these embodiments, after the planarization process, the first dielectric layer 120 may have a thickness Td smaller than the initial thickness Ti. In other embodiments, the first dielectric layer 120 may have a substantially flat upper surface that is perpendicularly aligned with the upper surface of the first passivation layer 118a. In some embodiments, after performing a planarization process, a buried color filter array (BCFA) process may be performed on the semiconductor substrate 110 in an area laterally offset from the pad 116 (e.g., see...). Figure 3 (Forms a filter.)

[0055] In some embodiments, the thickness Td is approximately 5, 10, or 15 times, or more, the step height h1. Since the step height h1 is substantially smaller than the thickness Td of the first dielectric layer 120, the first dielectric layer 120 can be formed to uniformly fill the gap around the pad 116. Furthermore, a planarization process ensures that the upper surface of the first dielectric layer 120 above the pad 116 is substantially flat (e.g., within the tolerances of a CMP process). This, in turn, prevents the first dielectric layer 120 and / or adjacent layers or structures (e.g., the second dielectric layer 502, the pad 116, the conductive ring structure 113, etc.) from cracking and / or delamination during subsequent dicing processes (not shown). In these embodiments, if the pad 116 is close to the dicing kerf (e.g., see...), Figure 4 This can further reduce delamination and / or cracking.

[0056] In some embodiments, the pad 116 may be formed, for example, laterally adjacent to the device area (e.g., Figure 3 The pad area of ​​the device area 101a (not shown) (e.g., Figure 3 Within the pad region 101b shown. In some embodiments, prior to forming the interconnect structure 104 (not shown), a plurality of photodetectors (e.g., ...) may be formed within the semiconductor substrate 110 in the device region via a selective ion implantation process. Figure 3Photodetector 328 shown). Furthermore, prior to forming the interconnect structure 104 (not shown), one or more semiconductor devices (e.g., ...) can be formed in the device region on the front side 110f of the semiconductor substrate 110 via one or more etching processes and one or more deposition processes. Figure 3 (Semiconductor device 320 shown). In other embodiments, after forming the first dielectric layer 120, a mesh structure may be formed in the device region (e.g., Figure 3 The grid structure 329 shown is applied over a photodetector (not shown). The process of forming the grid structure may include, for example, performing one or more deposition processes (e.g., CVD, PVD, ALD, etc.) to deposit one or more grid layers over the plurality of photodetectors (not shown); and performing a patterning process according to a masking layer, wherein the patterning process defines a plurality of color filter openings (not shown) within a device region and directly overlays the corresponding photodetectors (not shown). In another embodiment, the patterning process may over-etch and remove at least a portion of the first passivation layer 118a within the device region (not shown).

[0057] like Figure 16 As shown in the cross-sectional view 1600, a dielectric protective layer 334 is formed over the upper surface of the first dielectric layer 120. In some embodiments, the dielectric protective layer 334 may be deposited or grown via, for example, CVD, PVD, ALD, or some other suitable growth or deposition process. After the dielectric protective layer 334 is formed, a patterning process may be performed on the first dielectric layer 120 and the dielectric protective layer 334 to expose the upper surface of the pads 116 between the pad openings 116o. After the patterning process, an electrical connection pad 122 is formed over the upper surface of the pads 116. Subsequently, the pads 116 may be electrically coupled to an external integrated circuit (not shown) via conductive wiring 124.

[0058] In some embodiments, the dielectric protective layer 334 at least partially liners the plurality of color filter openings within the device region (not shown). Furthermore, the dielectric protective layer 334 may directly contact the first passivation layer 118a within the device region (e.g., see...). Figure 3 In other embodiments, multiple filters may be formed within the color filter opening (not shown). Figure 3 (Filter 336 shown). In these embodiments, the filter can be deposited via CVD, PVD, or another suitable deposition process. In other embodiments, a plurality of microlenses (e.g., ...) are formed on the plurality of filters (not shown). Figure 3The microlenses 338) are shown. In some embodiments, the microlens material can be deposited (e.g., via a spin-on process or a deposition process) on a filter (not shown) to form the microlenses. A microlens template (not shown) having a curved upper surface is patterned over the microlens material. The microlenses are then formed by selectively etching the microlens material according to the microlens template (not shown).

[0059] Figure 17 A method 1700 of forming a contact pad having a reduced step height and a contact pad isolation structure surrounding the contact pad according to the present disclosure is described. Although the method 1700 is described and / or illustrated as a series of acts or events, it is understood that the method is not limited by the order of the sequence of acts or events. Accordingly, some of the acts or events can be performed in a different order than that described, and / or performed concurrently with one another. Furthermore, some of the acts or events can be performed at a different time than that described, and / or performed at the same time as other acts or events. In some embodiments, some of the acts or events can be omitted, and other acts or events can be added.

[0060] At act 1702, a shallow trench isolation (STI) structure is formed on a front side of a semiconductor substrate. Figure 6 A cross-sectional view 600 corresponding to some embodiments of act 1702 is described.

[0061] At act 1704, an interconnect structure is formed on the front side of the semiconductor substrate. Figure 7 A cross-sectional view 700 corresponding to some embodiments of act 1704 is described.

[0062] At act 1706, the back side of the semiconductor substrate is patterned, thereby defining an upper surface of the semiconductor substrate. Figure 9 A cross-sectional view 900 corresponding to some embodiments of act 1706 is described.

[0063] At act 1708, a first passivation layer is formed over the semiconductor substrate. Figure 9 A cross-sectional view 900 corresponding to some embodiments of act 1708 is described.

[0064] At act 1710, the semiconductor substrate and the first passivation layer are patterned, thereby defining a contact pad isolation opening and a contact pad protrusion opening. Figure 10 A cross-sectional view 1000 corresponding to some embodiments of act 1710 is described.

[0065] At act 1712, a contact pad isolation layer is formed over the semiconductor substrate. The contact pad isolation layer fills the contact pad isolation opening and lines the contact pad protrusion opening. Figure 11Cross-sectional view 1100 corresponding to some embodiments of act 1712.

[0066] At act 1714, the pad isolation layer, the shallow trench isolation structure, and the interconnect structure are etched, thereby defining a pad opening and defining a first pad isolation structure and a second pad isolation structure. Figure 12 Cross-sectional view 1200 corresponding to some embodiments of act 1714.

[0067] At act 1716, a pad is formed in at least a portion of the pad opening. The first passivation layer and the second pad isolation structure separate the pad from the semiconductor substrate. Figure 13 and Figure 14 Cross-sectional views 1300 and 1400 corresponding to some embodiments of act 1716.

[0068] At act 1718, a first dielectric layer is formed over the pad. The first dielectric layer fills a remaining portion of the pad opening. Figure 15 Cross-sectional view 1500 corresponding to some embodiments of act 1718.

[0069] Thus, in some embodiments, the invention relates to a pad that extends laterally through a semiconductor substrate and laterally away from a device region. An upper surface of the pad is lower than a backside surface of the semiconductor substrate in a vertical direction by a reduced step height. A first pad isolation structure and a second pad isolation structure electrically isolate the pad from semiconductor devices (e.g., photodetectors, transistors, etc.) disposed within the device region.

[0070] In some embodiments, the invention provides a semiconductor structure, comprising: a semiconductor substrate having a backside surface and a frontside surface opposite the backside surface, wherein an upper surface of the semiconductor substrate is lower than the backside surface in a vertical direction; a pad extending through the semiconductor substrate, wherein the pad includes a conductive body located above the upper surface of the semiconductor substrate and a conductive protrusion extending from above the upper surface of the semiconductor substrate to below the frontside surface, and wherein a vertical distance between a top surface of the pad and the backside surface of the semiconductor substrate is less than a height of the conductive protrusion; and a first pad isolation structure extending through the semiconductor substrate and laterally surrounding the conductive protrusion.

[0071] In some embodiments, the semiconductor structure further comprises: a second pad isolation structure disposed around the conductive protrusion, wherein the second pad isolation structure is disposed between the conductive protrusion and an inner sidewall of the semiconductor substrate; and wherein the first pad isolation structure and the second pad isolation structure comprise a same dielectric material.

[0072] In some embodiments, the height of the electrically conductive protrusion is greater than the height of the first contact pad isolation structure and the height of the second contact pad isolation structure.

[0073] In some embodiments, the second contact pad isolation structure directly contacts sidewalls of the electrically conductive protrusion, and wherein the first contact pad isolation structure is laterally offset from the electrically conductive protrusion by a non-zero distance.

[0074] In some embodiments, the vertical distance between the top surface of the contact pad and the backside surface of the semiconductor substrate is less than a height of the electrically conductive body.

[0075] In some embodiments, the semiconductor structure further comprises: a passivation structure overlying the semiconductor substrate, wherein the passivation structure is disposed between the electrically conductive body and the top surface of the semiconductor substrate; and a shallow trench isolation structure (STI) disposed along the frontside surface of the semiconductor substrate, wherein the contact pad is laterally spaced between sidewalls of the shallow trench isolation structure.

[0076] In some embodiments, the first contact pad isolation structure continuously extends from the passivation structure to the shallow trench isolation structure.

[0077] In some embodiments, the first contact pad isolation structure is ring-shaped when viewed from above.

[0078] In some embodiments, the semiconductor structure further comprises: an electrically conductive ring structure overlying the top surface of the semiconductor substrate, wherein the electrically conductive ring structure laterally surrounds the electrically conductive body, wherein the electrically conductive ring structure comprises a same material as the contact pad.

[0079] In some embodiments, a top surface of the electrically conductive ring structure is aligned with the top surface of the contact pad, and wherein the first contact pad isolation structure is laterally spaced between sidewalls of the electrically conductive ring structure.

[0080] In some embodiments, the present disclosure provides a semiconductor structure comprising: a first substrate overlying a second substrate and comprising a top surface higher than an upper surface in a vertical direction, wherein a photodetector is disposed in the first substrate; an interconnect structure disposed between the first substrate and the second substrate, wherein an upper conductive wiring layer is disposed within the interconnect structure; a landing pad overlying the upper surface of the first substrate and extending through the first substrate to the interconnect structure, wherein the landing pad contacts the upper conductive wiring layer and is laterally offset from the photodetector, and wherein a vertical distance between the top surface of the first substrate and a top surface of the landing pad is less than a height of the landing pad overlying the upper surface of the first substrate; a first landing pad isolation structure disposed within the first substrate and laterally surrounding an outer sidewall of the landing pad; and a second landing pad isolation structure disposed within the first substrate, wherein the second landing pad isolation structure directly contacts a sidewall of the landing pad extending through the first substrate.

[0081] In some embodiments, the semiconductor structure further comprises: a passivation structure overlying the first substrate, wherein the passivation structure continuously extends from over the photodetector to over the upper surface of the first substrate; and a first dielectric layer overlying the landing pad, wherein an upper surface of the first dielectric layer is aligned with an upper surface of the passivation structure, and wherein a height of the first dielectric layer is less than a height of the landing pad.

[0082] In some embodiments, an upper surface of the first landing pad isolation structure and an upper surface of the second landing pad isolation structure directly contact a lower surface of the landing pad.

[0083] In some embodiments, the landing pad comprises a conductive body and a conductive protrusion extending from the conductive body into the first substrate, the conductive body comprising a sidewall defining a landing pad opening overlying the conductive protrusion, wherein electrical connection pads overlie the landing pad and are laterally spaced between the landing pad openings.

[0084] In some embodiments, the semiconductor structure further comprises: a plurality of optical filters overlying the photodetector, wherein the optical filters are configured to pass near-infrared radiation (NIR); and wherein a thickness of the first substrate is in a range of 3.5 microns to 6 microns.

[0085] In some embodiments, the landing pad and the upper conductive wiring layer comprise a same conductive material.

[0086] In some embodiments, the present disclosure provides a method for forming a semiconductor structure, the method comprising: forming a shallow trench isolation (STI) structure on a front side surface of a substrate; forming an interconnect structure on the front side surface of the substrate, wherein the interconnect structure comprises a conductive wiring layer; patterning the substrate to define an upper surface of the substrate to be lower than a back side surface of the substrate in a vertical direction, wherein the back side surface is opposite the front side surface; forming a first passivation layer over the back side surface of the substrate; patterning the first passivation layer and the substrate to define a pad isolation opening and a pad protrusion opening, wherein the patterning the first passivation layer and the substrate exposes an upper surface of the shallow trench isolation structure; depositing a pad isolation layer over the substrate, wherein the pad isolation layer fills the pad isolation opening and lines the pad protrusion opening; etching the pad isolation layer and the shallow trench isolation structure to expose an upper surface of the conductive wiring layer and to define a first pad isolation structure and a second pad isolation structure; and forming a pad over the conductive wiring layer.

[0087] In some embodiments, etching the pad isolation layer and the shallow trench isolation structure comprises performing a blanket etch process.

[0088] In some embodiments, forming the pad comprises: forming a pad layer over the substrate and the interconnect structure, wherein the pad layer fills a remaining portion of the pad protrusion opening and overlies the upper surface of the substrate; and patterning the pad layer to define the pad and a conductive ring structure, wherein the conductive ring structure overlies the upper surface of the substrate and is laterally offset from a sidewall of the pad by a non-zero distance.

[0089] In some embodiments, patterning the first passivation layer and the substrate over-etches and removes a portion of the shallow trench isolation structure, wherein a lower surface of the first pad isolation structure and a lower surface of the second pad isolation structure are disposed lower than a top surface of the shallow trench isolation structure.

[0090] The foregoing outlines features of a number of embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: a semiconductor substrate having a backside surface and a frontside surface opposite the backside surface, wherein an upper surface of the semiconductor substrate is lower in a vertical direction than the backside surface; a landing pad extending through the semiconductor substrate, wherein the landing pad includes a conductive body above the upper surface of the semiconductor substrate and a conductive protrusion extending from above the upper surface of the semiconductor substrate to below the frontside surface, and wherein a vertical distance between a top surface of the landing pad and the backside surface of the semiconductor substrate is less than a height of the conductive protrusion; a first landing pad isolation structure extending through the semiconductor substrate and laterally surrounding the conductive protrusion; and a conductive ring structure overlying the upper surface of the semiconductor substrate, wherein the conductive ring structure laterally surrounds the conductive body and a top surface of the conductive ring structure is aligned with the top surface of the landing pad.

2. The semiconductor structure of claim 1, further comprising: a second landing pad isolation structure disposed around the conductive protrusion, wherein the second landing pad isolation structure is disposed between the conductive protrusion and an interior sidewall of the semiconductor substrate; and wherein the first landing pad isolation structure and the second landing pad isolation structure comprise a same dielectric material.

3. The semiconductor structure of claim 2, wherein the height of the conductive protrusion is greater than a height of the first landing pad isolation structure and a height of the second landing pad isolation structure.

4. The semiconductor structure of claim 2, wherein the second landing pad isolation structure directly contacts a sidewall of the conductive protrusion, and wherein the first landing pad isolation structure is laterally offset from the conductive protrusion by a non-zero distance.

5. The semiconductor structure of claim 1, wherein the vertical distance between the top surface of the landing pad and the backside surface of the semiconductor substrate is less than a height of the conductive body.

6. The semiconductor structure of claim 1, further comprising: a passivation structure overlying the semiconductor substrate, wherein the passivation structure is disposed between the conductive body and the upper surface of the semiconductor substrate; and a shallow trench isolation structure disposed along the frontside surface of the semiconductor substrate, wherein the landing pad is laterally spaced between sidewalls of the shallow trench isolation structure.

7. The semiconductor structure of claim 6, wherein the first landing pad isolation structure continuously extends from the passivation structure to the shallow trench isolation structure.

8. The semiconductor structure of claim 1, wherein the first landing pad isolation structure is annular when viewed in a top-down view.

9. The semiconductor structure of claim 1, wherein the conductive ring structure and the landing pad comprise a same material.

10. The semiconductor structure of claim 9, wherein the first landing pad isolation structure is laterally spaced between sidewalls of the conductive ring structure.

11. A semiconductor structure comprising: a first substrate overlying a second substrate and including a top surface higher in a vertical direction than an upper surface, wherein a photodetector is disposed in the first substrate; ​ ​ ​ an interconnect structure disposed between the first substrate and the second substrate, wherein an upper conductive wiring layer is disposed within the interconnect structure; a landing pad overlying the upper surface of the first substrate and extending through the first substrate to the interconnect structure, wherein the landing pad contacts the upper conductive wiring layer and is laterally offset from the photodetector, and wherein a vertical distance between the top surface of the first substrate and a top surface of the landing pad is less than a height of the landing pad overlying the upper surface of the first substrate, wherein the landing pad includes a conductive body overlying the upper surface of the first substrate and first and second conductive protrusions continuously extending from a bottom surface of the conductive body to the upper conductive wiring layer; a first landing pad isolation structure disposed within the first substrate and laterally surrounding an outer sidewall of the landing pad; a second landing pad isolation structure disposed within the first substrate, wherein the second landing pad isolation structure directly contacts opposing sidewalls of each of the first and second conductive protrusions, respectively, and continuously extends vertically from the bottom surface of the conductive body to a point aligned with a bottom surface of the first landing pad isolation structure; and a conductive ring structure overlying the upper surface of the first substrate, wherein the conductive ring structure laterally surrounds the conductive body and a top surface of the conductive ring structure is aligned with the top surface of the landing pad.

12. The semiconductor structure of claim 11, further comprising: a passivation structure overlying the first substrate, wherein the passivation structure continuously extends from over the photodetector to over the upper surface of the first substrate; and a first dielectric layer overlying the landing pad, wherein an upper surface of the first dielectric layer is aligned with an upper surface of the passivation structure, and wherein a height of the first dielectric layer is less than a height of the first and second conductive protrusions.

13. The semiconductor structure of claim 11, wherein the conductive body includes sidewalls defining first and second landing pad openings directly overlying the first and second conductive protrusions, wherein an electrical connector pad overlying the landing pad is laterally spaced between the first and second landing pad openings.

14. The semiconductor structure of claim 11, further comprising: a plurality of optical filters overlying the photodetector, wherein the optical filters are configured to pass near-infrared radiation; and wherein a thickness of the first substrate is in a range of 3.5 microns to 6 microns.

15. The semiconductor structure of claim 11, wherein the landing pad and the upper conductive wiring layer comprise a same conductive material.

16. A method for forming a semiconductor structure, the method comprising: forming a shallow trench isolation structure on a front side surface of a substrate; forming an interconnect structure on the front side surface of the substrate, wherein the interconnect structure includes a conductive wiring layer; patterning the substrate to define an upper surface of the substrate to be lower in a vertical direction than a backside surface of the substrate, wherein the backside surface is opposite the frontside surface; forming a first passivation layer over the backside surface of the substrate; patterning the first passivation layer and the substrate to define a first contact pad isolation opening and first and second contact pad protrusion openings, wherein the patterning the first passivation layer and the substrate exposes an upper surface of the shallow trench isolation structure; depositing a contact pad isolation layer over the substrate, wherein the contact pad isolation layer fills the contact pad isolation opening and lines the first and second contact pad protrusion openings; etching the contact pad isolation layer and the shallow trench isolation structure to expose an upper surface of the conductive wiring layer and to define first and second contact pad isolation structures, wherein a lower surface of the first contact pad isolation structure directly contacts a top surface of the shallow trench isolation structure, the second contact pad isolation structure is disposed along opposing sidewalls of the first and second contact pad protrusion openings, and the second contact pad isolation structure is disposed between an inner sidewall of the second contact pad protrusion opening and the first contact pad isolation structure; and forming a contact pad and a conductive ring structure over the conductive wiring layer, wherein the contact pad includes a conductive body over the upper surface of the substrate and first and second conductive protrusions extending from above the upper surface of the substrate below the frontside surface, the conductive ring structure overlies the upper surface of the substrate, the conductive ring structure laterally surrounds the conductive body, and a top surface of the conductive ring structure is aligned with a top surface of the contact pad.

17. The method of claim 16, wherein etching the contact pad isolation layer and the shallow trench isolation structure includes performing a blanket etch process.

18. The method of claim 16, wherein forming the contact pad and the conductive ring structure includes: forming a contact pad layer over the substrate and the interconnect structure, wherein the contact pad layer fills remaining portions of the first and second contact pad protrusion openings and overlies the upper surface of the substrate; and patterning the contact pad layer to define the contact pad and the conductive ring structure, wherein the conductive ring structure is laterally offset from sidewalls of the contact pad by a non-zero distance.

19. The method of claim 16, wherein patterning the first passivation layer and the substrate over-etches and removes a portion of the shallow trench isolation structure, wherein a lower surface of the second contact pad isolation structure is disposed lower than the top surface of the shallow trench isolation structure. ​

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