Semiconductor device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a method for manufacturing the same. The device includes a substrate; a first semiconductor layer formed on the substrate; a second semiconductor layer formed on the first semiconductor layer; the first semiconductor layer having a smaller bandgap width than the second semiconductor layer; a first electrode, a second electrode, and a third electrode formed on the second semiconductor layer; a first region with strong P-type doping in the first semiconductor layer corresponding to the third electrode, and a second region with weak P-type doping in the first semiconductor layer corresponding to the second electrode. The present disclosure helps to achieve one of the following effects: reducing gate leakage current, having a high threshold voltage, high power, and high reliability, being able to achieve a low on-resistance and a normally-off state of the device, being able to provide a stable threshold voltage, so that the semiconductor device has good switching characteristics and is safer to use.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Group III nitride semiconductors are an important new type of semiconductor material, mainly including AlN, GaN, InN, and compounds of these materials such as AlGaN, InGaN, AlInGaN, etc. Due to their advantages such as direct bandgap, wide bandgap, high breakdown electric field strength, and high saturated electron velocity, group III nitride semiconductors have broad application prospects in the fields of light-emitting devices, power electronics, radio frequency devices, etc.

[0003] Taking advantage of the above-mentioned advantages of group III nitride semiconductors, it is desirable to develop semiconductor devices with high performance such as high breakdown voltage, high power, and low on-resistance through optimized design of device structures and processes. Summary of the Invention

[0004] A brief overview of the present disclosure will be given below to provide a basic understanding of certain aspects of the present disclosure. It should be understood that this overview is not an exhaustive overview of the present disclosure. It is not intended to identify the key or important parts of the present disclosure, nor is it intended to limit the scope of the present disclosure. Its purpose is merely to present certain concepts in a simplified form as a prelude to a more detailed description to follow.

[0005] According to one aspect of the present disclosure, there is provided a semiconductor device, which includes: a substrate; a first semiconductor layer on the first surface of the substrate; a second semiconductor layer on the first surface of the first semiconductor layer; the first semiconductor layer having a smaller bandgap than the second semiconductor layer; a first electrode, a second electrode, and a third electrode on the second semiconductor layer; wherein the first semiconductor layer further includes a strongly P-type doped first region and a weakly P-type doped second region; the first region is located below the third electrode, and the second region is located below the second electrode.

[0006] Further, the substrate is sapphire, ZnO, SiC, AlN, GaAs, LiAlO, GaAlLiO, GaN, Al2O3, or single crystal silicon.

[0007] Further, the first semiconductor layer is an intrinsic nitride semiconductor layer or an unintentionally doped nitride semiconductor layer, and the epitaxial direction of the intrinsic nitride semiconductor layer or the unintentionally doped nitride semiconductor layer parallel to the substrate is the

[0001] direction.

[0008] Further, the second semiconductor layer is an AlN, AlGaN, InAlGaN, or InAlN layer.

[0009] Further, the area of the substrate projected by the first region is within the area of the substrate projected by the third electrode.

[0010] Further, the first region depletes 95% - 100% of the two-dimensional charge carrier gas at the overlap with the projected area of the third electrode.

[0011] Further, when the bias voltage of the third electrode is 0, the two-dimensional charge carrier gas corresponding to at least a part of the third electrode is less than 5E+11 / cm 2 。

[0012] Further, the two-dimensional charge carrier gas in the second region is not less than 2E+12 / cm 2 。

[0013] Further, the epitaxial direction of the first region in the first semiconductor layer parallel to the substrate is the

[0001] direction, and its lateral epitaxial direction is 。

[0014] Further, the doping concentration of the first region is 1E18 - 5E19 / cm 3 。

[0015] Further, the first region includes a single-layer structure or multiple discrete layer structures with a number greater than or equal to 2.

[0016] Further, the multiple discrete layer structures are discrete layer structures perpendicular to the substrate or parallel to the substrate.

[0017] Further, the discrete layer structures perpendicular to the substrate completely overlap, do not overlap, or partially overlap in the orthographic projection;

[0018] Further, the discrete layer structures are in close contact with each other, or there is a certain gap between the discrete layer structures.

[0019] Further, the gap is composed of a weakly P-doped region.

[0020] Further, the first region is a layer structure with a gradually changing doping concentration.

[0021] Further, the doping concentration of the first region gradually changes from the center of the first region to both sides parallel to the substrate, or the doping concentration of the first region gradually changes from the center of the first region to both sides perpendicular to the substrate, or the doping concentration of the first region has a unilateral gradient.

[0022] Further, the thickness range of the first region is greater than 0 and less than or equal to the thickness of the first semiconductor layer.

[0023] Further, the thickness range of the second region is greater than 0 and less than or equal to the thickness of the first semiconductor layer.

[0024] Further, the first semiconductor layer has a second surface opposite to the first surface of the substrate and a first surface facing away from the first surface of the substrate. The first region has a second surface opposite to the first surface of the first semiconductor layer and a first surface facing away from the first surface of the first semiconductor layer. The first region further has a third surface connecting the first and second surfaces of the first region. The third surface of the first region forms an angle greater than 30 degrees and less than or equal to 90 degrees with the second surface of the third semiconductor layer.

[0025] Further, the length range of the first region is 0.01 - 10 microns, and the thickness is 0.01 - 10 microns.

[0026] Further, the second region of the first semiconductor layer extends from the region overlapping with the projection region of the second electrode along the direction parallel to the movement of the two-dimensional charge carriers towards both ends.

[0027] Further, the first region and the second region are interconnected.

[0028] Further, the second region includes a buffer structure; or the second region includes a strongly P-type doped third region; or the second region includes a strongly P-type doped third region and the third region includes a buffer structure.

[0029] Further, there is also a third semiconductor layer between the first semiconductor layer and the second semiconductor layer.

[0030] Further, there are also the fourth and / or fifth semiconductor layers between the first semiconductor layer and the substrate.

[0031] Further, the fifth semiconductor layer is a group III nitride buffer layer, and the fourth semiconductor layer is a nitride semiconductor layer.

[0032] Further, there is a weakly P-type doped fourth region below the second electrode in the fourth semiconductor layer, and a strongly P-type doped third region below the third electrode in the fourth semiconductor layer.

[0033] Further, a second region with weak P-type doping is provided below the second electrode in the fourth semiconductor layer to replace the second region in the first semiconductor layer, and a first region with strong P-type doping is provided below the third electrode in the fourth semiconductor layer to replace the first region in the first semiconductor layer.

[0034] Further, the second electrode includes a metal in ohmic contact with the two-dimensional electron gas; or the second electrode includes a metal in ohmic contact with the two-dimensional electron gas and a doped region in ohmic contact with the second region; the metal element forming ohmic contact with the two-dimensional electron gas and the doped element forming ohmic contact with the second region in the second electrode are the same; or the metal element forming ohmic contact with the two-dimensional electron gas and the doped element forming ohmic contact with the second region in the second electrode are different.

[0035] Further, a first insulating layer is formed between the first semiconductor layer and the substrate, and a seed layer is provided in the first insulating layer, and the seed layer is located below the second electrode.

[0036] Further, a second insulating layer is provided between the second semiconductor layer and the third electrode.

[0037] Further, the second insulating layer is silicon dioxide, silicon nitride, and / or Al2O3.

[0038] Further, the second region has a fourth electrode connected thereto.

[0039] Further, the substrate has a second surface opposite to its first surface, and a fourth electrode connected to the second region is formed at the second surface of the substrate; or the second region extends along a direction perpendicular to the flow of the two-dimensional charge carrier gas, and a fourth electrode connected to the second region is formed at a position not covered by the projection of the second electrode.

[0040] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device includes: Step 100: providing a substrate; Step 200: forming a first semiconductor layer on the first surface of the substrate; Step 300: forming a first region with strong P-type doping and a second region with weak P-type doping in the first semiconductor layer; Step 400: forming a second semiconductor layer on the first surface of the first semiconductor layer; a two-dimensional charge carrier gas is generated between the first semiconductor layer and the second semiconductor layer; Step 500: forming a first electrode and a second electrode in ohmic contact with the two-dimensional charge carrier gas, and forming a third electrode on one side of the first surface of the second semiconductor layer; wherein the first region is located below the third electrode, and the second region is located below the second electrode.

[0041] Further, the method for forming the first and second regions is lateral epitaxy or ion implantation, and the first region is prepared as a discrete or gradually changing doping concentration structure.

[0042] Further, between step 300 and step 400, a third semiconductor layer is further formed on the first semiconductor layer.

[0043] Further, in step 500, a sacrificial layer is formed on the second semiconductor layer by depositing a sacrificial material. The sacrificial layer is developed / etched to expose the portion of the second semiconductor layer corresponding to the first to third electrodes. Through a doping process, a first portion of the N+ doped source-drain region is formed at the corresponding position. Then, a metal material for the first and second electrodes is formed on the exposed second semiconductor layer, and then etched and annealed to form a second portion of the ohmic contact of the source-drain region.

[0044] Further, in step 500, a second insulating layer is in-situ formed on the second semiconductor layer by MOCVD. The second insulating layer is etched to expose the portion of the second semiconductor layer corresponding to the first to third electrodes. Through a doping process, a first portion of the N+ doped source-drain region is formed at the corresponding position. Then, a metal material for the first and second electrodes is formed on the exposed second semiconductor layer, and then etched and annealed to form a second portion of the ohmic contact of the source-drain region.

[0045] Further, the doping element of the first portion is the same as the metal element of the second portion, or the doping element of the first portion is different from the metal element of the second portion.

[0046] Further, the formation step of the first portion can be omitted.

[0047] Further, the second insulating layer in-situ formed on the second semiconductor layer is in-situ formed together with other semiconductor layers; or the second insulating layer is in-situ formed on the second semiconductor layer only together with the second semiconductor layer.

[0048] Further, it further includes step 210: depositing and forming a first insulating layer on the first surface of the substrate, removing at least a part of the first insulating layer corresponding to the region where the second electrode is subsequently formed to form an opening to expose a part of the substrate, and then depositing and forming a seed layer on the first insulating layer having the opening.

[0049] Further, it further includes step 210': depositing and forming a seed crystal material on the first surface of the substrate, retaining a part of the seed crystal material to form a seed crystal layer, then depositing an insulating material on the first surface of the substrate, the insulating material completely covering the substrate and the seed crystal layer, removing a part of the insulating material until the seed crystal layer is exposed, and the seed crystal layer corresponding to the subsequent formation of the second electrode region.

[0050] Further, it further includes step 220: on the first surface of the first insulating layer and / or the seed crystal layer, laterally epitaxially growing a non-intentionally doped nitride semiconductor or an intrinsic nitride semiconductor with the seed crystal layer as the center, and stopping the growth when the nitride semiconductor does not completely cover the first insulating layer and / or the seed crystal layer by controlling its growth rate, thereby forming the first part of the first semiconductor layer.

[0051] Further, the first part is subjected to full weak P-type doping; or the first part is first subjected to strong P-type doping and then weak P-type doping; or the first part is first formed into a structure of an unintentionally doped or intrinsic nitride semiconductor and then weak P-type doping is carried out; or the first part is first formed into a structure of an unintentionally doped or intrinsic nitride semiconductor and then strong P-type doping is carried out, and then weak P-type doping is carried out.

[0052] Further, it further includes step 230: with the first part of the grown first semiconductor layer as the core, continuing to grow a strongly P-type doped nitride layer on its surface and side surfaces. After growing a strongly P-type doped nitride semiconductor layer with a certain thickness, continuing to grow a low-doped or undoped nitride semiconductor layer, the low-doped or undoped nitride semiconductor layer forming the connection region of the first semiconductor layer, and then by removing a part of the connection region and the strongly P-type doped nitride semiconductor layer to expose the weakly P-type nitride semiconductor doped layer, and step 230 can be repeated multiple times.

[0053] Further, a first region of strongly P-type doping is formed within the projection region where the third electrode is to be formed subsequently.

[0054] Further, the strongly P-type doped region is strongly P-GaN, the weakly P-type doped region is weakly P-GaN, and the lateral growth direction of the P-GaN is crystal orientation.

[0055] Further, it further includes step 240: continuing to grow a weakly doped, unintentionally doped or intrinsic nitride semiconductor layer with the structure obtained in step 230 as the core until the nitride semiconductor layer completely covers the first insulating layer and / or the seed crystal layer.

[0056] Further, the removing step further includes: removing a part of the connection region and the strong P-type doped region to expose the weak P-type region; or removing a part of the connection region and the strong P-type doped region to leave an extremely thin strong P-type doped layer on the weak P-type region; or removing a part of the connection region and the strong P-type doped region, and after exposing the weak P-type region, further removing a part of the connection region, the strong P-type region, and the weak P-type region.

[0057] Further, it further includes the step of: laterally epitaxially forming the fourth semiconductor layer with the seed layer as the center, where the fourth semiconductor layer has a strong P-doped region and a weak P-doped region.

[0058] Further, it further has step 600: forming a through hole at a position corresponding to the weak P-type doped region on the second surface of the substrate, the through hole reaching the second region of the weak P-type doped region, and forming a fourth electrode in the through hole, thereby controlling the potential of the first region.

[0059] Further, it further has step 600: growing along a direction perpendicular to the two-dimensional carrier charge flow direction in the weak P-type doped region, forming a through hole by etching on one side of the weak P-type doped region not covered by the positive projection of the second electrode, and forming a fourth electrode connected to the weak P-type doped region in the through hole.

[0060] According to another aspect of the present disclosure, there is provided an electronic device, which includes the semiconductor device described in the present disclosure.

[0061] The solution of the present disclosure can at least help to achieve one of the following effects: the semiconductor device can reduce the gate leakage current, has a high threshold voltage, high power, and high reliability, can achieve a low on-resistance and the normally-off state of the device, can provide a stable threshold voltage, so that the semiconductor device has good switching characteristics and is safer to use. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The specific content of the present disclosure will be described below with reference to the drawings, which will help to more easily understand the above and other objects, features, and advantages of the present disclosure. The drawings are only for showing the principle of the present disclosure. The dimensions and relative positions of the units do not have to be drawn to scale in the drawings. In the drawings:

[0063] Figure 1 A schematic cross-sectional view showing the semiconductor device structure according to the first embodiment is shown;

[0064] Figures 2a - 2c A schematic cross-sectional view showing a modified example of the semiconductor device structure according to the first embodiment is shown;

[0065] Figure 3 Shows a schematic cross-sectional view of a modified example of a semiconductor device structure according to the first embodiment;

[0066] Figure 4 Shows the energy band diagram of the semiconductor device in the first embodiment;

[0067] Figure 5 Shows a schematic cross-sectional view of a modified example of a semiconductor device structure according to the first embodiment;

[0068] Figure 6 Shows a schematic cross-sectional view of a semiconductor device structure according to the second embodiment;

[0069] Figure 7 Shows a schematic cross-sectional view of a semiconductor device structure according to the third embodiment;

[0070] Figure 8 Shows a schematic cross-sectional view of a semiconductor device structure according to the fourth embodiment;

[0071] Figure 9 Shows a schematic cross-sectional view of a semiconductor device structure according to the fifth embodiment;

[0072] Figure 10 Shows a schematic cross-sectional view of a semiconductor device structure according to the sixth embodiment;

[0073] Figure 11 Shows a schematic cross-sectional view of a semiconductor device structure according to the seventh embodiment;

[0074] Figures 12 - 26 Shows a schematic cross-sectional view of a method for manufacturing a semiconductor device according to the eighth embodiment;

[0075] Figure 27 Shows a schematic cross-sectional view of a method for manufacturing a semiconductor device according to the ninth embodiment;

[0076] Figure 28 Shows a schematic cross-sectional view of a method for manufacturing a semiconductor device according to the tenth embodiment. Detailed implementation manners

[0077] In the following, the exemplary disclosures of the present disclosure will be described with reference to the accompanying drawings. For clarity and conciseness, not all features of the actual present disclosure are described in the specification. However, it should be understood that many decisions specific to the present disclosure may be made in the process of developing any such actual present disclosure in order to achieve the specific goals of the developer, and these decisions may vary with different actualizations of the present disclosure.

[0078] Here, it should also be noted that in order to avoid obscuring the present disclosure with unnecessary details, only the device structures closely related to the solutions according to the present disclosure are shown in the drawings, while other details less related to the present disclosure are omitted.

[0079] It should be understood that the present disclosure is not limited to the described embodiments only due to the following description with reference to the drawings. Here, where feasible, features between different embodiments can be replaced or borrowed, and one or more features can be omitted in one embodiment.

[0080] Specifically, the semiconductor device of the present disclosure is a compound semiconductor device. Further, the compound semiconductor device is a compound semiconductor device including a nitride semiconductor material, also referred to as a nitride semiconductor device. The nitride semiconductor device includes a field effect transistor in which a nitride semiconductor material is used. Still further, the field effect transistor is a GaN field effect transistor including a GaN semiconductor material. In particular, the GaN field effect transistor is a normally-off transistor GaN-HEMT.

[0081] First Embodiment

[0082] Refer to Figure 1 to describe the semiconductor device according to the first embodiment.

[0083] As Figure 1 shown, in the first embodiment, the semiconductor device, exemplarily a normally-off transistor GaN-HEMT, includes a substrate 100, and the material of the substrate 100 can be selected according to actual needs, and the specific form of the substrate 100 is not limited in this embodiment. Optionally, the substrate 100 can be sapphire, ZnO, SiC, AlN, GaAs, LiAlO, GaAlLiO, GaN, Al2O3 or single crystal silicon, etc.; further, the substrate 100 can be (0001)-plane Al2O3; still further, the substrate 100 can be a (111)-plane silicon substrate. A first semiconductor layer 105 is formed on the first surface 1001 of the substrate 100. Optionally, the first semiconductor layer 105 is a GaN layer. Further, the first semiconductor layer 105 is an intrinsic GaN layer (i-GaN) or an unintentionally doped GaN layer. The first semiconductor layer 105 has a second surface 1052 opposite to the first surface 1001 of the substrate 100 and a first surface 1051 facing away from the first surface 1001 of the substrate 100. The epitaxial direction of the GaN layer parallel to the substrate is substantially parallel to the

[0001] orientation.

[0084] A second semiconductor layer 106 is formed on the first surface 1051 of the first semiconductor layer 105. The first semiconductor layer 105 has a smaller bandgap than the second semiconductor layer 106, thereby forming a two-dimensional charge carrier gas, such as 2DEG, between the first semiconductor layer 105 and the second semiconductor layer 106. The second semiconductor layer 106 has a second surface 1062 opposite to the first surface 1051 of the first semiconductor layer 105 and a first surface 1061 facing away from the first surface of the first semiconductor layer 105. Optionally, the second semiconductor layer 106 is an AlGaN, InAlGaN, InAlN layer, etc.

[0085] A first electrode 107, a second electrode 108, and a third electrode 109 are formed on the second semiconductor layer 106. The first electrode 107 can be a drain and form an ohmic contact with the two-dimensional charge carrier gas. The third electrode 109 can be a gate, which forms a Schottky contact with the second semiconductor layer to reduce the off-state leakage current. The second electrode 108 is a source and forms an ohmic contact with the two-dimensional charge carrier gas. It should be clear that the first electrode 107 and the second electrode 108 can also be a corresponding doped region (drain region) and another doped region (source region) of the device.

[0086] The first semiconductor layer 105 region includes a strongly P-type doped first region 1053. The projection region of the first region 1053 on the substrate falls within the projection region of the third electrode 109 on the substrate. The doping concentration of the strongly P-type doped first region is exemplarily 1E18 - 5E19 / cm3. Typically, the doping concentration of the first region is greater than 5E18 / cm3. Further, the length range of the strongly P-type doped first region 1053 parallel to the moving direction of the two-dimensional charge carriers is greater than 0 and less than or equal to the length of the third electrode 109 (i.e., less than or equal to the gate length). The doping concentration of the strongly P-type doped first region 1053 can be a single-sided gradient along the length direction or a double-sided gradient from the center of the length to both sides. The thickness range of the strongly P-type doped first region 1053 is greater than 0 and less than or equal to the thickness of the first semiconductor layer 105. The strongly P-type doped first region 1053 can be a region composed of multiple discrete layers with a number greater than 2 along the length direction, such as Figure 2a shown, or a region composed of multiple discrete layers with a number greater than 2 along the thickness direction of the first semiconductor layer, such as Figures 2b - 2cAs shown. The layers separated along the thickness direction of the first semiconductor layer may overlap in the orthographic projection or may not overlap in the orthographic projection. There may be a gap between the separated layers or there may be no gap. The region between the separated layers with a gap may be a weakly P-type doped region. Further, in addition to being located within the range where the projection area of the first semiconductor layer 105 overlaps with the third electrode 109, the strongly P-type doped first region 1053 may extend from the overlapping range along the direction perpendicular to the movement of the two-dimensional charge carriers towards both ends.

[0087] The first semiconductor layer 105 further includes a weakly P-type doped second region 1054 that extends from the region overlapping with the projection area of the second electrode 108 along the direction parallel to the movement of the two-dimensional charge carriers towards both ends. The second region 1054 is connected to the first region 1053. The thickness range of the second region is greater than 0 and less than or equal to the thickness of the first semiconductor layer 105. The exemplary doping concentration of the second region 1054 <5E18 / cm 3 , for example, 1E18 / cm 3 , 5E17 cm 3 etc. In the above semiconductor device (HEMT), the strong P-type doping in the first region 1053 and the weak P-type doping in the second region 1054 are relative and are related to the two-dimensional charge carrier gas formed between the first semiconductor layer 105 and the second semiconductor layer 106. When the concentration of the intrinsic two-dimensional charge carrier gas at the interface between the first semiconductor layer 105 and the second semiconductor layer 106 is higher, the doping concentration corresponding to the strong P-type doping is also higher, and thus the doping concentration corresponding to the weak P-type doping can also be relatively increased compared to the normal situation. Conversely, when the concentration of the intrinsic two-dimensional charge carrier gas is lower, the doping concentration corresponding to the strong P-type doping is also lower, and thus the doping concentration corresponding to the weak P-type doping can also be relatively decreased compared to the normal situation. In the same device, the doping concentration of the strong P-type doping can be, for example, more than twice the doping concentration of the weak P-type doping.

[0088] As Figure 3 shown, the second electrode 108 may form an ohmic contact with the weakly P-type doped second region 1054, so that the potential of the strongly P-type doped first region 1053 is connected to the second electrode 108 through the weakly P-type doped second region 1054. Further, the metal element forming an ohmic contact with the two-dimensional charge carrier gas and the doping element forming an ohmic contact with the weakly P-type doped second region 1054 on the second electrode 108 may be the same or different.

[0089] Since the first region 1053 of the first semiconductor layer has a lower Fermi level, it can deplete the two-dimensional charge carriers located above it, thereby causing the device to have a higher threshold voltage and a normally-closed state of the device. The setting of the first region 1053, such as its thickness, length, width, P-type doping concentration, etc., can be set through device parameters to satisfy the depletion of 95%-100% of the two-dimensional charge carriers above it. Exemplarily, the two-dimensional charge carrier gas in at least a partial region under the third electrode is less than 5E12 / cm2 when the gate bias is 0. The first region 1053 arranged within the gate length can quickly deplete the two-dimensional charge carrier gas, thereby further improving its performance parameters, and further causing the device to have a lower on-resistance and good switching characteristics.

[0090] The second region 1054 of the first semiconductor layer has a lower P-type doping to protect the two-dimensional charge carrier gas in this region to still maintain a relatively high concentration. Exemplarily, the setting of the second region, such as its thickness, length, width, P-type doping concentration, etc., can be set through device parameters to satisfy the depletion of less than 80% of the two-dimensional charge carriers above it. It is related to both the distance between the second region and the channel and the two-dimensional charge carrier gas. Exemplarily, the concentration of the two-dimensional charge carrier gas in this region is not less than 2E12 / cm 2 。

[0091] Further, the first region 1053 has a second surface opposite to the first surface of the substrate and a first surface facing away from the first surface 1001 of the substrate. The first region 1053 also has a third surface (such as a side plane) connecting the first and second surfaces of the first region. The third surface of the first region and the second surface of the first region form an angle C. The angle C can be between 30 and 90 degrees.

[0092] Optionally, the lateral growth direction of the first region is ,but it can be understood that this is only an exemplary description.

[0093] Furthermore, the threshold voltage of the device can be controlled by the doping element, doping concentration of the first region 1053, the setting of the distance between the first region 1053 and the second semiconductor layer 106, the width of the first region 1053, the gate electrode material, as well as the composition and thickness of the second semiconductor layer 106. Preferably, the doping concentration of the first region 1053 is about 1E+17 - 5E+19 / cm3, such as 1E+17 / cm3, 1E+18 / cm3, 1E+19 / cm3, 5E+19 / cm3. The third electrode material can be TiN, Ni, ITO, Au, etc. The length of the first region 1053 is about 0.01 - 10 microns, and the thickness is about 0.01 - 10 microns. The length of the first region (i.e., the length along the direction of charge carrier flow), exemplarily, can precisely control process parameters such as epitaxial time through lateral epitaxy to achieve very thin width control. Since the resistance of the depletion region is usually relatively high, reducing the width of this part can effectively reduce the on-state resistance of the device, and at the same time, it is also beneficial to reduce the size of the device and improve the area utilization rate of the wafer.

[0094] Attached Figure 4 is the energy band diagram of the semiconductor device. In the present disclosure, when the first region 1053 is disposed under the third electrode, the depletion layer of the semiconductor device is relatively narrow, and the depletion of two-dimensional carrier charges is fast, which can effectively achieve the controllability of the depletion of the two-dimensional electron gas corresponding to the third electrode (gate stack) in the semiconductor device; while when the first region is disposed deviating from the third electrode, it will deplete the two-dimensional electron gas outside the corresponding position of the third electrode (gate stack) and cannot be controlled by the third electrode, resulting in a significant increase in the on-state resistance of the semiconductor device or even inability to turn on.

[0095] Furthermore, a third semiconductor layer may also be provided between the first semiconductor layer 105 and the second semiconductor layer 106. Exemplarily, the third semiconductor layer may be an AlN layer, and the third semiconductor layer can reduce effects such as impurity scattering and improve the mobility of electrons in the channel.

[0096] Furthermore, a fourth and / or fifth semiconductor layer may also be provided between the first semiconductor layer and the substrate 100. Exemplarily, the fifth semiconductor layer may be a group III nitride buffer layer, and the fourth semiconductor layer 112 may be a nitride semiconductor layer, such as an AlN layer.

[0097] Furthermore, as Figure 5 the weakly P-type doped fourth region 1122 and the strongly P-type doped third region 1121 may be formed in the fourth semiconductor layer 112.

[0098] When the fourth semiconductor layer is provided, since the first semiconductor layer 105 contains an intrinsic semiconductor (eg, i-GaN) or an unintentionally doped semiconductor, ion scattering at the channel is greatly reduced, thereby improving device performance.

[0099] This semiconductor device structure avoids the problem of poor crystal quality and electrical performance of a P-GaN semiconductor layer, which can occur when a semiconductor layer, such as P-GaN, is grown on the first surface of the second semiconductor layer after the first insulating layer 105 is formed. This semiconductor device structure enables the production of a high-quality P-GaN semiconductor layer during or before channel formation. Furthermore, when no bias is applied to the gate electrode, the device is turned off, resulting in no current or only a very low gate leakage current, thus achieving a reliable normally-off device with low on-resistance when in the on state.

[0100] Second embodiment

[0101] See also Figure 6 Based on the first embodiment, a first insulating layer 101 can be formed between the substrate 100 and the first semiconductor layer 105, a groove can be formed in the insulating layer below the second electrode 108, and a seed layer 102 can be formed in the groove. The seed layer 102 helps form a nitride semiconductor layer with low roughness and low dislocation density. In addition, the seed layer below the second electrode 108 also helps the first semiconductor layer 105 or the fourth semiconductor layer 112 to grow symmetrically during lateral epitaxy, thereby improving the growth quality of the semiconductor layer and effectively utilizing the wafer area.

[0102] Third embodiment

[0103] See also Figure 7 On the basis of the second embodiment, the weakly P-type doped region of the first semiconductor layer may further have a buffer structure 10541, and the buffer structure 10541 helps to improve the crystal quality during area selection / lateral epitaxy.

[0104] Fourth Implementation Plan

[0105] See also Figure 8 On the basis of the second embodiment, the second weakly P-type doped region of the first semiconductor layer may further have a third region 10542 with strong P-type doping. The third strongly P-type doped region 10542 helps to improve the subsequent P-type ohmic contact quality and reduce the contact resistance. Exemplarily, the doping concentration of the third strongly P-type doped region 10542 can be set with reference to the doping concentration of the aforementioned first region.

[0106] Fifth Implementation Plan

[0107] See also Figure 9, based on the second embodiment, a buffer structure 10541 and a third region 10542 with strong P-type doping may also be provided in the second region with weak P-type doping of the first semiconductor layer. The buffer structure helps improve the crystal quality during selective / side epitaxy, and the third region with strong P-type doping helps improve the quality of subsequent P-type ohmic contact and reduce the contact resistance.

[0108] Sixth Embodiment

[0109] See Figure 10 , based on the second embodiment, a second insulating layer 110 may also be provided between the second semiconductor layer 106 and the second electrode 108. The second insulating layer 110 may be silicon nitride. The silicon nitride layer can effectively protect the surface of the second semiconductor layer, resulting in fewer interface defect states at the second semiconductor layer / second insulating layer interface. Moreover, the second insulating layer may cover the area except at the first and second electrodes, or may only be formed at the third electrode 109 (i.e., at the gate stack), and be used as the dielectric layer (gate dielectric layer) of the third electrode. The provision of the second insulating layer 110 at the third electrode 109 can further reduce the gate off-state leakage current of the third electrode 109 (gate). Meanwhile, the presence of the second insulating layer 110 can expand the voltage range of the third electrode 109 and enhance the reliability of the device. It can be understood that the insulating layer at the third electrode may also be other gate dielectric layers, such as silicon dioxide, Al2O3, etc.

[0110] Seventh Embodiment

[0111] See Figure 11 , based on the first embodiment, a fourth electrode 111 in contact with the weak P-type doping region may also be provided. The fourth electrode 111 is led out from either side of the weak P-type doping region. Exemplarily, it may be led out from the side of the weak P-type doping region; it may also be led out from the first surface of the weak P-type doping region facing away from the first surface of the substrate; or it may be led out from the second surface of the weak P-type doping region facing the first surface of the substrate. Thus, the potential of the fourth electrode 111 can be independently controlled, and then the weak P-type doping region can be electrically connected to the strong P-type doping region through the fourth electrode 111.

[0112] Eighth Embodiment

[0113] Now, a manufacturing method for manufacturing the semiconductor device of the first embodiment will be described exemplarily with reference to Figures 12 - 26 to be described.

[0114] Provide a substrate 100. For the selection of the substrate 100 material, refer to the description in the first embodiment, which will not be elaborated here.

[0115] The first semiconductor layer 105 (eg, intrinsic i-GaN or unintentionally doped GaN layer) is formed on the substrate 100. The growth method of the first semiconductor layer 105 is not particularly limited, and lateral epitaxial growth, hydride vapor phase epitaxy (HVPE), etc. can be used.

[0116] A second semiconductor layer 106 is deposited on the first semiconductor layer 105. Optionally, the second semiconductor layer 106 is an AlGaN, InAlGaN, InAlN layer, etc. It should be noted that before forming the second semiconductor layer 106, a third semiconductor layer may be deposited on the first semiconductor layer 105. This forms a two-dimensional charge carrier gas at the interface between the third semiconductor layer and the first semiconductor layer 105, or between the second semiconductor layer 106 and the first semiconductor layer 105.

[0117] A strongly P-type doped first region and a weakly P-type doped second region are formed in the first semiconductor layer 105 through a doping process. The doping process can be an ion implantation or diffusion process. The doping concentration of the strongly P-type doped first region is exemplarily in the range of 1E17 / cm3 to 5E19 / cm3. Exemplarily, the length of the strongly P-type doped first region 1053 along the two-dimensional carrier charge flow direction can be formed to be approximately 3.5 microns, and the thickness of the strongly P-type doped first region perpendicular to the two-dimensional carrier charge flow direction can be formed to be approximately 0.79 microns.

[0118] A second insulating layer is deposited and formed on the second semiconductor layer. Exemplarily, it can be a silicon nitride layer formed by MOCVD. The second insulating layer is used to protect the underlying structural layers during the annealing of subsequent ohmic contacts. The second insulating layer can have a thickness of several - several hundred nanometers, and the second insulating layer can be epitaxially grown in situ together with the structural layers of the semiconductor device. Or after other semiconductor layers are epitaxially grown before the growth of the second semiconductor layer and then removed from the epitaxial equipment for process treatment, the second insulating layer is epitaxially grown in situ together with the second semiconductor layer 106. The second insulating layer is etched to expose the portions of the second semiconductor layer or the first semiconductor layer corresponding to the respective electrodes. Exemplarily, through doping processes such as ion implantation, the first part of the N+ doped source / drain regions is formed at the corresponding positions. Then, the metal materials of the first and second electrodes are formed on the exposed second semiconductor layer / first semiconductor layer through processes such as sputtering and evaporation. Subsequently, etching and annealing are performed to form the second part of the ohmic contacts of the first and second electrodes (source / drain). The doping element of the first part and the metal element of the second part can be the same or different. It can be understood that the first part of the N+ doping can improve the ohmic contact performance, but the first part is not necessary and can be omitted during the preparation. Then, the third electrode 109 is formed at the corresponding third electrode position on the second semiconductor layer 106 through a conventional process, and the third electrode 109 can be in direct contact with the second semiconductor layer 106.

[0119] Further, the specific process of lateral epitaxy in step 200 is as follows: Step 210: The first insulating layer 101 is deposited and formed on the first surface of the substrate 100, and the first insulating layer 101 covers the entire surface of the substrate 100. At least a part of the first insulating layer 101 is removed. Preferably, at least a part of the first insulating layer 101 corresponding to the region where the second electrode 108 (source electrode) is subsequently formed is removed to form an opening to expose a part of the substrate 100. Then, a seed layer 102 is deposited and formed on the substrate at the opening of the insulating layer through a deposition process. The seed layer and the first insulating layer each have a second surface opposite to the first surface 1001 of the substrate 100 and a first surface facing away from the first surface of the substrate 100. The material of the first insulating layer 101 is not limited. The material of the seed layer can be selected as the material that can serve as the growth core of the first semiconductor layer 105.

[0120] Alternatively, in step 210', a seed material is deposited on the first surface of the substrate 100, and a portion of the seed material is removed by photolithography to expose the first surface of the substrate 100, thereby allowing the remaining seed layer to serve as the growth core for the first semiconductor layer 105. Preferably, the region of the retained seed layer corresponds to the region where the second electrode (source) region will be subsequently formed. An insulating material is then deposited on the first surface of the substrate 100, fully covering the substrate 100 and the seed layer. The material is then etched or planarized until the seed layer is exposed. The seed layer and the first insulating layer each have a second surface opposite the first surface of the substrate 100, and a first surface opposite the first surface of the substrate 100.

[0121] Step 220: Laterally epitaxially grow an unintentionally doped nitride semiconductor or an intrinsic nitride semiconductor on the first surface of the first insulating layer and / or the seed layer, centered around the seed layer, and control the growth rate to stop growth when the nitride semiconductor does not fully cover the first insulating layer and / or the seed layer, thereby forming a first portion of the first semiconductor layer. It is understood that in this step, the first semiconductor layer 105 can be fully doped by adjusting the doping concentration; or first strongly P-type doping can be performed followed by weak P-type doping; or an undoped structure can be first formed followed by weak P-type doping; or an undoped structure can be first formed followed by strong P-type doping and then weak P-type doping.

[0122] In step 230, a strongly P-type doped nitride layer is continuously grown on the surface and side surfaces of the first portion of the grown first semiconductor layer, with the first portion of the grown first semiconductor layer as the core. After the strongly P-type doped nitride semiconductor layer has grown to a certain thickness, a low-doped or undoped nitride semiconductor layer is continuously grown. The low-doped or undoped nitride semiconductor layer forms a partial connection region of the first semiconductor layer. Part of the partial connection region and the strongly P-type doped nitride semiconductor layer can be removed by methods such as CMP or etching to expose the weakly P-type nitride semiconductor doping layer, so that the formed first semiconductor layer 105 includes a strongly P-type doped region 1053 and the weakly P-type doped region 1054, or includes the strongly P-type doped region 1053 and the weakly P-type doped region 1054 embedded therein with a buffer layer 10541 and / or a strongly P-type doped region 10542. Preferably, the strongly P-type nitride semiconductor layer is formed only in the region directly adjacent to the orthogonal projection of the third electrode 109 to be formed subsequently. More specifically, the lateral growth direction of the strong / weak P-type doped nitride layer, such as P-GaN, is Crystal orientation, the growth plane can be vertical Surface. Exemplarily, the specific dimensions of the strong P-type doped nitride layer can be about 1 micron in length and about 2 microns in height. Taking the crystal orientation, its stable growth surface is inclined surface case, when the lateral growth direction is crystal orientation, its lateral growth rate is faster and the performance of the device is more excellent. The removing step can remove part of the connection region and the strong P-type region through an etching or planarization process to expose the weak P-type region. It can be understood that an extremely thin strong P-type layer can be retained on the weak P-type layer. After retaining the weak P-type region, the etching or planarization process can also be continued to further remove part of the connection region, the strong P-type region, and the weak P-type region.

[0123] It can be understood that the step 230 can be repeated several times to prepare the discrete strong P-type regions as described in the accompanying drawings.

[0124] Step 240: Using the structure formed in the above step 230 as a nucleation center, continue to grow the first semiconductor layer 105 until the first semiconductor layer 105 completely covers the first insulating layer 101 and / or the seed layer. The continuously grown first semiconductor layer can be weakly P-type doped, or the continuously grown first semiconductor layer can be an intrinsic nitride semiconductor layer or an unintentionally doped semiconductor layer, thereby completing the growth of the connection region. Exemplarily, an etching or planarization process can be used to make the first surfaces of the connection region, the strong P-type region, and the weak P-type region coplanar. Then, structural layers such as the second semiconductor layer 106 and the second insulating layer 110 are formed in sequence. It can be clear that during the growth of the strong P-type doped nitride region, the strong P-type doped region with unilateral or bilateral graded doping as described in Embodiment 1 can be realized by controlling the P-type doping concentration in the process. The specific form of P-type doping is not specifically limited here.

[0125] It can be understood that before step 500, a second insulating layer that completely covers the second semiconductor layer can also be formed in-situ on the second semiconductor layer. Exemplarily, the second insulating layer can be silicon nitride.

[0126] Ninth Embodiment

[0127] It can be understood that in step 120, on the first surfaces of the One insulating layer and the seed layer, it can also be as Figure 27The fourth semiconductor layer 112 is laterally epitaxially formed centering around the seed layer. Subsequently, the method of laterally epitaxially forming the fourth semiconductor layer 112 with a strong P-doped region 1121 and a weak P-doped region 1122 centering around the seed layer is the same as the method of forming the first semiconductor layer 105 with a strong P-doped region and a weak P-doped region described above, and will not be elaborated here. Then, other structures such as the first semiconductor layer 105, the second semiconductor layer 106, etc. are sequentially formed as described in Embodiment VIII. An exemplary structure including the fourth semiconductor layer is as Figure 27 shown.

[0128] Tenth Embodiment

[0129] Based on the eighth embodiment, a through hole reaching the weak P-type doped region is etched on the back surface of the substrate, electrode material is deposited in the hole, and the fourth electrode is etched and formed.

[0130] Alternatively, referring to Figure 28 , a through hole reaching the weak P-type doped region is etched on the surface of the passivation layer, electrode material is deposited in the hole, and the fourth electrode is etched and formed.

[0131] Eleventh Embodiment

[0132] A power supply device includes any one of the semiconductor devices in the above embodiments. The power supply device includes a primary circuit, a secondary circuit, a transformer, etc. Among them, both the primary circuit and the secondary circuit include switching elements, and any one of the semiconductor devices in the above embodiments is used as the switching element.

[0133] Twelfth Embodiment

[0134] A mobile phone includes any one of the semiconductor devices in the above embodiments. The mobile phone includes a display screen, a charging unit, etc. Among them, the charging unit includes any one of the semiconductor devices in the above embodiments.

[0135] Thirteenth Embodiment

[0136] An amplifier, the amplifier can be used as a power amplifier in fields such as mobile phone base stations, and the power amplifier can include any one of the semiconductor devices in the above embodiments.

[0137] The above describes the present disclosure content in combination with specific embodiments, but those skilled in the art should understand that these descriptions are exemplary and do not limit the protection scope of the present disclosure content. Those skilled in the art can make various variations and modifications based on the spirit and principle of the present disclosure content, and these variations and modifications are also within the scope of the present disclosure content.

Claims

1. A semiconductor device, comprising: A substrate; A first semiconductor layer on the first surface of the substrate; A second semiconductor layer on the first surface of the first semiconductor layer; Generating a two-dimensional charge carrier gas between the first semiconductor layer and the second semiconductor layer; A first electrode, a second electrode, and a third electrode on the second semiconductor layer; Wherein the first semiconductor layer further includes a first region with strong P-type doping and a second region with weak P-type doping; the first region is located below the third electrode, and the second region is located below the second electrode; Wherein the region of the first region projected onto the substrate is within the region of the third electrode projected onto the substrate.

2. The semiconductor device according to claim 1, wherein the substrate is sapphire, ZnO, SiC, AlN, GaAs, LiAlO, GaAlLiO, GaN, Al2O3, or single crystal silicon.

3. The semiconductor device according to claim 1 or 2, wherein the epitaxial direction of the first semiconductor layer parallel to the substrate is the [0001] direction.

4. The semiconductor device according to claim 1 or 2, wherein the second semiconductor layer is an AlN, AlGaN, InAlGaN, or InAlN layer.

5. The semiconductor device according to claim 1, wherein the first region depletes 95%-100% of the two-dimensional charge carrier gas at the overlap with the projected area of the third electrode.

6. The semiconductor device according to claim 1, wherein when the bias voltage of the third electrode is 0, the two-dimensional charge carrier gas corresponding to at least a partial region of the third electrode is less than 5E+11 / cm 2 .

7. The semiconductor device according to claim 1, wherein the two-dimensional charge carrier gas in the second region is not less than 2E+12 / cm 2 .

8. The semiconductor device according to claim 3, wherein the epitaxial direction parallel to the substrate of the first region in the first semiconductor layer is the [0001] direction, and its lateral epitaxial direction is .

9. The semiconductor device according to claim 1, wherein the doping concentration of the first region is 1E18 - 5E19 / cm 3 .

10. The semiconductor device according to claim 5, wherein the first region includes a single-layer structure or a plurality of discrete layer structures with a number greater than or equal to 2.

11. The semiconductor device according to claim 10, wherein the plurality of discrete layer structures are discrete layer structures in the direction perpendicular to the substrate or discrete layer structures in the direction parallel to the substrate.

12. The semiconductor device according to claim 11, wherein the discrete layer structures in the direction perpendicular to the substrate completely overlap in the orthographic projection; do not overlap in the orthographic projection; or partially overlap in the orthographic projection direction.

13. The semiconductor device according to claim 10, wherein the discrete layer structures are in close contact with each other, or there is a certain gap between the discrete layer structures.

14. The semiconductor device according to claim 13, wherein the gap is formed by a weakly P-type doped region.

15. The semiconductor device according to claim 1, wherein the first region is a layer structure with a gradually changing doping concentration.

16. The semiconductor device according to claim 15, wherein the doping concentration of the first region gradually changes from the center of the first region to both sides parallel to the substrate, or the doping concentration of the first region gradually changes from the center of the first region to both sides perpendicular to the substrate, or the doping concentration of the first region changes gradually on one side.

17. The semiconductor device according to claim 1, wherein the thickness range of the first region is greater than 0 and less than or equal to the thickness of the first semiconductor layer.

18. The semiconductor device according to claim 1, wherein the thickness range of the second region is greater than 0 and less than or equal to the thickness of the first semiconductor layer.

19. The semiconductor device according to claim 1, wherein the first semiconductor layer has a second surface opposite to the first surface of the substrate and a first surface facing away from the first surface of the substrate, the first region has a second surface opposite to the first surface of the first semiconductor layer, a first surface facing away from the first surface of the first semiconductor layer, and the first region further has a third surface connected to the first and second surfaces of the first region, and the third surface of the first region forms an angle greater than 30 degrees and less than or equal to 90 degrees with the second surface of the first region.

20. The semiconductor device according to claim 1, wherein the length range of the first region is 0.01 - 10 micrometers, and the thickness is 0.01 - 10 micrometers.

21. The semiconductor device according to claim 1, wherein the second region of the first semiconductor layer extends from the region overlapping with the projection region of the second electrode along the direction parallel to the movement of two-dimensional charge carriers towards both ends.

22. The semiconductor device according to claim 1, wherein the first region and the second region are connected to each other.

23. The semiconductor device according to claim 1, wherein the second region includes a buffer structure; or the second region includes a strongly P-type doped third region; or the second region includes a strongly P-type doped third region and the third region includes a buffer structure.

24. The semiconductor device according to claim 1, wherein there is also a third semiconductor layer between the first semiconductor layer and the second semiconductor layer.

25. The semiconductor device according to claim 1, wherein there is also a fourth semiconductor layer and / or a fifth semiconductor layer between the first semiconductor layer and the substrate.

26. The semiconductor device according to claim 25, wherein the fifth semiconductor layer is a group III nitride buffer layer, and the fourth semiconductor layer is a nitride semiconductor layer.

27. The semiconductor device according to claim 1, wherein the second electrode includes a metal in ohmic contact with the two-dimensional electron gas; or the second electrode includes a metal in ohmic contact with the two-dimensional electron gas and a doped region in ohmic contact with the second region; the metal element forming ohmic contact with the two-dimensional electron gas and the doped element forming ohmic contact with the second region of the second electrode are the same; or the metal element forming ohmic contact with the two-dimensional electron gas and the doped element forming ohmic contact with the second region of the second electrode are different.

28. The semiconductor device according to claim 1, further including a first insulating layer formed between the first semiconductor layer and the substrate, and a seed layer is provided in the first insulating layer, and the seed layer is located below the second electrode.

29. The semiconductor device according to claim 1, wherein there is also a second insulating layer between the second semiconductor layer and the third electrode.

30. The semiconductor device according to claim 29, wherein the second insulating layer is silicon dioxide, silicon nitride, and / or Al2O3.

31. The semiconductor device according to claim 1, wherein the second region has a fourth electrode connected thereto.

32. The semiconductor device as claimed in claim 31, wherein the substrate has a second surface opposite to its first surface, and a fourth electrode connected to the second region is formed at the second surface of the substrate; or the second region extends along a direction perpendicular to the flow of the two-dimensional charge carrier gas, and a fourth electrode connected to the second region is formed at a position not covered by the projection of the second electrode.

33. A method for manufacturing a semiconductor device, comprising: Step 100: Providing a substrate; Step 200: Forming a first semiconductor layer on the first surface of the substrate; Step 300: Forming a weakly P-type doped second region and a strongly P-type doped first region in the first semiconductor layer; Step 400: Forming a second semiconductor layer on the first surface of the first semiconductor layer; A two-dimensional charge carrier gas is generated between the first semiconductor layer and the second semiconductor layer; Step 500: Forming a first electrode and a second electrode having ohmic contact with the two-dimensional charge carrier gas, and forming a third electrode on one side of the first surface of the second semiconductor layer; wherein the first region is located below the third electrode, and the second region is located below the second electrode; The region of the first region projected onto the substrate is within the region of the third electrode projected onto the substrate.

34. The method as claimed in claim 33, wherein the method for forming the first and second regions is lateral epitaxy or ion implantation, and the first region is prepared as a discrete or gradually varying doping concentration structure.

35. The method as claimed in claim 33, further comprising forming a third semiconductor layer on the first semiconductor layer between step 300 and step 400.

36. The method as claimed in claim 33, in step 500, forming a sacrificial layer by depositing a sacrificial material on the second semiconductor layer, developing / etching the sacrificial layer to expose the portions of the second semiconductor layer corresponding to the first to third electrodes, forming a first portion of the N+-doped source / drain region at the corresponding positions by doping process, then forming the metal materials of the first and second electrodes on the exposed second semiconductor layer, and subsequently etching and annealing to form a second portion of the ohmic contact of the source / drain region.

37. The method as claimed in claim 33, in step 500, in-situ forming a second insulating layer on the second semiconductor layer by MOCVD method, etching the second insulating layer to expose the portions of the second semiconductor layer corresponding to the first to third electrodes, forming a first portion of the N+-doped source / drain region at the corresponding positions by doping process, then forming the metal materials of the first and second electrodes on the exposed second semiconductor layer, and subsequently etching and annealing to form a second portion of the ohmic contact of the source / drain region.

38. The method as claimed in claim 36 or 37, wherein the doping element of the first portion is the same as the metal element of the second portion, or the doping element of the first portion is different from the metal element of the second portion.

39. The method as claimed in claim 36 or 37, wherein the formation step of the first portion can be omitted.

40. The method according to claim 37, wherein a second insulating layer formed in situ on the second semiconductor layer is formed in situ together with other semiconductor layers; or the second insulating layer formed in situ on the second semiconductor layer is formed in situ only together with the second semiconductor layer.

41. The method according to claim 33, further comprising step 210: depositing and forming a first insulating layer on a first surface of a substrate, removing at least a part of the first insulating layer corresponding to a region where a second electrode is to be formed subsequently, forming an opening to expose a part of the substrate, and then depositing and forming a seed layer on the first insulating layer having the opening.

42. The method according to claim 33, further comprising step 210': depositing a seed material on a first surface of a substrate, retaining a part of the seed material to form a seed layer, and then depositing a first insulating layer on the first surface of the substrate, the first insulating layer completely covering the substrate and the seed layer, removing a part of the first insulating layer until the seed layer is exposed, and the seed layer corresponds to a region where a second electrode is to be formed subsequently.

43. The method according to claim 41 or 42, further comprising step 220: laterally epitaxially growing, on a first surface of the first insulating layer and the seed layer, a nitride semiconductor including an unintentionally doped nitride semiconductor or an intrinsic nitride semiconductor centered on the seed layer, and stopping the growth when the nitride semiconductor does not completely cover the first insulating layer by controlling its growth rate, to form a first part of the first semiconductor layer.

44. The method according to claim 43, wherein the first part is subjected to overall weak P-type doping; or the first part is first subjected to strong P-type doping and then weak P-type doping; or a structure of an unintentionally doped or intrinsic nitride semiconductor is first formed on the first part and then strong P-type doping is performed, and then weak P-type doping is performed.

45. The method according to claim 44, further comprising step 230: taking the first part of the grown first semiconductor layer as a core, and continuing to grow a strongly P-type doped nitride layer on its surface and side surfaces. After growing a strongly P-type doped nitride semiconductor layer with a certain thickness, a low-doped or undoped nitride semiconductor layer is further grown, and the low-doped or undoped nitride semiconductor layer forms a connection region of the first semiconductor layer. Then, by removing a part of the connection region and the strongly P-type doped nitride semiconductor layer, a weakly P-type nitride semiconductor doped layer is exposed. Step 230 is repeated multiple times. Among them, The strongly P-type doped nitride semiconductor layer is the first region of the strongly P-type doping; The weakly P-type nitride semiconductor doped layer is the second region of the weakly P-type doping.

46. The method according to claim 44, wherein the first region of strongly P-type doping is strongly P-GaN, the second region of weakly P-type doping is weakly P-GaN, and the lateral growth direction of the P-GaN is crystal orientation.

47. The method according to claim 45, further comprising step 240: continuing to grow a weakly doped, unintentionally doped or intrinsic nitride semiconductor layer with the structure obtained in step 230 as a core until the nitride semiconductor layer completely covers the first insulating layer and / or the seed layer.

48. The method according to claim 45, wherein the removing step further comprises: Remove a part of the connection region and the first region of the strongly P-type doping to expose the second region of the weakly P-type doping; Alternatively, remove a part of the connection region and the first region of the strongly P-type doping to leave an extremely thin strongly P-type doping layer on the second region of the weakly P-type doping; Alternatively, after removing a part of the connection region and the strongly P-type doping region to expose the second region of the weakly P-type doping, further remove a part of the connection region, the first region of the strongly P-type doping, and the second region of the weakly P-type doping.

49. The method according to claim 41 or 42, further comprising the step of: laterally epitaxially forming a fourth semiconductor layer centered on the seed crystal layer, the fourth semiconductor layer having a strongly P-doped region and a weakly P-doped region.

50. The method according to claim 33, further having step 600: forming a through hole at a position corresponding to the second region of the weakly P-type doping on the second surface of the substrate, the through hole reaching the second region of the weakly P-type doping, and forming a fourth electrode in the through hole, thereby controlling the potential of the first region of the strongly P-doped.

51. The method according to claim 33, further having step 600: growing along a direction perpendicular to the direction of two-dimensional carrier charge flow in the second region of the weakly P-type doping, forming a through hole by etching on one side of the second region of the weakly P-type doping not covered by the positive projection of the second electrode, and forming a fourth electrode connected to the second region of the weakly P-type doping in the through hole.

52. An electronic device, comprising a semiconductor device according to any one of claims 1-32.

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