Pixel circuit and display panel

Abstract

A pixel circuit and a display panel. Compared to connecting a gate of a compensation transistor (T3) to identical low potentials at different refresh frequencies, by connecting the gate of the compensation transistor (T3) to different low potentials at different refresh frequencies, the pixel circuit can reduce a difference between low potentials of a first gate drive signal (Nscan1) after crosstalk at different refresh frequencies, so as to reduce a difference between gate leakage currents of a drive transistor (T1) at different refresh frequencies, thereby mitigating flickering.

Description

Pixel circuit and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel circuit and a display panel. Background Art

[0002] Normally, a pixel circuit can provide corresponding brightness for a display panel. However, in the case of a variable refresh rate, the brightness difference of the pixel circuit at different refresh rates reaches a certain level, which will cause flickering, thereby affecting the visual effect. SUMMARY OF THE INVENTION

[0003] The present application provides a pixel circuit and a display panel to alleviate the technical problem of large brightness differences under different refresh frequencies.

[0004] In a first aspect, the present application provides a pixel circuit, which includes a driving transistor and a compensation transistor, wherein the first electrode of the driving transistor is connected to the first power line, and the second electrode of the driving transistor is connected to the second power line; the first electrode of the compensation transistor is connected to the gate of the driving transistor, and the second electrode of the compensation transistor is connected to the second electrode of the driving transistor, and the gate of the compensation transistor is connected to a first gate drive signal, and the first gate drive signal has different low potentials at different refresh frequencies.

[0005] In the second aspect, the present application further provides a pixel circuit, which includes a driving transistor and a compensation transistor, wherein the first electrode of the driving transistor is connected to the first power line, and the second electrode of the driving transistor is connected to the second power line; the first electrode of the compensation transistor is connected to the gate of the driving transistor, and the second electrode of the compensation transistor is connected to the second electrode of the driving transistor, and the gate of the compensation transistor is connected to the first gate drive signal; wherein, when the first gate drive signal has an alternating voltage in a frame, the first gate drive signal has a first low potential; when the first gate drive signal has a constant voltage in a frame, the first gate drive signal has a second low potential; the first low potential is different from the second low potential.

[0006] In a third aspect, the present application provides a display panel comprising the above-mentioned pixel circuit. Beneficial effects

[0007] The pixel circuit and display panel provided in the present application can reduce the difference between the low potentials of the first gate drive signal after crosstalk at different refresh frequencies by connecting the gate of the compensation transistor to different low potentials at different refresh frequencies, compared to connecting the gate of the compensation transistor to the same low potential at different refresh frequencies. This reduces the difference between the gate leakage currents of the driving transistor at different refresh frequencies, and further reduces the brightness difference at different refresh frequencies. This can improve the flicker phenomenon and enhance the visual effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG1 is a circuit schematic diagram of a pixel circuit in the related art.

[0009] FIG2 is a timing diagram of the pixel circuit shown in FIG1 at a high refresh rate.

[0010] FIG3 is a timing diagram of the pixel circuit shown in FIG1 at a low refresh frequency.

[0011] FIG4 is a schematic diagram showing the potential change of the first gate driving signal at different refresh frequencies.

[0012] FIG. 5 is a schematic diagram showing brightness changes corresponding to changes in the potential of the first gate driving signal at different refresh frequencies.

[0013] FIG6 is a schematic diagram of potential changes of the improved first gate driving signal provided in an embodiment of the present application.

[0014] FIG. 7 is a schematic diagram showing brightness changes corresponding to potential changes of the first gate driving signal in FIG. 6 . Modes for Carrying Out the Invention

[0015] To make the purpose, technical solutions and effects of this application clearer and more specific, the following further describes this application in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain this application and are not intended to limit this application.

[0016] Figure 1 is a schematic diagram of a pixel circuit in the related art. As shown in Figure 1, the pixel circuit includes a driving transistor T1, a writing transistor T2, a compensation transistor T3, a first emission control transistor T5, a second emission control transistor T6, a first initialization transistor T4, a second initialization transistor T7, a third initialization transistor T8, a bootstrap capacitor Cboost, a storage capacitor Cst, and at least one of a light-emitting device D1.

[0017] The first power line is connected to the first electrode of the first light-emitting control transistor T5 and one end of the storage capacitor Cst. The second electrode of the first light-emitting control transistor T5 is connected to the first electrode of the driving transistor T1, the first electrode of the writing transistor T2, and the first electrode of the third initialization transistor T8. The gate of the driving transistor T1 is connected to the other end of the storage capacitor Cst, the first electrode of the compensation transistor T3, the first electrode of the first initialization transistor T4, and one end of the bootstrap capacitor Cboost. The second electrode of the driving transistor T1 is connected to the second electrode of the compensation transistor T3 and the first electrode of the second light-emitting control transistor T6. The second electrode of the second light-emitting control transistor T6 is connected to the anode of the light-emitting device D1 and the first electrode of the second initialization transistor T7. The cathode of the light-emitting device D1 is connected to the second power line. The second electrode of the write transistor T2 is connected to the data line, the gate of the write transistor T2 is connected to the second gate drive line and the other end of the bootstrap capacitor Cboost, the second electrode of the third initialization transistor T8 is connected to the third initialization line, the gate of the third initialization transistor T8 is connected to the third gate drive line, the light emitting control line is connected to the gate of the first light emitting control transistor T5 and the gate of the second light emitting control transistor T6, the gate of the compensation transistor T3 is connected to the first gate drive line, the second electrode of the first initialization transistor T4 is connected to the first initialization line, the gate of the first initialization transistor T4 is connected to the fourth gate drive line, the second electrode of the second initialization transistor T7 is connected to the second initialization line, and the gate of the second initialization transistor T7 is connected to the third gate drive line.

[0018] The light emitting device D1 may be an organic light emitting diode, a mini light emitting diode, a micro light emitting diode or a quantum dot light emitting diode.

[0019] Among them, each of the above transistors can be an N-channel transistor or a P-channel transistor.

[0020] The first electrode may be one of the source and the drain, and the second electrode may be the other of the source and the drain. For example, if the first electrode is the source, the second electrode may be the drain; or if the first electrode is the drain, the second electrode may be the source.

[0021] The first electrode of the driving transistor T1 is the first node A. The second electrode of the driving transistor T1 is the second node B. The anode of the light emitting device D1 is the third node C. The gate of the driving transistor T1 is the fourth node Q.

[0022] The first power line is used to transmit a positive power signal VDD, and the second power line is used to transmit a negative power signal VSS. The potential of the positive power signal VDD is greater than the potential of the negative power signal VSS. The data line is used to transmit a data signal DS. The light control line is used to transmit a light control signal EM. The first initialization line is used to transmit a first initialization signal Vi_G. The second initialization line is used to transmit a second initialization signal Vi_Ano. The third initialization line is used to transmit a third initialization signal Vi3. The first gate drive line is used to transmit a first gate drive signal Nscan1. The second gate drive line is used to transmit a second gate drive signal Pscan1. The third gate drive line is used to transmit a third gate drive signal Pscan2. The fourth gate drive line is used to transmit a fourth gate drive signal Nscan2.

[0023] FIG2 is a timing diagram of the pixel circuit shown in FIG1 at a high refresh rate. FIG3 is a timing diagram of the pixel circuit shown in FIG1 at a low refresh rate. The following description is made using an example in which the compensation transistor T3 and the first initialization transistor T4 are both N-channel transistors and the other transistors are all P-channel transistors:

[0024] When the pixel circuit operates at the highest refresh frequency, each frame is a write frame as shown in Figure 2; when the pixel circuit operates at a non-highest refresh frequency, it operates according to a continuous write frame as shown in Figure 2 and at least one hold frame as shown in Figure 3. For example, when the highest refresh frequency is 120Hz, the pixel circuit operates according to the write frame as shown in Figure 2 for each frame at a refresh frequency of 120Hz. When the pixel circuit operates at 60Hz, it operates alternately according to a write frame as shown in Figure 2 and a hold frame as shown in Figure 3. When the pixel circuit operates at 30Hz, it operates alternately according to a write frame as shown in Figure 2 and three hold frames as shown in Figure 3. The same applies to other refresh frequencies.

[0025] The writing frame shown in FIG2 includes the following stages:

[0026] First stage M1: the first gate drive signal Nscan1 and the third gate drive signal Pscan2 both output corresponding pulses. In this case, the compensation transistor T3, the second initialization transistor T7 and the third initialization transistor T8 are all turned on to reset the potential of the first node A, the potential of the second node B, the potential of the third node C and the potential of the fourth node Q.

[0027] Second stage M2: the fourth gate drive signal Nscan2 outputs a corresponding pulse, and the first initialization transistor T4 is turned on; the potential of the first gate drive signal Nscan1 jumps from a low potential to a high potential, and the compensation transistor T3 is first turned off and then turned on; the fourth node Q is reset again, and the data signal DS is written to the fourth node Q in the subsequent third stage M3.

[0028] Phase 3 M3 : the second gate driving signal Pscan1 outputs a corresponding pulse, the write transistor T2 is turned on, and the data signal DS is written to the fourth node Q via the write transistor T2 , the drive transistor T1 , and the compensation transistor T3 .

[0029] The fourth stage M4: the third gate driving signal Pscan2 outputs a corresponding pulse, and the second initialization transistor T7 and the third initialization transistor T8 are both turned on to drive the first electrode of the transistor T1 and the anode of the light emitting device D1.

[0030] Phase 5 M5: The driving transistor T1 is turned on, and the other transistors are turned off. To achieve low brightness (e.g., 10 nits), the lighting duration of phase 6 M6 needs to be reduced. The total duration from phases 1 M1 to 6 M6 is a fixed frame time, and the total duration from phases 1 M1 to 4 M4 is also fixed. Therefore, the duration of phase 5 M5 varies with the duration of phase 6 M6.

[0031] The sixth stage M6: the light emitting control signal EM switches from a high potential to a low potential, the first light emitting control transistor T5 and the second light emitting control transistor T6 are both turned on, the light emitting current flows through the light emitting device D1, and the light emitting device D1 starts to emit light.

[0032] The hold frame shown in FIG3 includes the following stages:

[0033] First stage M1′: the third gate driving signal Pscan2 outputs corresponding pulses. In this case, the second initialization transistor T7 and the third initialization transistor T8 are both turned on to reset the potentials of the first node A, the second node B, and the third node C.

[0034] Second stage M2 ′: the compensation transistor T3 , each initialization transistor, each light emitting control transistor and the writing transistor T2 are all turned off.

[0035] The third stage M3 ′: the compensation transistor T3 , each initialization transistor, each light-emitting control transistor and the writing transistor T2 are all turned off, and the data signal DS is not written.

[0036] The fourth stage M4 ′: is the same as the first stage M1 ′, and is performed on the first electrode of the driving transistor T1 and the anode of the light emitting device D1 .

[0037] Stage 5 M5': Same as Stage 5 M5.

[0038] The sixth stage M6 ′: the light emitting control signal EM switches from a high potential to a low potential, the first light emitting control transistor T5 and the second light emitting control transistor T6 are both turned on, the light emitting current flows through the light emitting device D1 , and the light emitting device D1 starts to emit light.

[0039] A comparison of Figures 2 and 3 shows that the first gate drive signal Nscan1 has alternating high and low potentials in the write frame, while remaining at a low potential in the hold frame. The gate drive circuit or shift register in the GOA circuit that generates the first gate drive signal Nscan1 is stage-by-stage, and crosstalk occurs between the first gate drive signals Nscan1 generated by different shift registers. Therefore, the first gate drive signal Nscan1 experiences different levels of crosstalk in the write frame and the hold frame, resulting in different degrees of positive and negative deflection of the low potential of the first gate drive signal Nscan1 due to crosstalk in the write frame and the hold frame.

[0040] As shown in Figure 4, NVGL represents the low potential of the first gate drive signal Nscan1. F represents the refresh frequency; F1 represents the high refresh frequency, taking 120Hz as an example; F2 represents the low refresh frequency, taking 1Hz as an example. When the low potential of the first gate drive signal Nscan1 is set to V0, the low potential of the first gate drive signal Nscan1 at the high refresh frequency is raised from V0 to V1, and the low potential of the first gate drive signal Nscan1 at the low refresh frequency is raised from V0 to V2. V1 is greater than V2, and V2 is greater than V0.

[0041] The low potential of the first gate driving signal Nscan1 affects the leakage current of the gate of the driving transistor T1 when the compensation transistor T3 is turned off, thereby affecting the luminous current flowing through the light emitting device D1 and thus affecting the luminous brightness.

[0042] As shown in Figure 5, Lum represents brightness, Lum1 represents brightness at a high refresh rate, and Lum2 represents brightness at a low refresh rate. F represents refresh rate; F1 represents a high refresh rate, 120Hz for example; F2 represents a low refresh rate, 1Hz for example. Since V1 is greater than V2 in Figure 4, for the N-channel compensation transistor T3, the gate potential (V1) of the compensation transistor T3 at a high refresh rate is higher than the gate potential (V2) of the compensation transistor T3 at a low refresh rate. This causes the gate leakage current of the driving transistor T1 at a high refresh rate to be greater than the gate leakage current of the driving transistor T1 at a low refresh rate, resulting in Lum1 being less than Lum2. This brightness difference can cause the screen to flicker when switching between high and low refresh rates, affecting the subjective visual effect.

[0043] This embodiment provides a pixel circuit, please refer to Figures 1, 6 and 7, the pixel circuit includes a driving transistor T1 and a compensation transistor T3, the first electrode of the driving transistor T1 is connected to the first power line, and the second electrode of the driving transistor T1 is connected to the second power line; the first electrode of the compensation transistor T3 is connected to the gate of the driving transistor T1, the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1, and the gate of the compensation transistor T3 is connected to the first gate drive signal Nscan1, and the first gate drive signal Nscan1 has different low potentials at different refresh frequencies.

[0044] It can be understood that the pixel circuit and display panel provided in this embodiment, by connecting the gate of the compensation transistor T3 to different low potentials at different refresh frequencies, can reduce the difference between the low potentials of the first gate drive signal Nscan1 after crosstalk at different refresh frequencies, compared to connecting the gate of the compensation transistor T3 to the same low potential at different refresh frequencies, thereby reducing the difference between the gate leakage currents of the driving transistor T1 at different refresh frequencies, and further reducing the brightness difference at different refresh frequencies. This can improve the flicker phenomenon and enhance the visual effect.

[0045] In one embodiment, when the first gate drive signal Nscan1 has an alternating voltage in a frame, it indicates that the pixel circuit operates in a write frame. In this case, the first gate drive signal Nscan1 has a first low potential. When the first gate drive signal Nscan1 has a constant voltage in a frame, it indicates that the pixel circuit operates in a hold frame. In this case, the first gate drive signal Nscan1 has a second low potential. The first low potential is different from the second low potential.

[0046] It should be noted that the pixel circuit operating in the write frame indicates that the pixel circuit operates at a high refresh rate, and the pixel circuit operating in the hold frame indicates that the pixel circuit operates at a low refresh rate. In this case, this embodiment can also reduce the difference between the low potentials of the first gate drive signal Nscan1 after crosstalk at different refresh rates, thereby reducing the difference between the gate leakage current of the driving transistor T1 at different refresh rates, and further reducing the brightness difference at different refresh rates, which can improve flicker and enhance visual effects.

[0047] In one embodiment, the first gate driving signal Nscan1 has a first low potential at a first refresh frequency and a second low potential at a second refresh frequency. The first refresh frequency is N times the second refresh frequency, where N is an integer greater than or equal to 2.

[0048] It should be noted that the first refresh frequency can be the high refresh frequency described above, and the second refresh frequency can be the low refresh frequency described above. This embodiment differentially configures the low potentials of the first gate drive signal Nscan1 at the first and second refresh frequencies, so that the low potentials of the first gate drive signal Nscan1 at the first and second refresh frequencies are closer after varying degrees of crosstalk, thereby minimizing the brightness difference at different refresh frequencies and improving the flickering phenomenon caused by switching between high and low refresh frequencies.

[0049] In one embodiment, when the first low potential is the initial low potential (V0), the second low potential is changed to the sum of the initial low potential and the compensation potential (ΔV).

[0050] It should be noted that, as shown in Figure 6, when the first low potential is the initial low potential, the first low potential is raised to V1 after crosstalk coupling. In order to make the first low potential after crosstalk coupling closer to the second low potential after crosstalk coupling, a compensation potential can be superimposed on the basis of the second low potential being raised from the initial low potential to V2 after crosstalk coupling. That is to say, superimposing a compensation potential on the basis of the initial low potential can increase the second low potential after crosstalk coupling, so that the first low potential after crosstalk coupling is closer to the second low potential after crosstalk coupling.

[0051] As shown in Figures 6 and 7, the second low potential after crosstalk coupling increases by ΔV on the basis of V2. Since the low potential of the first gate drive signal Nscan1 varies inversely with the brightness of the pixel circuit, in other words, the compensation potential also varies inversely with the brightness of the pixel circuit. Therefore, the brightness at the low refresh rate (F2) is reduced by ΔLum on the basis of the original brightness (Lum2). This reduces the brightness difference between the high refresh rate (F1) and the low refresh rate (F2), thereby improving the flicker phenomenon.

[0052] Among them, △Lum and △V satisfy the following relationship 1-1:

[0053] △Lum=-k△V (1-1)

[0054] The size of k is related to the screen brightness and refresh rate at this time. For example, in one of the products, △V=0.1V, the screen brightness is 600nit, and the refresh rate is 10Hz, and the △Lum is -2.6nit; the screen brightness is 110nit and the refresh rate is 10Hz, and the △Lum is -1.6nit.

[0055] In one embodiment, the compensation potential is greater than or equal to -1V and less than or equal to 1V.

[0056] It should be noted that when △V is too small, it may lead to insufficient brightness compensation, and flickering may still be visible when switching the frequency (switching the refresh rate); when △V is too large, overcompensation may occur, resulting in the inversion of brightness differences under different refresh rates, and flickering may still occur when switching the frequency.

[0057] In one embodiment, when the second low potential is the initial low potential, the first low potential is lowered.

[0058] It can be understood that in order to make the first low potential after crosstalk coupling closer to the second low potential after crosstalk coupling, this can be achieved by adjusting at least one of the first low potential and the second low potential. This embodiment improves the flickering phenomenon under different refresh frequencies by lowering the first low potential when the second low potential is the initial low potential.

[0059] In one embodiment, this embodiment provides a display panel, which includes the above-mentioned pixel circuit.

[0060] It can be understood that since the display panel provided by this embodiment includes the above-mentioned pixel circuit, it can also compensate for the gate of the transistor T3 being connected to different low potentials at different refresh frequencies. Compared with the case where the gate of the transistor T3 is connected to the same low potential at different refresh frequencies, the difference between the low potentials of the first gate drive signal Nscan1 after crosstalk at different refresh frequencies can be reduced, thereby reducing the difference between the gate leakage currents of the driving transistor T1 at different refresh frequencies, and further reducing the brightness difference at different refresh frequencies. This can improve the flicker phenomenon and enhance the visual effect.

[0061] It is understandable that those skilled in the art can make equivalent substitutions or changes based on the technical solution and inventive concept of this application, and all these changes or substitutions should fall within the scope of protection of the claims attached to this application.

Claims

1. A pixel circuit, wherein: The pixel circuit comprises: a driving transistor, wherein a first electrode of the driving transistor is connected to the first power line, and a second electrode of the driving transistor is connected to the second power line; A compensation transistor, wherein a first electrode of the compensation transistor is connected to the gate of the driving transistor, a second electrode of the compensation transistor is connected to the second electrode of the driving transistor, and the gate of the compensation transistor is connected to a first gate drive signal, wherein the first gate drive signal has different low potentials at different refresh frequencies.

2. The pixel circuit according to claim 1, wherein: The first gate driving signal has a first low potential at a first refresh frequency and a second low potential at a second refresh frequency. The first refresh frequency is N times the second refresh frequency, where N is an integer greater than or equal to 2.

3. The pixel circuit according to claim 2, wherein: In a case where the first low potential is an initial low potential, the second low potential is changed to the sum of the initial low potential and a compensation potential.

4. The pixel circuit according to claim 3, wherein: The compensation potential changes inversely with the brightness of the pixel circuit.

5. The pixel circuit according to claim 4, wherein: The compensation potential is greater than or equal to -1V and less than or equal to 1V. The pixel circuit according to claim 2 , wherein: When the second low potential is the initial low potential, the first low potential is lowered.

7. A pixel circuit, wherein: The pixel circuit comprises: a driving transistor, wherein a first electrode of the driving transistor is connected to the first power line, and a second electrode of the driving transistor is connected to the second power line; a compensation transistor, wherein a first electrode of the compensation transistor is connected to the gate of the driving transistor, a second electrode of the compensation transistor is connected to the second electrode of the driving transistor, and the gate of the compensation transistor is connected to a first gate drive signal; Among them, when the first gate drive signal has an alternating voltage in a frame, the first gate drive signal has a first low potential; when the first gate drive signal has a constant voltage in a frame, the first gate drive signal has a second low potential; the first low potential is different from the second low potential.

8. The pixel circuit according to claim 7, wherein: In a case where the first low potential is an initial low potential, the second low potential is changed to the sum of the initial low potential and a compensation potential.

9. The pixel circuit according to claim 7, wherein: When the second low potential is the initial low potential, the first low potential is lowered.

10. A display panel, wherein: The display panel includes a pixel circuit, and the pixel circuit includes: a driving transistor, wherein a first electrode of the driving transistor is connected to the first power line, and a second electrode of the driving transistor is connected to the second power line; A compensation transistor, wherein a first electrode of the compensation transistor is connected to the gate of the driving transistor, a second electrode of the compensation transistor is connected to the second electrode of the driving transistor, and the gate of the compensation transistor is connected to a first gate drive signal, wherein the first gate drive signal has different low potentials at different refresh frequencies.

11. The display panel according to claim 10, wherein: The first gate driving signal has a first low potential at a first refresh frequency and a second low potential at a second refresh frequency. The first refresh frequency is N times the second refresh frequency, where N is an integer greater than or equal to 2.

12. The display panel according to claim 11, wherein: In a case where the first low potential is an initial low potential, the second low potential is changed to the sum of the initial low potential and a compensation potential.

13. The display panel according to claim 12, wherein: The compensation potential changes inversely with the brightness of the pixel circuit.

14. The display panel according to claim 13, wherein: The compensation potential is greater than or equal to -1V and less than or equal to 1V.

15. The display panel according to claim 11, wherein When the second low potential is the initial low potential, the first low potential is lowered.

16. The display panel according to claim 10, wherein: When the first gate drive signal has an alternating voltage in a frame, the first gate drive signal has a first low potential; when the first gate drive signal has a constant voltage in a frame, the first gate drive signal has a second low potential; the first low potential is different from the second low potential.

17. The display panel according to claim 16, wherein: In a case where the first low potential is an initial low potential, the second low potential is changed to the sum of the initial low potential and a compensation potential.

18. The display panel according to claim 16, wherein: When the second low potential is the initial low potential, the first low potential is lowered.

19. The display panel according to any one of claims 10 to 18, wherein: The pixel circuit further includes: a first light-emitting control transistor, wherein a first electrode of the first light-emitting control transistor is connected to the first power line, a second electrode of the first light-emitting control transistor is connected to the first electrode of the driving transistor, and a gate of the first light-emitting control transistor is connected to a light-emitting control line; a second light emitting control transistor, wherein a first electrode of the second light emitting control transistor is connected to the second electrode of the driving transistor and the second electrode of the compensation transistor, and a gate of the second light emitting control transistor is connected to the light emitting control line; A light emitting device, wherein an anode of the light emitting device is connected to the second electrode of the second light emitting control transistor, and a cathode of the light emitting device is connected to the second power line.

20. The display panel according to claim 19, wherein The pixel circuit further includes: a write transistor, wherein a first electrode of the write transistor is connected to the first electrode of the drive transistor, a second electrode of the write transistor is connected to the data line, and a gate of the write transistor is connected to the second gate drive line; A storage capacitor, one end of which is connected to the first power line, and the other end of which is connected to the gate of the driving transistor and the first electrode of the compensation transistor.

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