An enhanced gallium nitride device based on dual-gate and dielectric layer regulation and its manufacturing method

Abstract

The application relates to an enhanced gallium nitride device based on double-gate and dielectric layer regulation and a manufacturing method thereof, and belongs to the technical field of semiconductor devices. The device comprises, from bottom to top, a substrate, a GaN buffer layer, a GaN channel layer, an AlN interlayer, an AlGaN barrier layer and a P-GaN cap layer. A dielectric layer is arranged on the upper side of the P-GaN cap layer and the AlGaN barrier layer on both sides of the P-GaN cap layer. A source metal and a drain metal are arranged on both sides of the dielectric layer respectively, and the source metal and the drain metal extend to the GaN buffer layer at the bottom. A gate metal is arranged on the dielectric layer above the P-GaN cap layer and the dielectric layer above the source metal on one side. The application effectively improves the breakdown voltage and the gate withstand voltage level, significantly reduces the gate leakage current, and realizes optimization of the overall device performance and improvement of reliability.

Description

Technical Field

[0001] The present invention relates to an enhanced gallium nitride device based on dual-gate and dielectric layer regulation and a manufacturing method thereof, belonging to the technical field of semiconductor devices. Background Art

[0002] As the performance of Si-based materials approaches theoretical limits, third-generation semiconductor materials, represented by GaN, are becoming the mainstream in semiconductor device development. GaN's exceptional electrical properties, including a wide bandgap, high electron mobility, high saturation velocity, and high breakdown electric field, demonstrate significant potential for application in demanding operating environments such as high frequency, high power, and high temperature. This has led to widespread interest and application of GaN devices in power electronics, microwave radio frequency, and 5G communications.

[0003] However, conventional enhancement-mode GaN HEMT devices still face several key technical challenges: First, the low and unstable threshold voltage can easily cause false triggering, placing higher demands on the drive circuit and potentially accelerating device aging. Second, the low breakdown voltage limits device reliability in high-power applications. Furthermore, existing devices commonly suffer from issues such as insufficient gate withstand voltage and high leakage current. While methods exist to improve threshold and breakdown performance, such as thickening the P-GaN layer, nitriding, extending the drift region length, introducing field plates, or adjusting the AlGaN composition, these improvements are often accompanied by negative effects such as increased process complexity, increased on-resistance, or decreased electron mobility, and can easily lead to gate leakage and parasitic effects. To address this issue, the present invention is proposed. Summary of the Invention

[0004] In response to the shortcomings of the existing technology, the present invention provides an enhancement-mode gallium nitride device based on dual-gate and dielectric layer regulation. By introducing a dual-gate design in the P-GaN region and combining it with the application of a high-k dielectric layer, an additional longitudinal depletion region is formed inside the device on the basis of the original lateral depletion region, thereby increasing "potential barriers" in both the lateral and vertical directions, thereby significantly improving the threshold voltage and current regulation capabilities. At the same time, the design also effectively improves the breakdown voltage and gate withstand voltage level, and significantly reduces the gate leakage current, thereby optimizing the overall device performance and improving reliability.

[0005] The present invention also provides a method for manufacturing the enhanced gallium nitride device based on dual-gate and dielectric layer regulation.

[0006] The technical solutions of the present invention are as follows:

[0007] An enhancement-mode gallium nitride device based on dual-gate and dielectric layer regulation comprises, from bottom to top, a substrate, a GaN buffer layer, a GaN channel layer, an AlN intercalation layer, an AlGaN barrier layer, and a P-GaN cap layer. A dielectric layer is provided on the upper side of the P-GaN cap layer and on the AlGaN barrier layers on both sides of the P-GaN cap layer. A source metal and a drain metal are provided on both sides of the dielectric layer, respectively. The bottoms of the source metal and the drain metal extend to the GaN buffer layer. A gate metal is provided on the dielectric layer near the source metal side and on the dielectric layer above the P-GaN cap layer.

[0008] Preferably, according to the present invention, the gate metal width is smaller than the width of the P-GaN cap layer, the gate metal on the dielectric layer on the upper side of the P-GaN cap layer is close to the drain metal, the dielectric layer on the upper side of the P-GaN cap layer has the same width as the gate metal and does not completely cover the p-GaN cap layer, which can reduce the interface state defects introduced by the dielectric layer and alleviate the increase in gate capacitance caused by the introduction of the dielectric layer.

[0009] Preferably, according to the present invention, the distance between the gate metal and the source metal on the side close to the source metal is 3μm, the distance between the gate metal and the drain metal on the side close to the drain metal is 12μm, the horizontal spacing between the two gate metals is 1μm, and the two gate metal structures have the same size, a gate length of 2μm, and a gate width of 100μm. The gate length is the length from the left end to the right end of the gate metal, and the gate width is the extension width of the gate into the paper.

[0010] According to the present invention, preferably, the substrate material is silicon carbide, silicon or sapphire;

[0011] The material of the dielectric layer is Al2O3 or HfO2, and the thickness of the dielectric layer is 1-100nm;

[0012] The thickness of the GaN buffer layer is 0.1-50 μm;

[0013] The thickness of the GaN channel layer is 5-1000nm;

[0014] The thickness of the AlN intercalation layer is 0.2-2 nm;

[0015] The thickness of the AlGaN barrier layer is 5-50 nm, and the molar ratio of Al is 5-35%;

[0016] The thickness of the p-GaN cap layer is 1-1000 nm, and the doping concentration of the p-GaN cap layer is 1×10 17 -1×10 20 cm -3 , the doping source is magnesium or boron;

[0017] The source metal and drain metal materials are the same, which are Ti / Al / Ni / Au metal stack, Ti / Al / Ti / Au metal stack or Ti / Al / Mo / Au metal stack;

[0018] The gate metal material is Ni / Au metal stack.

[0019] According to the present invention, it is further preferred that the substrate material is silicon carbide;

[0020] The material of the dielectric layer is Al2O3;

[0021] The thickness of the GaN buffer layer is 2 μm;

[0022] The thickness of the GaN channel layer is 200nm;

[0023] The thickness of the AlN intercalation layer is 0.5 nm;

[0024] The thickness of the AlGaN barrier layer is 12.5 nm, and the molar ratio of Al is 18%;

[0025] The thickness of the p-GaN cap layer is 100 nm, and the doping concentration of the p-GaN cap layer is 3×10 19 cm -3 ;

[0026] The thickness of the dielectric layer is 10 nm;

[0027] The source metal and drain metal materials are Ti / Al / Ni / Au metal stacks.

[0028] The manufacturing method of the enhancement-mode gallium nitride device based on dual-gate and dielectric layer control comprises the following steps:

[0029] S1, sequentially growing a GaN buffer layer, a GaN channel layer, an AlN intercalation layer, an AlGaN barrier layer, and a p-GaN cap layer on a substrate;

[0030] S2, dry etching away the excess p-GaN cap layer;

[0031] S3, removing the GaN channel layer, AlN intercalation layer, and AlGaN barrier layer outside the device by dry etching to form a mesa;

[0032] S4, evaporating source metal and drain metal on the table;

[0033] S5, annealing the drain metal and source metal regions to form ohmic contacts;

[0034] S6. depositing a dielectric layer on the AlGaN barrier layer and the p-GaN cap layer;

[0035] S7, evaporating gate metal on the dielectric layer near the drain metal and the dielectric layer above the p-GaN cap layer near the source metal;

[0036] S8, removing the excess dielectric layer by dry etching.

[0037] According to the application, preferably, in step S1, the growth method of the GaN buffer layer, the GaN channel layer, the AlN interlayer, the AlGaN barrier layer and the p-GaN cap layer is a high-quality film forming method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0038] In steps S2, S3 and S8, the etching method is inductively coupled plasma etching (ICP) or reactive ion etching (RIE).

[0039] According to the application, further preferably, in step S1, the growth method is metal organic chemical vapor deposition.

[0040] In steps S2, S3 and S8, the etching method is inductively coupled plasma etching.

[0041] According to the application, preferably, in step S5, the annealing method of the source metal and the drain metal is laser selective annealing.

[0042] The application has the following advantages:

[0043] 1. Threshold voltage improvement: The application forms a wider longitudinal depletion region in the P-GaN area by adopting a double-gate design, significantly improves the threshold voltage, and greatly enhances the opening control ability and anti-mis-triggering performance of the device.

[0044] 2. Wide-range threshold voltage regulation: By adjusting the double-gate spacing and the dielectric layer thickness, the application can accurately control the depletion region in both the vertical and horizontal directions. This regulation ability is unmatched by traditional single-gate structures and can meet the demand for precise regulation of threshold voltage in different application scenarios.

[0045] 3. Breakdown voltage improvement: The application adopts a double-gate dielectric structure, which exhibits higher breakdown voltage under high-voltage working conditions, thereby greatly enhancing the stability and reliability of the device in high-voltage applications.

[0046] 4. Increase the gate voltage resistance: The synergistic effect of the double-gate design and the high dielectric constant dielectric layer of the application makes the electric field distribution in the gate region more uniform, effectively improving the gate voltage resistance level, and ensuring that the device operates more stably and reliably in a high-voltage environment.

[0047] 5. Significantly reduce the leakage current: The present application effectively suppresses unnecessary channel carrier diffusion and short channel effect through the regulation of double gate and dielectric layer, significantly reduces the leakage current, makes the device still maintain low leakage state under high temperature or large bias, thereby improves the overall energy efficiency and stability.

[0048] 6. Improve current regulation and conduction performance: The double gate structure of the present application not only improves the electric field distribution, but also alleviates the problem of electron mobility reduction caused by the dielectric layer, reduces the on-resistance, and further improves the conduction capability of the device, which is suitable for high-efficiency power switch applications.

[0049] 7. Enhanced surge resistance: The balanced electric field distribution and all-around depletion region control of the present application reduce the risk of local high field damage to the material, thereby significantly improving the surge resistance of the device and ensuring the reliability in long-term operation.

[0050] 8. Prolong the service life of the device: The introduction of the double gate dielectric structure of the present application reduces the degradation and damage of the device in long-term operation, prolongs the service life of the device.

[0051] 9. Expand the application range: The GaN HEMT device of the present application improves the threshold voltage, breakdown voltage and gate withstand voltage, while reducing the gate leakage current, which can be widely used in high-power fields such as radio frequency communication, radar system, satellite communication, power electronics, etc. BRIEF DESCRIPTION OF DRAWINGS

[0052] Figure 1 is a structural diagram of the present application;

[0053] Figure 2 is a structural diagram of a conventional device;

[0054] Figure 3 is a comparison diagram of transfer curves of the present application and conventional devices;

[0055] Figure 4 is a comparison diagram of breakdown curves of the present application and conventional devices;

[0056] Figure 5 is a comparison diagram of gate withstand voltage and leakage current of the present application and conventional devices;

[0057] Wherein: 1, substrate; 2, GaN buffer layer; 3, GaN channel layer; 4, AlN interlayer; 5, AlGaN barrier layer; 6, P-GaN cap layer; 7, dielectric layer; 8, source metal; 9, drain metal; 10, gate metal. DETAILED DESCRIPTION

[0058] The present application will be further described below by way of examples and in conjunction with the accompanying drawings, but is not limited thereto.

[0059] Example 1:

[0060] like Figure 1 As shown, this embodiment provides an enhancement-mode gallium nitride device based on dual-gate and dielectric layer regulation, which includes, from bottom to top, a substrate 1, a GaN buffer layer 2, a GaN channel layer 3, an AlN intercalation layer 4, an AlGaN barrier layer 5 and a P-GaN cap layer 6. A dielectric layer 7 is provided on the upper side of the P-GaN cap layer 6 and on the AlGaN barrier layer 5 on both sides of the P-GaN cap layer. A source metal 8 and a drain metal 9 are provided on both sides of the dielectric layer 7, respectively. The bottoms of the source metal 8 and the drain metal 9 extend to the GaN buffer layer 2. A gate metal 10 is provided on the dielectric layer 7 near the side of the source metal 8 and on the dielectric layer 7 above the P-GaN cap layer 6.

[0061] In this embodiment, a second gate metal 10 is introduced on the left side of the P-GaN cap layer 6. The introduction of the side gate not only compensates for the control capability of the side gate metal 10 on the shortened P-GaN cap layer 6, but also introduces a vertical depletion region. The depletion region of all HEMT devices is a lateral depletion region, while the vertical depletion region introduced by the side gate in this embodiment in the P-GaN cap layer extends from the top to the bottom of the P-GaN cap layer 6. Such a wide depletion region can significantly achieve voltage division and blocking effects, significantly increasing the threshold voltage.

[0062] In addition, in E-Mode HEMTs, gate leakage and gate breakdown voltage are determined by the gate-source. The main path for gate leakage is electrons leaking upward from the left side of the P-GaN cap layer to the gate metal. The vertical depletion region provided by the side gate in this embodiment can innovatively and perfectly block this sidewall leakage path, thereby significantly reducing gate leakage.

[0063] The width of the gate metal 10 is smaller than the width of the P-GaN cap layer 6. The gate metal 10 on the dielectric layer 7 on the upper side of the P-GaN cap layer 6 is close to the drain metal 9. The dielectric layer 7 on the upper side of the P-GaN cap layer 6 has the same width as the gate metal 10 and does not completely cover the p-GaN cap layer. This can reduce the interface state defects introduced by the dielectric layer and alleviate the increase in gate capacitance caused by the introduction of the dielectric layer.

[0064] The distance between the gate metal 10 and the source metal 8 on the side close to the source metal 8 is 3μm, the distance between the gate metal 10 and the drain metal 9 on the side close to the drain metal 9 is 12μm, the horizontal spacing between the two gate metals 10 is 1μm, and the two gate metals 10 have the same structural dimensions, a gate length of 2μm, and a gate width of 100μm. The gate length is the length from the left end to the right end of the gate metal, and the gate width is the extension width of the gate into the paper.

[0065] The substrate 1 is made of silicon carbide;

[0066] The material of the dielectric layer 7 is Al2O3, and the thickness of the dielectric layer 7 is 10nm;

[0067] The thickness of the GaN buffer layer 2 is 2 μm;

[0068] The thickness of the GaN channel layer 3 is 200 nm;

[0069] The thickness of the AlN intercalation layer 4 is 0.5 nm;

[0070] The thickness of the AlGaN barrier layer 5 is 12.5 nm, and the molar ratio of Al is 18%;

[0071] The thickness of the p-GaN cap layer 6 is 100 nm, and the doping concentration of the p-GaN cap layer 6 is 3×10 19 cm -3 , the doping source is magnesium or boron;

[0072] The source metal 8 and the drain metal 9 are made of Ti / Al / Ni / Au metal stacks.

[0073] The manufacturing method of the enhancement-mode gallium nitride device based on dual-gate and dielectric layer control comprises the following steps:

[0074] S1, sequentially growing a GaN buffer layer 2, a GaN channel layer 3, an AlN intercalation layer 4, an AlGaN barrier layer 5, and a p-GaN cap layer 6 on a substrate 1;

[0075] S2, dry etching away the excess p-GaN cap layer 6;

[0076] S3, removing the GaN channel layer 3, AlN intercalation layer 4, and AlGaN barrier layer 5 outside the device by dry etching to form a mesa;

[0077] S4, evaporating source metal 8 and drain metal 9 on the table;

[0078] S5, annealing in the drain metal 9 and source metal 8 regions to form ohmic contacts;

[0079] S6, depositing a dielectric layer 7 on the AlGaN barrier layer 5 and the p-GaN cap layer 6;

[0080] S7, evaporating a gate metal 10 on the dielectric layer 7 on the side of the p-GaN cap layer 6 close to the source metal 8 and on the dielectric layer 7 above the p-GaN cap layer 6 close to the drain metal 9;

[0081] S8. Remove the excess dielectric layer 7 by dry etching.

[0082] In step S1 , the growth method of the GaN buffer layer 2 , the GaN channel layer 3 , the AlN intercalation layer 4 , the AlGaN barrier layer 5 , and the p-GaN cap layer 6 is metal organic chemical vapor deposition (MOCVD);

[0083] The etching method of steps S2, S3 and S8 is inductively coupled plasma etching.

[0084] In step S5 , the annealing method of the source metal 8 and the drain metal 9 is laser selective annealing.

[0085] Conventional device structures such as Figure 2 As shown, only a gate metal is provided on the P-GaN cap layer without a dielectric layer. The improved device of the present invention is a dual-gate dielectric device. The performance of the dual-gate dielectric device of the present invention is verified in Sentaurus TCAD simulation.

[0086] (1) Simulation model construction: Construct two-dimensional structural models of this embodiment and conventional devices in Sentaurus TCAD software;

[0087] (2) Simulation parameter settings: Set boundary conditions and initial conditions, including voltage and current. For the transfer curve, first apply a 10V drain voltage, then apply a variable gate voltage. For breakdown, first apply a -6V gate voltage to ensure depletion, then apply the drain voltage until breakdown. For gate withstand voltage and leakage, first float the drain, then apply the gate voltage until breakdown.

[0088] (3) Simulation process: Simulation is performed to observe the changes in the electrical properties of this embodiment compared with conventional devices.

[0089] (4) Result analysis: According to the linear extrapolation method, Figure 3 It can be seen that the threshold voltage of the dual-gate dielectric device of this embodiment is twice that of the conventional device, increasing from 2.6V to 4.2V. Figure 4 In the breakdown curve, with the critical breakdown field strength of GaN material of 3.3MV / cm as the judgment standard, the breakdown voltage of the dual-gate dielectric device reached 1192V, which is better than the 957V of conventional devices. Figure 5 In the gate breakdown voltage curve, the gate breakdown voltage of the dual-gate dielectric device reached 19.53V, which is better than the 13.68V of the conventional device; and the leakage of the dual-gate dielectric device was reduced by two orders of magnitude, which shows that the new enhanced device architecture with dual-gate coordinated regulation and dielectric layer integration can significantly improve the overall performance and reliability of the device.

Claims

1. An enhancement-mode gallium nitride device based on dual-gate and dielectric layer control, characterized in that: From bottom to top, it includes a substrate, a GaN buffer layer, a GaN channel layer, an AlN intercalation layer, an AlGaN barrier layer, and a P-GaN cap layer. A dielectric layer is provided on the upper side of the P-GaN cap layer and on the AlGaN barrier layers on both sides of the P-GaN cap layer. A source metal and a drain metal are provided on both sides of the dielectric layer. The bottoms of the source metal and the drain metal extend to the GaN buffer layer. A gate metal is provided on the dielectric layer near the source metal side and on the dielectric layer above the P-GaN cap layer. The gate metal width is smaller than the width of the P-GaN cap layer, the gate metal on the dielectric layer on the upper side of the P-GaN cap layer is close to the drain metal, and the dielectric layer on the upper side of the P-GaN cap layer has the same width as the gate metal; The gate metal and dielectric layer on the upper side of the P-GaN cap layer are aligned with one side of the P-GaN cap layer, and the other gate metal is attached to the side wall of the P-GaN cap layer.

2. The enhancement-mode gallium nitride device based on dual-gate and dielectric layer control according to claim 1, characterized in that: The distance between the gate metal and the source metal close to the source metal is 3μm, the distance between the gate metal and the drain metal close to the drain metal is 12μm, the horizontal distance between the two gate metals is 1μm, and the two gate metal structures have the same size, a gate length of 2μm, and a gate width of 100μm.

3. The enhancement-mode gallium nitride device based on dual-gate and dielectric layer control according to claim 2, characterized in that: The substrate material is silicon carbide, silicon or sapphire; The material of the dielectric layer is Al2O3 or HfO2, and the thickness of the dielectric layer is 1-100nm; The thickness of the GaN buffer layer is 0.1-50 μm; The thickness of the GaN channel layer is 5-1000nm; The thickness of the AlN intercalation layer is 0.2-2 nm; The thickness of the AlGaN barrier layer is 5-50 nm, and the molar ratio of Al is 5-35%; The thickness of the p-GaN cap layer is 1-1000 nm, and the doping concentration of the p-GaN cap layer is 1×10 17 -1×10 20 cm -3 , the doping source is magnesium or boron; The source metal and drain metal materials are the same, which are Ti / Al / Ni / Au metal stack, Ti / Al / Ti / Au metal stack or Ti / Al / Mo / Au metal stack; The gate metal material is Ni / Au metal stack.

4. The enhancement-mode gallium nitride device based on dual-gate and dielectric layer control according to claim 3, characterized in that: The substrate material is silicon carbide; The material of the dielectric layer is Al2O3; The thickness of the GaN buffer layer is 2 μm; The thickness of the GaN channel layer is 200nm; The thickness of the AlN intercalation layer is 0.5 nm; The thickness of the AlGaN barrier layer is 12.5 nm, and the molar ratio of Al is 18%; The thickness of the p-GaN cap layer is 100 nm, and the doping concentration of the p-GaN cap layer is 3×10 19 cm -3 ; The thickness of the dielectric layer is 10 nm; The source metal and drain metal materials are Ti / Al / Ni / Au metal stacks.

5. The method for manufacturing an enhancement-mode gallium nitride device based on dual-gate and dielectric layer control according to claim 4, wherein: Here are the steps: S1, sequentially growing a GaN buffer layer, a GaN channel layer, an AlN intercalation layer, an AlGaN barrier layer, and a p-GaN cap layer on a substrate; S2, dry etching away the excess p-GaN cap layer; S3, removing the GaN channel layer, AlN intercalation layer, and AlGaN barrier layer outside the device by dry etching to form a mesa; S4, evaporating source metal and drain metal on the table; S5, annealing the drain metal and source metal regions to form ohmic contacts; S6. depositing a dielectric layer on the AlGaN barrier layer and the p-GaN cap layer; S7, evaporating gate metal on the dielectric layer on the side of the p-GaN cap layer close to the source metal and on the dielectric layer above the p-GaN cap layer close to the drain metal; S8. Remove the excess dielectric layer by dry etching.

6. The method for manufacturing an enhancement-mode gallium nitride device based on dual-gate and dielectric layer control according to claim 5, wherein: In step S1, the growth method of the GaN buffer layer, the GaN channel layer, the AlN intercalation layer, the AlGaN barrier layer, and the p-GaN cap layer is metal organic chemical vapor deposition or molecular beam epitaxy; The etching method in steps S2, S3 and S8 is inductively coupled plasma etching or reactive ion etching.

7. The method for manufacturing an enhancement-mode gallium nitride device based on dual-gate and dielectric layer control according to claim 6, wherein: In step S5 , the annealing method of the source metal and the drain metal is laser selective annealing.

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