A HEMT device and a method of manufacturing the same

Abstract

The application provides a HEMT device and a preparation method thereof, and the HEMT device comprises a semiconductor layer, a cap layer, a passivation dielectric layer, a source / drain / gate and a gate contact structure, wherein the semiconductor layer comprises a channel layer and a barrier layer which are stacked in sequence; the cap layer is located on the upper surface of the barrier layer; the passivation dielectric layer covers the exposed upper surface of the barrier layer and the exposed surface of the cap layer; the source and the drain respectively penetrate through the passivation dielectric layer and are electrically connected with the conductive channel at the interface of the barrier layer and the channel layer, and the source and the drain are located on the two sides of the cap layer which are oppositely arranged and are arranged at intervals from the cap layer; the gate contact structure penetrates through the passivation dielectric layer, and the gate contact structure comprises first and second barrier contact parts which respectively form Schottky contact with the cap layer and have different barrier heights between the cap layer; the gate is electrically connected with the top of the first and second barrier contact parts. Through the arrangement of the gate contact structure, the gate leakage current is reduced, the threshold voltage drift is avoided, and the performance of the device is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a HEMT device and its fabrication method. Background Technology

[0002] P-GaN gate HEMT (High Electron Mobility Transistor) devices, with their unique characteristics of high electron mobility, high electron saturation velocity, and high breakdown voltage, have great development potential in high-power devices and new energy vehicles. However, after prolonged operation, the potential of the P-GaN cap layer in Schottky P-GaN gate HEMT devices fluctuates, leading to threshold voltage drift, performance degradation, and severely impacting device stability and reliability. While ohmic P-GaN gate HEMT devices avoid threshold voltage drift, they suffer from severe gate leakage, further limiting reliability and stability. Currently, to improve the performance of P-GaN gate HEMT devices, researchers are modifying the P-GaN gate structure, such as... Figure 1 The diagram shows a cross-sectional view of a P-GaN gate HEMT device, including a substrate 01, a channel layer 011, a barrier layer 012, a P-GaN cap layer 02, a fin structure 021, a passivation dielectric layer 03, a source metal layer 04, a first ohmic contact region 041, a drain metal layer 05, a second ohmic contact region 051, a gate metal layer 06, and a third ohmic contact region 061. This structure forms a heavily doped P-GaN or AlGaN fin structure above the P-GaN cap layer, and then forms gate metal layers that form Schottky contacts with the P-GaN cap layer and ohmic contacts with the fin structure, respectively. An ohmic contact region (i.e., ...) is formed in the gate metal layer at the top of the heavily doped fin structure. Figure 1 The third ohmic contact region in the structure improves the performance of the device to some extent, but it is difficult to dope the fin structure of P-GaN or AlGaN, the process is complicated, the manufacturing cost is high, the activation rate is very low, it is difficult to achieve the ideal effect, and the performance is relatively poor.

[0003] Therefore, there is an urgent need to find a HEMT device that can reduce gate leakage current, avoid threshold voltage drift, reduce the fabrication difficulty of the device, and improve the device performance. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a HEMT device and its fabrication method, which solves the problems of high fabrication difficulty and poor performance of P-GaN gate HEMT devices in the prior art while avoiding threshold voltage drift and reducing gate leakage current.

[0005] To achieve the above and other related objectives, the present invention provides a HEMT device, comprising the following steps:

[0006] A semiconductor layer, comprising a channel layer and a barrier layer stacked sequentially;

[0007] The cap layer is located on the upper surface of the barrier layer;

[0008] A passivated dielectric layer covers the exposed upper surface of the barrier layer and the exposed surface of the cap layer;

[0009] The source electrode penetrates the passivation dielectric layer and is electrically connected to the conductive channel at the interface between the barrier layer and the channel layer;

[0010] The drain penetrates the passivation dielectric layer and is electrically connected to the conductive channel at the interface between the barrier layer and the channel layer. The source and drain are located on opposite sides of the cap layer and are spaced apart from the cap layer.

[0011] A gate contact structure extends through the passivated dielectric layer. The gate contact structure includes a first barrier contact portion and a second barrier contact portion whose bottoms respectively form Schottky contacts with the cap layer and have different barrier heights with the cap layer.

[0012] The gate is electrically connected to the top of the first barrier contact and the second barrier contact, respectively.

[0013] Optionally, the semiconductor layer further includes a substrate, and the channel layer is located on the upper surface of the substrate.

[0014] Optionally, the bottom cross-sectional dimension of the gate contact structure is smaller than the top cross-sectional dimension of the cap layer.

[0015] Optionally, the barrier height between the first barrier contact portion and the cap layer is greater than the barrier height between the second barrier contact portion and the cap layer.

[0016] Optionally, the second barrier contact portion penetrates the first barrier contact portion.

[0017] Optionally, a plurality of the second barrier contacts are arranged in an array.

[0018] Optionally, the material of the first barrier contact includes at least one of tungsten, titanium, aluminum, nickel, and gold; the material of the second barrier contact includes at least one of tungsten, titanium, aluminum, nickel, and gold.

[0019] Optionally, the first barrier contact portion and the second barrier contact portion are made of different materials.

[0020] Optionally, the source electrode includes a first ohmic contact portion located at the bottom of the source electrode, and the first ohmic contact portion forms an ohmic contact with the barrier layer; the drain electrode includes a second ohmic contact portion located at the bottom of the drain electrode, and the second ohmic contact portion forms an ohmic contact with the barrier layer.

[0021] This invention also provides a method for fabricating a HEMT device, comprising the following steps:

[0022] A semiconductor layer comprising a channel layer and a barrier layer stacked sequentially is provided, and a cap layer of a predetermined size is formed on the upper surface of the barrier layer;

[0023] A passivation dielectric layer is formed covering the exposed upper surface of the barrier layer and the exposed surface of the cap layer;

[0024] A gate contact structure is formed that penetrates the passivation dielectric layer. The gate contact structure includes a first barrier contact portion and a second barrier contact portion whose bottoms respectively form Schottky contacts with the cap layer and have different barrier heights with the cap layer.

[0025] A source and a drain are formed on opposite sides of the cap layer and spaced apart from the cap layer. The source penetrates the passivation dielectric layer and is electrically connected to a conductive channel at the interface between the barrier layer and the channel layer. The drain penetrates the passivation dielectric layer and is electrically connected to a conductive channel at the interface between the barrier layer and the channel layer.

[0026] A gate is formed that is electrically connected to the top of the first barrier contact and the second barrier contact, respectively.

[0027] As described above, the HEMT device and its fabrication method of the present invention utilize a gate contact structure disposed between the gate and the cap layer, wherein the contact type between the gate contact structure and the cap layer is a Schottky contact. The upper and lower ends of the first and second barrier contact portions in the gate contact structure are electrically connected to the gate and the cap layer, respectively. The barrier height between the first barrier contact portion and the cap layer is greater than the barrier height between the second barrier contact portion and the cap layer. This higher barrier between the first barrier contact portion and the cap layer reduces the gate leakage current of the device, while the lower barrier between the second barrier contact portion and the cap layer forms a charge release path between the cap layer and the gate, facilitating the release of shallow energy levels and carriers trapped in traps. This ensures the stability of the electrical characteristics of the device under long-term stress, thereby guaranteeing the stability of the cap layer potential, preventing threshold voltage drift, and improving device performance. Furthermore, the fabrication process of this gate contact structure is simple and the manufacturing cost is low, making it highly valuable for industrial applications. Attached Figure Description

[0028] Figure 1The diagram shows a cross-sectional structure of a P-GaN gate HEMT device.

[0029] Figure 2 The diagram shown is a cross-sectional view of the HEMT device of the present invention.

[0030] Figure 3 The diagram shown is a schematic diagram of the top structure of the HMET device of the present invention.

[0031] Figure 4 The diagram shown is a process flow diagram of the fabrication method of the HEMT device of the present invention.

[0032] Figure 5 The diagram shows a cross-sectional structure of the semiconductor layer in the fabrication method of the HEMT device of the present invention.

[0033] Figure 6 The diagram shows a cross-sectional structure after the cap layer is formed, which is a method for fabricating the HEMT device of the present invention.

[0034] Figure 7 The diagram shows a cross-sectional structure after forming the first ohmic contact and the second ohmic contact in the fabrication method of the HEMT device of the present invention.

[0035] Figure 8 The diagram shows a cross-sectional structure of the HEMT device fabrication method of the present invention after the formation of the passivation dielectric layer.

[0036] Figure 9 The diagram shown is a cross-sectional view of the HEMT device fabrication method of the present invention after the formation of the first barrier material layer.

[0037] Figure 10 The diagram shows a cross-sectional structure after the formation of the fifth contact hole in the fabrication method of the HEMT device of the present invention.

[0038] Figure 11 The diagram shows a cross-sectional view of the HEMT device fabrication method of the present invention after the gate contact structure is formed.

[0039] Explanation of icon numbers

[0040] 01 Substrate

[0041] 011 Channel Layer

[0042] 012 Barrier Layer

[0043] 02 P-GaN cap layer

[0044] 021 Fin Structure

[0045] 03 Passivation Dielectric Layer

[0046] 04 Source Metal Layer

[0047] 041 First Ohmic Contact Zone

[0048] 05 Drain metal layer

[0049] 051 Second Ohmic Contact Area

[0050] 06 Gate metal layer

[0051] 061 Third Ohmic Contact Zone

[0052] 1 Semiconductor layer

[0053] 11 Substrate

[0054] 12. Channel layer

[0055] 13 Barrier Layer

[0056] 14 First contact hole

[0057] 15 Second contact hole

[0058] 2. Hat layer

[0059] 3. Passivation dielectric layer

[0060] 31 Gate contact hole

[0061] 32 Third contact hole

[0062] 33 Fourth contact hole

[0063] 4 Source

[0064] 41 First Ohmic Contact

[0065] 42 First Main Body

[0066] 5 Drain

[0067] 51 Second Ohmic Contact

[0068] 52 Second Main Body

[0069] 6 gates

[0070] 61. Grid contact structure

[0071] 62 First Barrier Contact Section

[0072] 63 Second Barrier Contact Section

[0073] 64 Fifth contact hole

[0074] 65 First Barrier Material Layer Detailed Implementation

[0075] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0076] Please see Figures 2 to 11 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0077] Example 1

[0078] This embodiment provides a HEMT device, such as Figure 2 and Figure 3 The figures shown are a cross-sectional view and a top view of the HEMT device, respectively. The HEMT device includes a semiconductor layer 1, a cap layer 2, a passivation dielectric layer 3, a source 4, a drain 5, a gate contact structure 61, and a gate 6. The semiconductor layer 1 includes a channel layer 12 and a barrier layer 13 stacked sequentially. The cap layer 2 is located on the upper surface of the barrier layer 13. The passivation dielectric layer 3 covers the exposed upper surface of the barrier layer 13 and the exposed surface of the cap layer 2. The source 4 penetrates the passivation dielectric layer 3 and forms a conductive channel at the interface between the barrier layer 13 and the channel layer 12. Electrical connection; the drain 5 penetrates the passivated dielectric layer 3 and is electrically connected to the conductive channel at the interface of the barrier layer 13 and the channel layer 12; the source 4 and the drain 5 are respectively located on opposite sides of the cap layer 2 and are spaced apart from the cap layer 2; the gate contact structure 61 penetrates the passivated dielectric layer 3, and the gate contact structure 61 includes a first barrier contact portion 62 and a second barrier contact portion 63 whose bottoms form Schottky contacts with the cap layer 2 and have different barrier heights with the cap layer 2; the gate 6 is electrically connected to the top of the first barrier contact portion 62 and the second barrier contact portion 63 respectively.

[0079] As an example, the semiconductor layer 1 also includes a substrate 11, and a channel layer 12 is located on the upper surface of the substrate 11.

[0080] Specifically, the substrate 11 is usually the process platform for fabricating the trench layer 12. While ensuring device performance, the size, thickness and shape of the substrate 11 can be selected according to the actual situation, and there are no restrictions here.

[0081] Specifically, the substrate 11 may be made of silicon, silicon germanium, glass, silicon carbide, sapphire, diamond, gallium nitride, or other suitable materials.

[0082] It should be noted that when the lattice mismatch between the substrate 11 and the channel layer 12 is small, the channel layer 12 can be directly formed on the upper surface of the substrate 11. When the lattice mismatch between the substrate 11 and the channel layer 12 is large, in order to ensure the quality of the formed channel layer 12, a buffer layer needs to be formed between the substrate 11 and the channel layer 12 to reduce the lattice mismatch between the substrate 11 and the channel layer 12. The lattice mismatch between the buffer layer and the channel layer 12 is small. Under the condition of ensuring the quality of the formed channel layer 12, the material of the buffer layer can be selected according to the actual situation. For example, an aluminum nitride layer can be set between the silicon substrate and the gallium nitride channel layer 12 as a buffer layer to ensure the quality of the formed gallium nitride channel layer 12.

[0083] Specifically, when the lattice mismatch between the substrate 11 and the channel layer 12 is large, the thickness of the buffer layer can be selected according to the actual situation while ensuring the quality of the formed channel layer 12. There are no restrictions here.

[0084] Specifically, the channel layer 12 may be made of GaN, AlGaN, InGaN, or other suitable semiconductor materials. Preferably, a GaN layer is used as the channel layer 12.

[0085] Specifically, the material of barrier layer 13 includes In x Al y Ga 1-x-y N, Al x Ga 1-x N、In x Al 1-x N or other suitable materials. Preferably, Al is used. x Ga 1-x N serves as barrier layer 13.

[0086] Specifically, while ensuring device performance, the thickness, size, and shape of the channel layer 12 can be selected according to the actual situation; the thickness, size, and shape of the barrier layer 13 can be selected according to the actual situation.

[0087] Specifically, the cap layer 2 is made of P-type GaN, P-type AlGaN, InGaP, or other semiconductor materials that can completely deplete the two-dimensional electron gas at the interface between the barrier layer 13 and the channel layer 12 below it. Preferably, a P-type GaN layer is used as the cap layer 2.

[0088] Specifically, while ensuring device performance, the size, shape, and thickness of the cap layer 2 can be selected according to the actual situation.

[0089] Specifically, the material of the passivation dielectric layer 3 includes aluminum nitride, silicon nitride, silicon oxide, or other suitable dielectric materials.

[0090] Specifically, the passivation dielectric layer 3 is used to passivate the surface of the barrier layer 13 to reduce defects on the surface of the barrier layer 13, and at the same time to insulate the gate 6, source 4 and drain 5 of the device, thereby improving the stability and reliability of the device. The thickness of the passivation dielectric layer 3 can be selected according to the actual situation while ensuring the device performance.

[0091] Specifically, the passivation dielectric layer 3 is further provided with a gate contact hole 31 that penetrates the passivation dielectric layer 3. The bottom surface of the gate contact hole 31 exposes the cap layer 2. The size of the bottom surface of the gate contact hole 31 is smaller than the size of the cap layer 2, so that only the cap layer 2 is exposed on the bottom surface of the gate contact hole 31, and the gate contact structure 61 fills the gate contact hole 31.

[0092] Specifically, while ensuring device performance, the opening size and shape of the gate contact hole 31 can be selected according to the actual situation.

[0093] As an example, the bottom cross-sectional dimension of the gate contact structure 61 is smaller than the top cross-sectional dimension of the cap layer 2, where the cross-section refers to the cross-section parallel to the upper surface of the barrier layer 13.

[0094] Specifically, the bottom cross-sectional dimension of the gate contact structure 61 is smaller than the top cross-sectional dimension of the cap layer 2, so that the bottom surface of the gate contact structure 61 only contacts the top surface of the cap layer 2, thereby ensuring the performance of the device.

[0095] As an example, the barrier height between the first barrier contact 62 and the cap layer 2 is greater than the barrier height between the second barrier contact 63 and the cap layer 2.

[0096] Specifically, by making the barrier height between the first barrier contact 62 and the cap layer 2 greater than the barrier height between the second barrier contact 63 and the cap layer 2, the leakage current of the gate 6 of the device can be significantly reduced, and the stability of the device can be improved. At the same time, by making the barrier between the second barrier contact 63 and the cap layer 2 smaller, a charge release path can be formed, which helps to release the carriers trapped in the shallow energy level trap, making the electrical characteristics of the device stable under long-term stress, thereby stabilizing the potential of the cap layer 2 and avoiding the problem of unstable threshold voltage of the device.

[0097] Specifically, while ensuring device performance, the barrier height between the first barrier contact 62 and the cap layer 2 can be selected according to the actual situation; the barrier height between the second barrier contact 63 and the cap layer 2 can be selected according to the actual situation.

[0098] As an example, the second barrier contact 63 penetrates the first barrier contact 62.

[0099] Specifically, by having the second barrier contact 63 penetrate the first barrier contact 62, the gate contact hole structure 61 can be formed through a simple process.

[0100] Specifically, while ensuring device performance, the first barrier contact 62 can also fill the gate contact hole 31 in parallel with the second barrier contact 63.

[0101] As an example, multiple second barrier contacts 63 are arranged in an array, that is, the gate contact structure 61 includes multiple second barrier contacts 63, and the multiple second barrier contacts 63 are arranged in an array in the gate contact structure 61.

[0102] Specifically, by arranging the second barrier contacts 63 in an array within the gate contact structure 61, a better bonding effect is achieved between the first barrier contacts 62 and the second barrier contacts 63, resulting in better release of carriers trapped in shallow energy level traps and improved threshold stability of the device. In this embodiment, multiple second barrier contacts 63 are spaced apart in the middle region of the gate contact structure 61 along the direction extending from it.

[0103] Specifically, while ensuring device performance, the cross-sectional shape and size of the first barrier contact 62 can be selected according to actual conditions; the cross-sectional size and shape of the second barrier contact 63 can be selected according to actual conditions; when the gate contact structure 61 includes multiple second barrier contacts 63, the distance between two adjacent second barrier contacts 63 can be selected according to actual conditions.

[0104] As an example, the material of the first barrier contact 62 includes at least one of tungsten, titanium, aluminum, nickel, and gold, or other metallic materials that form a preset barrier height with the cap layer 2.

[0105] As an example, the material of the second barrier contact 63 includes at least one of tungsten, titanium, aluminum, nickel, and gold, and other metal materials that form a preset barrier height with the cap layer 2.

[0106] As an example, the first barrier contact 62 and the second barrier contact 63 are made of different materials. By utilizing the different work functions of the different materials, it is easy to make the barrier height of the first barrier contact 62 greater than the height of the second barrier contact 63.

[0107] Specifically, while ensuring device performance, the material of the first barrier contact 62 can be the same as that of the second barrier contact 63. When the materials of the first barrier contact 62 and the second barrier contact 63 are the same, it is necessary to adjust the formation conditions of the first barrier contact 62 and the second barrier contact 63 so that the first barrier contact 62 and the cap layer 2 have a higher barrier and the second barrier contact 63 and the cap layer 2 have a lower barrier.

[0108] It should be noted that the sidewall of the second barrier contact 63 is usually surrounded by the first barrier contact 62, or it can be surrounded by the first barrier contact 62 and the passivation dielectric layer 3.

[0109] As an example, the source electrode 4 includes a first ohmic contact portion 41 located at the bottom of the source electrode 4, and the first ohmic contact portion 41 forms an ohmic contact with the barrier layer 13. The drain electrode 5 includes a second ohmic contact portion 51 located at the bottom of the drain electrode 5, and the second ohmic contact portion 51 forms an ohmic contact with the barrier layer 13.

[0110] It should be noted that, typically, the first ohmic contact 41 is used to form an ohmic contact between the source 4 and the barrier layer 13 it contacts, and the second ohmic contact 51 is used to form an ohmic contact between the drain 5 and the barrier layer 13 it contacts. The passivation dielectric layer 3 covers the exposed surfaces of the first ohmic contact 41 and the second ohmic contact 51. However, while ensuring device performance, the first ohmic contact 41 can also form an ohmic contact with the channel layer 12 directly below the source 4, and the second ohmic contact 51 can also form an ohmic contact with the channel layer 12 directly below the drain 5. Preferably, both the first ohmic contact 41 and the second ohmic contact 51 penetrate the barrier layer 13, that is, both the first ohmic contact 41 and the second ohmic contact 51 form an ohmic contact with the channel layer 12, so that the source electrode 4 and the drain electrode 5 are electrically connected to the conductive channel (two-dimensional electron gas layer) at the interface between the channel layer 12 and the barrier layer 13, and the upper surfaces of both the first ohmic contact 41 and the second ohmic contact 51 protrude from the upper surface of the barrier layer 13.

[0111] Specifically, a first contact hole 14 and a second contact hole 15 are formed in the barrier layer 13. The bottom surface of the first contact hole 14 exposes the channel layer 12 directly below the source electrode 4, and the bottom surface of the second contact hole 15 exposes the channel layer 12 directly below the drain electrode 5. The first ohmic contact portion 41 fills the first contact hole 14 and its top edge region covers the upper surface of the barrier layer 13. The second ohmic contact portion 51 fills the second contact hole 15 and its top edge region covers the upper surface of the barrier layer 13. That is, the cross-sections of the first ohmic contact portion 41 and the second ohmic contact portion 51 are both T-shaped to facilitate the fabrication of the portion above the first ohmic contact portion 41 in the source electrode 4 and the portion above the second ohmic contact portion 51 in the drain electrode 5.

[0112] Specifically, while ensuring device performance, the opening size and shape of the first contact hole 14 can be selected according to the actual situation; the opening size and shape of the second contact hole 15 can be selected according to the actual situation; the first contact hole 14 may not penetrate the barrier layer 13 and the bottom surface of the first contact hole 14 may be spaced apart from the bottom surface of the barrier layer 13 by a preset distance; the second contact hole 15 may not penetrate the barrier layer 13 and the bottom surface of the second contact hole 15 may be spaced apart from the bottom surface of the barrier layer 13 by a preset distance.

[0113] Specifically, the material of the first ohmic contact 41 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials; the material of the second ohmic contact 51 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials.

[0114] Specifically, the passivation dielectric layer 3 is further provided with a third contact hole 32 and a fourth contact hole 33 that penetrate the passivation dielectric layer 3. The bottom surface of the third contact hole 32 exposes the upper surface of the first ohmic contact portion 41, and the bottom surface of the fourth contact hole 33 exposes the upper surface of the second ohmic contact portion 51. The first main body portion 42 above the first ohmic contact portion 41 in the source electrode 4 fills the third contact hole 32, and the second main body portion 52 above the second ohmic contact portion 51 in the drain electrode 5 fills the fourth contact hole 33.

[0115] It should be noted that, generally, the upper surface of the first main body 42 protrudes from the upper surface of the passivation dielectric layer 3 at the opening of the third contact hole 32 and the top covers the upper surface of the passivation dielectric layer 3 in the area surrounding the opening of the third contact hole 32, and the upper surface of the second main body 52 protrudes from the upper surface of the passivation dielectric layer 3 at the opening of the fourth contact hole 33 and the top covers the upper surface of the passivation dielectric layer 3 in the area surrounding the opening of the fourth contact hole 33.

[0116] Specifically, the material of the first main body 42 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials; the material of the gate 6 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials; and the material of the second main body 52 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials.

[0117] Specifically, the gate contact structure 61 is configured such that the upper and lower ends of the first barrier contact portion 62 and the second contact area in the gate contact structure 61 are electrically connected to the gate 6 and the cap layer 2 of the device, respectively. The first barrier contact portion 62, which has a high barrier between it and the cap layer 2, reduces the gate leakage current of the device and improves the stability of the device. The second barrier contact portion 63, which has a lower barrier between it and the cap layer 2, serves as a path for charge release, releasing the carriers trapped in the shallow energy level trap. This ensures the stability of the electrical characteristics of the device under long-term stress, guarantees the potential stability of the cap layer 2, and consequently stabilizes the threshold voltage of the device.

[0118] Specifically, by combining the first barrier contact 62 and the second barrier contact 63, the gate leakage current of the device is reduced, the threshold voltage drift of the device is avoided, and the performance of the device is improved.

[0119] In this embodiment, the HEMT device has a gate contact structure 61 between the gate 6 and the cap layer 2. The upper and lower ends of the first barrier contact portion 62 and the second barrier contact portion 63 in the gate contact structure 61 are electrically connected to the gate 6 and the cap layer 2 of the device, respectively. The contact type between the first barrier contact portion 62 and the second barrier contact portion 63 and the cap layer 2 is a Schottky contact. The barrier height between the first barrier contact portion 62 and the cap layer 2 is greater than the barrier height between the second barrier contact portion 63 and the cap layer 2. The first barrier contact portion 62, which has a high barrier with the cap layer 2, reduces the gate leakage current of the device and improves the stability of the device. The second barrier contact portion 63, which has a lower barrier with the cap layer 2, serves as a charge release path to release the carriers trapped in the shallow energy level traps. This ensures the stability of the electrical characteristics of the device under long-term stress, guarantees the potential stability of the cap layer 2, avoids the threshold voltage drift of the device, and improves the performance of the device.

[0120] Example 2

[0121] This embodiment also provides a method for fabricating a HEMT device, such as... Figure 4 The figures shown are process flow diagrams of the fabrication method of the HEMT device, including the following steps:

[0122] S1: Provide a semiconductor layer including a channel layer and a barrier layer stacked sequentially, and form a cap layer of a predetermined size on the upper surface of the barrier layer;

[0123] S2: Form a passivation dielectric layer covering the exposed upper surface of the barrier layer and the exposed surface of the cap layer;

[0124] S3: Form a gate contact structure that penetrates the passivation dielectric layer. The gate contact structure includes a first barrier contact portion and a second barrier contact portion whose bottoms respectively form Schottky contacts with the cap layer and have different barrier heights with the cap layer.

[0125] S4: Form a source and a drain located on opposite sides of the cap layer and spaced apart from the cap layer. The source penetrates the passivation dielectric layer and is electrically connected to a conductive channel at the interface between the barrier layer and the channel layer. The drain penetrates the passivation dielectric layer and is electrically connected to a conductive channel at the interface between the barrier layer and the channel layer.

[0126] S5: Form a gate that is electrically connected to the top of the first barrier contact and the second barrier contact, respectively.

[0127] Please see Figures 5 to 8 Steps S1 and S2 are performed: a semiconductor layer 1 including a channel layer 12 and a barrier layer 13 stacked sequentially is provided, and a cap layer 2 of a predetermined size is formed on the upper surface of the barrier layer 13; a passivation dielectric layer 3 is formed covering the exposed upper surface of the barrier layer 13 and the exposed surface of the cap layer 2.

[0128] Specifically, such as Figure 5 The diagram shows a cross-sectional view of semiconductor layer 1. Semiconductor layer 1 also includes a substrate 11, and a channel layer 12 is formed on the upper surface of substrate 11.

[0129] It should be noted that semiconductor layer 1 is the semiconductor structure formed after the formation of barrier layer 13, and its specific size, shape and thickness can be selected according to the actual situation.

[0130] Specifically, such as Figure 6 The diagram shows a cross-sectional view of the structure after the cap layer 2 is formed. The cap layer 2 is used to enhance the threshold voltage of the device and reduce its on-resistance. The methods for forming the cap layer 2 include physical vapor deposition, chemical vapor deposition, or other suitable methods. Preferably, metal-organic chemical vapor deposition is used to form the cap layer 2.

[0131] Specifically, such as Figure 7 The diagram shows a cross-sectional view of the first ohmic contact 41 and the second ohmic contact 51 after their formation. After the cap layer 2 is formed and before the passivation dielectric layer 3 is formed, the process includes forming a first contact hole 14, a second contact hole 15, the first ohmic contact 41, and the second ohmic contact 51. The first contact hole 14 penetrates the barrier layer 13 and exposes the channel layer 12 on its bottom surface. The second contact hole 15 penetrates the barrier layer 13 and exposes the channel layer 12 on its bottom surface. The first contact hole 14 and the second contact hole 15 are located on opposite sides of the cap layer 2 and are spaced a predetermined distance from the cap layer 2. The first ohmic contact 41 fills the first contact hole 14 and its top edge region covers the upper surface of the barrier layer 13. The second ohmic contact 51 fills the second contact hole 15 and its top edge region covers the upper surface of the barrier layer 13. That is, the cross-sections of the first ohmic contact 41 and the second ohmic contact 51 are both T-shaped.

[0132] It should be noted that, while ensuring device performance, the first contact hole 14 and the second contact hole 15 may not penetrate the barrier layer 13. That is, the bottom surface of the first contact hole 14 is spaced apart from the bottom surface of the barrier layer 13 by a predetermined distance, and the bottom surface of the second contact hole 15 is spaced apart from the bottom surface of the barrier layer 13 by a predetermined distance, thereby forming an ohmic contact between the first ohmic contact portion 41 and the barrier layer 13, and an ohmic contact between the second ohmic contact portion 51 and the barrier layer 13.

[0133] Specifically, the method for forming the first contact hole 14 includes dry etching, wet etching, or other suitable methods; the method for forming the second contact hole 15 includes dry etching, wet etching, or other suitable methods.

[0134] Specifically, the first contact hole 14 and the second contact hole 15 can be formed simultaneously or in stages. Preferably, the first contact hole 14 and the second contact hole 15 are formed simultaneously to reduce the number of process steps and lower the manufacturing cost of the device.

[0135] Specifically, the methods for forming the first ohmic contact 41 include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods; the methods for forming the second ohmic contact 51 include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0136] Specifically, the first ohmic contact 41 and the second ohmic contact 51 can be formed simultaneously or in stages. Preferably, the ohmic contact material layer is formed simultaneously, and then the ohmic contact material layer is etched to simultaneously obtain the first ohmic contact 41 and the second ohmic contact 51.

[0137] Specifically, such as Figure 8 The diagram shown is a cross-sectional view of the passivation dielectric layer 3 after its formation. The passivation dielectric layer 3 also covers the exposed surfaces of the first ohmic contact 41 and the second ohmic contact 51. The methods for forming the passivation dielectric layer 3 include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0138] Please see Figures 9 to 11Steps S3, S4, and S5 are executed: a gate contact structure 61 is formed that penetrates the passivation dielectric layer 3. The gate contact structure 61 includes a first barrier contact portion 62 and a second barrier contact portion 63, which form Schottky contacts with the cap layer 2 at their bottoms and have different barrier heights with the cap layer 2; a source electrode 4 and a drain electrode 5 are formed on opposite sides of the cap layer 2 and spaced apart from the cap layer 2. The source electrode 4 penetrates the passivation dielectric layer 3 and is electrically connected to a conductive channel at the interface between the barrier layer 13 and the channel layer 12. The drain electrode 5 penetrates the passivation dielectric layer 3 and is electrically connected to a conductive channel at the interface between the barrier layer 13 and the channel layer 12; and a gate electrode 6 is formed that is electrically connected to the top of the first barrier contact portion 62 and the second barrier contact portion 63.

[0139] Specifically, forming the gate contact structure 61 includes the following steps: forming a patterned masking layer on the upper surface of the passivation dielectric layer 3, and forming a gate contact hole 31 that penetrates the passivation dielectric layer 3 and whose bottom surface is exposed only on the upper surface of the cap layer 2 based on the patterned masking layer; forming a first barrier material layer 65 that fills the gate contact hole 31, and forming a fifth contact hole 64 that penetrates the first barrier material layer 65 in the first barrier material layer 65 in the gate contact hole 31, with the bottom surface of the fifth contact hole 64 exposed on the upper surface of the cap layer 2; forming a second barrier material layer that fills the fifth contact hole 64, and removing the second barrier material layer and the first barrier material layer 65 directly above the passivation dielectric layer 3 to obtain a gate contact structure 61 that only fills the gate contact hole 31, wherein the remaining part of the first barrier material layer 65 serves as the first barrier contact portion 62, and the remaining part of the second barrier material layer serves as the second barrier contact portion 63.

[0140] Specifically, the masking layer includes a photoresist layer, a hard mask layer, or a stacked film layer composed of a hard mask layer and a photoresist layer. Preferably, a hard mask layer or a stacked film layer composed of a hard mask layer and a photoresist layer is used as the masking layer.

[0141] Specifically, the process for creating the patterned masking layer is the commonly used photolithography process, which will not be elaborated here.

[0142] Specifically, the methods for forming the gate contact hole 31 include dry etching, wet etching, or other suitable methods.

[0143] Specifically, after forming the gate contact hole 31 and before forming the first barrier material layer 65, there is also a step of removing the masking layer. The method for removing the masking layer is usually the same as the method for removing the photoresist layer or the hard mask layer, which will not be described in detail here.

[0144] Specifically, such as Figure 9The diagram shown is a cross-sectional view of the structure after the formation of the first barrier material layer 65. The first barrier material layer 65 fills the gate contact hole 31 and also covers the exposed upper surface of the passivation dielectric layer 3. The methods for forming the first barrier material layer 65 include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0145] Specifically, while ensuring device performance, the number, opening size, opening shape, bottom size, and bottom shape of the fifth contact hole 64 can be selected according to the actual situation.

[0146] Specifically, such as Figure 10 The diagram shown is a cross-sectional view of the structure after the fifth contact hole 64 is formed. The methods for forming the fifth contact hole 64 include dry etching, wet etching, or other suitable methods.

[0147] It should be noted that, typically, the sidewall of the fifth contact hole 64 is the first barrier material layer 65. However, while ensuring device performance, the fifth contact hole 64 can also be formed by the first barrier material layer 65 and the passivation dielectric layer 3, that is, the sidewall of the fifth contact hole 64 is the first barrier material layer 65 and the passivation dielectric layer 3. In this embodiment, the sidewall of the fifth contact hole 64 is the first barrier material layer 65.

[0148] Specifically, the second barrier material layer fills the fifth contact hole 64 while also covering the exposed upper surface of the first barrier material layer 65. The method for forming the second barrier material layer includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, evaporation, or other suitable methods. Preferably, an evaporation process is used to form the second barrier material layer.

[0149] Specifically, such as Figure 11 The diagram shown is a cross-sectional view of the gate contact structure 61 after it has been formed. The methods for removing the second barrier layer 13 and the first barrier material layer 65 directly above the passivation dielectric layer 3 include dry etching, wet etching, chemical mechanical polishing, or other suitable methods.

[0150] Specifically, before forming the source electrode 4 and the drain electrode 5, the process includes forming a third contact hole 32 and a fourth contact hole 33. The third contact hole 32 penetrates the passivation dielectric layer 3 directly above the first ohmic contact portion 41 and only exposes the first ohmic contact portion 41 on its bottom surface. The fourth contact hole 33 penetrates the passivation dielectric layer 3 directly above the second ohmic contact portion 51 and only exposes the second ohmic contact portion 51 on its bottom surface.

[0151] Specifically, the source electrode 4 includes a first main body portion 42 and a first ohmic contact portion 41 that fill the third contact hole 32, and the drain electrode 5 includes a second main body portion 52 and a second ohmic contact portion 51 that fill the fourth contact hole 33.

[0152] Specifically, the method for forming the third contact hole 32 includes dry etching, wet etching, or other suitable methods; the method for forming the fourth contact hole 33 includes dry etching, wet etching, or other suitable methods.

[0153] It should be noted that the third contact hole 32 and the fourth contact hole 33 can be formed simultaneously or in stages. Preferably, the third contact hole 32 and the fourth contact hole 33 are formed simultaneously to reduce the number of process steps in manufacturing the device and lower the cost of manufacturing the device.

[0154] Specifically, the methods for forming the first body portion 42 include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods; the methods for forming the second body portion 52 include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods; and the methods for forming the gate 6 include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0155] It should be noted that the first main body portion 42, the second main body portion 52, and the gate 6 can be formed simultaneously or in stages. Preferably, the first injection portion, the second main body portion 52, and the gate 6 are formed simultaneously.

[0156] Specifically, by forming a first barrier material layer 65 filling the gate contact hole 31 in the gate contact hole 31, and forming a second barrier material layer penetrating the first barrier material fifth contact hole 64 and filling the fifth contact hole 64, and then removing the second barrier material layer and the first barrier material layer 65 directly above the passivation dielectric layer 3, a gate contact structure 61 that forms a Schottky contact with the cap layer 2 is formed using a simple process, and the barrier height between the first barrier contact portion 62 in the gate contact structure 61 and the cap layer 2 is greater than the barrier height between the second barrier contact portion 63 and the cap layer 2.

[0157] Specifically, by combining the first barrier contact 62 with a higher barrier between it and the cap layer 2 and the second barrier contact 63 with a lower barrier between it and the cap layer 2, the gate leakage current of the device is significantly reduced, the threshold voltage drift of the device is avoided, the cost is reduced, and the performance of the device is improved.

[0158] The HEMT device fabrication method of this embodiment involves forming a first barrier material layer 65 filling the gate contact hole 31, forming a fifth contact hole 64 penetrating the first barrier material layer and a second barrier material layer filling the fifth contact hole 64, and then removing the second barrier material layer and the first barrier material layer 65 directly above the passivation dielectric layer 3. This method utilizes a simple process and low cost to form a gate contact structure 61 between the gate 6 and the cap layer 2, forming a Schottky contact with the cap layer 2. Furthermore, the barrier height between the first barrier contact portion 62 and the cap layer 2 in the gate contact structure 61 is greater than the barrier height between the second barrier contact portion 63 and the cap layer 2, significantly reducing the gate leakage current of the device, preventing threshold voltage drift, and improving device performance.

[0159] In summary, the HEMT device and its fabrication method of the present invention improve the device structure by setting a gate contact structure between the gate and the cap layer. The upper and lower ends of the first and second barrier contacts in the gate contact structure are electrically connected to the gate and the cap layer, respectively, and form Schottky contacts with the cap layer. The barrier height between the first barrier contact and the cap layer is greater than the barrier height between the second barrier contact and the cap layer. The high barrier between the first barrier contact and the cap layer reduces the gate leakage current and improves the device's stability. The lower barrier between the second barrier contact and the cap layer serves as a charge release path, releasing carriers trapped in shallow energy level traps, thus ensuring the stability of the device's electrical characteristics under long-term stress. This, in turn, ensures the stability of the cap layer's potential, avoids threshold voltage drift, and improves device performance. Furthermore, the fabrication process of this gate contact structure is simple and low-cost. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0160] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A HEMT device, characterized in that, include: A semiconductor layer, comprising a channel layer and a barrier layer stacked sequentially; The cap layer is located on the upper surface of the barrier layer; A passivated dielectric layer covers the exposed upper surface of the barrier layer and the exposed surface of the cap layer; The source electrode penetrates the passivation dielectric layer and is electrically connected to the conductive channel at the interface between the barrier layer and the channel layer; The drain penetrates the passivation dielectric layer and is electrically connected to the conductive channel at the interface between the barrier layer and the channel layer. The source and drain are located on opposite sides of the cap layer and are spaced apart from the cap layer. A gate contact structure extends through the passivated dielectric layer. The gate contact structure includes a first barrier contact portion and a second barrier contact portion whose bottoms respectively form Schottky contacts with the cap layer and have different barrier heights with the cap layer. The gate is electrically connected to the top of the first barrier contact and the second barrier contact, respectively.

2. The HEMT device according to claim 1, characterized in that: The semiconductor layer also includes a substrate, and the channel layer is located on the upper surface of the substrate.

3. The HEMT device according to claim 1, characterized in that: The bottom cross-sectional dimension of the gate contact structure is smaller than the top cross-sectional dimension of the cap layer.

4. The HEMT device according to claim 1, characterized in that: The barrier height between the first barrier contact portion and the cap layer is greater than the barrier height between the second barrier contact portion and the cap layer.

5. The HEMT device according to claim 1, characterized in that: The second barrier contact portion penetrates the first barrier contact portion.

6. The HEMT device according to claim 5, characterized in that: Multiple second barrier contacts are arranged in an array.

7. The HEMT device according to claim 1, characterized in that: The material of the first barrier contact includes at least one of tungsten, titanium, aluminum, nickel, and gold; the material of the second barrier contact includes at least one of tungsten, titanium, aluminum, nickel, and gold.

8. The HEMT device according to claim 1, characterized in that: The first barrier contact portion and the second barrier contact portion are made of different materials.

9. The HEMT device according to claim 1, characterized in that: The source electrode includes a first ohmic contact portion located at the bottom of the source electrode, and the first ohmic contact portion forms an ohmic contact with the barrier layer. The drain electrode includes a second ohmic contact portion located at the bottom of the drain electrode, and the second ohmic contact portion forms an ohmic contact with the barrier layer.

10. A method for fabricating a HEMT device, characterized in that, Includes the following steps: A semiconductor layer comprising a channel layer and a barrier layer stacked sequentially is provided, and a cap layer of a predetermined size is formed on the upper surface of the barrier layer; A passivation dielectric layer is formed covering the exposed upper surface of the barrier layer and the exposed surface of the cap layer; A gate contact structure is formed that penetrates the passivation dielectric layer. The gate contact structure includes a first barrier contact portion and a second barrier contact portion whose bottoms respectively form Schottky contacts with the cap layer and have different barrier heights with the cap layer. A source and a drain are formed on opposite sides of the cap layer and spaced apart from the cap layer. The source penetrates the passivation dielectric layer and is electrically connected to a conductive channel at the interface between the barrier layer and the channel layer. The drain penetrates the passivation dielectric layer and is electrically connected to a conductive channel at the interface between the barrier layer and the channel layer. A gate is formed that is electrically connected to the top of the first barrier contact and the second barrier contact, respectively.

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