A semiconductor device and a manufacturing method thereof

Abstract

The present disclosure provides a semiconductor device and a manufacturing method thereof, which comprises a substrate, a groove formed on the substrate, a channel layer structure grown under the restriction of the groove structure, the channel layer structure exposing the upper surface of the substrate, a barrier layer covering the exposed channel layer structure, a two-dimensional electron gas and a two-dimensional hole gas respectively formed on the second surface and the first surface of the channel layer structure, and a source electrode, a gate electrode and a drain electrode formed on the first surface / second surface of the channel layer structure, and a bottom electrode formed on the second surface / first surface of the channel layer structure. The semiconductor device can reduce the gate leakage current, has high threshold voltage, high power and high reliability, can realize low on-resistance and the normally-off state of the device, can provide stable threshold voltage, so that the semiconductor device has good switching characteristics and is safer in use. The local electric field strength can be effectively reduced, and the overall performance and reliability of the device can be improved. The structure and preparation process of the semiconductor device are relatively simple, and the production cost can be effectively reduced.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor, and more particularly, to a semiconductor device with adjustable electric field distribution and a manufacturing method thereof. BACKGROUND

[0002] Group III nitride semiconductor is an important new type of semiconductor material, mainly including AlN, GaN, InN and compounds of these materials such as AlGaN, InGaN, AlInGaN, etc. With the advantages of direct band gap, wide band gap, high breakdown field strength, etc., through the optimization design of device structure and process, group III nitride semiconductor has great prospects in the field of power devices and radio frequency devices. One important device type of group III nitride semiconductor is high electron mobility and high hole mobility transistor, and it is desirable to realize high performance high electron mobility and high hole mobility transistor with high withstand voltage, high power, low on-resistance and high reliability, etc.

[0003] In order to utilize the high critical breakdown field characteristics of group III nitride semiconductor material to improve the voltage resistance of the device, many studies have been made in the prior art, such as increasing the thickness or mass of the channel layer in the vertical direction, and increasing the length of the drift region in the horizontal direction. However, the above improvements can increase the area of the device, increase the cost, even increase the on-resistance of the device, increase the power consumption, and reduce the switching speed, or the voltage resistance effect of the scheme used in the prior art is limited. Based on this, the present disclosure provides a novel semiconductor device structure and a manufacturing method thereof, which aims to overcome the above defects, provide a safe and energy-saving semiconductor device with simple process, low cost, high aspect ratio, higher channel density in unit area, high withstand voltage, high power and low on-resistance, etc. SUMMARY

[0004] Hereinafter, a brief summary will be given about the present disclosure in order to provide a basic understanding of some aspects of the present disclosure. It should be understood that this summary is not an exhaustive overview of the present disclosure. It is not intended to identify key or important parts of the present disclosure, nor is it intended to limit the scope of the present disclosure. Its purpose is only to give some concepts in a simplified form as a prelude to the more detailed description discussed later.

[0005] According to an aspect of the present disclosure, a manufacturing method of a semiconductor device is provided, comprising:

[0006] providing a substrate; forming a recess on the substrate, the side surface of the recess having a hexagonal symmetry lattice structure;

[0007] forming a single crystal seed layer on the side surface in the recess;

[0008] growing a channel layer structure along the groove with the single crystal seed layer as the core and being limited by the groove;

[0009] etching the substrate, the structure protruding from the etched substrate upper surface;

[0010] forming a barrier layer on the exposed structure, thereby forming a two-dimensional electron gas and immobile background positive charges on the first surface of the structure, and / or forming a two-dimensional hole gas and immobile background negative charges on the second surface of the structure;

[0011] forming a source, a gate, and a drain on the first / second surface of the structure, and forming a bottom electrode on the second / first surface of the channel layer.

[0012] Further, wherein step 400 is replaced by step 401, the step 401 comprises growing a first channel layer, a first adjustment layer, and a second channel layer structure along the groove with the single crystal seed layer as the core and being limited by the groove.

[0013] Further, wherein step 400 is replaced by step 402, the step 402 comprises growing a first channel layer, a second adjustment layer, and a second channel layer structure along the groove with the single crystal seed layer as the core and being limited by the groove.

[0014] Further, wherein step 400 is replaced by step 403, the step 403 comprises growing a first channel layer, a first adjustment layer, a second adjustment layer, and a second channel layer structure along the groove with the single crystal seed layer as the core and being limited by the groove.

[0015] Further, the bottom electrode is connected to at least one of the first adjustment layer, the second adjustment layer, and the two-dimensional electron gas / two-dimensional hole gas.

[0016] Further, the first / second adjustment layer has P-type doping when the bottom electrode is formed on the second surface of the channel layer, or the first / second adjustment layer has N-type doping when the bottom electrode is formed on the first surface of the channel layer.

[0017] Further, the first adjustment layer has a doping concentration less than 5E18 / cm 3 , and the second adjustment layer has a doping concentration of 1E17-5E19 / cm 3 .

[0018] Further, the source, the gate, and the drain are coplanar or not coplanar.

[0019] Further, the source and the drain are directly or indirectly formed on the channel layer, and the gate is directly or indirectly formed on the barrier layer.

[0020] Further, a buffer layer is deposited on the seed layer before growing the structure.

[0021] Further, the seed layer is disposed at a location corresponding to the source, a location corresponding to the drain, or at a location corresponding to between the gate and the drain.

[0022] Further, when the seed layer is disposed at a location corresponding to the drain, a current blocking layer is formed on the seed layer.

[0023] Further, when forming a HEMT device, the source and drain regions are N-type doped; when forming a HHMT device, the source and drain regions are P-type doped.

[0024] Further, a dielectric layer is formed on the side surface and the bottom surface of the recess.

[0025] According to another aspect of the present disclosure, a semiconductor device is provided, comprising:

[0026] a substrate;

[0027] the substrate has a side surface with a hexagonal symmetry lattice structure;

[0028] a single-crystal seed layer;

[0029] a channel layer structure grown with the seed layer as a core; the structure protrudes above the substrate;

[0030] a barrier layer formed on the protruding structure, further a two-dimensional electron gas and immobile background positive charge formed on a first face of the structure, and / or a two-dimensional hole gas and immobile background negative charge formed on a second face of the structure;

[0031] a source, a gate, a drain formed on the first / second face of the structure, a bottom electrode formed on the second / first face of the structure, wherein when the bottom electrode is formed on the second face of the structure, a HEMT device is formed; when the bottom electrode is formed on the first face of the structure, a HHMT device is formed.

[0032] Further, the channel layer structure is replaced with a first channel layer, a first modulation layer, and a second channel layer structure.

[0033] Further, the channel layer structure is replaced with a first channel layer, a second modulation layer, and a second channel layer structure.

[0034] Further, the channel layer structure is replaced with a first channel layer, a first modulation layer, a second modulation layer, and a second channel layer structure.

[0035] Further, the bottom electrode is connected to at least one of the first adjusting layer, the second adjusting layer and the two-dimensional electron gas / two-dimensional hole gas to adjust the distribution of electric field of the device.

[0036] Further, the first / second adjusting layer has P-type doping when the bottom electrode is formed on the second surface of the channel layer; or the first / second adjusting layer has N-type doping when the bottom electrode is formed on the first surface of the channel layer.

[0037] Further, the first adjusting layer has a doping concentration less than 5E18 / cm 3 ; and the second adjusting layer has a doping concentration of 1E17-5E19 / cm 3 .

[0038] Further, the source, the gate and the drain are coplanar or not coplanar.

[0039] Further, the seed layer further has a buffer layer thereon.

[0040] Further, the seed layer is arranged at a position corresponding to the source, a position corresponding to the drain or a position between the gate and the drain.

[0041] Further, when the seed layer is arranged at a position corresponding to the drain, a current blocking layer is further formed on the seed layer.

[0042] Further, when the HEMT device is formed, the source and drain regions further have N-type doping; and when the HHMT device is formed, the source and drain regions further have P-type doping.

[0043] Further, the recess further has a dielectric layer on the sidewall and the bottom surface.

[0044] According to another aspect of the present disclosure, there is provided a complementary semiconductor device, comprising any one of the HEMT device and the HHMT device.

[0045] According to another aspect of the present disclosure, there is provided a radio frequency device, comprising any one of the semiconductor device.

[0046] According to another aspect of the present disclosure, there is provided a power power device, comprising any one of the semiconductor device.

[0047] The scheme of the present disclosure can at least help to achieve one of the following effects: the semiconductor device can reduce gate leakage current, have high threshold voltage, high power, high reliability, achieve low on-resistance and off-state of the device, provide stable threshold voltage, and thus have good switching characteristics and be safer in use.

[0048] The scheme of the present disclosure can also help to achieve one of the following effects: the local electric field strength can be effectively reduced, and the overall performance and reliability of the device can be improved; the structure of the semiconductor device and the preparation process are relatively simple, and the production cost can be effectively reduced. BRIEF DESCRIPTION OF DRAWINGS

[0049] The specific content of the present disclosure will be described below with reference to the accompanying drawings, which will help to more easily understand the above and other purposes, features and advantages of the present disclosure. It should be understood that the drawings are only to illustrate the principles of the present disclosure, and the sizes and relative positions of the units are not necessarily drawn according to the scale in the drawings. In the drawings:

[0050] Figure 1 -15 shows a schematic diagram of a semiconductor device structure and a manufacturing method thereof according to a first embodiment;

[0051] Figure 16 -19 shows a schematic diagram of a semiconductor device structure and a manufacturing method thereof according to a second embodiment;

[0052] Figure 20 -23 shows a schematic diagram of a semiconductor device structure and a manufacturing method thereof according to a third embodiment;

[0053] Figure 24 -28 shows a schematic diagram of a semiconductor device structure and a manufacturing method thereof according to a fourth embodiment;

[0054] Figure 29 -31 shows a schematic diagram of a semiconductor device structure and a manufacturing method thereof according to a fifth embodiment;

[0055] Figure 32 -35 shows a schematic diagram of a semiconductor device structure and a manufacturing method thereof according to a sixth embodiment;

[0056] Figure 33 -39 shows a schematic diagram of a semiconductor device structure and a manufacturing method thereof according to a seventh embodiment; DETAILED DESCRIPTION

[0057] The exemplary disclosure of the present disclosure will be described hereinafter with reference to the drawings. For the purpose of clarity and a concise description, all the features that make up the present disclosure are not described in the specification. However, it should be appreciated that many decisions specific to the present disclosure can be made in the process of developing any such implementation of the present disclosure in order to achieve the specific goals of the developers, and these decisions can vary from one implementation of the present disclosure to another.

[0058] It should also be noted that, in the drawings, only the structures closely related to the scheme according to the present disclosure are shown, and other details not closely related to the present disclosure are omitted, in order to avoid obscuring the present disclosure with unnecessary details.

[0059] It should be understood that the present disclosure is not limited to the described embodiments by virtue of the following description with reference to the drawings. In the present disclosure, features between different embodiments can be replaced or borrowed, and one or more features can be omitted in one embodiment, if possible.

[0060] Reference will now be made to the drawings in the following detailed description of specific embodiments. The drawings are diagrammatic and schematic representations of actual or conceptual structures, devices, and processes, and should not necessarily be construed as limiting the present disclosure to only the embodiments described herein. In the drawings, like reference numerals designate similar, but not necessarily identical, elements. Additionally, it should be understood that the drawings are not necessarily drawn to scale.

[0061] As used in the specification and the appended claims, the singular forms "a," "an" and "the" include plural references unless the context clearly dictates otherwise. It will also be understood that the term "and / or," as used herein, refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0062] In particular, the semiconductor device of the present disclosure is a compound semiconductor device comprising a nitride semiconductor material, also referred to as a nitride semiconductor device, wherein the nitride semiconductor device is a Group III nitride semiconductor device. Further, the Group III nitride semiconductor device comprises a transistor using a Wurtzite Group III nitride semiconductor material. Still further, the transistor is a GaN transistor comprising a GaN semiconductor material. In particular, the GaN transistor is a normally-off transistor GaN-HEMT and / or GaN-HHMT.

[0063] First embodiment

[0064] Reference Figure 1 -Figure 15 A semiconductor device and a method for manufacturing the same according to a first embodiment will be described.

[0065] like Figure 1 As shown in FIG-15 , in a first embodiment, the semiconductor device includes a substrate 100. The material of the substrate 100 can be selected based on actual needs. The present disclosure does not limit the specific material of the substrate 100. Any substrate material can be used as long as the side surfaces of the vertical grooves formed perpendicular to the surface plane thereof have a hexagonal symmetric lattice structure. For example, the material of the substrate 100 can be Si, Al 2 O 3 , SiC, GaN, etc.

[0066] Since silicon substrates have advantages such as low price and strong processability, the present disclosure will further illustrate the Si substrates as an example. Figure 1 As shown, the single crystal silicon substrate can be a silicon substrate with a (110) or (112) surface. A substrate 100 is provided, and the substrate has a first surface 1001; a first dielectric layer 101 is formed on the first surface 1001 of the substrate 100. Exemplarily, the first dielectric layer 101 is a SiO2 layer formed by thermal oxidation or vapor deposition. Exemplarily, the thickness of the first dielectric layer 101 is about 0.5 microns. It should be noted that the numerical ranges described in the present invention are only examples and not limitations of the present disclosure. The first dielectric layer 101 has a first surface 1011 parallel to the first surface 1001 of the substrate. Part of the first dielectric layer 101 and the substrate 100 thereunder are etched to form a plurality of vertical grooves. Specifically, the grooves are first grooves 102 and second grooves 102' arranged at intervals, and the first and second grooves have the same structure and size. Exemplarily, the depth of the first groove and the second groove is about 5 microns. The lower part of the first surface 1021 and the second surface 1022 of the groove is respectively formed by the second surface 1002 and the third surface 1003 exposed by the substrate, wherein the second surface 1002 and the third surface 1003 of the substrate have a hexagonal symmetrical lattice structure, such as Si (111) plane. It is understood that the second surface and the third surface of the substrate can also be Al2O3 (0001), SiC (0001), or SiC , GaN(0001), or GaN The first surface 1021 and the second surface 1022 of the groove are respectively composed of the second surface 1012 and the third surface 1013 of the first dielectric layer 101. The second dielectric layer 103 is formed on the third surface 1023 of the groove, which is exemplarily a silicon dioxide layer formed by oxidation, and the thickness thereof is exemplarily about 500 nm. The fourth dielectric layer 105 is formed on the first surface 1021 and the second surface 1022 of the groove, and the thickness thereof is exemplarily about 100 nm, which can avoid the interaction between the silicon substrate and the Ga-containing precursor during epitaxy and is more conducive to improving the selectivity during epitaxy. Further, the fourth dielectric layer 104 on the second surface of the first groove and on the first surface of the second groove is removed partially, and a single-crystal seed layer 106 is formed on the third surface 1003 of the substrate 100 exposed in the first groove and on the second surface 1002 of the substrate 100 exposed in the second groove. Exemplarily, the single-crystal seed layer is an ALN layer, the growth direction of the ALN crystal is the direction of <0001>, and the surface thereof is the (0001) plane. Exemplarily, the position of the single-crystal seed layer corresponds to the position of the source of the subsequent device. Since the subsequent device structure is referenced to the source, the semiconductor device structure can exhibit a symmetrical structure, and the voltage of the source region is very low, and the crystal quality of the nucleation region is poor. Therefore, based on the low voltage of the first electrode region, the influence of the poor crystal quality of the nucleation region is minimized. Then, the channel layer 201 is selectively grown from the seed layer 106, and the channel layer 201 can be a nitride, exemplarily such as an intrinsic GaN (i-GaN) or an unintentionally doped GaN layer. Due to the presence of the groove 102, the channel layer 201 starts to grow from the seed layer along the groove 102, wherein the growth includes growth in the first direction along the length of the groove and growth in the second direction perpendicular to the groove. The channel layer 201 can also grow outside the groove, and the channel layer 201 outside the groove is removed by planarization or etching technology.

[0067] The channel layer is etched on both sides to remove the first insulating layer 101 and part of the substrate 100, so that the channel layer 201 protrudes from the fourth surface 1004 of the substrate 100 after etching. The channel layer 201 has a first surface 2013 with spontaneous and piezoelectric polarization effects and a second surface 2014 opposite to the first surface 2013 with spontaneous and piezoelectric polarization effects. When the channel layer is GaN, the first surface 2013 is the (0001) plane, and the second surface 2014 is the (0000 1) plane. A third dielectric layer 107, for example a silicon dioxide layer, is formed on the etched substrate 100 to isolate the exposed silicon substrate. A barrier layer 202, which is an AlN layer or an AlGaN layer, is then formed on the channel layer 201, and a two-dimensional electron gas 2DEG and a two-dimensional hole gas 2DHG are formed on the first surface 2013 and the second surface 2014 of the channel layer 201 respectively, and there are also immobile background positive charges and background negative charges at the interface, wherein the background positive charges attract the two-dimensional electron gas 2DEG and the background negative charges attract the two-dimensional hole gas 2DHG, that is, a complementary charge vertical channel device structure is formed.

[0068] A source electrode 401, a gate electrode 402, a drain electrode 403 and a bottom electrode 404 are then formed on the barrier layer 202 along the direction of the channel length. It can be understood that when the device formed is a HEMT, the source electrode and the drain electrode can also be formed on the channel 201 along the direction of the two-dimensional electron gas transmission, and the bottom electrode is in electrical contact with the two-dimensional hole gas; when the device formed is a HHMT, the source electrode and the drain electrode can also be formed on the channel 201 along the direction of the two-dimensional hole gas transmission, and the bottom electrode is in electrical contact with the two-dimensional electron gas; the bottom electrode can be an independently controlled electrode, or can be electrically connected with the source electrode or the gate electrode. The position of the bottom electrode can be between the gate electrode and the drain electrode, or between the source electrode and the gate electrode, or below the gate electrode.

[0069] Due to the presence of the groove, the channel layer can grow very flat when it is grown in a lateral epitaxial manner, and the vertical surface of the semiconductor device including the channel layer can be defined very flat by means of the groove, so that a higher aspect ratio is easily achieved. More specifically, when the channel layer 201 is used as a vertical channel, a higher channel density per unit area can be achieved, thereby reducing the resistance of the device and improving the performance of the device.

[0070] After the bottom electrode 404 is provided, when the device is turned on, the HEMT (high electron mobility transistor) is taken as an example Figure 15As shown, current flows from drain to source (electrons flow from source to drain), in which case the bottom electrode has no effect on the current flow; when the device is off, the drain is at a high voltage, in which case the channel is off, the 2DEG from gate to drain is depleted due to the high voltage at the drain, and only the background positive charge remains. At the same time, due to the voltage at the bottom electrode being much lower than the voltage at the drain, the 2DHG connected to the bottom electrode is also partially depleted due to the electric field, leaving behind background negative charge. The background negative charge can generate an electric field that counteracts part of the electric field in the 2DEG, and the background negative charge and the background positive charge remaining above make the electric field distribution more uniform, thereby reducing the local electric field strength. For a HHMT (high hole mobility transistor) device, similarly to the HEMT device, when the device is on, current flows from drain to source (holes flow from drain to source). The bottom electrode has no effect on the current flow. When the device is off, the drain is at a high negative voltage, in which case the 2DHG from gate to drain is depleted, leaving behind background negative charge. At this time, due to the voltage at the bottom electrode being much higher than the voltage at the drain, the 2DEG connected to the bottom electrode is also partially depleted due to the electric field, leaving behind background positive charge. The background positive charge can partially counteract the electric field of the background negative charge in the 2DHG channel layer, making the electric field distribution more uniform.

[0071] Reference will now be made in detail to the manufacturing method for manufacturing the semiconductor device of the first embodiment, as shown in Figure 1 -14, which will be described in detail below. Figure 1 , 2 , 6, 10 are cross-sectional views, Figure 3 -5, 7-14 are top views.

[0072] Step 1: As shown in Figure 1 , a substrate 100 is provided, which can be a silicon substrate with a (110) or (112) surface. A first dielectric layer 101 is formed on the first surface 1001 of the substrate 100. The first dielectric layer 101 is, for example, a thermal oxidation or vapor deposition formed SiO2 layer. The thickness of the first dielectric layer 101 is, for example, about 0.5 microns.

[0073] Step 2: As shown in Figure 2As shown in FIG. 1, a first dielectric layer 101 is formed on a substrate 100. The substrate 100 can be a single crystal silicon wafer. The first dielectric layer 101 can be a silicon dioxide layer. The first dielectric layer 101 is patterned by photolithography to expose a portion of the first dielectric layer 101. The substrate 100 and the first dielectric layer 101 are etched to form a vertical trench structure 102. The trench structure 102 includes a first trench 102 and a second trench 102'. The first and second trenches 102 and 102' are spaced apart. The substrate 100 is exposed at the bottom of the first and second trenches 102 and 102'. The exposed substrate 100 has a second surface 1002 and a third surface 1003. The second and third surfaces 1002 and 1003 have a hexagonal lattice structure, such as a Si(111) surface. As described above, the second surface of the substrate can also be an Al2O3(0001), SiC(0001), GaN(0001), or GaN(0001) surface.

[0074] Step 3: As shown in FIG. 2, a sacrificial layer 104 is deposited on the structure formed in Step 2. The sacrificial layer 104 is a silicon nitride layer having a thickness of about 100 nm. It is understood that the first dielectric layer and the sacrificial layer are selected to have a high etching selectivity therebetween. For example, the etchant used to etch the sacrificial layer does not substantially etch the first dielectric layer or etches the first dielectric layer very slowly. Figure 3

[0075] Step 4: As shown in FIG. 3, dry etching is performed to remove the sacrificial layer 104 on the first surface of the first dielectric layer 101 and on the third surface 1023 of the trench 102. The sacrificial layer 104 on the first surface 1021 and the second surface 1022 of the trench 102 is retained. Figure 4

[0076] Step 5: As shown in FIG. 4, a second dielectric layer 103 (silicon dioxide layer) is formed on the third surface 1023 of the trench 102 by an oxidation process. The first surface and the second surface of the trench 102 are protected by the retained sacrificial layer 104 and are not oxidized. The second dielectric layer 103 prevents the gallium atoms of the nitride semiconductor from being incompatible with the silicon substrate and prevents the melt-back phenomenon when the nitride semiconductor is subsequently grown. The second dielectric layer 103 also effectively blocks the leakage current between the nitride semiconductor and the silicon substrate and reduces the parasitic capacitance of the silicon substrate. Figure 5

[0077] Step 6: As shown in FIG. 5, the sacrificial layer 104 on the first and second surfaces of the trench 102 is removed by selective wet etching using the etching selectivity between the sacrificial layer 104 and the second dielectric layer 103 (silicon dioxide layer). Figure 6 Step 7: As shown in FIG. 6, a nitride semiconductor layer 105 is grown on the second dielectric layer 103. The second dielectric layer 103 prevents the gallium atoms of the nitride semiconductor from being incompatible with the silicon substrate and prevents the melt-back phenomenon when the nitride semiconductor is subsequently grown. The second dielectric layer 103 also effectively blocks the leakage current between the nitride semiconductor and the silicon substrate and reduces the parasitic capacitance of the silicon substrate.​​​​​

[0078] Step 7: Figure 7 As shown, a relatively thin fourth dielectric layer 105 (silicon dioxide layer) is formed on the first and second surfaces of the groove 102 through an oxidation process. The thickness of the fourth dielectric layer is set differently from the thickness of the first and second dielectric layers so that when the fourth dielectric layer is subsequently removed, the first and second dielectric layers are still thick enough to protect the substrate. These dielectric layers can prevent incompatibility between gallium atoms and the silicon substrate during the subsequent growth of the nitride semiconductor, preventing melt-back.

[0079] Step 8: Figure 8 As shown, photoresist is applied and a photolithography pattern is formed between the first groove and the second groove to expose the first dielectric layer 101 between the first groove and the second groove. It is understood that the photolithography pattern can expose the entire first dielectric layer 101 between the first groove and the second groove.

[0080] Step 9: Figure 9 As shown, the fourth dielectric layer 105 exposed on the second surface of the first groove and on the first surface of the second groove is removed. Since the thickness of the first dielectric layer is much greater than that of the fourth dielectric layer, during the process of removing part of the first dielectric layer, the exposed first dielectric layer portion is only etched by a small thickness and is not completely removed. Then, the photoresist is removed, thereby exposing a portion of the third surface 1003 of the substrate 100 in the first groove and a portion of the second surface 1002 of the substrate 100 in the second groove.

[0081] Step 10: Figure 9 As shown, due to the melt-back effect between the silicon substrate and gallium, GaN cannot be deposited directly on the silicon substrate. It is usually necessary to deposit an AlN seed layer first, and then form the subsequent nitride semiconductor structure on this basis. Therefore, a single crystal AlN seed layer 106 is formed on the third surface 1003 of the substrate 100 exposed in the first groove, and on the second surface 1002 of the substrate 100 exposed in the second groove. The growth direction of the single crystal AlN crystal is <0001>, and the surface is the (0001) plane. It should be pointed out that the selectivity of AlN is very low. Under normal process conditions, polycrystalline or amorphous AlN is easily generated on the dielectric layer, which is not conducive to the formation of the desired structure. Therefore, it is necessary to remove the AlN on the silicon dioxide layer after the seed layer is formed. Alternatively, a chlorine-containing gas is introduced when growing the AlN seed layer to ensure that it grows only on the silicon substrate and not on the silicon dioxide layer.

[0082] It is understood that if other substrates such as Al2O3 are used, the seed layer can also be GaN. In this case, by adjusting the process, it is relatively easy to achieve nucleation only on the exposed substrate surface.

[0083] Step 11: Figure 10 As shown, a channel layer 201 is then grown epitaxially with the seed layer 106 as the core. Due to the presence of the groove 102, the channel layer 201 begins to grow epitaxially from the seed layer along the groove 102. The growth includes growth along a first direction of the groove and growth in a second direction perpendicular to the groove. The channel layer 201 can also grow outside the groove and is removed by planarization or etching techniques. Lateral epitaxy can effectively improve the quality of the nitride semiconductor crystal in the lateral epitaxial region, thereby improving the electrical performance of the device. Removing the channel layer outside the groove can prevent the device from being essentially unconstrained during the formation process, which is conducive to forming a specific structure and size. It is particularly advantageous and easy to implement for forming devices with a high aspect ratio, enriching the means of realizing high-aspect ratio devices in addition to adjusting the growth process parameters. Since the growth of the channel layer in the groove is restricted by the first surface and the second surface of the groove, the growth process of the channel layer avoids the situation where it cannot be maintained completely vertical or the growth surface is not in the same plane, and the possibility of multiple and complex growth surfaces, which is extremely convenient for achieving control of the device and improving the electrical performance. It can be understood that the growth of the channel layer 201 outside the groove does not need to be removed, but a portion protruding from the groove is formed.

[0084] Step 12: Figure 11 As shown, a photolithographic pattern is formed to expose the entire area between the adjacent first groove and the second groove, and the first dielectric layer 101 and part of the substrate 100 material in the area are etched so that the channel layer covered with the fourth dielectric layer in the groove 102 protrudes from the fourth surface 1004 of the substrate after etching.

[0085] Step 13: Figure 12 As shown, a third dielectric layer 107 is formed on the fourth surface 1004 of the etched substrate 100. The third dielectric layer can be, for example, a silicon dioxide layer formed by oxidation. Then, the fourth dielectric layer covering the channel layer 201 is removed, thereby exposing the first surface of the channel layer 201 having a piezoelectric effect and the second surface opposite thereto having spontaneous and piezoelectric polarization effects.

[0086] Step 14: Figure 13As shown, a barrier layer 202 is then formed on the channel layer 201 , and the barrier layer can be the AlN layer or the AlGaN layer, thereby forming a two-dimensional electron gas 2DEG and a two-dimensional hole gas 2DHG on the first surface 2013 and the second surface 2014 of the channel layer, respectively.

[0087] It is understandable that before growing the channel layer, a buffer layer may be deposited first.

[0088] Step 15: Figure 14 As shown, an insulating layer can be deposited, photolithographically etched, and then metal deposited thereon. For a HEMT, a source and drain are formed on the first surface of the channel layer 201 along the two-dimensional electron gas transport direction, and a gate is formed on the barrier layer 202 along the two-dimensional electron gas transport direction, with the gate located between the source and drain. Alternatively, the source, gate, and drain are all formed on the barrier layer 202 along the two-dimensional electron gas transport direction. A bottom electrode 204 is formed on the second surface of the two-dimensional hole gas transport direction. For a HHMT, a source and drain are formed on the second surface of the channel layer 201 along the two-dimensional hole gas transport direction, and a gate is formed on the barrier layer 202 along the two-dimensional hole gas transport direction, with the gate located between the source and drain. Alternatively, the source, gate, and drain are all formed on the barrier layer 202 along the two-dimensional hole gas transport direction. A bottom electrode 204 is formed at the first surface of the two-dimensional electron gas.

[0089] Second embodiment

[0090] Reference Figure 16 -19 to describe a semiconductor device and a method for manufacturing the same according to a second embodiment, Figure 16 -19 are all top views.

[0091] The second embodiment is different from the first embodiment in that in the second embodiment, a first sub-layer 2011 of the channel layer, a first adjustment layer 2013, and a second sub-layer 2012 of the channel layer are formed in the recess along the direction of the first surface and the second surface of the channel, and the first sub-layer 2011, the first adjustment layer 2013, and the second sub-layer 2012 completely fill the recess so that the respective first surfaces are coplanar. It can be understood that the adjustment layer can have P-type doping or N-type doping, and exemplary P-type doping is P-type GaN, and exemplary N-type doping is N-type GaN, and the doping concentration is exemplary less than 5E18 / cm3. The specific selection of P-type doping or N-type doping depends on the specific type of subsequent device, and for HEMT devices, P-type doping is selected, and for HHMT devices, N-type doping is selected. It can be understood that the doping can be gradual. The projection of the first adjustment layer on the first surface of the channel layer falls within the range between the gate and the drain, or partially overlaps the projection of the gate in the direction.

[0092] The adjustment layer with doping is arranged vertically or obliquely to the surface of the channel layer, and through the designed doping distribution, the external electric field is reacted and the electric field distribution is changed when the device is off, so that the local electric field strength can be effectively reduced, and the electric field peak near the gate end of the drain is particularly reduced. The adjustment layer here is preferably formed laterally and epitaxially, which does not have serious defects such as ion implantation damage compared with ion implantation, and has good electrical performance

[0093] When the device is off, the adjustment layer is electrically connected through the bottom electrode, so that the potential instability of the electric field adjustment doping layer is avoided. It can be understood that the bottom electrode can not be provided and only the floating electric field adjustment doping layer can be relied on to reduce the local electric field strength.

[0094] It can be understood that the bottom electrode is in electrical contact with the two-dimensional charge carrier gas and the adjustment layer, so that the doping of the adjustment layer and the background charge of one type of complementary channel offset part of the electric field in the other type of two-dimensional charge carrier, so as to achieve the purpose of reducing the local electric field strength.

[0095] The manufacturing method for manufacturing the semiconductor device of the second embodiment will be described in detail below.

[0096] Step 11': as Figure 16As shown in Figure 19, after forming the seed layer 106, a first sublayer 2011 of the channel layer is selectively grown with the seed layer 106 as the core. Due to the presence of the groove 102, the first sublayer 2011 begins to epitaxially grow laterally from the seed layer along the groove 102, wherein the growth includes growth in a first direction along the first or second surface of the groove, as well as growth perpendicular to the third surface of the groove. Then, a doped first adjustment layer 2013 is grown with the first sublayer 2011 as the core. The growth of the first adjustment layer 2013 also includes growth in a first direction along the first or second surface of the groove, growth in a second direction perpendicular to the first or second surface of the groove, and growth perpendicular to the third surface of the groove. As previously described, the projection of the first adjustment layer 2013 on the first surface of the channel layer falls within the range between the gate and the drain, or partially overlaps with the projection of the gate in the aforementioned direction.

[0097] Then, with the first adjustment layer 2013 as the core, the second sublayer 2012 of the channel layer is grown. The second sublayer can also be an intrinsic GaN layer or an unintentionally doped GaN layer. The growth direction of the second sublayer 2012 is the same as the growth direction of the first sublayer or the adjustment layer. Finally, the portions of the first sublayer, the adjustment layer, and the second sublayer that grew perpendicular to the third surface of the groove and were located outside the groove are removed through planarization or etching techniques, thereby ensuring that the first sublayer, the adjustment layer, and the second sublayer are all located within the groove, forming a coplanar structure. The coplanar structure can ensure that the device is not in a basically unconstrained state during the formation process, which is conducive to the formation of specific structures and dimensions. It is particularly advantageous and easy to implement for forming devices with a high aspect ratio, and enriches the means of realizing high-aspect ratio devices in addition to adjusting the growth process parameters. Since the growth of the channel layer and the adjustment layer in the groove is restricted by the first surface and the second surface of the groove, the growth process of the channel layer and the adjustment layer avoids the situation where they cannot be kept completely vertical or the growth surfaces are not in the same plane, and the possible appearance of multiple and complex growth surfaces, which makes it extremely convenient to control the device and improve the electrical performance.

[0098] Third embodiment

[0099] Reference Figure 20 -23 to describe a semiconductor device and a method for manufacturing the same according to a third embodiment, as shown in FIG. Figure 20 -23 is the top view.

[0100] The third embodiment is different from the second embodiment in that in the third embodiment, a first sub-layer 2011 of the channel layer, a second adjustment layer 2014, and a second sub-layer 2012 of the channel layer are formed in the recess along the direction of the first surface and the second surface of the channel, and the first sub-layer, the second adjustment layer 2014, and the second sub-layer completely fill the recess so that the respective first surfaces are coplanar. The second adjustment layer is used to control the threshold voltage. It can be understood that the first and second adjustment layers have P-type doping or N-type doping, and the P-type doping is exemplarily P-type GaN, and the N-type doping is exemplarily N-type GaN, wherein the doping concentration of the second adjustment layer 2014 is exemplarily 1E17-5E19 / cm3, and more preferably 1E+18 / cm3-5E+19 / cm3. The P-type GaN layer can deplete the two-dimensional electron gas on the first surface of the channel layer, and the N-type GaN layer can deplete the two-dimensional hole gas on the second surface of the channel layer, thereby causing the device to have a normally-off state. The specific selection of P-type doping or N-type doping depends on the specific type of subsequent device. For an HEMT device, P-type doping is selected, and for an HHMT device, N-type doping is selected. It can be understood that the doping can be gradual. The projection of the second adjustment layer on the first surface of the channel layer falls within the range of the gate. The second adjustment layer can be set, such as its doping concentration, size parameters, etc., by device parameter setting to satisfy the depletion of 95%-100% of the two-dimensional electron gas or two-dimensional hole gas above it. The higher the concentration of the two-dimensional charge carrier gas, the higher the corresponding doping concentration can be increased.

[0101] When the device is in an off state, the bottom electrode can be connected to the first adjustment layer and the two-dimensional carrier, or connected to the two-dimensional carrier. When the HEMT device is formed, the bottom electrode is connected to the two-dimensional hole gas, and when the HHMT device is formed, the bottom electrode is connected to the two-dimensional electron gas. The connection mode of the bottom electrode causes the second adjustment layer and the two-dimensional carrier to act together or alone, avoiding the case that the electric field adjustment doping layer potential is unstable.

[0102] The manufacturing method for manufacturing the semiconductor device of the third embodiment will be described in detail below, wherein the third embodiment is different from the foregoing embodiments in that:

[0103] Step 11': as Figure 20As shown in Fig. 23, after the seed layer 106 is formed, a first sub-layer 2011 of the channel layer is selectively grown with the seed layer 106 as the core. Due to the presence of the groove 102, the first sub-layer 2011 starts to grow laterally from the seed layer along the groove 102, wherein the growth includes growth along the first direction of the first or second surface of the groove, and growth perpendicular to the third surface of the groove. Then, with the first sub-layer 2011 as the core, a doped second adjustment layer 2014 is grown, which also includes growth along the first direction of the first or second surface of the groove, growth along the second direction of the first or second surface of the groove, and growth perpendicular to the third surface of the groove. As mentioned above, the adjustment layer 203 is located in the projection range of the gate electrode in the subsequent device projection direction. Then, with the second adjustment layer 2014 as the core, a second sub-layer 2012 of the channel layer is grown, which can also be an intrinsic GaN layer or a non-intentionally doped GaN layer. The growth direction of the second sub-layer 2012 is the same as that of the first sub-layer or the adjustment layer. Finally, through planarization or etching technology, the portions of the first sub-layer, the second adjustment layer and the second sub-layer located outside the groove due to growth perpendicular to the third surface of the groove are removed, so that the first sub-layer, the second adjustment layer and the second sub-layer are all located in the groove, forming a coplanar structure. The coplanar structure can make the device in the forming process not in a substantially unconstrained state, which is conducive to forming a specific structure and size, is particularly advantageous and easy to implement for forming a device with a high aspect ratio, enriches the means for realizing a high aspect ratio device in addition to adjusting the growth process parameters, and due to the growth of the channel layer and the adjustment layer in the groove being limited by the first surface and the second surface of the groove, the growth process of the channel layer and the adjustment layer avoids the case that the growth surface cannot be kept completely vertical or the growth surface is not in the same plane, and multiple or complex growth surfaces can occur, which is extremely convenient for controlling the device and improving the electrical performance.

[0104] Fourth Embodiment

[0105] Referring to Figure 24 The semiconductor device and the method for manufacturing the same according to the fourth embodiment are described with reference to Fig. 28, which is a top view. Figure 24

[0106] ​The third embodiment is different from the second embodiment in that in the third embodiment, a first sub-layer 2011 of the channel layer is formed in the recess along the direction of the first surface and the second surface of the channel, and a second adjustment layer 2014, a first adjustment layer 2013, and a second sub-layer 2012 of the channel layer are formed in the recess, the first sub-layer, the second adjustment layer 2014, the first adjustment layer 2013, and the second sub-layer completely fill the recess so that the respective first surfaces are coplanar. The second adjustment layer is used to control the threshold voltage, and the first adjustment layer is used to adjust the electric field distribution, in particular, the electric field distribution at the edge of the gate electrode. It can be understood that the first and second adjustment layers have P-type doping or N-type doping, and the P-type doping is exemplarily P-type GaN, and the N-type doping is exemplarily N-type GaN, wherein the doping concentration of the second adjustment layer 2014 is exemplarily 1E17-5E19 / cm3, and more preferably 1E+18 / cm3-5E+19 / cm3. The P-type GaN layer can deplete the two-dimensional electron gas of the first surface of the channel layer; the N-type GaN layer can deplete the two-dimensional hole gas of the second surface of the channel layer, thereby causing the device to have a normally closed state; and the specific selection of P-type doping or N-type doping depends on the specific type of the subsequent device, and for an HEMT device, P-type doping is selected, and for an HHMT device, N-type doping is selected. It can be understood that the doping can be gradual. The projection of the second adjustment layer on the first surface of the channel layer falls within the range of the gate electrode; the projection of the first adjustment layer on the first surface of the channel layer falls within the range between the gate electrode and the drain electrode, or partially overlaps with the projection of the gate electrode in the direction. The second adjustment layer can be set, such as its doping concentration, size parameter, etc., to satisfy the depletion of 95%-100% of the two-dimensional electron gas or two-dimensional hole gas above it, and the higher the concentration of the two-dimensional charge carrier gas, the higher the corresponding doping concentration can be increased. The doping concentration of the first adjustment layer is exemplarily less than 5E18 / cm3.

[0107] The first and second adjustment layers doped therein are arranged vertically or obliquely to the surface of the channel layer, and by designing the doping distribution, the external electric field is reacted and the electric field distribution is changed when the device is turned off, so that the local electric field strength can be effectively reduced, and in particular, the electric field peak near the gate end of the drain can be reduced. The adjustment layer here is preferably formed laterally by epitaxy, and compared with ion implantation, there is no serious defect such as ion implantation damage, and the electrical performance is good

[0108] When the device is in off state, the bottom electrode can be electrically connected to the first adjusting layer, the second adjusting layer and the two-dimensional carrier gas in various combinations, for example, the bottom electrode can be connected to the first adjusting layer and / or the second adjusting layer, can be connected to the first adjusting layer and the two-dimensional carrier gas, or can be connected to the first adjusting layer, the second adjusting layer and the two-dimensional carrier gas at the same time, and so on. The first adjusting layer, the second adjusting layer and the two-dimensional carrier gas are combined in various combinations, and the individual or synergistic effect of the various combinations is achieved, so that the instability of the electric field adjusting doped layer potential is avoided.

[0109] The manufacturing method for manufacturing the semiconductor device of the fourth embodiment will be described in detail below, wherein the fourth embodiment is different from the foregoing embodiments in that:

[0110] Step 11': as Figure 24As shown in Fig. 28, after the seed layer 106 is formed, a first sub-layer 2011 of the channel layer is selectively grown with the seed layer 106 as the core. Due to the presence of the groove 102, the first sub-layer 2011 starts to grow laterally from the seed layer along the groove 102, wherein the growth includes growth along the first direction of the first or second surface of the groove, and growth perpendicular to the third surface of the groove. Then, with the first sub-layer 2011 as the core, a doped second adjustment layer 2014 is grown, which also includes growth along the first direction of the first or second surface of the groove, growth along the second direction perpendicular to the first or second surface of the groove, and growth perpendicular to the third surface of the groove. As described above, the second adjustment layer 2014 is located in the projection range of the gate electrode in the projection direction of the subsequent device. Then, with the second adjustment layer 2014 as the core, a doped first adjustment layer 2013 is grown, which also includes growth along the first direction of the first or second surface of the groove, growth along the second direction perpendicular to the first or second surface of the groove, and growth perpendicular to the third surface of the groove. As described above, the first adjustment layer 2013 is located in the range from the gate electrode to the drain electrode in the projection direction of the subsequent device, or partially overlaps with the projection of the gate electrode. Then, with the first adjustment layer 2013 as the core, a second sub-layer 2012 of the channel layer is continuously grown, which can also be an intrinsic GaN layer or a non-intentionally doped GaN layer. The growth direction of the second sub-layer 2012 is the same as that of the first sub-layer or the adjustment layer. Finally, through planarization or etching technology, the portions of the first sub-layer, the adjustment layer, and the second sub-layer located outside the groove due to growth perpendicular to the third surface of the groove are removed, so that the first sub-layer, the adjustment layer, and the second sub-layer are all located in the groove, forming a coplanar structure. The coplanar structure can make the device not in a substantially unrestrained state during the formation process, which is conducive to the formation of a specific structure and size, is particularly advantageous and easy to implement for forming a device with a high aspect ratio, and enriches the means for realizing a high-aspect-ratio device in addition to adjusting growth process parameters. Since the growth of the channel layer and the adjustment layer in the groove is limited by the first surface and the second surface of the groove, the growth process of the channel layer and the adjustment layer avoids the situation that the growth surface cannot remain completely vertical or in the same plane, and multiple or complex growth surfaces can occur, which is extremely convenient for controlling the device and improving the electrical performance.

[0111] Fifth embodiment

[0112] Reference is made to the accompanying drawings Figure 29-31. The difference between the fifth embodiment and the second embodiment or the fourth embodiment is that one side of the channel layer is etched to remove the first dielectric layer 101 and part of the substrate 100, so that the substrate has a first surface and a fifth surface lower than and parallel to the first surface. When forming a HEMT, the first surface 2013 of the channel layer 201 with spontaneous and piezoelectric polarization effects is exposed. When the channel layer is GaN, the first surface 2013 is a (0001) surface. The second surface 2014 with spontaneous and piezoelectric polarization effects opposite to the first surface 2013 is still covered by the substrate and the first dielectric layer. The second surface 2014 is GaN. When forming the HHMT, the second surface 2014 of the channel layer 201 having the spontaneous and piezoelectric polarization effects is exposed. When the channel layer is GaN, the second surface 2014 is The first surface 2013, which has both spontaneous and piezoelectric polarization effects and is opposite to the second surface 2014, is still covered by the substrate and the first dielectric layer. The first surface 2013 is the (0001) surface of GaN. A third dielectric layer 107 is formed on the etched substrate 100 to isolate the exposed silicon substrate. The third dielectric layer can be, for example, a silicon dioxide layer. A barrier layer 202 is then formed on the first surface 2013 or the second surface 2014 of the channel layer 201. The barrier layer can be the AlN layer or the AlGaN layer, thereby forming a two-dimensional electron gas (2DEG) on the first surface 2013 of the channel layer or a two-dimensional hole gas (2DHG) on the second surface 2014 of the channel layer.

[0113] Thus, the bottom electrode 204 is connected to the first adjustment layer 2013 or the bottom electrode is connected to the first adjustment layer 2013 and the second adjustment layer 2014, and then reacts to the external electric field and changes the electric field distribution when the device is turned off, thereby effectively reducing the local electric field strength, especially reducing the electric field peak at the gate end close to the drain.

[0114] A method for manufacturing the HEMT semiconductor device of the fifth embodiment will now be exemplarily described with reference to Figures 29 to 31 in conjunction with the manufacturing methods of the aforementioned embodiments.

[0115] Step 12', such as Figure 29As shown, a photolithographic pattern is formed to expose the area on the first side 2013 of the channel layer. The first dielectric layer 101 and a portion of the substrate 100 in this area are then etched, exposing the fourth dielectric layer on the first side of the channel layer 201 having both spontaneous and piezoelectric polarization effects. The second side 2014 having both spontaneous and piezoelectric polarization effects, opposite the first side 2013, remains surrounded by the fourth dielectric layer, the substrate, and the first dielectric layer.

[0116] Step 13', such as Figure 30 As shown, a third dielectric layer 107' is formed on the etched substrate 100. The third dielectric layer can be an oxidized silicon dioxide layer. The third dielectric layer isolates the exposed silicon substrate and removes the fourth dielectric layer covering the first surface 2013 of the channel layer 201.

[0117] Step 14', such as Figure 31 As shown, a second semiconductor layer 202 is then formed on the first surface 2013 of the channel layer 201 by chemical deposition. The second semiconductor layer may be the AlN layer or the AlGaN layer, thereby forming a two-dimensional electron gas 2DEG on the first surface 2013 of the channel layer.

[0118] It is understandable that the manufacturing method of the HHMT semiconductor device is similar thereto and will not be described in detail here.

[0119] It is understandable that in the second, fourth, and fifth embodiments, a photolithographic pattern can also be formed to expose the entire area between the adjacent first grooves and the second grooves, and the first dielectric layer 101 and part of the material of the substrate 100 in the area are etched so that the channel layer covered with the fourth dielectric layer in the groove 102 protrudes from the fourth surface of the substrate after etching, and then only the area on the first surface / second surface side of the channel layer is further etched. The specific method can be referred to the aforementioned embodiment and will not be repeated here.

[0120] Sixth Implementation Plan

[0121] The sixth embodiment differs from the previous embodiment only in that the position of the single crystal seed layer corresponds to the formation position of the third electrode (drain) of the subsequent device. In order to avoid problems such as poor crystal quality and large leakage current in the active nucleation area, Figure 32 As shown, a current blocking layer can be added on the single crystal seed layer. The current blocking layer can be, for example, heavily doped with C or Fe elements. The doping range of C or Fe can be 1E17-1E20 / cm 3 .

[0122] Alternatively, the position of the single-crystal seed layer can also be arranged in the region between the second electrode and the third electrode. Illustratively, by arranging the position of the seed layer away from the position of the subsequent drain electrode region by a certain distance, the above technical problem can be overcome.

[0123] The region of the single-crystal seed layer can be opened by the arrangement of a photoetching pattern to open the regions of the first and second recesses.

[0124] The formation of the current blocking layer can be formed by corresponding doping when epitaxial growth is performed with the single-crystal seed layer as the core.

[0125] Seventh embodiment

[0126] The seventh embodiment is distinguished from the foregoing embodiments only in that, as shown in the figure, the source region and the drain region are doped to reduce the contact resistance. It can be understood that, when forming a HEMT device, the doping type of the source and drain regions is N-type; when forming a HHMT device, the doping type of the source and drain regions is P-type. Figure 33 Further, in a HEMT device, the source and / or drain can be in physical contact with the channel layer after the barrier layer is removed and form an ohmic contact with the two-dimensional electron carrier gas (2DEG). Due to the existence of the doped source and drain regions, through process and structure design, this direct physical contact with the channel layer is more conducive to reducing the ohmic contact resistance.

[0127] Further, in a HHMT device, since P-type ohmic contact is more difficult to form, when the source (and / or drain) is in physical contact with the channel layer after the barrier layer is removed and forms an ohmic contact with the two-dimensional hole carrier gas (2DHG), due to the existence of the doped source and drain regions, through process and structure design, this direct physical contact with the channel layer is more conducive to reducing the ohmic contact resistance.

[0128] The manufacturing method for manufacturing the semiconductor device of the seventh embodiment is illustratively described in combination with the manufacturing method in the foregoing embodiments.

[0129] The doping of the source and drain regions is described taking the case where the seed layer corresponds to the source region as an example. For the case where the seed layer corresponds to the drain region, or the seed layer is located between the gate and drain regions, it is similar to the case where the seed layer corresponds to the source region, and is not described again here. As shown in the figure,

[0130] Figure 25 ​As shown, after the seed layer is formed, the source region is doped with P-type or N-type dopants during the growth of the channel layer 201 with the seed layer as the core.

[0131] Alternatively, the source region can be grown after the growth of the channel layer 201 with the seed layer as the core, without being doped with P-type or N-type dopants, and then the channel layer is grown with the source region doped with P-type or N-type dopants.

[0132] Then, after the doped source region is formed, the channel layer is grown epitaxially to form a channel region, which can be doped with P-type or N-type dopants to form the first and / or second modulation layer.

[0133] Then, after the doped source region is formed, the channel layer is grown epitaxially to form a channel region, which can be doped with P-type or N-type dopants to form the first and / or second modulation layer.

[0134] It is understood that the doping of the source region and the doping of the modulation layer can be performed simultaneously or sequentially.

[0135] It is further understood that the device can be a complementary semiconductor device in which both HHMT and HEMT exist.

[0136] Eighth Embodiment

[0137] A power supply device including any of the semiconductor devices of the above embodiments. The power supply device includes a primary circuit, a secondary circuit, a transformer, and the like, and each of the primary circuit and the secondary circuit includes a switching element, and the switching element includes any of the semiconductor devices of the above embodiments.

[0138] Ninth Embodiment

[0139] A mobile phone including any of the semiconductor devices of the above embodiments. The mobile phone includes a display screen, a charging unit, and the like, and the charging unit includes any of the semiconductor devices of the above embodiments.

[0140] Tenth Embodiment

[0141] An amplifier, which can be used as a power amplifier in a mobile phone base station, an optical communication system, and the like, and the power amplifier can include any of the semiconductor devices of the above embodiments.

[0142] The present disclosure is described above with reference to specific embodiments. As one skilled in the art will readily appreciate, the description is illustrative of the present disclosure and not in limitation thereof. Various modifications and changes can be made thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A method for regulating a distributed electric field in a semiconductor device, comprising: Step 100: Providing a substrate; Step 200: forming a groove on the substrate, wherein a side surface of the groove has a hexagonal symmetrical lattice structure; Step 300: forming a single crystal seed layer on the side surface of the groove; Step 400: growing a first sublayer of a channel layer structure, a second adjustment layer, the first adjustment layer, and a second sublayer of the channel layer structure along the groove with the single crystal seed layer as the core and restricted by the groove; Step 500: etching the substrate, so that the channel layer structure protrudes from the upper surface of the etched substrate; Step 600: forming a barrier layer on the exposed channel layer structure, thereby forming a two-dimensional electron gas and immovable background positive charges on a first surface of the channel layer structure, and forming a two-dimensional hole gas and immovable background negative charges on a second surface of the channel layer structure; Step 700: forming a source, a gate, and a drain on the first surface of the channel layer structure, and forming a bottom electrode on the second surface of the channel layer structure, or forming a source, a gate, and a drain on the second surface of the channel layer structure, and forming a bottom electrode on the first surface of the channel layer structure; The first adjustment layer is doped with a P-type for a HEMT device and an N-type for a HHMT device, and the projection of the first adjustment layer on the first surface of the channel layer structure falls within a range between the gate and the drain, or the projection of the first adjustment layer on the first surface of the channel layer structure partially overlaps with the projection of the gate on the first surface of the channel layer structure; The second adjustment layer is P-type doped for HEMT devices and N-type doped for HHMT devices. The projection of the second adjustment layer on the first surface of the channel layer structure falls within the range of the gate. 2 . The method according to claim 1 , wherein the bottom electrode is connected to at least one of the two-dimensional electron gas or the two-dimensional hole gas. 3 . The method according to claim 1 , wherein the bottom electrode is connected to at least one of the first adjustment layer, the two-dimensional electron gas, or the two-dimensional hole gas. 4 . The method according to claim 1 , wherein the bottom electrode is connected to at least one of the second adjustment layer, the two-dimensional electron gas, or the two-dimensional hole gas. 5 . The method according to claim 1 , wherein the bottom electrode is connected to at least one of the first adjustment layer, the second adjustment layer, the two-dimensional electron gas, or the two-dimensional hole gas.

6. The method according to claim 1 or 5, wherein the first adjustment layer or the second adjustment layer has P-type doping when the bottom electrode is formed on the second surface of the channel layer structure; or the first adjustment layer or the second adjustment layer has N-type doping when the bottom electrode is formed on the first surface of the channel layer structure. 7 . The method according to claim 1 , wherein the doping concentration of the first adjustment layer is less than 5E18 / cm 3 ; and the doping concentration of the second adjustment layer is 1E17-5E19 / cm 3 .

8. The method according to any one of claims 2 to 5, wherein the source, gate and drain are arranged in a coplanar or non-coplanar manner. 9 . The method according to claim 2 , wherein the source and drain are formed directly or indirectly on the channel layer structure, and the gate is formed directly or indirectly on the barrier layer. 10 . The method according to claim 1 , wherein a buffer layer is deposited on the seed layer before growing the channel layer structure. 11 . The method according to claim 1 , wherein the seed layer is provided at a position corresponding to the source electrode, a position corresponding to the drain electrode, or a position corresponding to between the gate electrode and the drain electrode. 12 . The method according to claim 1 , wherein when the seed layer is disposed at a position corresponding to the drain electrode, a current blocking layer is further formed on the seed layer.

13. The method of claim 1, wherein when forming a HEMT device, the source and drain regions are N-type doped; when forming a HHMT device, the source and drain regions are P-type doped.

14. The method of claim 1, wherein a dielectric layer is formed on side surfaces and a bottom surface of the groove.

15. A semiconductor device comprising: a substrate; A groove is formed on the substrate, and a side surface of the groove has a hexagonal symmetrical lattice structure; a single crystal seed layer formed on the side surface of the groove; a channel layer structure, with the single crystal seed layer as the core and restricted by the groove to grow along the groove to form a first sublayer of the channel layer structure, a second adjustment layer, a first adjustment layer and a second sublayer of the channel layer structure; the channel layer structure protrudes from the upper surface of the substrate; A barrier layer is formed on the protruding channel layer structure, thereby forming a two-dimensional electron gas and an immovable background positive charge on a first surface of the channel layer structure, and a two-dimensional hole gas and an immovable background negative charge on a second surface of the channel layer structure; forming a source electrode, a gate electrode, and a drain electrode on a first surface of the channel layer structure and a bottom electrode on a second surface of the channel layer structure, or forming a source electrode, a gate electrode, and a drain electrode on the second surface of the channel layer structure and a bottom electrode on the first surface of the channel layer structure; When the bottom electrode is formed on the second surface of the channel layer structure, a HEMT device is formed; when the bottom electrode is formed on the first surface of the channel layer structure, a HHMT device is formed; The first adjustment layer is doped with a P-type for a HEMT device and an N-type for a HHMT device, and the projection of the first adjustment layer on the first surface of the channel layer structure falls within a range between the gate and the drain, or the projection of the first adjustment layer on the first surface of the channel layer structure partially overlaps with the projection of the gate on the first surface of the channel layer structure; The second adjustment layer is P-type doped for HEMT devices and N-type doped for HHMT devices. The projection of the second adjustment layer on the first surface of the channel layer structure falls within the range of the gate. 16 . The device according to claim 15 , wherein the bottom electrode is connected to at least one of the two-dimensional electron gas or the two-dimensional hole gas to adjust the distributed electric field of the device. 17 . The device according to claim 15 , wherein the bottom electrode is connected to at least one of the first adjustment layer, the two-dimensional electron gas, or the two-dimensional hole gas to adjust the distributed electric field of the device. 18 . The device according to claim 15 , wherein the bottom electrode is connected to at least one of the second adjustment layer, the two-dimensional electron gas, or the two-dimensional hole gas to adjust the distributed electric field of the device.

19. The device according to claim 15, wherein the bottom electrode is connected to at least one of the first adjustment layer, the second adjustment layer, the two-dimensional electron gas, or the two-dimensional hole gas to adjust the distributed electric field of the device.

20. The device according to claim 15 or 19, wherein when the bottom electrode is formed on the second side of the channel layer structure, the first adjustment layer or the second adjustment layer has P-type doping; or when the bottom electrode is formed on the first side of the channel layer structure, the first adjustment layer or the second adjustment layer has N-type doping. 21 . The device according to claim 20 , wherein the doping concentration of the first adjustment layer is less than 5E18 / cm 3 ; and the doping concentration of the second adjustment layer is 1E17-5E19 / cm 3 .

22. The device of any one of claims 16 to 19, wherein the source, gate, and drain are arranged coplanar or non-coplanar.

23. The device according to claim 15, further comprising a buffer layer on the seed layer. 24 . The device of claim 15 , wherein the seed layer is provided at a position corresponding to the source electrode, at a position corresponding to the drain electrode, or at a position corresponding to between the gate electrode and the drain electrode. 25 . The device according to claim 15 , wherein when the seed layer is disposed at a position corresponding to the drain electrode, a current blocking layer is further formed on the seed layer.

26. The device of claim 15, wherein when forming a HEMT device, the source and drain regions further have N-type doping; when forming a HHMT device, the source and drain regions further have P-type doping.

27. The device according to claim 15, wherein a dielectric layer is further provided on the sidewalls and bottom surface of the groove.

28. A complementary semiconductor device comprising: A semiconductor device as claimed in any one of claims 15 to 27.

29. A radio frequency device comprising a semiconductor device prepared by the method for adjusting the distributed electric field of a semiconductor device according to any one of claims 1 to 14, or the semiconductor device according to any one of claims 15 to 27, or the complementary semiconductor device according to claim 28.

30. An electric power device comprising a semiconductor device prepared by the method for adjusting the distributed electric field of a semiconductor device according to any one of claims 1 to 14, or the semiconductor device according to any one of claims 15 to 27, or the complementary semiconductor device according to claim 28.

Images