Lateral conductive gallium nitride-based normally-off field effect transistor and preparation method thereof

Abstract

The invention discloses a transverse conductive gallium nitride-based normally-off field effect transistor and a preparation method thereof, and relates to the technical field of power electronic devices. The structure comprises a substrate, a buffer layer, an i-GaN epitaxial layer, an AlN epitaxial layer, a SiO2 layer, an Mg-Al-O layer located above the AlN epitaxial layer, a source electrode and a drain electrode which are arranged on the AlN epitaxial layer, a diffusion layer generated after high-temperature processing, and a grid electrode arranged on the Mg-Al-O layer. The preparation process is simple, the threshold voltage of the obtained device is easy to adjust, and the performance is stable and reliable; the high-temperature-resistant lithium ion battery not only has high output current density, but also has good high-temperature-resistant operation capability. In addition, the Al-Mg-O structure is adopted as the gate oxide layer of the field effect transistor device, the gate leakage current is small, and the transconductance of the device is obviously improved compared with the transconductance of the device when the gate is made of a single material.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of rate electron device technology, and particularly refers to a lateral conduction gallium nitride-based normally-off field effect transistor and a preparation method thereof. BACKGROUND

[0002] Gallium nitride-based materials have the characteristics of large band gap, high critical electric field, high mobility, high electron saturation drift speed, large thermal conductivity, and small dielectric constant, which are very suitable for making high-temperature and high-current operating power electronic devices.

[0003] In order to realize normally-off devices, based on AlGaN / GaN heterostructure, some existing methods include: thin AlGaN barrier layer method, etched recess gate structure method, fluorine ion implantation under gate method, cap layer structure method, selective area growth method, etc. By combining the above methods with the MIS gate, a normally-off device with a certain current density output is realized.

[0004] However, the AlGaN / GaN heterostructure material system currently used (Al component <0.4) is difficult to further improve the two-dimensional electron gas concentration, thereby fundamentally limiting the improvement of device performance. To solve this problem, an ultra-thin binary material system AlN / GaN heterostructure is proposed. Because of the large spin and piezoelectric polarization difference between AlN and GaN, when the AlN barrier layer is very thin (d<5nm), a two-dimensional electron gas with a concentration of 3×10 13 cm -2 and a high mobility (>1000 cm 2 / V.s) can be generated at the AlN / GaN heterojunction interface, and the obtained material has a small sheet resistance. This shows that theoretically, AlN / GaN heterostructure devices can greatly improve the output current density, thereby breaking through the performance bottleneck of AlGaN / GaN heterojunction field effect transistor devices.

[0005] Currently, AlN / GaN HFET device research is mostly focused on normally-on microwave power devices. The maximum output current density of the device can reach 2.9A / mm, and the corresponding maximum transconductance of the device reaches 430mS / mm. In many studies, the output current density can reach more than 1 A / mm, which is much higher than that of general AlGaN / GaN heterostructure devices. However, there are few studies on gallium nitride-based normally-off AlN / GaN heterojunction field effect transistors, and most of the methods used are the same as the above-mentioned methods.

[0006] In 2009, Chang et al. of the University of Florida used oxygen plasma to treat the AlN layer under the gate of the device, and obtained a device with a threshold voltage of +1V (reference: Chang C Y, Pearton S J, Lo C F, et al. Development of enhancement mode AlN / GaN high electron mobility transistors [J]. Applied Physics Letters, 2009, 94(26): 263505.).

[0007] In 2012, Huang et al. of the Hong Kong University of Science and Technology grew a heterostructure material with an AlN barrier layer of only 1.5 nm thick, and made a MOSHFET device with Al2O3 as the gate dielectric layer, which realized a normally-off device with a threshold voltage of +0.21V, a current density of 860mA / mm, and a maximum transconductance of 509mS / mm (reference: Huang T, Zhu X, Lau K M. Enhancement-Mode AlN / GaN MOSHFETs on Si Substrate With Regrown Source / Drain by MOCVD [J]. IEEE Electron Device Letters, 2012, 33(8): 1123-1125.).

[0008] However, in these prior arts, complex preparation methods are often required, and the performance stability of the obtained products is not ideal. SUMMARY

[0009] One of the purposes of the present application is to provide a preparation method of a lateral conduction gallium nitride-based normally-off field effect transistor, which is simpler in process, and the threshold voltage of the obtained device is easy to adjust, and the performance is stable and reliable.

[0010] In order to solve the above technical problems, the technical scheme adopted by the present application is as follows: a preparation method of a lateral conduction gallium nitride-based normally-off field effect transistor, comprising the following steps: (A) growing a buffer layer, an i-GaN epitaxial layer and an AlN epitaxial layer on a substrate in sequence, wherein the i-GaN epitaxial layer and the AlN epitaxial layer form an AlN / GaN heterojunction; (B) depositing a layer of SiO2 on the AlN epitaxial layer; (C) photoetching and removing part of the mask film of the SiO2 layer by dry etching to open a gate window; (D) using a magnetron sputtering method to make a Mg-Al-O layer on the SiO2 layer and the gate window to form a composite structure gate oxide layer; (E) photoetching the source and drain region patterns, removing the source region oxide layer by plasma etching, then making the source and drain by electron beam evaporation of metal, and forming an ohmic contact by high temperature thermal annealing, under the action of high temperature, the Al, Mg, O atoms in the gate oxide layer diffuse into the AlN epitaxial layer to form a diffusion layer; (F) photoetching the gate pattern on the Mg-Al-O layer, and evaporating metal to form the gate.

[0011] Preferably, in step (A), the thickness of the AlN epitaxial layer is 2-5 nm.

[0012] More preferably, in step (D), the ratio of the sputtering amount of magnesium element to aluminum element gradually changes from high to low during the magnetron sputtering process, specifically, it can gradually decrease from magnesium element: aluminum element = 7:3 to magnesium element: aluminum element = 3:7 (i.e. from magnesium element accounting for 70% of the total amount of magnesium and aluminum elements to magnesium element accounting for 30% of the total amount of magnesium and aluminum elements). The thickness of the Mg-Al-O layer is 5-20 nm. Of course, those skilled in the art can also gradually reduce the proportion of magnesium element in the magnetron sputtering process to 0 according to the needs to change to a sputtering state with an aluminum element proportion of 100%.

[0013] More preferably, in step (E), the temperature of high temperature thermal annealing is 700-900°C.

[0014] More preferably, in step (E), the metal material selected by electron beam evaporation of metal is Ti / Al / Ni / Au or Ti / Al / Pt / Au or Ti / Al / Mo / Au.

[0015] More preferably, in step (F), the metal selected for the gate is Ni / Au or Pt / Au or Pd / Au.

[0016] More preferably, in step (A), the growth temperature of the i-GaN epitaxial layer and the AlN epitaxial layer is 1050-1200°C.

[0017] More preferably, in step (A), the buffer layer is an AlN or low-temperature GaN structure layer, and the growth temperature is 700-1000°C.

[0018] More preferably, in step (B), a SiO2 layer is deposited on the AlN epitaxial layer by plasma enhanced chemical vapor deposition.

[0019] In addition, the application further provides a lateral conductive gallium nitride-based normally-off field effect transistor prepared by the preparation method of the lateral conductive gallium nitride-based normally-off field effect transistor.

[0020] The application diffuses Mg elements and oxygen elements accumulated at the interface into the AlN layer through high-temperature heat treatment of the Al-Mg-O gate oxide layer in the process, so that Mg-O bonds with small ionization energy are formed in the AlN layer, and thus a P-type AlN layer is formed in the diffusion layer below the gate, and the 2DEG (two-dimensional electron gas) in the channel is depleted when the concentration is high enough, so that a normally-off device is formed.

[0021] Compared with the prior art, the application has the following technical effects: (1) The P-type AlN layer is formed by diffusing Mg elements and oxygen elements into the AlN / GaN heterojunction, the process is simple and feasible, the threshold voltage of the obtained device is easy to adjust, and the performance is stable and reliable.

[0022] (2) The AlN / GaN heterojunction is used as the conductive channel of the device, which not only has a high output current density, but also has good high-temperature operation capability.

[0023] (3) The Al-Mg-O structure is used as the gate oxide layer of the field effect transistor device, which has a small gate leakage current, and the transconductance of the device is obviously improved compared with the single material gate. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 It is a structure schematic diagram obtained in step (A) in the process flow of the embodiment 1 of the application; Figure 2 It is a structure schematic diagram obtained in step (B) in the process flow of the embodiment 1 of the application; Figure 3 It is a structure schematic diagram obtained in step (C) in the process flow of the embodiment 1 of the application; Figure 4 It is a structure schematic diagram obtained in step (D) in the process flow of the embodiment 1 of the application; Figure 5 It is a structure schematic diagram obtained in step (E) in the process flow of the embodiment 1 of the application; Figure 6 It is a structure schematic diagram obtained in step (F) in the process flow of the embodiment 1 of the application (i.e. a structure schematic diagram of the lateral conductive gallium nitride-based normally-off field effect transistor prepared in the embodiment 1); Figure 7 It is a transistor structure schematic diagram prepared in the embodiment 2 of the application.

[0025] In the drawings: 1 - substrate 2 - buffer layer 3 - i-GaN epitaxial layer 4 - AlN epitaxial layer 5 - SiO2 layer 6 - Mg-Al-O layer 7 - source 8 - drain 9 - diffusion layer 10 - gate 11 - SiN layer. DETAILED DESCRIPTION

[0026] For the convenience of those skilled in the art, the present application will be further described below in conjunction with the embodiments and the accompanying drawings, and the content mentioned in the embodiments is not a limitation on the present application. Example 1

[0027] As Figure 6 shown in the schematic diagram of the device structure prepared for Example 1. The structure includes a substrate 1, a buffer layer 2, an i-GaN epitaxial layer 3, an AlN epitaxial layer 4, a SiO2 layer 5, a Mg-Al-O layer 6 located above the AlN epitaxial layer 4, a source 7 and a drain 8 disposed on the AlN epitaxial layer 4, a diffusion layer 9 generated after high-temperature treatment, and a gate 10 disposed on the Mg-Al-O layer 6.

[0028] The preparation method of the above-mentioned lateral conduction gallium nitride-based normally-off field effect transistor includes the following process steps: (A) As Figure 1 shown, a metal organic chemical vapor deposition (MOCVD) method is used to grow a buffer layer 2, an i-GaN epitaxial layer 3, and an AlN epitaxial layer 4 on a substrate 1 in sequence, wherein the growth temperature of the i-GaN epitaxial layer 3 and the AlN epitaxial layer 4 is 1050-1200°C, the substrate 1 is one of sapphire, silicon, silicon carbide, or gallium nitride, and the buffer layer 2 is AlN or a low-temperature GaN structure layer, and the growth temperature is 700-1000°C.

[0029] (B) As Figure 2 shown, a layer of SiO2 layer 5 is deposited on the AlN epitaxial layer 4, which can be achieved by a plasma enhanced chemical vapor deposition (PECVD) method.

[0030] (C) As Figure 3 shown, a gate window is opened by photolithography and removing part of the mask film of the SiO2 layer 5 through CF4 reactive ion etching.

[0031] (D) As Figure 4 shown, a Mg-Al-O layer 6 is made on the SiO2 layer 5 and the gate window by a magnetron sputtering method to form a composite structure gate oxide layer. The ratio of magnesium element to aluminum element is adjusted during the sputtering process, and the gate oxide layer transitions from being rich in magnesium element to being rich in aluminum element, specifically, the proportion of magnesium element in the total amount of magnesium and aluminum element decreases from 70% to 30%.

[0032] (E) As shown in Figure 5 Figure 2, the source and drain regions are patterned by photolithography, and the oxide layer in the source region is removed by CF4 reactive ion etching, and then the source 7 and the drain 8 are fabricated by electron beam evaporation of metal. The electrode metal material used is Ti / Al / Ni / Au (four-layer electrode metal), and high-temperature thermal annealing is used to form ohmic contact. Under the action of high temperature, Al, Mg, and O atoms in the gate oxide layer diffuse into the AlN epitaxial layer 4 to form a diffusion layer 9.

[0033] (F) As shown in Figure 6 Figure 3, the gate pattern is photolithographed on the Mg-Al-O layer 6, and the gate 10 is formed by metal evaporation. The electrode metal material used is Ni / Au (two-layer electrode metal). Example 2

[0034] Figure 7 The device structure prepared for Example 2 is shown in Figure 4. It is similar to the device structure of Example 1, and the only difference is that the SiO2 layer 5 in steps (B), (C), and (D) in the manufacturing process flow is replaced by a SiN layer 10.

[0035] Specifically: in step (B), the SiN layer 11 is grown in situ on the AlN epitaxial layer 4 by MOCVD method; in step (C), the mask film of part of the SiN layer 11 is removed by photolithography and CF4 reactive ion etching to open a gate window; in step (D), the Mg-Al-O layer 6 is fabricated on the SiN layer 11 and the gate window by magnetron sputtering. The other steps are the same.

[0036] The transverse-conducting gallium nitride-based normally-off field effect transistor and the method for manufacturing the same provided by the present application have been described in detail above. In order to make those skilled in the art more easily understand the improvements of the present application over the prior art, some of the drawings and descriptions of the present application have been simplified, and the above examples are the preferred implementation of the present application. In addition to this, the present application can also be implemented in other ways, and any obvious substitutions within the concept of the present technical solution are within the protection scope of the present application.

Claims

1. A method for fabricating a laterally conductive gallium nitride-based normally-off field-effect transistor, characterized in that, The method comprises the following steps: (A) growing a buffer layer (2), an i-GaN epitaxial layer (3) and an AlN epitaxial layer (4) on a substrate (1) in sequence; (B) depositing a SiO2 layer (5) on the AlN epitaxial layer (4); (C) performing photoetching and removing part of the mask film of the SiO2 layer by dry etching to open a gate window; (D) using a magnetron sputtering method to make a Mg-Al-O layer (6) on the SiO2 layer (5) and the gate window to form a composite structure gate oxide layer; (E) performing photoetching on the source and drain regions, removing the oxide layer in the source region by plasma etching, then making a source (7) and a drain (8) by electron beam evaporation of metal and forming an ohmic contact by high-temperature thermal annealing, under the action of high temperature, Al, Mg and O atoms in the gate oxide layer diffuse into the AlN epitaxial layer (4) to form a diffusion layer (9); (F) performing photoetching on the Mg-Al-O layer (6) to form a gate (10).

2. The method of claim 1, wherein the method further comprises: In step (A), the thickness of the AlN epitaxial layer (4) is 2-5 nm.

3. The method of claim 1, wherein the method further comprises: In step (D), the sputtering amount ratio of magnesium element to aluminum element in the magnetron sputtering process gradually changes from high to low, and the thickness of the Mg-Al-O layer is 5-20 nm.

4. The method of claim 1, wherein the method further comprises: In step (E), the high-temperature thermal annealing temperature is 700-900℃.

5. The method of claim 1, wherein the method further comprises: In step (E), the metal material selected by electron beam evaporation of metal is Ti / Al / Ni / Au or Ti / Al / Pt / Au or Ti / Al / Mo / Au.

6. The method of claim 1, wherein the method further comprises: In step (F), the metal selected for the gate (10) is Ni / Au or Pt / Au or Pd / Au.

7. The method of claim 1, wherein the method further comprises: In step (A), the growth temperature of the i-GaN epitaxial layer (3) and the AlN epitaxial layer (4) is 1050-1200℃.

8. The method of claim 1, wherein the method further comprises: In step (A), the buffer layer (2) is an AlN or low-temperature GaN structure layer, and the growth temperature is 700-1000℃.

9. The method of claim 1, wherein the method further comprises: depositing a gate dielectric layer on the substrate; depositing a gate electrode on the gate dielectric layer; and depositing a passivation layer on the gate electrode. In step (B), a SiO2 layer (5) is deposited on the AlN epitaxial layer (4) by a plasma-enhanced chemical vapor deposition method.

10. A laterally conductive gallium nitride based normally-off field effect transistor, characterized by: The transverse-conducting gallium nitride-based normally-off field effect transistor is prepared by the method of any one of claims 1-9.

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