Junction field effect transistor and semiconductor device comprising a junction field effect transistor

Abstract

The application discloses a junction field effect transistor. The junction field effect transistor comprises a drain region, a drain terminal coupled to the drain region, an insulating electrode, and an insulating terminal coupled to the insulating electrode. The junction field effect transistor has an active region. The insulating electrode presents a capacitance to the drain terminal, and the capacitance value is between 0.1 nanofarad per square centimeter of the active region and 10 nanofarad per square centimeter of a lateral range of the active region. The junction field effect transistor reduces the cell size, has better shielding performance, and makes the device have stronger voltage resistance.

Description

Technical Field

[0001] The present invention relates to a power semiconductor device, and more specifically, to a junction field-effect transistor. Background Technology

[0002] A junction field-effect transistor (JFET) operates by providing a conductive path between its source and drain terminals, formed by a conductive channel in response to a voltage applied to a third terminal. This third terminal is the channel control terminal, such as the gate or base. In contrast to a metal-insulated field-effect transistor (MISFET), a JFET includes at least one channel control terminal independent of the channel region, not through an insulator. The channel control terminal can be understood as the transistor being turned on because current flows through the drain and source terminals when a suitable bias voltage is applied to the gate or base terminal, thus altering the channel characteristics. Conversely, when a suitable reverse bias voltage is applied to the gate or base terminal, the channel of the device is pinched off, and the transistor is turned off. The bias voltage depends on the conductivity type of several regions (e.g., n-type or p-type) and whether the transistor is normally on (i.e., normally conducting) or normally off (i.e., normally off).

[0003] JFETs are used in power transistors for high-voltage applications. In high-voltage applications, power transistors are required to withstand off-voltages ranging from several hundred volts and have on-current currents of several or tens of amperes. In some high-voltage applications, large voltage fluctuations can damage transistors, such as channel damage or source-drain voltage fluctuations that override the signal at the channel control terminal, causing the device to switch on and transmit noise and oscillations to other parts of the circuit. Therefore, system, circuit, and device-level modifications that can avoid these harmful conditions represent an important area of ​​innovation in this field. Summary of the Invention

[0004] Therefore, the purpose of this invention is to solve the above-mentioned technical problems of the prior art and to propose an improved junction field-effect transistor.

[0005] According to an embodiment of the present invention, a junction field-effect transistor is provided, comprising: a drain region; a drain terminal coupled to the drain region; an insulating electrode; and an insulating end coupled to the insulating electrode; wherein: the junction field-effect transistor has an active region; the insulating electrode presents a capacitance to the drain terminal, the capacitance value of which is between 0.1 nanofarads per square centimeter of the active region and 10 nanofarads per square centimeter of the lateral range of the active region.

[0006] According to an embodiment of the present invention, a junction field-effect transistor (JFET) is also provided, comprising: a drain region, a source region, and a base region; a channel formed by the channel region; a first terminal coupled to the drain region; a second terminal coupled to the source region; a third terminal coupled to the base region; and an integrated high-voltage capacitor terminal coupled to an integrated high-voltage capacitor electrode; wherein: the integrated high-voltage capacitor electrode and the drain region form a capacitor; if a bias voltage is applied to the base region, the majority carriers of the channel will be completely depleted; if a bias voltage is applied to the integrated high-voltage capacitor terminal, due to the positioning of the integrated high-voltage capacitor electrode relative to the channel region, the majority carriers lost in the channel are at most 10% of the unbiased concentration.

[0007] According to an embodiment of the present invention, a junction field-effect transistor is also provided, comprising: a drain region, a source region, a base region, and a channel region; a first terminal coupled to the drain region; a second terminal coupled to the source region; a third terminal coupled to the base region; an insulating electrode insulated by an insulator; and a fourth terminal coupled to an insulating electrode; wherein a portion of the channel is in contact with the insulator and is not covered by the insulating electrode.

[0008] According to various aspects of the present invention, the junction field-effect transistor reduces the cell size, has better shielding performance, and enables the device to have stronger voltage withstand capability. Attached Figure Description

[0009] Figure 1 A schematic diagram illustrates an axial cross-sectional view 100 of a device in the form of a vertical plane JFET 140 according to an embodiment of the present invention and its corresponding device 150;

[0010] Figure 2 This is an example circuit diagram of the composite device 200 according to an embodiment of the present invention;

[0011] Figure 3 This is an example circuit diagram of the composite device 300 according to an embodiment of the present invention;

[0012] Figure 4 This is a schematic diagram of two cross-sections 400 and 450 of a JFET according to an embodiment of the present invention;

[0013] Figure 5 This is a schematic diagram of the cross-section 500 of a JFET according to an embodiment of the present invention;

[0014] Figure 6 The cross-section 600 and axial cross-section 650 of the vertical JFET with integrated capacitor are shown. Detailed Implementation

[0015] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0016] Throughout this specification, references to “an embodiment,” “an example,” or “an example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases “in an embodiment,” “in an embodiment,” “an example,” or “an example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It should be understood that when an element is referred to as “coupled to” or “connected to” another element, it can be directly coupled to or coupled to the other element, or there may be intermediate elements. Conversely, when an element is referred to as “directly coupled to” or “directly connected to” another element, there are no intermediate elements. The same reference numerals indicate the same elements. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0017] The specific applications of the transistors disclosed in this specification can be applied in a variety of situations. For example, the transistors discussed in this application can be used as power transistors. These power transistors can be used in power factor correction (PFC) circuits, all types of power converters (such as AC-to-AC, DC-to-AC, etc.), motor drive circuits, and other high-power applications well known to those skilled in the art. These power transistors can be used in enterprise-level data center infrastructure applications, electric vehicle power supplies, high-energy microwave generators such as microwave ovens, and other high-power applications well known to those skilled in the art. Specific applications involve power transistors that can withstand disconnect voltages in the range of several hundred volts and have on-state currents of several or tens of amperes.

[0018] The specific applications of the transistors disclosed in this specification can utilize different semiconductor materials. For example, transistors can be fabricated using various III-IV materials (e.g., gallium nitride or silicon carbide) as the base semiconductor material. In the case of silicon carbide, dopants may include aluminum or boron as p-type dopants and phosphorus or nitrogen as n-type dopants. When gallium nitride is used, dopants may include magnesium as p-type dopants and silicon or oxygen as n-type dopants. Therefore, the various regions of the materials disclosed in this application can be formed in a variety of semiconductor materials such as silicon carbide and can be activated by introducing compatible dopant species into the selected semiconductor material to form active regions such as channels, channel controls, drains, and source regions.

[0019] In specific high-voltage applications, capacitors can be used to prevent ringing or other instabilities caused by large fluctuations in voltage and current. For transistors used in high-voltage applications, capacitors can be used to shield the transistor terminals from voltage and current fluctuations at alternative (i.e., other doped) terminals, thereby improving the transistor's slew rate, preventing ringing or other instabilities caused by rapid changes in transistor channel states, and increasing the phase and voltage margin of any feedback loops formed between the nodes and terminals of the circuit. However, while stability is an important aspect of transistor device performance, space is also a significant factor, as the cost of a device increases with the surface area of ​​the substrate (e.g., wafer) consumed by the device, among other reasons. Furthermore, for a capacitor to perform some of the aforementioned operations, it needs to be physically close to its shielded terminals. Therefore, high-power transistors can benefit from the integration of high-voltage capacitors. More specifically, high-power transistors composed of a set of unit cells can benefit from integrating high-voltage capacitors into the unit cells of the device.

[0020] In a specific embodiment of the present invention, a JFET with an integrated capacitor is disclosed. In this embodiment, the JFET is a power JFET, and the integrated capacitor is a high-voltage capacitor. The integrated capacitor may include an insulating electrode in the side region of the JFET. This insulating electrode provides capacitance to the drain terminal of the JFET. In other words, the drain terminal and the insulating electrode may be part of two electrodes that define a capacitor with the aforementioned capacitance. In high-power applications, where the JFET acts as a power transistor to withstand high voltages and carry tens of amperes of current, the insulating electrode provides capacitance to the drain terminal of the JFET, with a capacitance value ranging from 0.1 nanofarads (0.1 nF / cm²) per square centimeter in the active region of the JFET. 2 ) to the lateral range of the active region, 10 nanofa (10 nF / cm) per square centimeter 2The parasitic capacitance between the terminals of a transistor operating within this range is typically tens of nanofarads to a few picofarads (pF) per square centimeter, although many transistors operating within this range will have parasitic capacitance between their terminals. Standard power transistors without dedicated integrated capacitors typically have parasitic capacitance between their active region lateral ranges of tens of nanofarads (pF). It is appropriate to normalize the capacitance according to the cell size, as this represents both the current that the cell can absorb and the capacitance formed between the device terminals relative to the insulating electrodes.

[0021] The specific benefits of the invention discussed in this application can arise from various types of transistors. As mentioned above, a transistor can be a JFET. A JFET can be a cellular JFET or a multi-cell JFET. A transistor can be a lateral device, a vertical device, a planar device, a fin device, and / or a trench device. A transistor can also be a BJT, IGBT, MISFET, HEMT, and many other device types. Therefore, although many embodiments of the present invention are directed to JFETs, the present invention is not limited to such devices.

[0022] Figure 1 A schematic diagram of an axial cross-sectional view 100 of a device in the form of a vertical plane JFET 140 according to an embodiment of the present invention and its corresponding device 150 are shown. The JFET 140 is located on a substrate 101 and is formed by introducing a dopant into the substrate 101, or by growing or depositing a layer on the substrate 101, or by being formed separately and then attached (or pasted) to the substrate 101.

[0023] JFET 140 is a four-terminal device including a drain region 102 and a drain terminal 193 coupled to the drain region. In a cross-sectional view, the drain region 102 is also the substrate 101 and the drain terminal 103 of the device; however, in a cross-section not shown, the drain region 102 may be a contact region formed on the bottom of the substrate 101. JFET 140 also includes an insulating terminal 114 coupled to an insulating electrode 106. Similarly, in a cross-section not shown, the insulating terminal 114 may be a contact formed to the insulating electrode 106. The insulating electrode 106 may be encased in an insulator 107. The insulator 107 may cover more of the JFET 140, but to make the remainder of the JFET 140 visible, Figure 1Only the area near the insulating electrode 106 is shown. The JFET 140 also includes source regions 104, 124 and source terminals 105, 125. The JFET 140 also includes a vertical channel region 108 and lateral channel regions 109, 129 formed on the epitaxial layer 110. The channel regions can be depleted by applying a bias voltage to the base regions 111, 113, 121 via the base terminal 112. The material of the base regions 111, 113, 121 is shown as a heavily doped, darker region (base region 113) connected to a lightly doped, brighter region (base regions 111, 121). The brighter region is the part that directly affects the device channel. The base terminal 112 can be the only control terminal of the JFET 140.

[0024] In a specific embodiment of the invention, the transistor discussed is a normally-on transistor, meaning that the transistor is in a conductive state when no bias voltage is applied to the control electrode. JFET 140 is an example of a normally-on transistor. The source regions 104, 124, the channel regions 108, 109, 129, the epitaxial layer 110, and the substrate 101 have a first conductivity type, while the base regions 111, 121 have a second conductivity type. Therefore, when no bias voltage is applied to the base regions 111, 121, there is a conductive path that runs vertically downward from the source regions 104, 124 through the device to the drain region 102, and JFET 140 is in a conducting or conductive state. However, when a bias is applied to the base regions 111, 121 via the base terminal 112, the channel (which can deplete most of the charge carriers (e.g., at the lateral channel regions 109, 129 in the illustrated case)) and the JFET become non-conductive. In a particular embodiment, the lightly shaded portions of base regions 111 and 121 can be heavily doped p-type (p+) regions, source regions 104 and 124 can be heavily doped n-type (n+) regions, the darkly shaded portion of base region 111 can be a more heavily doped p-type region (p++), and the vertical channel region 108, lateral channel regions 109 and 129, epitaxial layer 110, and substrate 101 can be lightly doped n-type (n) regions. In other embodiments of the invention, the polarity of these regions can be switched to form devices with opposite conductivity types.

[0025] The JFET 140 is configured such that the insulating electrode 106 presents a capacitance to the drain terminal 103, which is represented as capacitor 151 in the device schematic 150, and has a capacitance of 0.1 nF / cm² over the lateral extent of the active region of the JFET 140. 2 ~10nF / cm 2In the case shown, JFET 140 is the cell of a larger multi-cell JFET. JFET 140 can be formed as part of a continuous pattern by copying to the left and right and rotating 180 degrees around the axis formed by lines drawn vertically on the page plane and copied to the front and back sides. Therefore, the boundary of the cross-section shown forms the complete lateral extent of the JFET 140 cell. Since the cell is a standard rectangle and the active regions of the channel region and base regions 111, 121, 113 extend to the entire lateral extent of the cell, the lateral extent of the active region in JFET 140 is equivalent to Figure 1 The area defined by the product of lengths 120 and 130 is the same as the area defined by the product of lengths 120 and 130. The same concept also applies to the individual transistors that are opposed to the unit cell; that is, the active region of an individual transistor defines the active region of the device.

[0026] In specific embodiments of the invention, the insulating electrode that presents capacitance to the drain terminal of the device is not the gate of the device. In the case of a JFET, the insulating electrode is configured and positioned such that it does not cause channel depletion. As will be seen in some embodiments discussed below, the fact that the insulating electrode does not need to affect the channel can provide significant benefits, such as reduced cell size, greater flexibility in shielding location, greater flexibility in the voltage that can be applied to the insulating end during device operation, and a thicker insulating layer that makes the capacitor more robust. In certain embodiments, the insulating electrode is positioned such that when a bias voltage is applied to the insulating electrode, it does not cause channel depletion exceeding 10% of the unbiased majority carrier concentration of the channel; whereas if this bias voltage is applied to the base region of the JFET, the channel will be completely depleted. In certain embodiments, the insulating electrode is positioned such that when a bias voltage is applied, it does not change the state of the JFET to a conducting state.

[0027] Figure 1 The insulating electrode 106 is not the gate of the JFET 140. The lateral channel regions 109, 129 of the JFET 140 have an unbiased concentration of majority carriers defined by the doping concentration in these regions, and the bias applied to the base regions 111, 121 completely depletes the majority carriers of the lateral channel regions 109, 129. However, the position of the insulating electrode 106 relative to the lateral channel regions 109, 129 such that if the same bias voltage is applied to the insulating terminal 114, the lateral channel regions 109, 129 will consume up to 10% of the communication region from the unbiased state. Because the insulating electrode 106 is not the gate of the device, the JFET 140 is a four-terminal JFET, but includes only a single-channel control terminal. The fourth terminal, provided in the form of the insulating terminal 114, is used only to bias the capacitor presented to the drain terminal 103 of the JFET 140.

[0028] In specific embodiments of the invention, the JFET may include an insulating terminal in the form of an integrated high-voltage capacitor. In specific embodiments of the invention, the integrated high-voltage capacitor is not a channel control terminal of the device. Although in some embodiments the bias voltage applied to this terminal may affect the channel conductivity, in other embodiments the effect of the bias voltage applied to this terminal on the conductivity is minimized. The integrated high-voltage capacitor may be coupled to an insulating electrode in the form of a metal or heavily doped polysilicon region within the lateral range of the device. The insulator covering the integrated electrode may be thicker than the gate insulator of a standard transistor, with a thickness greater than 1000 Å. While the increased thickness is detrimental to the performance of a standard gate electrode, it makes the capacitor more robust in its ability to withstand high voltages without breakdown. In certain embodiments, the insulator of the insulating electrode may contact the channel region of the device and separate the channel region from the insulating electrode by a distance greater than 1000 Å.

[0029] Back Figure 1 In the illustrated embodiment, for a standard power transistor, insulator 107 can be thicker than the gate insulator. For example, insulator 107 can be greater than 1000 Å. This thickness typically limits the ability of the bias applied to the insulating electrode 106 to surge through the channel regions 109, 129, 108. However, it does allow insulator 107 to withstand higher voltages applied to the drain region 102 compared to insulating electrode 106 (e.g., through capacitor 151), which is advantageous for high-power applications, as the voltage at drain terminal 103 can reach hundreds of volts.

[0030] In specific embodiments of the invention, the devices disclosed herein can be used in systems such as composite devices. Composite devices may include high-voltage transistors and low-voltage transistors. Composite devices may include normally-on transistors and normally-off transistors. Composite devices may include a JFET connected to a second transistor, such as a JFET having one or more of the characteristics discussed above. For example, the JFET may be a high-voltage normally-on device connected in series with a normally-off low-power device to form a composite high-voltage switch. The normally-off low-power device may be an enhancement-mode FET (field-effect transistor). The normally-off device may be a silicon device formed on a separate substrate, like the normally-on device. The normally-on and normally-off devices may be connected in series and operate as a single switch. Although this type of system is used as an example in the remainder of this application, the devices disclosed herein are more broadly applicable to various types of systems.

[0031] Figure 2 An example circuit diagram of the composite device 200 is provided. The composite device 200 includes a FET 201 connected to the FET 201. Figure 1The JFET 140 is described above as a high-power normally-on device, while FET 201 is a normally-off enhancement-mode FET. In this composite device, the state of FET 201 sets the state of the composite device. These two devices are coupled together to create a high-voltage switch with specific characteristics that depend not only on the circuit topology but also on the physical layout of the devices. Regarding the internal topology of the circuit, the source terminal 105 of JFET 140 is connected to the drain terminal 202 of FET 201, the base terminal 112 of JFET 140 is connected to the source terminal 203 of FET 201, and the insulating terminal 114 of JFET 140 is connected to the channel control terminal 207 of FET 201.

[0032] The composite device 200 is a three-terminal device comprising a drain terminal 210, a gate terminal 220, and a source terminal 230. The gate terminal 220 is coupled to the channel control terminal 207 of the FET 201. The drain terminal 210 is connected to the drain terminal 103 of the JFET 140. The source terminal 230 is connected to the source terminal 203 of the FET 201 and the base terminal 112 of the JFET 140. In response to an appropriate bias signal applied to the gate terminal 220, the composite device 200 forms a conductive path between the drain terminal 210 and the source terminal 230. The composite device 200 can be used in high-voltage switching applications where the switch changes its state based on a bias voltage applied to the gate terminal 220. For example, when the bias voltage on the gate terminal 220 is low, there may be no conductive path between the drain terminal 210 and the source terminal 230, while when the bias voltage on the gate terminal 220 is high, a low-impedance conductive path may exist between the drain terminal 210 and the source terminal 230. Capacitor 151 provides a significant advantage in this case because it can control the slew rate of the composite device, thereby improving circuit stability. In a specific embodiment of the invention, the device can withstand a current of approximately 1 to 100 amperes, and the capacitor can have a capacitance value of approximately 1 pF to 10 nF.

[0033] In specific embodiments of the invention, the device disclosed herein may include shielding for integrating a high-voltage capacitor. This shielding can be achieved by introducing another capacitor into the device that shares a common node with the integrated high-voltage capacitor. For example, shielding can be provided for an integrated capacitor, such as capacitor 151, by presenting more surface area of ​​the base region of the JFET 140 to the drain terminal 103 of the device compared to the surface area of ​​the insulating electrode coupled to the insulating terminal 114. This base region can at least partially shield the insulating electrode from the drain terminal of the device. This approach may be advantageous in certain applications. For example, in Figure 2In the circuit type shown, the insulated electrode is coupled to the channel control terminal of FET 201. Therefore, noise introduced by the coupling of capacitor 151 may cause FET 201 to be turned on or off when it should not be, resulting in system instability. Therefore, the device with integrated high-voltage capacitor disclosed in this application can also be configured to present a shielding capacitor to the drain terminal of the composite device, for example... Figure 3 The composite device 300 shows a shielding capacitor 301. By adding this shielding capacitor 301, the composite device 300 can exhibit all the characteristics of the composite device 200 described above. The shielding capacitor 301 can be conceptualized as follows: the potential change at the drain terminal 210 caused by the movement of charge carriers causes the capacitor 151 to discharge or charge, and has a corresponding effect on the potential of the channel control terminal 207. Now, since the change in charge carriers must be counteracted by the presence of the shielding capacitor 301, the effect on the channel control terminal 207 is reduced. The degree of shielding increases with the capacitance of the shielding capacitor 301 relative to the capacitor 151.

[0034] Figure 4 Two cross-sections, 400 and 450, are used to illustrate specific benefits of certain embodiments of the invention. As described above, the inclusion of insulating electrodes not used for controlling the channel in certain devices disclosed in this application increases design flexibility, which will be specifically described below with reference to cross-sections 400 and 450. Both cross-sections shown are JFET devices formed on substrates 401 and 451. The devices also include epitaxial regions 402, 452, lateral channel regions 403, 453 extending along the top of base regions 404 and 454, and vertical channel regions 420, 460 formed by the gap between base regions 404, 454. The devices also include extended regions extending below base regions 404, 454. The devices also include source regions 405, 455 and source terminals 406 and 456. Base regions 404, 454 are connected to... Figure 1 The base region 111 in the middle is biased out of the page plane in a similar way.

[0035] In a specific embodiment of the invention, the integrated capacitor is more robust than a capacitor formed by a standard gate electrode. Cross-section 400 includes an insulating electrode 407 that forms a capacitor with the drain of the device. An insulator 408 covering the insulating electrode 407 and contacting the top of the lateral channel region 403 is the dielectric of the capacitor. The insulating electrode 407 is biased by applying a voltage to its insulating end outside the page plane. The insulator can be various materials, such as silicon nitride, silicon dioxide, silicon nitride oxide, aluminum oxide, aluminum nitride, or other dielectrics. Because the insulating electrode 407 does not need to be used as the gate of the device, the device of cross-section 400 exhibits several advantageous characteristics. For example, the thickness 409 of the insulator can be greater than 1000 Å. In certain embodiments, such as the one shown in cross-section 400, the insulator can be anywhere between 1200 Å and 2500 Å. This is advantageous because the voltage at the drain end (e.g., substrate 401) can be several hundred volts, while the increased insulator thickness makes the capacitor less likely to break down.

[0036] In a specific embodiment of the invention, the integrated capacitor does not need to extend to the entire lateral channel region of the device to which it is integrated. For example, the insulating electrode 407 does not need to cover the entire channel region of the device (i.e., it does not need to extend all the way to the contact between the source region and the lateral channel region). A portion of the lateral channel region 403 contacts the insulator 408 and is not covered by the insulating electrode 407. Figure 4 As shown, the insulating electrode 407 extends a distance 410 over the lateral channel, but does not extend over a portion of the lateral channel (i.e., it does not continue to extend). Similarly, a device according to the invention may include an insulating electrode in which at least a portion of the channel region is not covered by the channel. This is advantageous because the distance between the source terminal 406 and the insulating electrode 407 (labeled as distance 411 in the figure) is a limiting feature size that minimizes the cell. In other words, since the insulating electrode 407 does not need to extend laterally all the way to the source region 405, the cell can be made narrower, thus achieving significant space savings. In cross-section 450, the insulating electrode 457 encased in the insulator 458 is even narrower than in cross-section 400. Therefore, the cell spacing of the device based on cross-section 450 can be smaller while still providing capacitance to the drain of the device. As shown in cross-section 450, the insulating electrode 457 does not even extend across the width of the vertical channel region 460. Distance 459 illustrates this difference. In any case, these two cross-sections illustrate how the cell spacing of the integrated electrodes disclosed in these embodiments is not affected by the minimum required source-to-gate spacing of the four-terminal device, wherein insulating electrodes 407, 457 are the gate of the device.

[0037] In specific embodiments of the invention, an insulating electrode can provide shielding for the source terminal of the device. In these embodiments, the insulating electrode can be conceptualized as a shielding plate for a transistor. In addition to the shielding provided by the base region of the device, the source terminal can be shielded using both the insulating electrode and the base region, while the base region also shields the insulating electrode itself. The device may include a base region with a gap in the base region for a vertical channel. In these devices, the current of the device can flow vertically between the drain and source regions through the gap. The base region may be located between the source and drain. In these embodiments, the insulating electrode may be located above the gap and may cover the gap. However, the lateral extent of the insulating electrode may still be smaller than the lateral extent of the channel region. In both cases, the insulating electrode can be used to shield the source terminal, while complete coverage of the gap may provide a higher degree of shielding. Figure 4 Examples of these two methods are provided, such as insulating electrode 407 covering the gap in base region 404, while insulating electrode 457 is located above the gap in base region 454 but does not cover it. In cross-section 400, the lateral extent of insulating electrode 407 does not extend to source region 405. However, in both cases, the cell spacing can be minimized, with the structure of cross-section 450 being more advantageous in terms of cell spacing. In some applications, the lack of overlap, marked by distance 459, is detrimental because less shielding is provided between source terminal 456 and drain (i.e., compared to the case of cross-section 400, in which the electrodes extend beyond the vertical channels 410 on both sides).

[0038] Figure 4 The cross-section also illustrates how the device provides a shielding capacitor (such as shielding capacitor 301) to the composite device (such as composite device 300). As described in the previous paragraph, insulating electrodes 407 and 457 are used to shield a portion of the device, protecting it from voltages applied to the device drain. Both devices can be conceptualized as shielding plates for the source terminals 406 and 456. In particular, insulating electrode 407 provides a high degree of shielding due to its extension to the base region 404. This is because the base regions 404 and 454 provide capacitance to the drain terminal of the device. Figure 4 The device is used as Figure 3 In the JFET 140, the capacitance provided by the base region can be Figure 3 It is part of the shielding capacitor 301.

[0039] In specific embodiments of the invention, the integrated capacitor can be positioned to be separated from the device channel. The integrated capacitor may be located on the same die as the unit cell, but not necessarily in the same cell as the transistor device. Alternatively, the integrated capacitor may be located in the same cell as the transistor, but in a portion away from the device channel. The integrated electrode may be located outside the region where the device source region is located, along the lateral dimension of the channel or perpendicular to that dimension. For example, the insulating electrode may be located in a region formed by… Figure 1 The base region contact occupies the device area, or may be located in, for example, Figure 5 The diagram shows the side view of the main portion of the device. In cross-section 500, the insulating electrode 501 is encased in insulator 502 and is located on the same die as device 503, but not near the channel of device 503. Device 503 and cross-section 500 generally include many elements of cross-section 400, with identical elements labeled with the same reference numerals. Current flowing through device 503 flows from substrate 401 through vertical channel region 420, lateral channel region 403, source region 405, and source end 406. As with cross-section 400, the source region 405, side channel region 403, epitaxial region 402, and substrate 401 may have the same conductivity type, while the base region 404 has the opposite conductivity type. Furthermore, the base contact region 504 may have the same conductivity type as the base region 404 and can be used to bias the base of device 503 via the base contact 505. Device 503 can be much smaller because there is no electrode spacing requirement between the two portions of source end 406. Furthermore, in a particular embodiment, the insulating electrode 501 may be shared with an adjacent device, which is similar to device 503, formed on the right side of the cross-section, and includes a gap similar to 506.

[0040] Although the foregoing specific embodiments of the present invention have been described with respect to vertical planar devices, the invention disclosed herein is more broadly applicable to a variety of transistor types, including mesa devices. A mesa device can be a JFET or a high-power FET. In a specific embodiment of the invention, the source region is formed in the mesa of the JFET, and the insulating electrode is located next to the mesa on a first side of the mesa. The channel region of the JFET may be closer to a second side of the mesa than the first side of the mesa. In a specific embodiment of the invention, the JFET may include an insulator for an insulating end, wherein the insulator contacts the first side of the mesa. The insulator may be formed on the side of the mesa and serve as a dielectric for an integrated high-voltage capacitor, wherein the insulating electrode is the high-voltage capacitor electrode of the capacitor.

[0041] Figure 6Cross-section 600 and axial cross-section 650 of a vertical JFET with integrated capacitors are shown. In axial cross-section 650, the contacts and capacitors are removed to expose more details of the device. The JFET illustrated is a mesa-type vertical JFET. It is called a mesa-type vertical JFET device because the vertical channels of both devices are formed in active material mesas (e.g., mesa 601). Mesa-type vertical JFET devices are also referred to in some cases as trench vertical JFETs. Current ultimately flows from source terminal 602 and source region 603 through vertical channel region 613, drift region 604, and drain region 605. As mentioned above, drain region 605 can be the substrate of the device, and drift region 604 can be an epitaxial layer grown on the substrate. The current is controlled by applying bias voltages to two sets of base contacts 606 and 607 and two sets of base regions 608 / 609 and 610 / 611. In cross-section 600, there is no connection between base regions 610 and 611. However, as can be seen in the axial cross-section 650, a break 651 exists at the junction of the base regions 610 / 611. An appropriate bias voltage can be applied to allow current to flow through the vertical channel region 613 of the device, or to pinch off the channel by depleting charge carriers. As mentioned above, this bias voltage can be positive or negative, depending on the conductivity type of the device channel.

[0042] In a specific embodiment of the present invention, source region 603 can be a heavily doped n-type region, drift region 604 and vertical channel region 613 can be lightly doped n-type regions, base region 608 / 610 can be a heavily doped p-type region, and base region 609 / 611 can be a lightly doped p-type region. In a specific embodiment of the present invention, the polarities of these regions can be reversed (i.e., interchanged).

[0043] Figure 6 It also includes an insulating electrode 614 surrounded by an insulator 615. The insulating electrode 614 can form a capacitor with the drain region 605 of the device. The position of the insulating electrode 614 prevents it from consuming more than 10% of the unbiased majority carrier concentration in the channel formed by the channel region 613. The capacitor can have a... Figure 1 For capacitors of the same capacitance value, cross section 600 represents the cross section of a transistor cell. An insulator 615 is formed on one side of mesa 601. In specific embodiments of the invention, insulator 615 can be any of the aforementioned insulating materials, such as silicon dioxide, silicon nitride, and other insulating materials. In specific embodiments of the invention, insulating electrode 614 can be heavily doped polysilicon or metal. The capacitor formed between drain region 605 and insulating electrode 614 can be used for the same purpose as capacitor 151 if the device in cross section 600 is used to replace JFET 140 in composite device 200.

[0044] Specific embodiments of the JFET disclosed in this application can take various forms and should not be limited to the illustrated cross-sections provided for illustrative purposes only. For example, Figure 6 A single mezzanine with a cross-section of 600 is provided, but the mezzanine shown can be a single unit in a multi-mezzanine device, where each mezzanine shares the channel control, drain, and / or source regions of electrical connection. Furthermore, although... Figure 6 The source region 603 located on the top side of the mesa 601 and the drain region 605 located below the mesa 601 are shown, wherein the vertical channel region 613 provides a conductive path between the drain and source layers when the JFET is turned on, but in certain embodiments, the positions of these terminals can be switched. Furthermore, although... Figure 6 This includes a drift region 604 that isolates the vertical channel region 613 from the drain region 605 and has the same conductivity type as the drain region 605, but with a lower doping concentration. However, the device according to the present invention does not necessarily require a drift region. Furthermore, as... Figure 6 As shown, the term "countertop" should not be limited to a structure with grooves on either side, because a countertop can be defined by a single groove on one side and some form of isolation structure on the other side (i.e., forming a countertop does not require forming two grooves).

[0045] While the specification has been described in detail with reference to specific embodiments of the invention, it should be understood that modifications, variations, and equivalents of these embodiments can be readily conceived by those skilled in the art upon understanding the foregoing. For example, although examples of power transistors are used in this invention, the specific embodiments disclosed herein are more broadly applicable to any JFET. Furthermore, although III-V materials are provided by way of example, the specific embodiments disclosed herein are broadly applicable to any form of semiconductor technology. Moreover, although most of the examples provided refer to drift or epitaxial layers in the illustrated devices, these layers are optional, and portions of the device in contact with epitaxial or drift regions can be replaced by contact with the substrate of the device. These and other modifications and variations to the invention can be made by those skilled in the art without departing from the scope of the invention, the scope of which is more specifically set forth in the appended claims.

[0046] Although the invention has been described with reference to several exemplary embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A semiconductor device, comprising: Junction field-effect transistors, including: Drain region; The drain terminal is coupled to the drain region; Insulating electrodes; and The insulating end is coupled to the insulating electrode; wherein: The junction field-effect transistor has an active region; and The insulating electrode presents a capacitance to the drain end, the capacitance value of which is between 0.1 nanofarads per square centimeter in the active region and 10 nanofarads per square centimeter in the lateral range of the active region.

2. The semiconductor device of claim 1, wherein the junction field-effect transistor further comprises: The channel region forms a channel with an unbiased majority carrier concentration; as well as Base region; where: If a bias voltage is applied to the base region, it will deplete the majority carriers in the channel region; and If a bias voltage is applied to the insulating end, the majority carriers of the channel loss will be at most 10% of the unbiased concentration due to the positioning of the insulating electrode relative to the channel region.

3. The semiconductor device as claimed in claim 1, wherein: The insulating terminal is an integrated high-voltage capacitor terminal, not a channel control terminal.

4. The semiconductor device of claim 1, further comprising: The second transistor, wherein the junction field-effect transistor further includes: The source terminal is coupled to the drain terminal of the second transistor; and The base terminal is coupled to the source terminal of the second transistor; wherein: The insulating end is coupled to the channel control terminal of the second transistor.

5. The semiconductor device of claim 4, wherein the junction field-effect transistor further comprises: A base region, coupled to the base terminal, at least partially shields the insulating electrode from the drain terminal of the junction field-effect transistor; wherein: The junction field-effect transistor and the second transistor form a composite device; and The drain terminal of the junction field-effect transistor is the drain terminal of the composite device.

6. The semiconductor device of claim 1, wherein the junction field-effect transistor further comprises: Base region; as well as The gap is located in the base region; where: The insulating electrode is located above the gap or covers the gap.

7. The semiconductor device of claim 1, wherein the junction field-effect transistor further comprises: Channel area; as well as The insulator of the insulating electrode; wherein: The insulator contacts the channel region and separates the channel region from the insulating electrode by a distance of more than 1,000 angstroms.

8. The semiconductor device of claim 1, wherein the junction field-effect transistor further comprises: Source region; Base region; as well as The gap is located in the base region; where: The current in a junction field-effect transistor (JFET) flows: (1) between the drain and source regions; and (2) perpendicularly through the gap. The lateral extent of the insulating electrode does not extend into the source region.

9. The semiconductor device of claim 8, wherein the junction field-effect transistor further comprises: The source terminal is coupled to the source region; The insulating electrode forms a shield at the source end.

10. The semiconductor device of claim 1, wherein the junction field-effect transistor further comprises: Source region; Base region; The first gap in the base region; as well as The second gap in the base region; wherein: The current in the junction field-effect transistor: (1) flows between the drain region and the source region; and (2) flows perpendicularly through the first gap; The insulating electrode is located above the second gap, but not above the first gap.

11. The semiconductor device of claim 1, wherein the junction field-effect transistor further comprises: Channel area; as well as The source region is formed within the mesa of the junction field-effect transistor; wherein: The insulating electrode is located next to the first side of the platform, which is opposite to the second side of the platform; and The channel area is closer to the second side of the countertop than the first side.

12. The semiconductor device of claim 11, wherein the junction field-effect transistor further comprises: An insulator for an insulating electrode, wherein the insulator is in contact with a first side of the platform.

13. A semiconductor device, comprising: Junction field-effect transistors, including: Drain region, source region, base region; The gullies formed in the gully area; The first end is coupled to the drain region; The second end is coupled to the source region; The third terminal is coupled to the base region; and The integrated high-voltage capacitor terminal is coupled to the integrated high-voltage capacitor electrode; wherein: The integrated high-voltage capacitor electrode and drain region form a capacitor; If a bias voltage is applied to the base region, the majority carriers in the channel will be completely depleted. If a bias voltage is applied to the integrated high-voltage capacitor terminal, the majority carriers of the channel loss will be at most 10% of the unbiased concentration due to the positioning of the integrated high-voltage capacitor electrodes relative to the channel region.

14. The semiconductor device of claim 13, further comprising: The second transistor, wherein the junction field-effect transistor further includes: The source terminal is coupled to the source region and the drain terminal of the second transistor; and The base terminal is coupled to the base region and the source terminal of the second transistor; wherein: The integrated high-voltage capacitor is coupled to the channel control terminal of the second transistor.

15. The semiconductor device of claim 14, wherein: The second terminal is the drain terminal of the junction field-effect transistor; The base region at least partially shields the integrated high-voltage capacitor electrode from the drain terminal of the junction field-effect transistor. The junction field-effect transistor and the second transistor form a composite device; The drain terminal of the junction field-effect transistor is the drain terminal of the composite device.

16. The semiconductor device of claim 13, wherein the junction field-effect transistor further comprises: An insulator is used to shield the integrated high-voltage capacitor electrodes; wherein: The insulator contacts the channel region and separates the channel region from the integrated high-voltage capacitor electrode by a distance of more than 1,000 angstroms.

17. The semiconductor device of claim 13, wherein the junction field-effect transistor further comprises: The gap is located in the base region; where: The current in a junction field-effect transistor (JFET) flows: (1) between the drain and source regions; and (2) perpendicularly through the gap. The lateral range of the integrated high-voltage capacitor electrode is not as large as that of the channel region.

18. The semiconductor device of claim 13, wherein the junction field-effect transistor further comprises: The source region is formed within the mesa of the junction field-effect transistor; wherein: The integrated high-voltage capacitor electrode is located next to the first side of the platform, which is opposite to the second side of the platform. The channel area is closer to the second side of the countertop than the first side.

19. A junction field-effect transistor, comprising: Drain region, source region, base region, channel region; The first terminal is coupled to the drain region; The second end is coupled to the source region; The third end is coupled to the base region; Insulating electrodes are insulated by an insulator. The fourth terminal is coupled to an insulating electrode; wherein: A portion of the channel is in contact with an insulator and is not covered by an insulating electrode, wherein the lateral extent of the active region of the junction field-effect transistor is defined by the combined extent of the source region, drain region and base region, measured from the top-down angle of the junction field-effect transistor; The capacitance value of the insulated electrode to the first end is 0.1 nanofarads per square centimeter in the active region to 10 nanofarads per square centimeter in the lateral range of the active region.

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