Display device and method of manufacturing the same

Abstract

The present invention discloses a display device and a method for manufacturing the display device. The display device includes: a substrate; a first insulating layer, the first insulating layer being disposed on the substrate and comprising an inorganic insulating material; an oxide semiconductor layer, the oxide semiconductor layer being disposed on the first insulating layer; a second insulating layer, the second insulating layer being disposed on the oxide semiconductor layer and comprising an inorganic insulating material; and a third insulating layer, the third insulating layer being disposed on a gate electrode and comprising an inorganic insulating material, the gate electrode being disposed on the second insulating layer. The oxide semiconductor layer includes a first conductive region, a second conductive region, and a channel region located between the first conductive region and the second conductive region, and according to equation (1), the value of HC in the channel region of the oxide semiconductor layer is less than 30%.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0108938, filed on September 3, 2019, in the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] One or more embodiments relate to a display device and a method of manufacturing the display device. Background Art

[0004] The purposes of display devices are diversifying. Furthermore, as display devices have become thinner and lighter, their scope of use has gradually expanded. In particular, with the increasing demand for high-resolution and large-area display devices, there is a need for high-quality thin-film transistors that can be miniaturized and are not affected by voltage drop. Summary of the Invention

[0005] One or more embodiments include a display device including a transistor including an oxide semiconductor layer and a method of manufacturing the display device.

[0006] According to one or more embodiments, a display device includes: a substrate; a first insulating layer disposed on the substrate and including an inorganic insulating material; an oxide semiconductor layer disposed on the first insulating layer; a second insulating layer disposed on the oxide semiconductor layer and including an inorganic insulating material; a gate electrode disposed on the second insulating layer; and a third insulating layer disposed on the gate electrode and including an inorganic insulating material. The oxide semiconductor layer includes a first conductive region, a second conductive region, and a channel region located between the first conductive region and the second conductive region. The hydrogen concentration of the oxide semiconductor layer is approximately 5×10 20 atoms / cm 3 to about 2×10 21 atoms / cm 3 , and according to equation (1), the value of HC in the channel region of the oxide semiconductor layer is less than 30%: HC = (Max-Min) / Avg×100%------Equation (1), wherein Max represents the maximum hydrogen concentration value detected from multiple points within the channel region, Min represents the minimum hydrogen concentration value detected from multiple points within the channel region, and Avg represents the average hydrogen concentration value detected from multiple points within the channel region.

[0007] The hydrogen concentration in the channel region can be around 1×10 21 atoms / cm 3 to about 2×10 21 atoms / cm 3within the range.

[0008] The second insulating layer may include a silicon oxide layer.

[0009] At least one of the first insulating layer and the third insulating layer may include a silicon oxide layer or a silicon nitride layer.

[0010] The display device may further include a metal layer interposed between the substrate and the first insulating layer.

[0011] The oxide semiconductor layer may contain fluorine, and the concentration of fluorine in the oxide semiconductor layer may be about 5×10 17 atoms / cm 3 to about 5×10 18 atoms / cm 3 within the range.

[0012] The metal layer may include a bottom gate electrode.

[0013] According to one or more embodiments, a display device includes: a substrate; a first transistor and a second transistor, each of the first transistor and the second transistor being disposed on the substrate, wherein one of the first transistor and the second transistor includes an oxide semiconductor layer, the oxide semiconductor layer including a channel region, a first conductive region, and a second conductive region, wherein the first conductive region and the second conductive region are respectively located on two opposite sides of the channel region; a first insulating layer, the first insulating layer being interposed between the substrate and the oxide semiconductor layer; a gate electrode, the gate electrode overlapping the channel region of the oxide semiconductor layer; a second insulating layer, the second insulating layer being interposed between the oxide semiconductor layer and the gate electrode; and a third insulating layer, the third insulating layer being disposed on the second insulating layer and covering the gate electrode. The hydrogen concentration of the oxide semiconductor layer is approximately 5×10 20 atoms / cm 3 to about 2×10 21 atoms / cm 3 , and according to equation (1), the value of HC in the channel region of the oxide semiconductor layer is less than 30%: HC = (Max-Min) / Avg×100%------Equation (1), wherein Max represents the maximum hydrogen concentration value detected from multiple points within the channel region, Min represents the minimum hydrogen concentration value detected from multiple points within the channel region, and Avg represents the average hydrogen concentration value detected from multiple points within the channel region.

[0014] The hydrogen concentration in the channel region can be around 1×10 21 atoms / cm 3 to about 2×10 21 atoms / cm 3 within the range.

[0015] The second insulating layer includes a silicon oxide layer. At least one of the first insulating layer and the third insulating layer includes a silicon oxide layer or a silicon nitride layer.

[0016] The display device may further include a metal layer interposed between the substrate and the first insulating layer.

[0017] The metal layer may have the same voltage level as that of the gate electrode.

[0018] The other of the first transistor and the second transistor may include a silicon transistor.

[0019] According to one or more embodiments, a method for manufacturing a display device includes: forming a first insulating layer including an inorganic insulating material on a substrate; forming an oxide semiconductor layer on the first insulating layer; forming a second insulating layer including an inorganic insulating material on the oxide semiconductor layer; forming a gate electrode on the second insulating layer; and forming a third insulating layer including an inorganic insulating material on the gate electrode. Forming the third insulating layer is performed by chemical vapor deposition without ammonia. The oxide semiconductor layer includes a first conductive region, a second conductive region, and a channel region located between the first conductive region and the second conductive region, and according to equation (1), the value of HC in the channel region of the oxide semiconductor layer is less than 30%: HC = (Max-Min) / Avg×100%------Equation (1), where Max represents the maximum hydrogen concentration value detected from multiple points in the channel region, Min represents the minimum hydrogen concentration value detected from the multiple points in the channel region, and Avg represents the average hydrogen concentration value detected from the multiple points in the channel region.

[0020] The hydrogen concentration in the channel region can be around 1×10 21 atoms / cm 3 to about 2×10 21 atoms / cm 3 within the range.

[0021] The second insulating layer may include a silicon oxide layer, and the silicon oxide layer may cover the channel region, at least a portion of the first conductive region, and at least a portion of the second conductive region.

[0022] The method may further include applying heat to the first insulating layer before forming the oxide semiconductor layer.

[0023] The method may further include forming a metal layer on the substrate before forming the first insulating layer.

[0024] Forming the metal layer may include forming an initial layer including a metal, and etching the initial layer so that the metal layer overlaps with a channel region of the oxide semiconductor layer, and etching the initial layer may include using a gas including fluorine.

[0025] The oxide semiconductor layer may include fluorine, and the concentration of fluorine may be about 5×1017 atoms / cm 3 to about 5×10 18 atoms / cm 3 within the range.

[0026] The foregoing and other aspects and features of certain embodiments of the present disclosure will be more fully apparent from the following description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figures 1 to 9 A process of forming an oxide transistor of a display device according to an embodiment is explained.

[0028] Figure 10 is a plan view of an oxide semiconductor layer of an oxide transistor according to an embodiment.

[0029] Figure 11 A secondary ion mass spectrometry apparatus for measuring the concentration of hydrogen or fluorine of an oxide transistor according to an embodiment is explained.

[0030] Figure 12 is an equivalent circuit diagram of one pixel of a display device according to an embodiment.

[0031] Figure 13 is a cross-sectional view of a display device according to an embodiment.

[0032] Figure 14 Graphs showing secondary ion mass spectrometry (SIMS) inspection results of an oxide transistor of a display device according to an embodiment and graphs showing analysis results of some materials of the oxide transistor.

[0033] Figure 15 is a graph showing the hydrogen concentration in the oxide semiconductor layer of the oxide transistor of the display device according to the embodiment. DETAILED DESCRIPTION

[0034] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals may refer to like elements throughout. In this regard, the embodiments may have different forms and should not be construed as limited to the descriptions set forth herein.

[0035] Hereinafter, the embodiments are described in detail with reference to the accompanying drawings. In the drawings, the same or corresponding elements may be given the same reference numerals, and their repeated descriptions may be omitted.

[0036] Herein, when a value is described as being approximately equal to another value, for example, "the width may be about 0.1 mm to about 1 mm," it is understood that the values are equal to each other within measurement error, or, if not equal in measurement, are close enough to be functionally equal to each other, as would be understood by one of ordinary skill in the art.

[0037] It will be understood that when a layer, region, or component is referred to as being “formed on” another layer, region, or component, it can be directly or indirectly formed on the other layer, region, or component.

[0038] The sizes of elements in the drawings may be exaggerated for convenience of explanation.

[0039] It will be understood that when a layer, region or component is referred to as being “connected” to another layer, region or component, it may be “directly connected” to the other layer, region or component and / or may be “indirectly connected” to the other layer, region or component with other layers, regions or components interposed therebetween.

[0040] In the examples described below, the x-axis, the y-axis, and the z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense.

[0041] For ease of description, although the display device according to the embodiment is described as an organic light emitting display device as an example, the display device according to the present disclosure is not limited thereto. For example, the display device may be an inorganic light emitting display.

[0042] Figures 1 to 9 A process of forming an oxide transistor of a display device according to an embodiment is explained.

[0043] refer to Figure 1 According to an embodiment, the metal layer 105 is formed on the substrate 100. The substrate 100 may include a glass material or a polymer resin. For example, the substrate 100 includes a glass material including SiO2 as a main component.

[0044] According to an embodiment, the metal layer 105 has a predetermined width and a predetermined length, and is formed by forming an initial metal layer and etching the initial metal layer. An exemplary, non-limiting etching process is dry etching. Etching uses a gas including fluorine. In an embodiment, the metal layer 105 may include a single layer or multiple layers and include one or more of aluminum (Al), molybdenum (Mo), copper (Cu), and titanium (Ti). The metal layer 105 is formed by forming an initial metal layer including the above materials on the substrate 100 and then etching the initial metal layer. For example, the metal layer 105 can be patterned by dry etching using sulfur hexafluoride (SF6).

[0045] According to an embodiment, the metal layer 105 will be connected to the Figure 4 In an embodiment, although the process shown in FIG. Figure 4, the metal layer 105 completely overlaps with the oxide semiconductor layer 120, but in another embodiment, the metal layer 105 overlaps with or covers a portion of the oxide semiconductor layer 120, such as a channel region of the oxide semiconductor layer 120. The metal layer 105 blocks light incident on the oxide semiconductor layer 120 or serves as a gate electrode of the oxide semiconductor layer 120 by having a predetermined voltage, such as a gate voltage.

[0046] refer to Figure 2 According to an embodiment, a bottom (or lower) insulating layer 110 is formed on the substrate 100. The bottom insulating layer 110 includes an inorganic insulating material and is formed by chemical vapor deposition (CVD). For example, the bottom insulating layer 110 is deposited by plasma enhanced chemical vapor deposition (PECVD). Alternatively, in other embodiments, the bottom insulating layer 110 can be deposited by various other deposition methods, such as atmospheric pressure CVD (APCVD) or low pressure CVD (LPCVD).

[0047] According to an embodiment, the bottom insulating layer 110 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. The bottom insulating layer 110 may have a single-layer structure or a multi-layer structure including the above materials. For example, the bottom insulating layer 110 may have a double-layer structure of a silicon nitride layer and a silicon oxide layer.

[0048] According to an embodiment, the silicon nitride layer is an insulating layer having a relatively high hydrogen content compared to the silicon oxide layer. A process according to an embodiment of the present invention for forming the silicon nitride layer by using PECVDA is described below.

[0049] According to an embodiment, a substrate 100 is inserted into a chamber and a plasma atmosphere is formed, with the substrate 100 being the object for deposition. A silicon nitride layer is formed using silane (SiH4) and ammonia (NH3). In an embodiment, the layer-forming gas for forming the silicon nitride layer includes nitrogen molecules (N2), silane, and ammonia. Silane is decomposed into silicon (Si) and hydrogen (H) by the plasma, and ammonia is decomposed into nitrogen (N) and hydrogen (H). When each decomposed atom falls on the substrate 100 and each falling atom reacts based on the surface temperature of the substrate 100, a silicon nitride layer is formed on the substrate 100.

[0050] According to an embodiment, the silicon oxide layer is formed by PECVD using silane and nitrogen oxide (NO). In this case, the silicon oxide layer contains hydrogen (H). Alternatively, in another embodiment, the silicon oxide layer is formed using a layer-forming gas including silicon fluoride and oxygen. For silicon fluoride, for example, silicon tetrafluoride (SiF4) and disilicon hexafluoride (Si2F6) are used. In the case where a layer-forming gas including silicon fluoride is used, the silicon oxide layer contains fluorine (F).

[0051] In one embodiment, the silicon oxide layer formed using silane and nitride oxide (N2O) also includes hydrogen (H) and fluorine (F). In this case, the fluorine (F) is derived from sulfur hexafluoride (SF6) gas used when etching the metal layer 105, or from a cleaning process or drying process of the chamber during the PECVD process.

[0052] refer to Figure 3 According to an embodiment, a heat treatment process is performed after forming the bottom insulating layer 110. The bottom insulating layer 110 includes hydrogen (H). Since hydrogen, hydroxyl groups, or moisture may affect the oxide semiconductor layer described below, their concentration is reduced in advance through the heat treatment process.

[0053] According to an embodiment, hydrogen (H) or fluorine (F) in the bottom insulating layer 110 is removed through a heat treatment process. The heat treatment process is performed at a temperature greater than about 400° C., for example, about 460° C., for about 1 hour. The heat treatment process reduces the concentration of hydrogen (H) or fluorine (F) in the bottom insulating layer 110.

[0054] refer to Figure 4 According to an embodiment, the oxide semiconductor layer 120 is formed on the bottom insulating layer 110. The oxide semiconductor layer 120 includes one of Zn oxide, In-Zn oxide, and Ga-In-Zn oxide as a Zn oxide-based material. The oxide semiconductor layer 120 includes a semiconductor including a Zn oxide-based material containing a metal such as In, Ga, and / or Sn. For example, the oxide semiconductor layer 120 may include one of an IGZO (In-Ga-Zn-O) semiconductor, an ITZO (In-Sn-Zn-O) semiconductor, and an IGTZO (In-Ga-Sn-Zn-O) semiconductor.

[0055] In an embodiment, the oxide semiconductor layer 120 is formed by a sputtering method using an In-Ga-Zn-O-based oxide target. For example, the oxide semiconductor layer 120 is formed by a sputtering method in an inert gas (such as argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere including an inert gas and oxygen.

[0056] refer to Figure 5 According to an embodiment, an intermediate insulating layer 130 is formed on the oxide semiconductor layer 120. The intermediate insulating layer 130 includes an inorganic insulating material and functions as a gate insulating layer between a gate electrode described below and the oxide semiconductor layer 120.

[0057] According to an embodiment, the intermediate insulating layer 130 completely covers the substrate 100. For example, Figure 3The top surface of the oxide semiconductor layer 120 shown in FIG is completely covered by the intermediate insulating layer 130. When the intermediate insulating layer 130 includes silicon nitride, because silicon nitride already includes a relatively high hydrogen content as described above, during the process of forming the intermediate insulating layer 130, the oxide semiconductor layer 120 below the intermediate insulating layer 130 becomes completely conductive. In this case, the oxide semiconductor layer 120 may not function as an active layer of the transistor. Therefore, the intermediate insulating layer 130 is formed to include silicon oxide.

[0058] According to the embodiment, Figure 2 The middle insulating layer 130 is formed by a CVD process, such as PECVD, APCVD or LPCVD, similar to the process for forming the bottom insulating layer 110 described above. The specific formation process is the same as the formation process described above.

[0059] refer to Figure 6 According to an embodiment, a gate electrode 140 is formed on the intermediate insulating layer 130. The gate electrode 140 may include a single layer or multiple layers including one or more of aluminum (Al), molybdenum (Mo), copper (Cu), and titanium (Ti). The gate electrode 140 overlaps a portion of the oxide semiconductor layer 120.

[0060] refer to Figure 7 According to an embodiment, a top (or upper) insulating layer 150 is formed on the gate electrode 140. The top insulating layer 150 includes an inorganic insulating material. The top insulating layer 150 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride. The top insulating layer 150 can have a single-layer structure or a multi-layer structure including the above materials. For example, the top insulating layer 150 has a double-layer structure of a silicon nitride layer and a silicon oxide layer.

[0061] According to the embodiment, Figure 2 Similar to the process for forming the bottom insulating layer 110 described above, the top insulating layer 150 is formed by a CVD process, such as PECVD, APCVD, or LPCVD.

[0062] Hydrogen from gases used during the process of forming the top insulating layer 150 (such as those used in PECVD) can help make a portion of the oxide semiconductor layer 120 conductive. For example, according to an embodiment, a portion of the oxide semiconductor layer 120 that does not overlap with the gate electrode 140 can be made conductive by the hydrogen, and the oxide semiconductor layer 120 will include a channel region 121, a first conductive region 122, and a second conductive region 123. The first conductive region 122 and the second conductive region 123 are on opposite sides of the channel region 121.

[0063] According to an embodiment, when a large amount of hydrogen is generated during the process of forming the top insulating layer 150 , an area of the oxide semiconductor layer 120 that becomes conductive by the hydrogen increases, and thus the length of the channel region 121 is reduced.

[0064] To prevent this, according to an embodiment, a silicon nitride layer is formed as the top insulating layer 150 by PECVD without ammonia (NH3). In this case, the silicon nitride layer is formed by using silane and nitrogen (N2). Since PECVD without ammonia (NH3) contains a small amount of hydrogen compared to the above-mentioned PECVD, the hydrogen concentration in the silicon nitride layer formed by PECVD without ammonia (NH3) is relatively low, which prevents the length of the channel region from being reduced.

[0065] refer to Figure 8 According to an embodiment, after forming the contact hole CNT exposing the conductive region (e.g., one or both of the first conductive region 122 and the second conductive region 123) of the oxide semiconductor layer 120, an annealing process is performed. In an embodiment, the annealing process is performed at a temperature of about 350° C. or higher, or about 400° C. or higher.

[0066] According to an embodiment, the oxide semiconductor layer 120 is further conductively modified by an annealing process. The hydrogen concentrations of the first conductive region 122 and the second conductive region 123 change before and after the annealing process. For example, the hydrogen concentrations of the first conductive region 122 and the second conductive region 123 after the annealing process are higher than the hydrogen concentrations of the first conductive region 122 and the second conductive region 123 before the annealing process. One of the first conductive region 122 and the second conductive region 123 corresponds to a source region, and the other of the first conductive region 122 and the second conductive region 123 corresponds to a drain region.

[0067] refer to Figure 9 According to an embodiment, an electrode layer connected to at least one of the first conductive region 122 and the second conductive region 123 is formed. In an embodiment, Figure 9 There are shown first and second electrode layers 161 and 162 respectively connected to the first and second conductive regions 122 and 123. One of the first and second electrode layers 161 and 162 corresponds to a source electrode of the transistor, and the other corresponds to a drain electrode of the transistor.

[0068] According to an embodiment, the first electrode layer 161 and the second electrode layer 162 each have a single-layer structure or a multi-layer structure including one or more of aluminum (Al), molybdenum (Mo), copper (Cu), and titanium (Ti). After forming layers including the above materials, the first electrode layer 161 and the second electrode layer 162 are patterned by a process such as dry etching.

[0069] Figure 10 is a plan view of an oxide semiconductor layer of an oxide transistor according to an embodiment.

[0070] refer to Figure 10 According to an embodiment, the oxide semiconductor layer 120 includes a channel region 121, a first conductive region 122, and a second conductive region 123, wherein the first conductive region 122 is on a first side of the channel region 121, and the second conductive region 123 is on a second side of the channel region 121. The oxide semiconductor layer 120 includes a Zn oxide-based material. The Zn oxide-based material includes one or more of Zn oxide, In-Zn oxide, and Ga-In-Zn oxide. The oxide semiconductor layer 120 includes a semiconductor including a Zn oxide-based material containing a metal, such as one or more of In, Ga, and Sn. For example, the oxide semiconductor layer 120 includes one of an IGZO (In-Ga-Zn-O) semiconductor, an ITZO (In-Sn-Zn-O) semiconductor, and an IGTZO (In-Ga-Sn-Zn-O) semiconductor.

[0071] According to an embodiment, the hydrogen concentrations of the first conductive region 122 and the second conductive region 123 are higher than the hydrogen concentration of the channel region 121. Figures 1 to 9 One or both of the described processes of forming the top insulating layer 150 and the annealing process introduce hydrogen into the first and second conductive regions 122 and 123 , so the hydrogen concentrations of the first and second conductive regions 122 and 123 are higher than that of the channel region 121 .

[0072] According to an embodiment, a typical hydrogen concentration of the oxide semiconductor layer 120 is about 5×10 20 atoms / cm 3 to about 2×10 21 atoms / cm 3 The hydrogen concentration in the channel region 121 of the oxide semiconductor layer 120 is about 1×10 21 atoms / cm 3 to about 2×10 21 atoms / cm 3 within the range.

[0073] According to the embodiment, when the difference in hydrogen concentration at each measurement point of the channel region 121 is large, the driving performance of the display device including the oxide semiconductor layer deteriorates, and the display quality of the display device also deteriorates. In contrast, in the channel region 121 of the oxide semiconductor layer 120 manufactured according to the above process, the hydrogen concentration value HC in the following equation (1) is less than 30%.

[0074] HC=(Max-Min) / Avg×100%-------Equation (1),

[0075] Where Max represents the maximum hydrogen concentration value detected from multiple points within the channel region 121, Min represents the minimum hydrogen concentration value detected from multiple points within the channel region 121, and Avg represents the average hydrogen concentration value detected from multiple points within the channel region 121. When the above conditions are not met, the channel length of the channel region 121 cannot be sufficiently ensured, and the display quality of the display device may not be ensured due to, for example, the occurrence of leakage current. More preferably, the HC value according to equation (1) may be 20% or less.

[0076] According to an embodiment, the hydrogen concentration of the channel region 121 is measured in an effective region 121VR defined inward from the edge of the channel region 121. Assuming that W is the width of the channel region 121 in the width direction and L is the length of the channel region 121 between the first conductive region 122 and the second conductive region 123, the edge region of the channel region 121 having a width and length of approximately 0.15%×L and 0.15%×W is where noise occurs when measuring the hydrogen concentration. Therefore, the hydrogen concentration is measured in an effective region 121VR separated from the edge of the channel region by approximately 0.15%×L and 0.15%×W. Figure 10 The hydrogen concentration is measured in the region marked in FIG. 1 (hereinafter referred to as the effective region 121VR). In an embodiment, Figure 10 The display active region 121VR has a quadrilateral shape. In an embodiment, the active region 121VR has a curved or serpentine shape. The active region 121VR, which is spaced apart from the edge of the channel region 121, has a length corresponding to approximately 99.7%×L and a width corresponding to approximately 99.7%×W. In an embodiment, the length L of the channel region 121 is approximately 10 μm or less.

[0077] In an embodiment, the hydrogen concentration of the active region 121VR of the channel region 121 is about 5×10 20 atoms / cm 3 to about 2×10 21 atoms / cm 3 , and the hydrogen concentration at any first point in the active region 121VR is less than twice the hydrogen concentration at the second point. For example, the hydrogen concentration in the active region 121VR of the channel region 121 may be about 1×10 21 atoms / cm 3 to about 2×10 21 atoms / cm 3 within the range.

[0078] According to an embodiment, the oxide semiconductor layer 120 includes Figure 1The fluorine concentration in the channel region 121 of the oxide semiconductor layer 120 is less than that in the first conductive region 122 or the second conductive region 123. In an embodiment, the fluorine concentration in the channel region 121 is about 5×10 17 atoms / cm 3 to about 5×10 18 atoms / cm 3 within the range.

[0079] According to an embodiment, the hydrogen concentration and the fluorine concentration may be measured by secondary ion mass spectrometry (SIMS).

[0080] Figure 11 A secondary ion mass spectrometry apparatus for measuring the concentration of hydrogen or fluorine of an oxide transistor according to an embodiment is explained.

[0081] refer to Figure 11 The SIMS device includes a chamber 1100, a primary ion source 1200, an electron generation source 1300 and a secondary ion optical system 1400.

[0082] According to an embodiment, the primary ion source 1200 generates and emits an ion beam. The primary ion source 1200 emits the primary ion beam PB1 toward a sample placed inside the chamber 1100, such as the oxide semiconductor layer OS on the substrate Sub. The chamber 1100 is in a vacuum state.

[0083] According to an embodiment, the primary ion source 1200 emits cesium ions (Cs + ) is a primary ion beam PB1. After the primary ion beam PB1 is irradiated onto the sample, secondary ions SB2 emitted from the sample propagate to the secondary ion optical system 1400 by sputtering. The primary ion beam PB1 moves in a direction perpendicular to the sample, such as the oxide semiconductor layer OS, and the secondary ions SB2 propagate in a direction perpendicular to the sample (e.g., the oxide semiconductor layer OS). For example, the path of the primary ion beam PB1 and the path of the secondary ions SB2 are on the same axis.

[0084] According to an embodiment, the electron generation source 1300 includes an electron gun that emits an electron beam EB to prevent the sample from being charged by sputtered ions.

[0085] According to the embodiment, Figure 11 The SIMS apparatus shown in FIG applies a predetermined voltage to a substrate Sub, such as a glass substrate. Because a glass substrate has low conductivity compared to a wafer, even when an electron generating source 1300 is provided, there is a limit to preventing charging, and the ion propagation path may be distorted.

[0086] According to an embodiment, in order to prevent the path from being twisted, the first to fourth wire portions 1501, 1502, 1503 and 1504 are arranged outside the chamber 1100 to generate an electromagnetic field. The electromagnetic field is formed in the X-axis direction (or Y-axis direction) and the Z-axis direction. The electromagnetic field can prevent the ion beam path, such as the deformation of the primary ion beam PB1 or the secondary ion beam SB2. In an embodiment, the first to fourth wire portions 1501, 1502, 1503 and 1504 include enameled wires.

[0087] According to an embodiment, although charging is prevented by using the electron generating source 1300 and the beam path is corrected by using the first to fourth wire portions 1501, 1502, 1503 and 1504, when the substrate Sub includes a glass substrate, the high voltage applied to the substrate Sub may cause cracks in the glass. In addition, charging on the surface of the test piece may deform the detected image. Therefore, a method is used in which the equipment source reduces the acceleration voltage. For example, the absolute value of the power supply voltage supplied to the SIMS device is about 4kV. The voltage applied to the test piece (such as a glass substrate) is about -4kV, and the voltage applied to the primary ion source 1200 is about +4kV.

[0088] Figure 12 is an equivalent circuit diagram of one pixel of a display device according to an embodiment.

[0089] refer to Figure 12 According to an embodiment, a pixel PX of a display device includes a pixel circuit PC and a light emitting diode, such as an organic light emitting diode OLED, electrically connected to the pixel circuit PC.

[0090] According to an embodiment, the pixel PX includes a plurality of first to seventh transistors T1, T2, T3, T4, T5, T6, and T7; a first capacitor Cst; a second capacitor Cbt; an organic light emitting diode OLED as a display element; signal lines SL1, SL2, SL3, SL4, EL, and DL; an initialization voltage line VIL; and a power supply voltage line PL connected to the initialization voltage line VIL. In another embodiment, at least one of the signal lines SL1, SL2, SL3, SL4, EL, and DL; the initialization voltage line VIL or the power supply voltage line PL may be shared by adjacent pixels. Figure 12 In the embodiment of the present invention, the third transistor T3 and the fourth transistor T4 are provided as n-channel metal oxide semiconductor (NMOS) field effect transistors, and the remaining transistors are provided as p-channel metal oxide semiconductor (PMOS) field effect transistors.

[0091] According to an embodiment, the signal lines include a plurality of data lines DL, a plurality of first scan lines SL1, a plurality of second scan lines SL2, a plurality of third scan lines SL3, a plurality of fourth scan lines SL4, and a plurality of emission control lines EL. In an embodiment, the second scan line SL2 is connected to the first scan line SL1. In this case, the first scan signal GP1 is the second scan signal GP2.

[0092] According to an embodiment, the power voltage line PL transmits the first power voltage ELVDD to the first transistor T1 , and the initialization voltage line VIL transmits the initialization voltage Vint to the pixel PX, wherein the initialization voltage Vint initializes the first transistor T1 and the organic light emitting diode OLED.

[0093] According to an embodiment, during a process of forming signal lines, power supply lines PL, and initialization voltage lines VIL on a substrate, first scan lines SL1, second scan lines SL2, third scan lines SL3, fourth scan lines SL4, emission control lines EL, and initialization voltage lines VIL extend in a first direction and are spaced apart from each other. Data lines DL and power supply voltage lines PL extend in a second direction intersecting the first direction and are spaced apart from each other.

[0094] According to an embodiment, the first transistor T1 is connected to the power supply voltage line PL through the fifth transistor T5 and is electrically connected to the organic light emitting diode OLED through the sixth transistor T6. The first transistor T1 is used as a driving transistor, receives the data signal DATA and drives the driving current I according to the switching operation of the second transistor T2. OLED Supplied to the organic light emitting diode OLED.

[0095] According to an embodiment, the second transistor T2 is connected to the first scan line SL1 and the data line DL, and is connected to the power supply voltage line PL through the fifth transistor T5. The second transistor T2 is turned on in response to the first scan signal GP1 received through the first scan line SL1, and performs a switching operation to transmit the data signal DATA received through the data line DL to the node N.

[0096] According to an embodiment, the third transistor T3 is connected to the fourth scan line SL4 and is electrically connected to the organic light emitting diode OLED through the sixth transistor T6. The third transistor T3 is turned on in response to the fourth scan signal GN2 received through the fourth scan line SL4 and diode-connects the first transistor T1.

[0097] According to an embodiment, the fourth transistor T4 is connected to the third scan line SL3 and the initialization voltage line VIL, is turned on in response to the third scan signal GN1 received through the third scan line SL3, and transmits the initialization voltage Vint from the initialization voltage line VIL to the gate electrode of the first transistor T1, thereby initializing the voltage of the gate electrode of the first transistor T1.

[0098] According to an embodiment, the fifth transistor T5 and the sixth transistor T6 are connected to the emission control line EL, are simultaneously turned on in response to the emission control signal EM received through the emission control line EL, and constitute a current path such that the driving current I OLED The voltage flows from the power supply line PL to the organic light emitting diode OLED.

[0099] According to an embodiment, the seventh transistor T7 is connected to the second scan line SL2 and the initialization voltage line VIL. The seventh transistor T7 is turned on in response to the second scan signal GP2 received through the second scan line SL2, and transmits the initialization voltage Vint from the initialization voltage line VIL to the organic light emitting diode OLED, thereby initializing the organic light emitting diode OLED. In some embodiments, the seventh transistor T7 is omitted.

[0100] According to an embodiment, the first capacitor Cst includes a first electrode CE1 and a second electrode CE2. The first electrode CE1 is connected to the gate electrode of the first transistor T1, and the second electrode CE2 is connected to the power supply voltage line PL. The first capacitor Cst is a storage capacitor. The first capacitor Cst stores and holds a voltage corresponding to the difference between the power supply voltage line PL and the two opposite end portions of the gate electrode of the first transistor T1, thereby holding the voltage applied to the gate electrode of the first transistor T1.

[0101] According to an embodiment, the second capacitor Cbt includes a third electrode CE3 and a fourth electrode CE4. The third electrode CE3 is connected to the first scan line SL1 and the gate electrode of the second transistor T2. The fourth electrode CE4 is connected to the gate electrode of the first transistor T1 and the first electrode CE1 of the first capacitor Cst. The second capacitor Cbt is a boost capacitor. When the first scan signal GP1 of the first scan line SL1 is a voltage that turns off the second transistor T2, the second capacitor Cbt boosts the voltage at the node N and reduces the black voltage required to display black.

[0102] According to an embodiment, the organic light emitting diode OLED is electrically connected to a pixel circuit PC including a transistor and a capacitor. The organic light emitting diode OLED includes a pixel electrode and an opposite electrode. The opposite electrode receives a second power supply voltage ELVSS. The organic light emitting diode OLED receives a driving current I from the first transistor T1. OLED And emits light to display images.

[0103] In this embodiment, at least one of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7 includes an oxide semiconductor layer, and the remaining transistors include silicon semiconductor layers. Specifically, the first transistor T1, which directly affects the brightness of the display device, includes a semiconductor layer containing highly reliable polycrystalline silicon, and this configuration enables the implementation of a high-resolution display device.

[0104] According to embodiments, because the oxide semiconductor layer has high carrier mobility and low leakage current, the voltage drop is small even when the driving time is long. That is, because the image color change corresponding to the voltage drop is small even during low-frequency driving, the display device can be driven at a low frequency. Because the oxide semiconductor layer has low leakage current, at least one of the fourth transistor T4 and the third transistor T3 connected to the gate electrode of the first transistor T1 may include an oxide semiconductor layer, thereby preventing leakage current from flowing to the gate electrode of the first transistor T1 and, at the same time, reducing power consumption.

[0105] Figure 13 is a cross-sectional view of a display device according to an embodiment. Figure 13 A partial area of the display device is shown, and shows a substrate 200 , first and sixth transistors T1 and T6 including a silicon semiconductor, a fourth transistor T4 including an oxide semiconductor layer, a first capacitor Cst, and a second capacitor Cbt.

[0106] According to an embodiment, the substrate 200 includes one of a glass material, a ceramic material, a metal material, and a flexible or bendable material. When the substrate 200 includes a flexible or bendable material, the substrate 200 includes a polymer resin such as polyethersulfone (PES), polyarylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP).

[0107] According to an embodiment, the buffer layer 210 is disposed on the substrate 200 , improves the flatness of the top surface of the substrate 200 , and includes an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0108] According to an embodiment, the first semiconductor layer AS1 of the first transistor T1 and the sixth semiconductor layer AS6 of the sixth transistor T6 are disposed on the buffer layer 210. The first semiconductor layer AS1 and the sixth semiconductor layer AS6 include silicon semiconductors. Figure 13The first high-concentration impurity region B1 and the channel region A1 of the first semiconductor layer AS1, and the first high-concentration impurity region B6 and the second high-concentration impurity region C6 and the channel region A6 of the sixth semiconductor layer AS6 are shown. The first high-concentration impurity region B1 is doped with impurities and is conductive, and the first high-concentration impurity region B6 and the second high-concentration impurity region C6 are also doped with impurities and are conductive.

[0109] According to an embodiment, the first gate electrode G1 of the first transistor T1 and the sixth gate electrode G6 of the sixth transistor T6 are respectively located on the first semiconductor layer AS1 and the sixth semiconductor layer AS6. The first insulating layer 211 is provided between the first semiconductor layer AS1 and the first gate electrode G1, and between the sixth semiconductor layer AS6 and the sixth gate electrode G6.

[0110] According to an embodiment, the first insulating layer 211 includes an inorganic material including one or more of oxide and nitride. For example, the first insulating layer 211 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide.

[0111] According to an embodiment, the first gate electrode G1 overlaps the channel region A1 of the first semiconductor layer AS1, and the sixth gate electrode G6 overlaps the channel region A6 of the sixth semiconductor layer AS6. The first gate electrode G1 and the sixth gate electrode G6 may each include a single layer or multiple layers including one or more of molybdenum (Mo), copper (Cu), and titanium (Ti).

[0112] According to an embodiment, the first electrode CE1 of the first capacitor Cst and the third electrode CE3 of the second capacitor Cbt are provided on the same layer as the first gate electrode G1 and the sixth gate electrode G6. The first electrode CE1 of the first capacitor Cst and the third electrode CE3 of the second capacitor Cbt include the same material as the first gate electrode G1 and the sixth gate electrode G6.

[0113] According to an embodiment, a second insulating layer 212 is provided on the first gate electrode G1 and the sixth gate electrode G6. The second insulating layer 212 includes an inorganic material including one or more of an oxide and a nitride. For example, the second insulating layer 212 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide.

[0114] According to an embodiment, the second electrode CE2 of the first capacitor Cst is disposed on the second insulating layer 212 and overlaps the first electrode CE1 of the first capacitor Cst. The second electrode CE2 may have a single layer structure or a multilayer structure including one or more of molybdenum (Mo), copper (Cu), and titanium (Ti).

[0115] According to an embodiment, the third insulating layer 213 is provided on the second electrode CE2 of the first capacitor Cst. The third insulating layer 213 includes an inorganic material including an oxide or a nitride. For example, the third insulating layer 213 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide.

[0116] According to an embodiment, the first capacitor Cst overlaps with the first transistor T1. For example, the first gate electrode G1 of the first transistor T1 serves as the first electrode CE1 of the first capacitor Cst.

[0117] According to an embodiment, the fourth semiconductor layer AO4 of the fourth transistor T4 includes an oxide semiconductor layer and is disposed on the third insulating layer 213. The fourth semiconductor layer AO4 includes a first conductive region B4 and a second conductive region C4, and a channel region A4 between the first conductive region B4 and the second conductive region C4. The first conductive region B4 and the second conductive region C4 are conductive and spaced apart from each other. The fourth semiconductor layer AO4 includes Zn oxide, In-Zn oxide, Ga-In-Zn oxide, or the like.

[0118] According to an embodiment, the fourth transistor T4 includes a dual gate electrode. For example, a first gate electrode G41 is disposed above the fourth semiconductor layer AO4 of the fourth transistor T4, and a second gate electrode G42 is disposed below the fourth semiconductor layer AO4. The first gate electrode G41 and the second gate electrode G42 overlap with the channel region A4 of the fourth semiconductor layer AO4.

[0119] According to an embodiment, the fourth insulating layer 214 is provided on the third insulating layer 213 and covers the fourth semiconductor layer AO4, and includes an inorganic material including an oxide or a nitride. For example, the fourth insulating layer 214 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide.

[0120] According to an embodiment, the first gate electrode G41 and the second gate electrode G42 include a single-layer structure or a multi-layer structure including one or more of molybdenum (Mo), copper (Cu), and titanium (Ti).

[0121] According to an embodiment, a fifth insulating layer 215 is provided on the fourth insulating layer 214 and covers the fourth transistor T4. The power supply voltage line PL, the first connection electrode 267, and the connection line 166 are provided on the fifth insulating layer 215. The fifth insulating layer 215 includes an inorganic material including an oxide or a nitride. For example, the fifth insulating layer 215 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide.

[0122] According to an embodiment, the power supply voltage line PL and the first connection electrode 267 include a relatively highly conductive material. The power supply voltage line PL and the first connection electrode 267 may have a single-layer structure or a multi-layer structure including one or more of aluminum (Al), copper (Cu), and titanium (Ti). In an embodiment, the power supply voltage line PL and the first connection electrode 267 have a three-layer stacked structure of Ti / Al / Ti stacked in sequence. The first connection electrode 267 is connected to the sixth semiconductor layer AS6 through a contact hole. The connection line 166 connects the first gate electrode G1 of the first transistor T1 (or the first electrode CE1 of the first capacitor Cst) to the fourth electrode CE4 of the second capacitor Cbt through a contact hole in the second insulating layer 212, the third insulating layer 213, the fourth insulating layer 214, and the fifth insulating layer 215. The connection line 166 is formed of a conductive material.

[0123] According to an embodiment, a sixth insulating layer 216, which is a planarization layer, is provided on the fifth insulating layer 215 and covers the power supply voltage line PL, the first connection electrode 267, and the connection line 166. The sixth insulating layer 216 includes an organic material, such as benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO). Alternatively, in other embodiments, the sixth insulating layer 216 includes an inorganic material. The sixth insulating layer 216 serves as a protective layer covering the first transistor T1, the sixth transistor T6, and the fourth transistor T4. The top portion of the sixth insulating layer 216 is flat. The sixth insulating layer 216 may have a single-layer structure or a multi-layer structure.

[0124] According to an embodiment, the data line DL and the second connection electrode 277 are arranged on the sixth insulating layer 216. The data line DL partially overlaps with the power supply voltage line PL. The second connection electrode 277 is connected to the first connection electrode 267 through a contact hole formed in the sixth insulating layer 216. The data line DL and the second connection electrode 277 include a conductive material, such as a metal or a conductive oxide. For example, the data line DL and the second connection electrode 277 may have a single-layer structure or a multi-layer structure including one or more of aluminum (Al), copper (Cu) and titanium (Ti). In an embodiment, the data line DL and the second connection electrode 277 have a stacked structure of three layers of Ti / Al / Ti stacked in sequence. The seventh insulating layer 217 is provided on the sixth insulating layer 216 and covers the data line DL and the second connection electrode 277.

[0125] According to an embodiment, the organic light emitting diode OLED is disposed on the seventh insulating layer 217. The organic light emitting diode OLED includes a pixel electrode 310, an opposite electrode 330, and an intermediate layer 320 interposed between the pixel electrode 310 and the opposite electrode 330 including an emission layer.

[0126] According to an embodiment, the pixel electrode 310 is connected to the second connection electrode 277 through a contact hole formed in the seventh insulating layer 217 , and is connected to the sixth transistor T6 through the second connection electrode 277 and the first connection electrode 267 .

[0127] According to an embodiment, an eighth insulating layer 218, which functions as a pixel defining layer, is disposed on the seventh insulating layer 217. The eighth insulating layer 218 defines the emission region of the pixel by including an opening 218OP corresponding to each pixel. Furthermore, the eighth insulating layer 218 can prevent arcing, etc., from occurring at the edge of the pixel electrode 310 by increasing the distance between the edge of the pixel electrode 310 and the opposing electrode 330 above the pixel electrode 310. The eighth insulating layer 218 includes an organic material such as polyimide or HMDSO.

[0128] According to an embodiment, the pixel electrode 310 is disposed on the seventh insulating layer 217 and includes a conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO) and aluminum zinc oxide (AZO) One or more. In another embodiment, the pixel electrode 310 includes a reflective layer, the reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) and one or more of its compounds. In another embodiment, the pixel electrode 310 further includes a layer including ITO, IZO, ZnO or In2O3 on or below the reflective layer.

[0129] According to an embodiment, the intermediate layer 320 of the organic light emitting diode OLED includes an emission layer. The emission layer includes a polymer organic material or a low molecular weight organic material that emits light of a predetermined color. The emission layer is one of a red emission layer, a green emission layer, and a blue emission layer. Alternatively, in another embodiment, the emission layer has a multilayer structure in which a red emission layer, a green emission layer, and a blue emission layer are stacked to emit white light, or has a single-layer structure including a red emission material, a green emission material, and a blue emission material. In an embodiment, the intermediate layer 320 includes one or more of a first functional layer below the emission layer and a second functional layer on the emission layer. The first functional layer and the second functional layer may each be a layer as a whole covering the plurality of pixel electrodes 310 or patterned as a layer corresponding to each of the plurality of pixel electrodes 310.

[0130] Depending on the embodiment, the first functional layer has a single-layer structure or a multi-layer structure. For example, when the first functional layer includes a polymer material, the first functional layer is a hole transport layer (HTL) having a single-layer structure. The first functional layer includes poly-(3,4)-ethylenedihydroxythiophene (PEDOT) or polyaniline (PANI). When the first functional layer includes a low molecular weight material, the first functional layer includes a hole injection layer (HIL) and a hole transport layer (HTL).

[0131] According to an embodiment, when the first functional layer and the emission layer include a polymer material, a second functional layer is formed to improve the characteristics of the organic light emitting diode (OLED). The second functional layer may have a single layer structure or a multilayer structure. The second functional layer includes one or more of an electron transport layer (ETL) and an electron injection layer (EIL). According to another embodiment, the second functional layer is omitted.

[0132] According to an embodiment, the relative electrode 330 faces the pixel electrode 310, and the intermediate layer 320 is between the relative electrode 330 and the pixel electrode 310. The relative electrode 330 includes a conductive material with a low work function. For example, the relative electrode 330 includes a (semi) transparent layer comprising one or more of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca) and alloys thereof. Alternatively, in another embodiment, the relative electrode 330 further includes a layer comprising ITO, IZO, ZnO or In2O3 on the (semi) transparent layer comprising the above-mentioned materials or below the (semi) transparent layer comprising the above-mentioned materials. The relative electrode 330 is arranged on the intermediate layer 320 and the eighth insulating layer 218. The relative electrode 330 may be a single body covering a plurality of organic light emitting diodes OLED in the display area, and may be a common electrode facing the plurality of pixel electrodes 310.

[0133] According to an embodiment, a thin film encapsulation layer or an encapsulation substrate is provided on the organic light emitting diode OLED to cover and protect the organic light emitting diode OLED. The thin film encapsulation layer covers the display area and extends away from the display area. The thin film encapsulation layer includes an inorganic encapsulation layer comprising at least one inorganic material and an organic encapsulation layer comprising at least one organic material. In an embodiment, the thin film encapsulation layer has a structure in which a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer are stacked in sequence. The encapsulation substrate faces the substrate 100 and is bonded to the substrate 100 by using a sealing member such as a sealant or a frit.

[0134] According to the embodiment, Figure 13 The fourth transistor T4 shown in FIG is connected to the Figures 1 to 9 The second gate electrode G42 of the fourth transistor T4 corresponds to Figure 9The metal layer 105, the first gate electrode G41 of the fourth transistor T4 corresponds to Figure 9 The gate electrode 140 of the fourth transistor T4 and the insulating layer between the second gate electrode G42 and the first gate electrode G41 of the fourth transistor T4 correspond to the reference Figure 9 The specific process of forming the fourth transistor T4 is similar to that of the reference Figures 1 to 9 The process described is the same.

[0135] Figure 14 is a graph showing SIMS inspection results of an oxide transistor included in a display device according to an embodiment and analysis results of some materials of the oxide transistor.

[0136] like Figure 9 or Figure 13 , according to an embodiment, insulating layers are formed on and below the oxide semiconductor layer of the oxide transistor. When SIMS is performed on a test piece including insulating layers formed on and below the oxide semiconductor layer, the obtained Figure 14 The curve graph shown in .

[0137] Figure 14 This graph shows the results of SIMS performed on a test piece (in which insulating layers including silicon were formed on and below an oxide semiconductor layer including IGZO), and shows the ionization intensity of secondary ions as a function of sputtering time. Because SIMS was performed in the depth direction of the test piece, the interface of the test piece was determined by the ionization intensity of secondary ions as a function of sputtering time.

[0138] refer to Figure 14 According to an embodiment, the metal oxide of the oxide semiconductor layer, such as gallium oxide (GaO) or indium oxide (InO), exhibits high intensity in a region corresponding to the oxide semiconductor layer. In contrast, because the insulating layers formed on and below the oxide semiconductor layer include silicon, the region where the silicon intensity is high is the region corresponding to the insulating layer.

[0139] According to an embodiment, since SIMS is performed on a test piece including an oxide semiconductor layer and insulating layers formed on and below the oxide semiconductor, a region corresponding to the oxide semiconductor layer corresponds to Figure 14 The half-width values of GaO on the graph shown in the figure and the related area ( Figure 14 Two opposite sides around the IGZO layer correspond to the insulating layer ILU provided above the oxide semiconductor layer and the insulating layer ILO provided below the oxide semiconductor layer, respectively.

[0140] exist Figure 14 In the method, although the region corresponding to the half-value width of GaO corresponds to the oxide semiconductor layer, the region corresponding to the half-value width of InO corresponds to the oxide semiconductor layer in another method.

[0141] Figure 15 is a graph showing the hydrogen concentration in the oxide semiconductor layer of the oxide transistor of the display device according to the embodiment. Figure 15 The “improved H concentration distribution” corresponds to an embodiment of the present inventive concept, and Figure 15 The “H concentration distribution before improvement” corresponds to the comparative example.

[0142] Figure 15 The implementation method is to use the reference Figures 1 to 9 The process described is essentially the same as the process formed, and with Figures 1 to 9 The difference is that a contact hole is formed to expose one of the first conductive region and the second conductive region. The oxide semiconductor layer of the embodiment formed by the above process has been manufactured so as to include IGZO, and the specific shape of the oxide semiconductor layer is the same as that of the reference Figure 13 The shape of the fourth transistor described is the same.

[0143] refer to Figure 15 , according to an embodiment, it is shown that the hydrogen concentration of the oxide semiconductor layer including IGZO manufactured according to an embodiment has a relatively constant value in the channel region. Figure 15 It shows that the hydrogen concentration in the channel region is about 1×10 21 atoms / cm 3 to about 2×10 21 atoms / cm 3 Specifically, Figure 15 The graph shows that about 1.5×10 21 atoms / cm 3 to about 2×10 21 atoms / cm 3 It is known that the HC value according to equation (1) in the channel region is less than 30%. Specifically, Figure 15 The graph shows that (Max-Min) / Avg×100%<15%.

[0144] As a comparative example, refer to Figure 15 When the process is different from the process of the embodiment of the present disclosure, such as when the reference is omitted, Figure 2 The process described in reference Figure 6When the third insulating layer is formed by using a layer-forming gas including ammonia during the described process of forming the top insulating layer 150, the difference in hydrogen concentration in the channel region is (Max-Min) / Avg×100%>30%, and because the effective channel length of the channel region is reduced in the oxide semiconductor layer according to the comparative example, sufficient specifications for driving the display device cannot be ensured.

[0145] According to the embodiment, an effective channel length in a channel region of an oxide semiconductor layer is sufficiently ensured, and thus operation characteristics of a pixel circuit electrically connected to a light emitting diode of a display device are improved, and thus high-quality images can be provided.

[0146] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. The description of features or aspects in each embodiment should generally be considered as other similar features or aspects that can be used in other embodiments. Although one or more embodiments have been described with reference to the drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the appended claims.

Claims

1. A display device, comprising: substrate; a first insulating layer disposed on the substrate and comprising an inorganic insulating material; an oxide semiconductor layer, the oxide semiconductor layer being provided on the first insulating layer; a second insulating layer provided on the oxide semiconductor layer and including an inorganic insulating material; a gate electrode, the gate electrode being disposed on the second insulating layer; as well as a third insulating layer, the third insulating layer being provided on the gate electrode and comprising an inorganic insulating material, wherein the oxide semiconductor layer includes a first conductive region, a second conductive region, and a channel region located between the first conductive region and the second conductive region, and The hydrogen concentration of the oxide semiconductor layer is 5×10 20 atoms / cm 3 to 2×10 21 atoms / cm 3 , and according to equation (1), the value of HC in the channel region of the oxide semiconductor layer is less than 30%: HC=(Max-Min) / Avg×100%------Equation (1), wherein Max represents the maximum hydrogen concentration value detected from a plurality of points within the channel region, Min represents the minimum hydrogen concentration value detected from a plurality of points within the channel region, and Avg represents the average hydrogen concentration value detected from a plurality of points within the channel region, and The hydrogen concentration is measured in an effective region separated from an edge of the channel region by 0.15% of the length of the channel region and 0.15% of the width of the channel region.

2. The display device according to claim 1, wherein the hydrogen concentration in the channel region is 1×10 21 atoms / cm 3 to 2×10 21 atoms / cm 3 within the range. The display device according to claim 1 , wherein the second insulating layer comprises a silicon oxide layer. 4 . The display device according to claim 1 , wherein at least one of the first insulating layer and the third insulating layer comprises a silicon oxide layer or a silicon nitride layer.

5. The display device according to claim 1, further comprising: A metal layer is interposed between the substrate and the first insulating layer.

6. The display device according to claim 1, wherein the oxide semiconductor layer contains fluorine, and The fluorine concentration of the oxide semiconductor layer is 5×10 17 atoms / cm 3 to 5×10 18 atoms / cm 3 within the range. The display device according to claim 5 , wherein the metal layer comprises a bottom gate electrode.

8. A display device, comprising: substrate; a first transistor and a second transistor, wherein the first transistor and the second transistor are each disposed on the substrate; wherein one of the first transistor and the second transistor comprises: an oxide semiconductor layer, the oxide semiconductor layer comprising a channel region, a first conductive region, and a second conductive region, wherein the first conductive region and the second conductive region are respectively located on two opposite sides of the channel region; a first insulating layer, the first insulating layer being interposed between the substrate and the oxide semiconductor layer; a gate electrode, the gate electrode overlapping the channel region of the oxide semiconductor layer; a second insulating layer interposed between the oxide semiconductor layer and the gate electrode; and a third insulating layer provided on the second insulating layer and covering the gate electrode, wherein the hydrogen concentration of the oxide semiconductor layer is within a range of 5×10 20 atoms / cm 3 to 2×10 21 atoms / cm 3 , and according to equation (1), the value of HC in the channel region of the oxide semiconductor layer is less than 30%: HC=(Max-Min) / Avg×100%------Equation (1), wherein Max represents the maximum hydrogen concentration value detected from a plurality of points within the channel region, Min represents the minimum hydrogen concentration value detected from a plurality of points within the channel region, and Avg represents the average hydrogen concentration value detected from a plurality of points within the channel region, and The hydrogen concentration is measured in an effective region separated from an edge of the channel region by 0.15% of the length of the channel region and 0.15% of the width of the channel region.

9. The display device according to claim 8, wherein the hydrogen concentration in the channel region is 1×10 21 atoms / cm 3 to 2×10 21 atoms / cm 3 within the range. 10 . The display device according to claim 8 , wherein the second insulating layer comprises a silicon oxide layer, and at least one of the first insulating layer and the third insulating layer comprises a silicon oxide layer or a silicon nitride layer. 11 . The display device according to claim 8 , further comprising a metal layer interposed between the substrate and the first insulating layer. 12 . The display device according to claim 11 , wherein the metal layer has the same voltage level as that of the gate electrode. 13 . The display device according to claim 8 , wherein the other of the first transistor and the second transistor comprises a silicon transistor.

14. A method for manufacturing a display device, the method comprising: forming a first insulating layer including an inorganic insulating material on a substrate; forming an oxide semiconductor layer on the first insulating layer; forming a second insulating layer including an inorganic insulating material on the oxide semiconductor layer; forming a gate electrode on the second insulating layer; as well as forming a third insulating layer comprising an inorganic insulating material on the gate electrode, wherein forming the third insulating layer is performed by chemical vapor deposition without ammonia, The oxide semiconductor layer includes a first conductive region, a second conductive region, and a channel region between the first conductive region and the second conductive region, and According to equation (1), the value of HC in the channel region of the oxide semiconductor layer is less than 30%: HC=(Max-Min) / Avg×100%------Equation (1), Wherein Max represents the maximum hydrogen concentration value detected from multiple points in the channel region, Min represents the minimum hydrogen concentration value detected from multiple points in the channel region, and Avg represents the average hydrogen concentration value detected from multiple points in the channel region.

15. The method according to claim 14, wherein the hydrogen concentration of the oxide semiconductor layer is 5×10 20 atoms / cm 3 to 2×10 21 atoms / cm 3 within the range.

16. The method according to claim 15, wherein the hydrogen concentration in the channel region is 1×10 21 atoms / cm 3 to 2×10 21 atoms / cm 3 within the range.

17. The method according to claim 14, wherein the second insulating layer comprises a silicon oxide layer, and The silicon oxide layer covers the channel region, at least a portion of the first conductive region, and at least a portion of the second conductive region. 18 . The method according to claim 14 , further comprising applying heat to the first insulating layer before forming the oxide semiconductor layer. 19 . The method of claim 14 , further comprising forming a metal layer on the substrate before forming the first insulating layer.

20. The method of claim 19, wherein forming the metal layer comprises: forming an initial layer comprising a metal; and etching the initial layer so that the metal layer overlaps with the channel region of the oxide semiconductor layer, and Etching the initial layer includes using a gas including fluorine.

21. The method according to claim 14, wherein the oxide semiconductor layer includes fluorine, and the concentration of the fluorine is within 5×10 17 atoms / cm 3 to 5×10 18 atoms / cm 3 within the range.

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