Cache implementation method with prediction mechanism

Abstract

The application provides a cache implementation method with a prediction mechanism. A local server and a remote server perform data transmission through RDMA. A memory of the local server stores at least one queue. Each queue is used for storing an IO command. The IO command indicates that the local server performs data access on the remote server. The method comprises the following steps: a network card predicts high-frequency queue information. The high-frequency queue information has a higher possibility of being accessed than other queue information. The high-frequency queue information is stored in a cache space. The cache space is in the network card. The queue information stored in the cache space corresponds to the queue in the memory in a one-to-one manner. Each queue information is used for processing the IO command in the queue corresponding to the queue information by the network card. The application can improve the hit rate of the cache space.

Description

[0001] The present application claims priority to the Chinese patent application No. 201910843922.1, filed on September 6, 2019, entitled "Cache implementation method with prediction mechanism", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of servers, and more particularly, to a cache implementation method with prediction mechanism. BACKGROUND

[0003] In the network system of a data center, in order to avoid the delay of server-side data processing in network transmission, a remote direct memory access (RDMA) technology can be used. When using the RDMA technology, the local server of the communication can transmit the data to be transmitted to the network card of the remote server through the network card, and the network card of the remote server transmits the data to be transmitted to the memory of the remote server.

[0004] In actual business, after the local server receives the input output (IO) command to be processed, the local server needs to process the IO command to be processed through the network card and send the processed IO command to the network card of the opposite server. The network card can obtain the queue information (for example, the context of the queue pair (QPC)) to process the IO command to be processed. Usually, these queue information are stored in the memory of the server. In order to avoid the network card frequently reading and writing the queue information in the memory through the bus, part of the queue information can be cached in the cache space of the network card. Since the size of the cache space in the network card is small, it is necessary to update the queue information cached in the cache space of the network card. How to improve the hit rate of the cache space of the network card and reduce the delay and waste of bus bandwidth caused by the network card frequently reading and writing the queue information stored in the memory through the bus has become a problem to be solved urgently. SUMMARY

[0005] The present application provides a network card information processing method and chip, which can improve the hit rate of the cache space.

[0006] In a first aspect, a method for processing information of a network card is provided. A local server and a remote server perform data transmission through remote direct memory access (RDMA). A memory of the local server stores at least one queue. Each queue is used to store an input / output (IO) command. The IO command indicates that the local server performs data access to the remote server. The method comprises the following steps: the network card predicts high-frequency queue information. The high-frequency queue information has a higher possibility of being accessed than other queue information. The network card stores the high-frequency queue information in a cache space. The cache space is in the network card. The queue information stored in the cache space corresponds to the queue in the memory of the local server in a one-to-one manner. Each queue information is used for the network card to process the IO command in the queue corresponding to the queue information.

[0007] In the above technical solution, the high-frequency queue information can be predicted and stored in the cache space of the network card. Therefore, the hit rate of the cache space of the network card is improved. Furthermore, the number of bus read / write access generated by the network card can be reduced, the bus bandwidth waste can be reduced, the processing delay of the IO command to be processed by the network card can be reduced, and the transmission performance of the server can be improved.

[0008] In a possible implementation manner of the first aspect, the network card predicting the high-frequency queue information specifically comprises the following steps: the network card searches the queue information cached in the cache space to find currently read queue information. The currently read queue information is determined as the high-frequency queue information.

[0009] In the above technical solution, the read / write access of the queue information in the cache space is in pairs. If a read request is received by a certain queue information, the possibility of the queue information being accessed in a short period of time is relatively high. The currently read queue information can be determined as the high-frequency queue information. Therefore, the hit rate of the cache space can be improved.

[0010] In a possible implementation manner of the first aspect, the network card predicting the high-frequency queue information specifically comprises the following steps: the queue information is a queue pair context (QPC). The network card calculates the difference between a read pointer and a write pointer in the cached QPC in the cache space. The QPC in which the difference between the read pointer and the write pointer is greater than a preset threshold is determined as the high-frequency queue information.

[0011] In the above technical solution, the number of IO commands to be processed in the queue corresponding to the QPC can be determined according to the difference between the read pointer and the write pointer in the QPC. The possibility of the QPC being accessed subsequently can be determined according to the number of IO commands to be processed. Therefore, the hit rate of the cache space can be improved.

[0012] In a possible implementation of the first aspect, the network card predicting the high-frequency queue information comprises: the network card searching for the currently read queue information in the queue information cached in the cache space, and determining the currently read queue information as the high-frequency queue information; and when the queue information is a queue pair context (QPC), the network card calculating a difference between a read pointer and a write pointer in the cached QPC, and determining a QPC with a difference between the read pointer and the write pointer greater than a preset threshold as the high-frequency queue information.

[0013] In the above technical solution, the unprocessed IO command can be read in advance, the queue information required for processing the IO command is determined according to the queue information to which the unprocessed IO command belongs, the queue information is more likely to be accessed subsequently, and the queue information can be determined as the high-frequency queue information, thereby improving the hit rate of the cache space.

[0014] It should be noted that the network card in the present application can also predict the high-frequency queue information according to any two or three of the above prediction methods, and save the predicted high-frequency queue information in the cache space of the network card.

[0015] In a possible implementation of the first aspect, the network card predicting the high-frequency queue information comprises: the network card searching for the currently read queue information in the queue information cached in the cache space, and determining the currently read queue information as the high-frequency queue information; and when the queue information is a queue pair context (QPC), the network card calculating a difference between a read pointer and a write pointer in the cached QPC, and determining a QPC with a difference between the read pointer and the write pointer greater than a preset threshold as the high-frequency queue information.

[0016] In a possible implementation of the first aspect, the network card predicting the high-frequency queue information comprises: the network card searching for the currently read queue information in the queue information cached in the cache space, and determining the currently read queue information as the high-frequency queue information; and the network card obtaining an IO command scheduling order, the IO command scheduling order recording an unprocessed IO command; and the network card determining, according to the IO command scheduling order, queue information corresponding to a queue to which the unprocessed IO command belongs, and determining the queue information corresponding to the queue to which the unprocessed IO command belongs as the high-frequency queue information.

[0017] In a possible implementation of the first aspect, the network card predicting the high-frequency queue information comprises: the queue information being a queue pair context (QPC), the network card calculating a difference between a read pointer and a write pointer in the cached QPC, and determining a QPC with a difference between the read pointer and the write pointer greater than a preset threshold as the high-frequency queue information; and the network card obtaining an IO command scheduling order, the IO command scheduling order recording an unprocessed IO command; and the network card determining, according to the IO command scheduling order, queue information corresponding to a queue to which the unprocessed IO command belongs, and determining the queue information corresponding to the queue to which the unprocessed IO command belongs as the high-frequency queue information.

[0018] In a possible implementation of the first aspect, the high-frequency queue information comprises: the queue information is a queue pair context (QPC), the network card calculates a difference between a read pointer and a write pointer in the QPC cached in the cache space, determines a QPC with a difference between the read pointer and the write pointer greater than a preset threshold as the high-frequency queue information, the network card obtains an IO command scheduling order, the IO command scheduling order records IO commands to be processed, the network card determines, according to the IO command scheduling order, queue information corresponding to a queue to which an IO command to be processed belongs, and determines the queue information corresponding to the queue to which the IO command to be processed belongs as the high-frequency queue information, and the network card searches the queue information cached in the cache space for currently read queue information, and determines the currently read queue information as the high-frequency queue information.

[0019] In a possible implementation of the first aspect, the network card reads the high-frequency queue information from the memory, and saves the high-frequency queue information in the cache space.

[0020] In the above technical solution, the high-frequency queue information determined by the network card can be obtained from the memory and saved in the cache space of the network card, thereby avoiding a large processing delay caused by obtaining required queue information from the memory when processing an IO command.

[0021] In a possible implementation of the first aspect, the network card determines that the high-frequency queue information has been saved in the cache space, and sets state information of the high-frequency queue information in the cache space, the state information being used to indicate that the high-frequency queue information continues to be saved in the cache space.

[0022] In a possible implementation of the first aspect, the state information comprises priority information or lock information, wherein the priority information is used to indicate a priority of updating the high-frequency queue information in the cache space, and the lock information is used to indicate that the high-frequency queue information is in a locked state of not being updated in the cache space.

[0023] In a possible implementation of the first aspect, the priority information or the lock information can be represented by a state flag bit.

[0024] In a possible implementation of the first aspect, when the state flag bit of the queue information is set, it indicates that the queue information is in a locked state of not being updated in the cache space.

[0025] In a possible implementation of the first aspect, the priority information of the queue information is represented by a plurality of state flag bits, each of which is used to represent a result obtained by a method for predicting high-frequency queue information. When a queue information is predicted by a method for predicting high-frequency queue information, if the result obtained is that the queue information is high-frequency queue information, the state flag bit corresponding to the queue information is set. The priority of the queue information to be updated can be determined by combining the plurality of state flag bits of each queue information.

[0026] In a possible implementation of the first aspect, the more the number of state flag bits corresponding to the queue information is set, the lower the priority of the queue information to be updated in the cache space.

[0027] In a possible implementation of the first aspect, the queue information comprises one or more of the following information: a queue pair context (QPC), a completion queue context (CQC), and an event queue context (EQC).

[0028] In a possible implementation of the first aspect, the method further comprises: the network card can also update or replace part or all of the queue information saved in the cache space.

[0029] In a possible implementation of the first aspect, the method further comprises: the network card can also update or replace part or all of the queue information stored in the cache space according to the priority information or the lock information.

[0030] In a possible implementation of the first aspect, the network card divides the queue information in the cache space into different levels according to the state information in the cache space, wherein the higher the level of the queue information, the greater the possibility of being accessed; and the queue information of a lower level in the cache space is preferentially updated.

[0031] In a second aspect, a chip is provided, which is applied to a server system. A local server and a remote server in the server system perform data transmission through remote direct memory access (RDMA). A memory of the local server stores at least one queue. Each queue is used to store an input / output (IO) command. The IO command indicates that the local server performs data access to the remote server. The chip comprises:

[0032] a prediction unit, configured to predict high-frequency queue information, wherein the high-frequency queue information has a greater possibility of being accessed than other queue information.

[0033] a processing unit, configured to save the high-frequency queue information in a cache space, wherein the cache space is in a network card of the local server, and the queue information saved in the cache space corresponds to the queues in the memory one by one, and each queue information is used for the network card to process the IO commands in the queue corresponding to the queue information.

[0034] In a possible implementation of the second aspect, the processing unit is further configured to update or replace part or all of the queue information saved in the cache space.

[0035] In another possible implementation of the second aspect, the prediction unit is specifically configured to: search for currently read queue information in the queue information cached in the cache space, and determine the currently read queue information as the high-frequency queue information.

[0036] In another possible implementation of the second aspect, the queue information is a queue pair context (QPC), and the prediction unit is specifically configured to: calculate the difference between a read pointer and a write pointer in the QPC cached in the cache space, and determine the QPC in which the difference between the read pointer and the write pointer is greater than a preset threshold as the high-frequency queue information.

[0037] In another possible implementation of the second aspect, the prediction unit is specifically configured to: obtain an IO command scheduling sequence, the IO command scheduling sequence recording the IO commands to be processed; and determine the queue information corresponding to the queue to which the IO commands to be processed belong according to the IO command scheduling sequence, and determine the queue information corresponding to the queue to which the IO commands to be processed belong as the high-frequency queue information.

[0038] It should be noted that the network card in the present application can also predict the high-frequency queue information according to any two or three prediction methods described above, and save the predicted high-frequency queue information in the cache space of the network card.

[0039] In another possible implementation of the second aspect, the processing unit is specifically configured to: read the high-frequency queue information from the memory; and save the high-frequency queue information in the cache space.

[0040] In another possible implementation of the second aspect, the processing unit is specifically configured to: determine that the high-frequency queue information has been saved in the cache space; and set state information of the high-frequency queue information in the cache space, the state information being used to indicate that the high-frequency queue information continues to be saved in the cache space.

[0041] In a possible implementation form of the second aspect, the state information comprises priority information or lock information, the priority information being used to indicate a priority of updating the high-frequency queue information in the cache space, and the lock information being used to indicate a lock state of the high-frequency queue information in the cache space.

[0042] In a possible implementation form of the second aspect, the priority information or the lock information can be represented by a state flag bit.

[0043] In a possible implementation form of the second aspect, the queue information comprises one or more of the following information: a queue pair context (QPC), a completion queue context (CQC), and an event queue context (EQC).

[0044] In a possible implementation form of the second aspect, the processing unit is further configured to update or replace part or all of the queue information stored in the cache space according to the priority information or the lock information.

[0045] In a possible implementation form of the second aspect, the processing unit is specifically configured to: store the state information in the cache space of the network card; divide the queue information in the cache space into levels, wherein the higher the level of the queue information, the more likely the queue information is accessed; and preferentially update the queue information of a lower level stored in the cache space.

[0046] The second aspect and the beneficial effects of any one of the possible implementation forms of the second aspect are corresponding to the beneficial effects of the first aspect and the beneficial effects of any one of the possible implementation forms of the first aspect, and thus are not described herein again.

[0047] In a third aspect, a network card is provided, comprising the chip in the second aspect or any one of the possible implementation forms of the second aspect.

[0048] In a fourth aspect, a server is provided, comprising a memory and the network card in the third aspect. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 FIG. 1 is a possible server system schematic diagram provided by an embodiment of the present application.

[0050] Figure 2 FIG. 2 is a schematic flowchart of a method for processing an IO command provided by an embodiment of the present application.

[0051] Figure 3 FIG. 3 is a schematic structural diagram of a possible server 110 provided by an embodiment of the present application.

[0052] Figure 4is a schematic structural diagram of queue information stored in a cache space on a network card provided by an embodiment of the present application.

[0053] Figure 5 is a schematic flow chart of a method for updating queue information in a cache space provided by an embodiment of the present application.

[0054] Figure 6 is a schematic diagram of QPC priority divided in a cache space on a network card provided by an embodiment of the present application.

[0055] Figure 7 is a schematic structural diagram of a chip 700 provided by an embodiment of the present application. DETAILED DESCRIPTION

[0056] The technical solutions in the present application will be described below with reference to the drawings.

[0057] In order to facilitate description, several concepts related to the embodiments of the present application will be described first.

[0058] (1) Input output (IO) command

[0059] The IO command can be divided into a read command and a write command, and refers to a command issued by an application program running on a server to instruct reading data from a remote device or writing data to the remote device. The processor of the server can receive the IO command and store it in the memory, so that the IO command waits to be processed. Specifically, the IO command can be stored in a queue of the memory.

[0060] It should be noted that the IO command mentioned in the embodiments of the present application can be understood as a to-be-processed IO command. The IO command can be processed by a network card.

[0061] (2) Queue

[0062] The queue is a special linear list, and a deletion operation can be performed at the front of the list, while an insertion operation can be performed at the rear of the list. The end at which the insertion operation is performed is called the queue tail, and the end at which the deletion operation is performed is called the queue head. When the queue is empty, it is called an empty queue. The data element in the queue is also called a queue element. Inserting a queue element into the queue is called enqueueing, and deleting a queue element from the queue is called dequeueing. The queue can be inserted at one end and deleted at the other end, and the queue can also be called a first in first out (FIFO) linear list.

[0063] The types of the queues can be various, such as a send queue (SQ), a receive queue (RQ), a complete queue (CQ), and an event queue (EQ).

[0064] The send queue of the local server and the receive queue of the remote server can be referred to as a queue pair (QP).

[0065] The send queue can be used to store the IO commands to be processed, and the receive queue can be used to store the memory information required for processing the IO commands.

[0066] As an example, the send queue in the local server is used to store the IO command issued by the local server to instruct the remote server to read or write data, for example, the IO command is a read command to read the data stored in the remote server, and the network card in the local server can send the processed read command to the remote server, and the read command can include the address and length of the data stored in the remote server to be read, so that the remote server can send the data to be read to the local server according to the processed read command.

[0067] For another example, the IO command is a write command to write data into the remote server, and the network card in the local server can process the write command and send the processed write command to the remote server, so that the remote server can find the memory information in the receive queue according to the processed write command, and store the data in the processed write command into the memory of the remote server according to the found memory information.

[0068] Similarly, the send queue in the remote server can also store the IO command issued by the remote server to instruct the local server to read or write data, and send the IO command to the local server through the network card in the remote server. For details, please refer to the description in the foregoing, which will not be described here.

[0069] The complete queue is used to store the completion command. That is, after the network card in the server processes the IO command, the completion information can be stored in the complete queue, and the completion information can also be referred to as the completion command.

[0070] The event queue is used to store the event command. That is, after the network card in the server stores the completion command in the complete queue, when the number of the completion commands in the complete queue reaches a certain number, the event command can be generated. As an example, the event command can include: event type, and complete queue index. In order to trigger the processor to process one or more completion commands stored in the complete queue.

[0071] It should be understood that storing the event command in the event queue can avoid the network card in the server frequently triggering the processor to process the completion command stored in the completion queue after storing a completion command in the completion queue.

[0072] (3) Queue information

[0073] The context information of the queue can also be referred to as queue information, which corresponds to the queue one-to-one and is used to process the IO command in the queue corresponding to the queue information.

[0074] In the embodiments of the present application, the possibility of accessing at least one queue information stored in the server can be predicted. If the possibility of accessing a certain queue information is greater than the possibility of accessing other queue information, the queue information can be referred to as high-frequency queue information. That is, the possibility of accessing the high-frequency queue information is greater. For specific methods of determining the high-frequency queue information, please refer to the methods described below, which will not be described here.

[0075] In the present application, the queue information can include one or more of the following information: queue pair context (QPC), complete queue context (CQC), and event queue context (EQC).

[0076] Specifically, as an example. The QPC is used for the network card in the server to process the IO command stored in the QP corresponding to the QPC, the CQC is used for the processor to process the completion command stored in the CQ corresponding to the CQC, and the EQC is used for the processor to process the event command stored in the EQ corresponding to the EQC.

[0077] In the embodiments of the present application, the server can also store state information corresponding to each queue information in at least one queue information, and the state information is used to indicate the possibility of accessing the queue information corresponding to the state information.

[0078] (4) Queue pair context (QPC)

[0079] When processing the IO command to be processed stored in the sending queue, it is necessary to perform permission check, virtual address conversion and other processing on the IO command to be processed stored in the QP according to the QPC corresponding to the QP.

[0080] It should be understood that the QPC is the context of a queue pair, which corresponds to a QP storing an IO command to be processed. When the network card processes the IO command to be processed according to the QPC, the network card needs to determine the QPC corresponding to the queue to which the IO command to be processed belongs, and process the IO command to be processed according to the QPC.

[0081] In a network system of a data center, in order to avoid the delay of server-side data processing in network transmission, a remote direct memory access (RDMA) technology can be used. It should be understood that the RDMA is a memory access technology that quickly transmits data stored in the memory of a device to the memory of another device without the intervention of the operating systems of both parties. The RDMA technology can be applied to high-throughput and low-latency network communication, and is particularly suitable for use in large-scale parallel computer clusters.

[0082] As an example, when the RDMA technology is used, the local server of the communication can transmit the data to be transmitted to the network card of the remote server through the network card, and the network card of the remote server transmits the data to be transmitted to the memory of the remote server.

[0083] The following will be described in detail Figure 1 A network system suitable for the embodiments of the present application is described in detail.

[0084] Figure 1 is a possible server system schematic diagram provided by the embodiments of the present application. The server system can include at least two servers, Figure 1 The server 110 and the server 120 are taken as examples for description in the following.

[0085] It should be noted that, in addition to the devices shown in Figure 1 The server 110 and the server 120 can further include a communication interface and other devices such as a disk as an external storage, which are not limited herein.

[0086] Take the server 110 as an example. The server 110 can include a memory 111, a processor 112, and a network card 113. Optionally, the server 110 can further include a bus 114. The memory 111, the processor 112, and the network card 113 can be connected through the bus 114. The bus 114 can be a peripheral component interconnect express (PCIE) bus or an extended industry standard architecture (EISA) bus, etc. The bus 114 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation,Figure 1 In the drawings, only one bus is shown for each system, but it should be understood that a bus could include any number of buses, bus segments and direct connections, and that the use of the term bus in a given context indicates that the components were likely connected using some form of bus; however, other distributions of components could also be used and are within the scope of the application.

[0087] The processor 112 is the operation core and control unit of the server 110. The processor 112 can include multiple processor cores. The processor 112 can be a very large scale integrated circuit. The processor 112 is installed with an operating system and other software programs, so that the processor 112 can realize access to the memory 111, cache, disk and network card 113. It can be understood that in the embodiments of the present application, the core in the processor 112 can be a central processing unit (CPU), and can also be a graphics processing unit (GPU) or other application specific integrated circuit (ASIC).

[0088] It should be understood that the processor 112 in the embodiments of the present application can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor.

[0089] The memory 111 is the main memory of the server 110. The memory 111 is usually used to store various running software programs in the operating system, input / output (IO) commands issued by the upper application and information exchanged with the external storage, etc. In order to improve the access speed of the processor 112, the memory 111 needs to have the advantage of fast access speed. In some computer system architectures, dynamic random access memory (DRAM) is used as the memory 111. The processor 112 can access the memory 111 at high speed through the memory controller (not shown in the figure), and perform read and write operations on any one storage unit in the memory 111. Figure 1

[0090] ​It should also be understood that the memory 111 in the embodiments of the present application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically EPROM (EEPROM) or a flash memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of random access memory (RAM) are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM) and direct rambus RAM (DR RAM).

[0091] The network card 113 is used for the server 110 to communicate with other servers in the communication network. The network card can be built-in in the server 110, or can also be an external device of the server 110, and is connected with the server 110 through an interface. The interface can be a network interface (network interface). For example, a PCIE interface. Figure 1 The network card 113 is built-in in the server 110 as an example.

[0092] For the server 120, the memory 121, the processor 122 and the network card 123 can be included. Optionally, the server 120 can also include a bus 124. The internal structure of the server 120 can be similar to that of the server 110, for example: the memory 121, the processor 122 and the network card 123 are similar to the memory 111, the processor 112 and the network card 113 in the foregoing server 110 respectively, and details are referred to the description of the parts in the server 110, which will not be described here.

[0093] In the scenario of data processing and communication, servers 110 and 120 in a communication network are taken as examples. The servers 110 and 120 respectively run an application (APP), for example, a "weather forecast" APP. In a specific example, in order to realize high-performance computing, the processor 112 in the server 110 undertakes a part of the calculation, stores the calculation result to the memory 111, and the processor 122 in the server 120 undertakes another part of the calculation and stores the calculation result to the memory 121. At this time, the calculation result stored in the memory 111 and the calculation result stored in the memory 121 need to be summarized, for example, the processor 122 in the server 120 summarizes the calculation result stored in the memory 111 and the calculation result stored in the memory 121. The "weather forecast" APP running in the server 110 issues an IO command, which is a write command, for instructing to write the calculation result stored in the memory 111 to the memory 121.

[0094] The processor 112 in the server 110 can send the above-mentioned IO command to the memory 111 through the bus 114. The network card 113 can acquire the above-mentioned IO command from the memory 111 through the bus 114 and process the IO command, which is a write command. The network card 113 acquires the data indicated by the write command to be written to the memory 121 from the memory 111. The network card 113 sends the data to the network card 123 of the server 120 through the network. The network card 123 can receive the data sent by the network card 113 and write the data to the memory 121 through the bus 124. The network card 123 can also send the processing result of writing the data to the memory 121 to the network card 113 through the network, and the network card 113 stores the result to the memory 111 through the bus 114. The result is used to indicate that the network card 123 has successfully stored the data required to be written to the memory 121 by the processor 112 to the memory 121.

[0095] The implementation process of the server 110 processing the IO command to be processed will be described below. Figure 2 The implementation process of the server 110 processing the IO command to be processed will be described below.

[0096] Figure 2 is a schematic flowchart of a method for processing an IO command by a server provided by an embodiment of the present application. As shown in Figure 2 the method can include steps 210-240, which will be described in detail below.

[0097] Step 210: The processor 112 in the server 110 sends an IO command to be processed to the memory 111.

[0098] Specifically, in the embodiments of the present application, the to-be-processed IO command can be stored into a sending queue of the memory 111, and the sending queue can store one or more to-be-processed IO commands.

[0099] The information in the IO command can include but is not limited to: a queue index of a queue to which the IO command belongs, a producer index (PI), and IO command related information.

[0100] The PI indicates the position of the to-be-processed IO command in the queue. The PI can also be understood as the number of to-be-processed IO commands in the queue. The ordering of the to-be-processed IO command in the queue can be counted from 1 from the head to the tail of the queue, and the PI count is increased by 1 when a to-be-processed IO command is added in the QP.

[0101] The PI can also be referred to as a write pointer (WT-POINTER) and is maintained by an upper layer application that issues the IO command in the server 110.

[0102] The IO command related information can include but is not limited to: a key (key) for permission verification, and a type of the IO command. The type of the IO command can be, for example, a read command or a write command. The to-be-processed IO command can also include: a length of data, a virtual address of data, and the like.

[0103] Step 220: The processor 112 sends a prompt message to the network card 113.

[0104] After the processor 112 sends the to-be-processed IO command to the memory 111, the processor 112 can send a prompt message to the network card 113, and the prompt message is used to indicate that there is a to-be-processed IO command in the memory 111. As an example, the prompt message can be a doorbell (DB).

[0105] In some embodiments, the DB sent by the processor 112 to the network card 113 can include: a queue index of a queue to which the to-be-processed IO command belongs, and a position (for example, a PI) of the to-be-processed IO command in the queue. Optionally, the DB can also include the IO command related information included in the above to-be-processed IO command.

[0106] Step 230: The network card 113 processes the to-be-processed IO command.

[0107] The network card 113 can process the IO command to be processed according to the queue information. The queue information used when the IO command to be processed is processed in the embodiment of the application can be one or any combination of the following: a queue pair context (QPC), a complete queue context (CQC), and an event queue context (EQC).

[0108] Taking the QPC as an example of the queue information, the QPC corresponds to the QP one by one, and the QP stores the IO command to be processed issued by the processor. The network card 113 determines that the IO command to be processed is stored in the sending queue according to the prompt message issued by the processor 112, determines the corresponding QPC according to the sending queue storing the IO command to be processed, and processes the IO command to be processed according to the QPC. For example, the network card 113 performs permission verification on the read command or the write command in the IO command to be processed, or performs virtual address conversion on the read command or the write command.

[0109] Taking the CQC as an example of the queue information, the CQC corresponds to the CQ one by one, and the CQ stores the completion command issued by the network card 113. For example, after the network card 113 processes the IO command in the sending queue, the network card 113 can store the completion command in the CQ. Specifically, the network card 113 can determine the corresponding CQC according to the CQ storing the completion command, and determine the address of the CQ according to the address information in the CQC, so that the network card 113 stores the completion command in the CQ according to the address of the CQ.

[0110] Taking the EQC as an example of the queue information, the EQC corresponds to the EQ one by one, and the EQ stores the event command issued by the network card 113. For example, after the network card 113 processes the IO command in the QP, the network card 113 can store the completion command in the CQ. After the number of completion commands in the CQ reaches a certain number, the network card 113 generates an event command and stores the event command in the EQ. Specifically, the network card 113 can determine the corresponding EQC according to the EQ storing the event command, and determine the address of the EQ according to the address information in the EQC, so that the network card 113 stores the event command in the EQ according to the address of the EQ.

[0111] The data structure of the QPC is described below.

[0112] The QPC can include, but is not limited to, a PI and a consumer index (CI). The CI represents the number of IO commands that have been processed by the network card 113 in the sending queue corresponding to the QPC, and can also be referred to as a read pointer (RD-POINTER) and is maintained by the network card 113. For example, after the network card 113 processes an IO command, the CI in the QP corresponding to the QPC in which the IO command is stored is modified, and the CI count is incremented by 1. The PI is the number of IO commands to be processed in the QP. For details of the PI, refer to the description in the foregoing, which will not be described here.

[0113] The QPC can also include a queue state, a key, and a physical base address of the queue. When processing the IO command to be processed, the network card 113 can determine whether the queue to which the IO command to be processed belongs is available or normal according to the queue state. The network card 113 can also verify the authority of the IO command to be processed according to the key. The network card 113 can also convert the virtual address of the read command or the write command in the IO command to be processed stored in the queue to the physical address of the read command or the write command in the IO command to be processed according to the physical base address of the queue to which the IO command to be processed belongs.

[0114] Optionally, the QPC can also include other related data, such as one or a combination of the following: a data length of the queue in the memory 111, a credit, a working mode, and the like.

[0115] The network card 113 can process the IO command to be processed according to the QPC. For ease of description, it is assumed that the IO command to be processed is stored in the queue A, and the queue A corresponds to the QPC A. For example, the network card 113 can determine whether the queue A is available or normal according to the queue state included in the QPC A. For another example, the network card 113 can verify the authority of the IO command to be processed stored in the queue A according to the key included in the QPC A. For another example, the network card 113 can also convert the virtual address of the read command or the write command in the IO command to be processed stored in the queue A to the physical address of the read command or the write command in the IO command to be processed according to the physical base address of the queue included in the QPC A.

[0116] The data structure of the CQC is described below.

[0117] The CQC can include: a physical base address of the queue, a PI, and a CI. The physical base address of the queue represents a physical base address of the CQ in the memory, so that the network card 113 stores a completion command in the CQ according to the physical base address. The PI represents a number of completion commands stored by the network card 113 in the CQ corresponding to the CQC. For example, the network card 113 stores a completion command, and the PI in the CQC corresponding to the CQ storing the completion command is modified, and the PI count is incremented by 1. The CI represents a number of completion commands processed by the processor in the CQ corresponding to the CQC. For example, the processor processes a completion command, and the CI in the CQC corresponding to the CQ storing the completion command is modified, and the CI count is incremented by 1.

[0118] The data structure of the EQC is described below.

[0119] The CQC can include: a physical base address of the queue, a PI, and a CI. The physical base address of the queue represents a physical base address of the CQ in the memory, so that the network card 113 stores a completion command in the CQ according to the physical base address. The PI represents a number of completion commands stored by the network card 113 in the CQ corresponding to the CQC. For example, the network card 113 stores a completion command, and the PI in the CQC corresponding to the CQ storing the completion command is modified, and the PI count is incremented by 1. The CI represents a number of completion commands processed by the processor in the CQ corresponding to the CQC. For example, the processor processes a completion command, and the CI in the CQC corresponding to the CQ storing the completion command is modified, and the CI count is incremented by 1.

[0120] Step 240: The network card 113 sends the processed IO command to the network card 123 of the server 120 through the network.

[0121] The above steps 210-240 describe a process of processing the IO command by the server after the upper-layer application running on the server sends the IO command to be processed. As known from the above process, the network card needs to process the IO command according to the queue information. Therefore, how to quickly obtain the corresponding queue information greatly affects the processing speed of the IO command.

[0122] The network card of the server can further include a cache space, for example, a high-speed buffer memory (cache space). The cache space can be used to store part of the queue information. When processing the IO command to be processed, the network card can directly obtain the stored queue information from the cache space of the network card, and process the IO command to be processed according to the queue information, thereby avoiding the network card frequently reading and writing the queue information in the memory through the bus.

[0123] Since the size of the cache space in the network card is small, only part of the queue information can be cached, thus, the queue information cached in the cache space needs to be updated. However, since the queue storing the IO commands to be processed has a certain randomness, it is difficult to replace the queue information not frequently used in the cache space, which leads to a decrease in the hit rate of the cache space, and further leads to unnecessary read and write access of the bus initiated by the network card, and increases the processing delay of the network card for the IO commands to be processed.

[0124] It should be understood that the ratio of the accessed queue information cached in the cache space to all the cached queue information in the cache space in a period of time is referred to as the hit rate of the cache space. The larger the ratio, the higher the hit rate of the cache space can be understood. The smaller the ratio, the lower the hit rate of the cache space.

[0125] The technical scheme provided by the embodiment of the present application can improve the hit rate of the cache space in the network card, and further reduce the delay and waste of the bus bandwidth caused by the network card frequently reading and writing the queue information stored in the memory through the bus, reduce the processing delay of the network card for the IO commands to be processed, and improve the transmission performance.

[0126] Figure 3 is a schematic structural diagram of a possible server 110 provided by the embodiment of the present application. As shown in Figure 3 The server 110 can include a memory 111, a processor 112, and a network card 113. Optionally, the server 110 can also include a bus 114. The memory 111, the processor 112, and the network card 113 can be connected through the bus 114.

[0127] It should be understood that the network card 113 can be in the server 110, or can also be an external device of the server 110 and connected with the server 110 through an interface. Figure 3 The network card 113 in the server 110 is taken as an example for description.

[0128] The memory 111 can include a plurality of queues, for example, a queue A, a queue B,..., and a queue N. One or more commands can be stored in each queue. Taking the queue as a sending queue in a QP for example, one or more IO commands to be processed can be stored in the QP. Taking the queue as a CQ for example, one or more completion commands can be stored in the CQ. Taking the queue as an EQ for example, one or more event commands can be stored in the EQ.

[0129] The network card 113 can include an input processing unit 310, a cache space 320, a prediction unit 330, and a processing unit 340. The above units will be described in detail as follows.

[0130] Input processing unit 310: mainly used for receiving prompt message (for example, DB) sent by processor 112, which is used to indicate that there is IO command to be processed in the queue of memory 111. Input processing unit 310 can process the IO command to be processed. Specifically, in one possible implementation, input processing unit 310 can obtain the IO command to be processed and the QPC corresponding to the queue from the queue of memory 111, and process the IO command to be processed according to the QPC. In another possible implementation, input processing unit 310 can also generate a completion command after processing the IO command, and process the completion command according to the CQC corresponding to the CQ in which the completion command is stored. In another possible implementation, input processing unit 310 can also generate an event command after processing the IO command, and process the event command according to the EQC corresponding to the EQ in which the event command is stored. For specific processing process, please refer to the description in the above, which will not be repeated here.

[0131] Cache space 320: used for storing queue information, for example, queue information A, queue information B,..., queue information M are stored in cache space 320. Wherein, M is less than N. Queue information A corresponds to queue A, which is used to process the command stored in queue A, queue information B corresponds to queue B, which is used to process the command stored in queue B, and so on.

[0132] One queue information can include queue information entry and corresponding state information. Referring to Figure 4 , DATA in cache space 320 is the space for storing queue information entry of queue information, and CTRL_DATA is used to store the corresponding state information of queue information in DATA in cache space 320. For example, as Figure 4 shown, queue information A can include queue information entry A and corresponding state information A.

[0133] The state information stores the related state information of queue information in cache space 320. The state information can be represented by flag bit, or can be represented by field, which is not limited in the present application.

[0134] The queue information in the embodiment of the present application can include one or more of the following: QPC, CQC, EQC.

[0135] Prediction unit 330: mainly responsible for predicting the possibility of subsequent access of queue information stored in cache space 320. If the possibility of access of a certain queue information is greater than that of other queue information, the queue information can be called high-frequency queue information.

[0136] The processing unit 340 is mainly responsible for saving the high-frequency queue information determined by the prediction unit 330 in the cache space, and can also update and replace the queue information stored in the cache space 320 according to the prediction result obtained by the prediction unit 330. The storage space occupied by the replaced queue information can be used to store other new queue information.

[0137] It should be understood that the term "unit" herein can be implemented by software and / or hardware, and is not specifically limited. For example, the "unit" can be a software program, a hardware circuit, or a combination of both, which implements the above functions. When any of the above units is implemented by software, the software exists in the form of computer program instructions, and is stored in the memory of the network card. The processor of the network card can be used to execute the program instructions to implement the above method flow. The processor can include but is not limited to at least one of the following: central processing unit (CPU), microprocessor, digital signal processor (DSP), microcontroller unit (MCU), or artificial intelligence processor, and various computing devices running software, each of which can include one or more cores for executing software instructions to perform operations or processing. The processor can be a separate semiconductor chip, or can be integrated with other circuits to form a semiconductor chip, for example, it can form a system on chip (SoC) with other circuits such as coding and decoding circuits, hardware acceleration circuits, or various bus and interface circuits, or it can be integrated as a built-in processor in an application-specific integrated circuit (ASIC). The ASIC that integrates the processor can be packaged separately or packaged together with other circuits. In addition to including cores for executing software instructions to perform operations or processing, the processor can further include necessary hardware accelerators, such as field programmable gate arrays (FPGA), programmable logic devices (PLD), or logic circuits that implement special logic operations.

[0138] When the above units are implemented in hardware circuit, the hardware circuit can be implemented in a general central processing unit (CPU), a micro controller unit (MCU), a micro processing unit (MPU), a digital signal processing (DSP), a system on chip (SoC), of course, can also be implemented by an application-specific integrated circuit (ASIC), or a programmable logic device (PLD), the above-mentioned PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof, which can run necessary software or be independent of software to execute the above method flow.

[0139] The following takes the server shown in Figure 3 as an example, in combination with Figure 5 , a method for processing information of a network card provided by the embodiments of the present application is described in detail.

[0140] Figure 5 is a schematic flow chart of a method for processing information of a network card provided by the embodiments of the present application. As Figure 5 shown, the method can include steps 510-530, which are described in detail below.

[0141] Step 510: The prediction unit 330 predicts high-frequency queue information, which has a greater possibility of being accessed than other queue information.

[0142] In the embodiments of the present application, the prediction unit 330 can predict the possibility of at least one queue information stored in the cache space 320 being accessed, and determine the queue information with a greater possibility of being accessed than other queue information as high-frequency queue information.

[0143] In the embodiments of the present application, the at least one queue information stored in the cache space 320 can be one or any combination of the following: QPC, CQC, EQC. For details, please refer to the description in the above, which will not be repeated here.

[0144] Taking the queue information as QPC as an example. In one possible implementation, the prediction unit 330 can predict the possibility of the subsequent access of at least one QPC stored in the cache space 320 according to whether the QPC is hit by a read request sent by the input processing unit 310. In another possible implementation, the prediction unit 330 can further pre-read the IO commands to be processed (for example, acquire the IO command scheduling sequence), and acquire the related information of the queue to which the IO commands to be processed belong, so as to predict the possibility of the subsequent access of at least one QPC stored in the cache space 320 according to the related information of the queue. In another possible implementation, the prediction unit 330 can further predict the possibility of the subsequent access of at least one QPC according to the difference between the value of the read pointer (for example, CI) and the value of the write pointer (for example, PI) in the QPC.

[0145] Taking the queue information as CQC as an example. The method by which the prediction unit 330 predicts the possibility of the access of at least one CQC is similar to the method by which the prediction unit 330 predicts the possibility of the access of at least one QPC. For example, the prediction unit 330 can predict the possibility of the subsequent access of at least one CQC stored in the cache space 320 according to whether the CQC is hit by a read request sent by the input processing unit 310. For another example, the prediction unit 330 can further pre-read the multiple completion commands to be processed (for example, acquire the IO command scheduling sequence), and acquire the related information of the CQ to which the multiple completion commands to be processed belong, so as to predict the possibility of the subsequent access of at least one CQC stored in the cache space 320 according to the related information of the CQ.

[0146] Taking the queue information as EQC as an example. The method by which the prediction unit 330 predicts the possibility of the access of at least one EQC is similar to the method by which the prediction unit 330 predicts the possibility of the access of at least one QPC. For example, the prediction unit 330 can predict the possibility of the subsequent access of at least one EQC stored in the cache space 320 according to whether the EQC is hit by a read request sent by the input processing unit 310. For another example, the prediction unit 330 can further pre-read the multiple event commands to be processed, and acquire the related information of the EQ to which the multiple event commands to be processed belong, so as to predict the possibility of the subsequent access of at least one EQC stored in the cache space 320 according to the related information of the EQ.

[0147] The above-mentioned possible implementation manners will be described in detail in combination with specific examples below, which will not be described herein in detail.

[0148] It should be understood that the method by which the prediction unit 330 predicts at least one queue information stored in the cache space 320 as high-frequency queue information can be to predict according to any one of the above-mentioned methods, or to predict according to the superposition of any two of the above-mentioned methods, or to predict according to the superposition of any three of the above-mentioned methods, which is not limited in the present application.

[0149] Step 520: The processing unit 340 saves the high-frequency queue information in the cache space.

[0150] In the embodiments of the present application, the queue information saved in the cache space corresponds to the queues in the memory one by one, and each queue information is used for the network card to process the IO commands in the queue corresponding to the queue information.

[0151] As an example, in one possible implementation, the network card can read the high-frequency queue information from the memory and save it in the cache space. In another possible implementation, the network card determines that the high-frequency queue information has been saved in the cache space and sets the state information of the high-frequency queue information in the cache space, which is used to indicate that the high-frequency queue information continues to be saved in the cache space.

[0152] In the embodiments of the present application, the state information is not limited, which can be priority information or lock information. The priority information is used to indicate the priority of updating the high-frequency queue information in the cache space, and the lock information is used to indicate that the high-frequency queue information is in a locked state of not being updated in the cache space.

[0153] Specifically, the processing unit 340 adjusts the state information corresponding to the high-frequency queue information according to the prediction result. The prediction unit 330 can predict the possibility of subsequent access of at least one queue information stored in the cache space 320, and the processing unit 340 sets the state information corresponding to the high-frequency queue information predicted. The high-frequency queue information is one or more of the queue information stored in the cache space, and the probability of being accessed of the queue information determined as the high-frequency queue information is greater than that of other queue information in the cache space.

[0154] There are many specific implementations, one possible implementation can set the flag bit corresponding to the high-frequency queue information, for example, perform a set operation on the flag bit. In another possible implementation, the field corresponding to one or more of the at least one queue information can also be modified.

[0155] Taking setting the flag bit corresponding to the high-frequency queue information as an example. The flag bit corresponding to the high-frequency queue information can include one or any combination of the following: valid, dirty, lock, etc. Among them, the valid flag bit indicates whether the queue information entry is valid, the dirty flag bit indicates whether the queue information entry is dirty data, and the lock flag bit indicates whether the queue information entry is locked.

[0156] The lock flag bit in the embodiments of the present application can be one or more. The number of lock flag bits is not limited in the present application.

[0157] Step 530: The processing unit 340 updates part or all of the queue information stored in the cache space 320 according to the state information corresponding to the queue information in the cache space.

[0158] Taking the state information corresponding to the queue information as the priority information as an example, the processing unit 340 can divide the queue information in the cache space according to the priority information of the queue information stored in the cache space, wherein the higher the level of the queue information, the greater the possibility of being accessed; and the queue information with a low level is updated preferentially.

[0159] Taking the state information corresponding to the queue information as the priority information as an example, the processing unit 340 can divide the queue information in the cache space according to the priority information, wherein the higher the level of the queue information, the greater the possibility of being accessed; and the queue information with a low level is updated preferentially.

[0160] In the embodiments of the present application, the high-frequency queue information can be determined by predicting the possibility of the queue information stored in the cache space of the network card being accessed, and the strategy of replacing or updating the queue information in the cache space is optimized, so that the high-frequency queue information that will be used later is avoided from being replaced, thereby improving the hit rate of the cache space of the network card, reducing the number of bus read-write accesses generated by the network card, reducing the waste of bus bandwidth, reducing the processing delay of the IO command to be processed by the network card, and improving the transmission performance.

[0161] Taking the queue information stored in the cache space as QPC as an example, different implementation manners of predicting the possibility of at least one QPC stored in the cache space being accessed and setting the state information of the high-frequency queue information in the foregoing steps 510 and 520 are described in detail.

[0162] In a possible implementation manner, since the read-write access of the QPC stored in the cache space 320 by the input processing unit 310 in the network card 113 occurs in pairs, the prediction unit 330 can determine that the QPC is the high-frequency queue information by judging whether the QPC stored in the cache space 320 is read, and determining that the QPC is accessed with a high possibility subsequently. That is, the network card searches for the QPC currently read from the QPC cached in the cache space, and determines the QPC currently read as the high-frequency queue information.

[0163] For example, the input processing unit 310 determines that the to-be-processed IO command needs to be processed according to the QPC A according to the queue A to which the to-be-processed IO command belongs, and the input processing unit 310 needs to read the QPC A. After the to-be-processed IO command is processed, the read pointer (for example, CI) in the QPC A needs to be modified, and therefore, a subsequent write operation on the QPC A is also needed.

[0164] For the QPCs in the cache space that are currently hit by read requests, the processing unit 340 can set the state information corresponding to the QPCs. Specifically, as an example, a flag bit corresponding to the QPC can be set. For example, the lock (lock) 1 can be included in one flag bit in an embodiment of the present application. The processing unit 340 can set the lock 1 flag bit corresponding to the QPC, for example, set the lock 1 flag bit to 1, and the lock 1 flag bit being 1 indicates that the QPC is more likely to be accessed subsequently.

[0165] Optionally, when the read QPC subsequently receives a write access request sent by the input processing unit 310, the processing unit 340 can clear the lock 1 flag bit corresponding to the QPC, for example, set the lock 1 flag bit to 0, and the lock 1 flag bit being 0 indicates that the QPC is less likely to be accessed subsequently.

[0166] II. In another possible implementation, the prediction unit 330 can also obtain a scheduling order of the to-be-processed IO command, and determine the QPC corresponding to the queue to which the to-be-processed IO command belongs according to the IO command scheduling order, and determine the QPC corresponding to the queue to which the to-be-processed IO command belongs as the high-frequency queue information. It should be understood that the scheduling order of the IO command records the to-be-processed IO command. That is, before the to-be-processed IO command is processed, the prediction unit 330 can predict the possibility of the QPC stored in the cache space 320 being read in the short term according to the pre-reading result of the to-be-processed IO command.

[0167] For example, the input processing unit 310 receives a plurality of prompt messages (e.g., DBs) sent by the processor 112, which indicates that there are a plurality of IO commands to be processed in the server 110. The input processing unit 310 can pre-read the plurality of DBs before processing the plurality of IO commands to be processed, and send the pre-reading result to the prediction unit 330. For example, the input processing unit 310 can determine the queue information to which the IO command to be processed belongs according to the queue index of the queue to which the IO command to be processed belongs, the position (e.g., PI) of the IO command to be processed in the queue, and other information included in the DB. The prediction unit 330 can determine a plurality of QPCs corresponding to the plurality of IO commands to be processed according to the queue information to which the plurality of IO commands to be processed belongs, and determine that the plurality of QPCs are high-frequency queue information. The processing unit 340 sets the state information corresponding to the plurality of QPCs. Specifically, as an example, the flag bit corresponding to the QPC can be set. For example, the lock 2 can be included in one flag bit in an embodiment of the present application. The prediction unit 330 can set the lock 2 flag bit corresponding to the QPC A, for example, set the lock 2 flag bit to 1.

[0168] Optionally, in some embodiments, if the plurality of QPCs determined according to the pre-reading result are not stored in the cache space 320, the network card can obtain the plurality of QPCs from the memory 111 in advance and store them in the cache space 320. In this way, the plurality of QPCs can be obtained from the memory 111 in advance, avoiding the large IO processing delay caused by obtaining the plurality of QPCs from the memory 111 when processing the IO command.

[0169] III. In another possible implementation, the prediction unit 330 can also predict the subsequent read-write access to the QPC according to the PI and CI of the QPC stored in the cache space 320, and according to the difference between the PI and the CI. When the difference between the read-write pointers is greater than a preset threshold, it indicates that the QPC is more likely to be accessed subsequently, and the QPC can be determined as high-frequency queue information.

[0170] It should be understood that the PI represents the number of IO commands in the queue corresponding to the QPC stored in the cache space 320, and the ordering of the IO commands in the queue can be counted from 1 from the head to the tail. The CI represents the number of IO commands that have been processed in the queue corresponding to the QPC, and the CI count is incremented by 1 when an IO command is processed. Therefore, if the difference between the PI and the CI is large, the PI is larger and the CI is smaller, the number of IO commands to be processed stored in the queue is larger, and the probability that the QPC corresponding to the queue is subsequently accessed is also larger.

[0171] For example, the prediction unit 330 can compare the difference between the PI and the CI in the QPC in real time, and when the difference exceeds a certain preset threshold, the processing unit 340 can set the state information corresponding to the QPC. Specifically, as an example, a flag bit corresponding to the QPC can be set. For example, a lock (lock) 3 can be included in one flag bit in an embodiment of the present application. The processing unit 340 can set the lock 3 flag bit corresponding to the QPC A to 1, for example, set the lock 3 flag bit to 1.

[0172] Optionally, when the difference between the PI and the CI in the QPC is less than a certain preset threshold, the processing unit 340 can clear the lock 3 flag bit corresponding to the QPC, for example, set the lock 3 flag bit to 0.

[0173] It should be noted that the three prediction methods listed above can be determined by one or any two or three prediction methods to determine the high-frequency queue information in the cache space.

[0174] It should also be noted that the setting of the state information is achieved by setting the flag bit. The flag bit can be set to one or more, and the number of flag bits is related to the selected prediction method, which is not limited in the present application. For example, if the prediction result is obtained by one of the methods, one flag bit can be set, for example, a lock (lock) flag bit. For example, if the prediction result is obtained by the combination of any two of the above methods, two flag bits can be set, for example, a lock (lock) 1 flag bit and a lock (lock) 2 flag bit. For example, if the prediction result is obtained by the combination of the three methods, three flag bits can be set, for example, a lock (lock) 1 flag bit, a lock (lock) 2 flag bit, and a lock (lock) 3 flag bit.

[0175] In the embodiments of the present application, the method for predicting the possibility of accessing at least one CQC or EQC by the prediction unit 330 is similar to the method for predicting the possibility of accessing at least one QPC. For example, because the read and write accesses to the CQC or EQC stored in the cache space 320 by the input processing unit 310 in the network card 113 are in pairs, after the network card 113 reads the CQC or EQC in the cache space 320, the PI pointer in the CQC or EQC is modified. Therefore, the prediction unit 330 can determine whether a certain CQC or EQC stored in the cache space 320 is read, and determine that the subsequent access to the CQC or EQC is more likely, and the processing unit 340 can adjust the state information corresponding to the CQC or EQC. For another example, the prediction unit 330 can also predict the possibility of short-term reading of the CQC or EQC stored in the cache space 320 according to the pre-reading result of the to-be-processed completion command or event command before the to-be-processed completion command or event command is processed according to the scheduling order of the to-be-processed completion command or event command. The specific prediction process and the process of setting the state information according to the prediction result are described above for the prediction of the QPC and the setting method of the state information, which will not be described here.

[0176] The following describes the setting of the flag corresponding to at least one queue information according to the prediction result obtained by combining the above three prediction methods as an example. The specific implementation process of replacing the queue information by the processing unit 340 is described in detail.

[0177] For ease of description, the prediction result of the QPC is taken as an example for description.

[0178] The processing unit 340 can divide at least one QPC entry stored in the cache space 320 into several priorities according to the lock flag corresponding to the QPC set by the prediction unit 330. For ease of description, Figure 6 The following describes the case of dividing at least one QPC entry into four levels.

[0179] Level 1: The QPC entry in the cache space 320 that is more likely to be accessed in the short term, the lock1 flag corresponding to the QPC entry is set to 1. The remaining lock flags, for example, the lock2 flag and the lock3 flag, can be 1 or 0, which is not limited in the present application.

[0180] Level 2: QPC entries in the cache space 320 that are more likely to be accessed in the short term, the lock 2 flag corresponding to the QPC entry is set, and the lock 1 flag is not set. That is, the lock 2 flag corresponding to the QPC entry is 1, and the lock 1 flag is 0. The rest of the lock flags, for example, the lock 3 flag can be 1 or 0, which is not limited in the present application.

[0181] Level 3: QPC entries in the cache space 320 that are more likely to be accessed in the long term, the lock 3 flag corresponding to the QPC entry is set, and the lock 1 flag and the lock 2 flag are not set. That is, the lock 3 flag corresponding to the QPC entry is 1, and the lock 1 flag and the lock 2 flag are 0.

[0182] Level 4: QPC entries in the cache space 320 that are less likely to be accessed in the long term, the lock 1 flag, the lock 2 flag, and the lock 3 flag corresponding to the QPC entry are not set. That is, the lock 1 flag, the lock 2 flag, and the lock 3 flag corresponding to the QPC entry are all 0.

[0183] Referring to Figure 6 When a new QPC needs to be cached in the cache space 320, if there is unoccupied space (level 5) in the cache space 320, the processing unit 340 can store the new QPC in the unoccupied space. If there is no unoccupied space in the cache space 320, replacement will occur, and the processing unit 340 needs to delete part of the QPC and store the new QPC in the storage space occupied by the deleted QPC.

[0184] The priority of the processing unit 340 in performing replacement is from high to low: level 4-level 3-level 2-level 1. That is, the processing unit 340 in the embodiment of the present application can perform replacement according to the meaning of the lock flag.

[0185] As an example, the QPCs corresponding to level 4, for example, the QPCs whose three lock flags (lock1 flag, lock2 flag, and lock3 flag) are not set, have a low possibility of being accessed in subsequent access processes, and the processing unit 340 can preferentially consider replacing the QPCs corresponding to level 4. As another example, if there is no QPC corresponding to level 4, the processing unit 340 can consider replacing the QPCs corresponding to level 3, which have a large number of read and write accesses in subsequent processes, but the IO commands are not scheduled in the short term, and thus the QPCs corresponding to level 3 can also be considered for replacement. As another example, if there is no QPC corresponding to level 3, the processing unit 340 can consider replacing the QPCs corresponding to level 2. As another example, if there is no QPC corresponding to level 2, the processing unit 340 can finally consider replacing the QPCs corresponding to level 1.

[0186] In the technical solution described above, the network card can predict the possibility of the QPCs stored in the cache space being accessed in advance, thereby avoiding replacing the QPCs that will be used in subsequent processes when the QPCs in the cache space need to be updated, optimizing the replacement strategy of the cache space, and thereby improving the hit rate of the cache space of the network card.

[0187] In the embodiment of the present application, the specific implementation process of the processing unit 340 replacing the stored CQC or EQC according to the prediction result of the CQC being accessed or the prediction result of the EQC being accessed is similar to the method described above, and for details, please refer to the method of replacing the QPC according to the prediction result of the QPC described above, which will not be described here.

[0188] Figure 7 is a schematic structural diagram of a chip 700 provided by an embodiment of the present application. The chip 700 is applied to a server system. A local server and a remote server in the server system perform data transmission through remote direct memory access (RDMA). A memory of the local server stores at least one queue. Each queue is used to store an input / output (IO) command. The IO command indicates that the local server performs data access to the remote server. The chip 700 comprises:

[0189] A prediction unit 330 is configured to predict high-frequency queue information. The high-frequency queue information has a higher possibility of being accessed than other queue information.

[0190] A processing unit 340 is configured to store the high-frequency queue information in a cache space. The cache space is in a network card of the local server. The queue information stored in the cache space corresponds to the queues in the memory in a one-to-one manner. Each queue information is used for the network card to process the IO command in the queue corresponding to the queue information.

[0191] Optionally, the processing unit 340 is further configured to update or replace part or all of the queue information stored in the cache space.

[0192] Optionally, the prediction unit 330 is specifically configured to search for currently read queue information from the queue information stored in the cache space, and determine the currently read queue information as the high-frequency queue information.

[0193] Optionally, the queue information is a queue pair context (QPC), and the prediction unit 330 is specifically configured to calculate a difference between a read pointer and a write pointer in the QPC stored in the cache space, and determine a QPC with a difference between the read pointer and the write pointer greater than a preset threshold as the high-frequency queue information.

[0194] Optionally, the prediction unit 330 is specifically configured to obtain an IO command scheduling sequence, the IO command scheduling sequence recording an IO command to be processed; and determine, according to the IO command scheduling sequence, queue information corresponding to a queue to which the IO command to be processed belongs, and determine the queue information corresponding to the queue to which the IO command to be processed belongs as the high-frequency queue information.

[0195] It should be noted that the network card in the present application can also predict high-frequency queue information according to any two or three of the above prediction methods, and save the predicted high-frequency queue information in the cache space of the network card.

[0196] Optionally, the processing unit 340 is specifically configured to read the high-frequency queue information from the memory and save the high-frequency queue information in the cache space.

[0197] Optionally, the processing unit 340 is specifically configured to determine that the high-frequency queue information has been saved in the cache space, and set state information of the high-frequency queue information in the cache space, the state information being used to indicate that the high-frequency queue information continues to be saved in the cache space.

[0198] Optionally, the state information includes priority information or lock information, the priority information being used to indicate a priority of updating the high-frequency queue information in the cache space, and the lock information being used to indicate a lock state of not updating the high-frequency queue information in the cache space.

[0199] Optionally, the priority information or the lock information can be represented by a state flag bit.

[0200] Optionally, the queue information includes one or more of the following information: a queue pair context (QPC), a completion queue context (CQC), and an event queue context (EQC).

[0201] Optionally, the processing unit 340 is further configured to update or replace part or all of the queue information stored in the cache space according to the priority information or the lock information.

[0202] Optionally, the processing unit 340 is specifically configured to cache the state information in the cache space of the network card, divide the queue information in the cache space according to levels, wherein the higher the level, the greater the possibility of being accessed; and update the queue information in the cache space with a low level in priority.

[0203] It should be understood that, in various embodiments of the present application, the size of the sequence number of each process described above does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0204] The embodiments of the present application also provide a network card, which comprises the chip 700 according to any one of the above embodiments. For specific description of the network card, please refer to the description of the chip 700. Figure 3 and the network card 113, which will not be repeated here.

[0205] The embodiments of the present application also provide a server, which comprises a memory, a processor, a network card, etc. For specific description of the server, please refer to the description of the chip 700, the network card, etc. Figure 1 and Figure 3 , which will not be repeated here.

[0206] Those skilled in the art can understand that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0207] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0208] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the described device embodiments are merely schematic. For example, the division of the units is only a logical function division. There can be another division manner for the actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrical, mechanical or in other forms.

[0209] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0210] In addition, each functional unit in the various embodiments of the present application can be integrated into a processing unit, or each unit can be a physically separate unit, or two or more units can be integrated into a unit.

[0211] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of a software product, and the computer software product is stored in a storage medium, and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0212] The above is merely specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for processing information using a network interface card (NIC), characterized in that, The local server and the remote server transmit data via Remote Direct Memory Access (RDMA). The local server's memory stores at least one queue, each queue used to store input / output (I / O) commands. These I / O commands instruct the local server to access data from the remote server. The method includes: The network interface card predicts high-frequency queue information, which is more likely to be accessed than other queue information. The network interface card (NIC) stores the high-frequency queue information in a cache space. The cache space is located in the NIC, and the queue information stored in the cache space corresponds one-to-one with the queues in the memory. Each queue information is used by the NIC to process the IO commands in the queue corresponding to the queue information. The network interface card (NIC) prediction high-frequency queue information includes: The network interface card (NIC) obtains the IO command scheduling order, which records the IO commands to be processed. The network interface card (NIC) determines the queue information corresponding to the queue to which the pending IO command belongs based on the IO command scheduling order, and determines the queue information corresponding to the queue to which the pending IO command belongs as the high-frequency queue information, and / or; The network interface card (NIC) prediction high-frequency queue information includes: The network interface card (NIC) calculates the difference between the read pointer and the write pointer in the context QPC of the queue cached in the cache space, and determines the QPC with the difference between the read pointer and the write pointer being greater than a preset threshold as the high-frequency queue information, wherein the queue information is the QPC.

2. The method according to claim 1, characterized in that, The network interface card (NIC) prediction high-frequency queue information also includes: The network card searches for the currently read queue information in the queue information cached in the cache space, and determines the currently read queue information as the high-frequency queue information.

3. The method according to claim 1 or 2, characterized in that, The network interface card (NIC) stores the high-frequency queue information in its cache space, including: The network card reads the high-frequency queue information from the memory; The high-frequency queue information is stored in the cache space.

4. The method according to any one of claims 1 to 3, characterized in that, The network interface card (NIC) stores the high-frequency queue information in its cache space, including: The network interface card (NIC) determines that the high-frequency queue information has been stored in the cache space; The network interface card (NIC) sets the status information of the high-frequency queue information in the cache space, and the status information is used to indicate that the high-frequency queue information continues to be stored in the cache space.

5. The method according to claim 4, characterized in that, The status information includes priority information or locking information. The priority information is used to indicate the priority at which the high-frequency queue information is updated in the cache space, and the locking information is used to indicate that the high-frequency queue information is in a locked state in the cache space and is not being updated.

6. The method according to any one of claims 1 to 5, characterized in that, The queue information includes one or more of the following: queue pair context (QPC), completion queue context (CQC), and event queue context (EQC).

7. A chip, characterized in that, The chip is used in a server system where a local server and a remote server transmit data via Remote Direct Memory Access (RDMA). The local server's memory stores at least one queue, each queue used to store input / output (I / O) commands. These I / O commands instruct the local server to access data from the remote server. The chip includes: A prediction unit is used to predict high-frequency queue information, which is more likely to be accessed than other queue information. The processing unit is used to store the high-frequency queue information in a cache space, wherein the cache space is located in the network card of the local server, and the queue information stored in the cache space corresponds one-to-one with the queues in the memory. Each queue information is used by the network card to process the IO commands in the queue corresponding to that queue information. The prediction unit is specifically used for: Obtain the IO command scheduling order, which records the IO commands to be processed; Based on the IO command scheduling order, determine the queue information corresponding to the queue to which the IO command to be processed belongs, and determine the queue information corresponding to the queue to which the IO command to be processed belongs as the high-frequency queue information, and / or; The prediction unit is specifically used for: Calculate the difference between the read pointer and the write pointer in the context QPC of the queue cached in the cache space, and determine the QPC whose difference between the read pointer and the write pointer is greater than a preset threshold as the high-frequency queue information, wherein the queue information is the QPC.

8. The chip according to claim 7, characterized in that, The prediction unit is further configured to: search for the currently read queue information in the queue information cached in the cache space, and determine the currently read queue information as the high-frequency queue information.

9. The chip according to claim 7 or 8, characterized in that, The processing unit is specifically used for: Read the high-frequency queue information from the memory; The high-frequency queue information is stored in the cache space.

10. The chip according to any one of claims 7 to 9, characterized in that, The processing unit is specifically used for: It is confirmed that the high-frequency queue information has been stored in the cache space; The status information of the high-frequency queue information in the cache space is set, and the status information is used to indicate that the high-frequency queue information continues to be stored in the cache space.

11. The chip according to claim 10, characterized in that, The status information includes priority information or locking information. The priority information is used to indicate the priority at which the high-frequency queue information is updated in the cache space, and the locking information is used to indicate that the high-frequency queue information is in a locked state in the cache space and is not being updated.

12. The chip according to any one of claims 7 to 11, characterized in that, The queue information includes one or more of the following: queue pair context (QPC), completion queue context (CQC), and event queue context (EQC).

13. A network interface card (NIC), characterized in that, include: The chip as described in any one of claims 7 to 12.

14. A server, characterized in that, Includes memory and network interface card as described in claim 13.

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