Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

Abstract

The present application provides a silicon carbide diode as a JBS structure in which a Schottky junction and a pn junction are mixed, a silicon carbide semiconductor device that maintains a low forward voltage of an SBD structure and improves surge current resistance, and a manufacturing method of a silicon carbide semiconductor device. A metal material film (52) made of an aluminum film (53) and a nickel film (54) that are in contact with a p-type region (13) and a connection region (20a) portion of an FLR (21) that are exposed to openings (51a, 51b) of an oxide film (51) in sequence is caused to react with a semiconductor substrate (30) in two heat treatments at low and high temperatures, and a nickel silicide film (33) is formed in self-alignment on the oxide film (51). Next, after the remaining metal is removed, only a field oxide film (15) portion in the oxide film (51) remains, and a titanium film (31) that is in Schottky junction with an n ‑ -type drift region (12) is formed on an active region (10) and the connection region (20a) exposed to a contact hole (15a) of the field oxide film (15).

Description

Technical Field

[0001] This invention relates to a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device. Background Technology

[0002] Silicon carbide (SiC) semiconductors have attracted much attention in recent years as a semiconductor material capable of manufacturing semiconductor devices (hereinafter referred to as silicon carbide semiconductor devices) that exceed the limits of semiconductor devices made using silicon (Si) semiconductors. In particular, compared with silicon semiconductors, silicon carbide semiconductors are expected to take advantage of their characteristics such as high dielectric breakdown electric field strength and high thermal conductivity, and be applied to high-voltage (e.g., above 1700V) semiconductor devices.

[0003] When the silicon carbide semiconductor device is a diode (hereinafter referred to as a silicon carbide diode), since it is possible to construct n - n-type drift region - The design specifications of the epitaxial layer are set to be thin and high impurity concentration. Therefore, silicon carbide diodes with a withstand voltage of about 3300V generally adopt the Schottky Barrier Diode (SBD) structure.

[0004] The structure of the conventional SBD (Silicon Carbide Diode) structure is explained. Figure 32 This is a top view showing the state of a conventional silicon carbide semiconductor device as viewed from the front side of a semiconductor substrate. Figure 32 The conventional silicon carbide semiconductor device 140 shown is a vertically oriented silicon carbide diode with a Schottky junction SBD structure formed on the entire front side of a semiconductor substrate 130 made of silicon carbide in the active region 110.

[0005] The Schottky junction of the conventional silicon carbide semiconductor device 140 is formed by the n-type junction exposed on the front side of the semiconductor substrate 130. - The drift region 112 and the front electrode (not shown) formed by the metal layer disposed on the front side of the semiconductor substrate 130 are formed. Reference numerals 120 and 121 are the edge termination region and the field limiting ring (FLR), respectively.

[0006] Typically, in SBD structures, there are problems such as high electric field strength at the junction surface between the semiconductor substrate 130 and the front electrode, leading to increased reverse leakage current due to electron tunneling through the Schottky barrier when a reverse voltage is applied, or increased reverse leakage current due to surface defects unique to silicon carbide. Therefore, a silicon carbide diode with a Junction Barrier Schottky (JBS) structure, formed by mixing a Schottky junction and a pn junction on the front side of the semiconductor substrate 130, has been proposed.

[0007] The structure of the conventional JBS silicon carbide diode is explained. Figure 33 This is a top view showing another example of a conventional silicon carbide semiconductor device viewed from the front side of a semiconductor substrate. Figure 33 The diagram omits the voltage-resistant structure of the edge terminal region, the front electrode 114 disposed on the front side of the semiconductor substrate 130, and the field oxide film 115. Figure 34 It is shown Figure 33 A cross-sectional view of the cross-sectional structure at the cutting line AA-AA'. Symbol 119 is the back electrode.

[0008] Figure 33 , Figure 34 The conventional silicon carbide semiconductor device 140' shown is... Figure 32 The difference between the conventional silicon carbide semiconductor device 140 shown is that, in the active region 110, an SBD structure and a JBS structure are mixed on the front side of the semiconductor substrate 130, and the SBD structure is composed of n - The p-type drift region 112 forms a Schottky junction with the titanium film 131 constituting the front electrode 114. The JBS structure consists of the p-type region 113 and the n-type region 114. - The pn junction is formed in the drift region 112.

[0009] p-type regions 113 are selectively disposed in the active region 110 on the surface region of the front side of the semiconductor substrate 130. Between adjacent p-type regions 113, n-type regions are exposed on the front side of the semiconductor substrate 130. - Type-across drift region 112. Passing through p-type region 113 and n... - A pn junction is formed on the front side of the semiconductor substrate 130 in the p-type drift region 112. The n-junction between adjacent p-type regions 113... - The drift region 112 forms a Schottky junction with the bottom titanium film 131 of the front electrode 114 disposed on the front side of the semiconductor substrate 130.

[0010] In this way, by adopting a JBS structure in which a Schottky junction and a pn junction are mixed at the junction surface between the semiconductor substrate 130 and the front electrode 114, the electric field strength at the junction surface between the semiconductor substrate 130 and the front electrode 114 can be reduced. Therefore, the reverse leakage current can be suppressed to the same level as that of a freewheeling diode (FWD) using silicon semiconductor. Figure 33 The striped p-type region 113 is represented by a shading line, which extends in a direction parallel to the front side of the semiconductor substrate 130.

[0011] In addition, Figure 32 In the conventional silicon carbide semiconductor device 140 shown, the surge current generated in the semiconductor substrate 130 and flowing in the forward direction when a surge voltage is applied is small compared to the amount of current (hereinafter referred to as the extraction amount) drawn from the semiconductor substrate 130 to the front electrode 114. This is because a diode with an SBD structure is a unipolar device that conducts electricity without using minority carriers. Therefore, in the high-current region where a high forward current flows through the diode, the contact (electrical contact) between the semiconductor substrate 130 and the front electrode 114 becomes highly resistive.

[0012] When the contact between the semiconductor substrate 130 and the front electrode 114 becomes highly resistive, and a high surge current flows in the forward direction within the semiconductor substrate, the surge current becomes locally concentrated due to heat generation at the interface between the semiconductor substrate 130 and the front electrode 114. This surge current concentration leads to an increase in the n-axis at the Schottky junction surface and directly below the Schottky junction surface. - Type epitaxial layer (n) - The drift region 112) breaks down, therefore, the amount of surge current drawn from the semiconductor substrate 130 to the front electrode 114 is reduced.

[0013] It was confirmed that the surge current extraction amount increases in diodes using a JBS structure with silicon semiconductors. Therefore, it was hypothesized that in Figure 33 The conventional silicon carbide semiconductor device 140' shown is similar to a diode with a JBS structure using silicon semiconductors, because it connects the p-type region 113 to the n-type region 140. - The rise in surge current caused by the bipolar action of the pn junction formed on the front side of the semiconductor substrate 130 in the drift region 112 increases the amount of surge current extracted, but the effect is not significant.

[0014] exist Figure 33One of the main reasons for the low surge current extraction in the conventional silicon carbide semiconductor device 140' is the failure to obtain a sufficiently low ohmic contact between the p-type region 113, which constitutes the pn junction of the JBS structure, and the front electrode 114. Therefore, it is conceivable to form a metal electrode (hereinafter referred to as an ohmic electrode) between the p-type region 113 and the front electrode 114, which is ohmically connected to the p-type region 113, and to allow surge current to flow locally in the pn junction of the JBS structure, thereby improving the surge current tolerance.

[0015] Figure 35 This is a cross-sectional view showing another example of a conventional silicon carbide semiconductor device. Figure 35 It is the following patent document 2 Figure 3 . Figure 35 The conventional silicon carbide semiconductor device 150 shown is... Figure 33 , Figure 34 The difference between the conventional silicon carbide semiconductor device 140' shown is that the lowest ohmic electrode 133', which serves as the front electrode 114, is disposed on the p-type region 113, and n-type electrodes are mixed on the front side of the semiconductor substrate 130. - The Schottky junction of the p-type drift region 112 and the Schottky electrode 131' and the ohmic junction of the p-type region 113 and the ohmic electrode 133'.

[0016] As a previous method for manufacturing silicon carbide diodes with JBS structure, a new method was proposed that only n - The type-type drift region is formed on the exposed portion of the front side of the semiconductor substrate, and is related to n. - A method for forming an ohmic electrode on the front side of a semiconductor substrate after a Schottky-bonded metal electrode (hereinafter referred to as a Schottky electrode) is formed on the Schottky electrode in such a way as to cover the Schottky electrode and forming an ohmic electrode with the p-type region constituting the pn junction of the JBS structure (for example, see Patent Document 1 below).

[0017] Patent Document 1 discloses the use of aluminum (Al) or nickel (Ni) as ohmic electrode materials and molybdenum (Mo) as Schottky electrode materials. Furthermore, Patent Document 1 discloses the selective formation of p-type regions with higher impurity concentrations than those in the p-type regions within the p-type region constituting the JBS structure's pn junction. + The silicon carbide diode improves the ohmic performance of the p-type region and the ohmic electrode by using a p-type contact area.

[0018] Another method for manufacturing silicon carbide diodes with a conventional JBS structure proposes forming an ohmic electrode only on the p-type region of the pn junction constituting the JBS structure, and then forming an ohmic electrode on the front side of the semiconductor substrate in a manner that covers the n-type region. -A method for Schottky electrode bonding in a drift region (for example, see Patent Document 2 below). Patent Document 2 below discloses the use of aluminum as the material for the ohmic electrode and molybdenum (Mo) as the material for the Schottky electrode.

[0019] Furthermore, another method for manufacturing silicon carbide diodes with a conventional JBS structure discloses a method that forms a silicon-nickel diode by means of a silicide reaction between silicon and nickel films sequentially stacked on a semiconductor substrate made of silicon carbide in a stoichiometric ratio of 2:1 (=Si:Ni). - A method for a silicide (NiSi2) film of an anode electrode in which a Schottky junction is formed in the p-type drift region and an ohmic junction is formed with the p-type region constituting the JBS structure (for example, see Patent Document 3 below).

[0020] As a method for forming an ohmic electrode on a p-type region, a method has been proposed in which an aluminum film and a nickel film are sequentially stacked on a semiconductor substrate made of silicon carbide in such a way as to cover the p-type region, and then an annealing (heat treatment) at 1000°C is performed to cause the silicon atoms in the semiconductor substrate to undergo a silicide reaction with the nickel atoms in the nickel film, thereby forming a nickel silicide (NiSi) film that forms an ohmic electrode that is ohmically bonded to the p-type region (for example, see Non-Patent Document 1 below).

[0021] As another method for forming an ohmic electrode on a p-type region, a method is proposed in which a nickel film and an aluminum film are sequentially stacked on a semiconductor substrate made of silicon carbide in such a way as to cover the p-type region, and then the metal films are reacted with the semiconductor substrate by heat treatment at a temperature of 850°C or higher and 1050°C or lower to form a p-type ohmic electrode made of an alloy of nickel, aluminum, silicon and carbon (C) (for example, see Patent Document 4 below).

[0022] As another method for forming an ohmic electrode on a p-type region, a method is proposed in which an aluminum film and a silicon film with an elemental composition ratio of 89:11 (=Al:Si) are sequentially stacked on a semiconductor substrate made of silicon carbide in such a way as to cover the p-type region, and then an alloy film of the aluminum film and silicon film is formed by heat treatment at a temperature of 400°C to 500°C, and an ohmic junction of the alloy film and the p-type region is formed (for example, see Patent Document 5 below).

[0023] As another method for forming ohmic electrodes, a method is proposed to form a nickel film on a high-concentration impurity region formed by ion implantation of silicon atoms into a semiconductor substrate made of silicon carbide, and to form a heating reaction layer precursor layer only at the interface between the high-concentration impurity region and the nickel film by heat treatment at a temperature of 400°C to 600°C, and then to transform the heating reaction layer precursor layer into a low-resistance heating reaction layer by heat treatment at 950°C (for example, see Patent Document 6 below).

[0024] As another method for forming ohmic electrodes, a method has been proposed in which a heating reaction layer precursor layer is formed between a semiconductor substrate made of silicon carbide and a metal material film through heat treatment within the contact holes of the interlayer insulating film, and the heating reaction layer precursor layer is transformed into a heating reaction layer through heat treatment at a temperature higher than that of the first stage heat treatment (for example, see Patent Document 7 below). Patent Document 7 discloses that the material of the metal material film is titanium aluminum and / or nickel, and that the first stage heat treatment is set at a low temperature that does not produce a harmful solid-phase reaction between the metal material film and the interlayer insulating film.

[0025] Furthermore, in the following Patent Document 7, a method is disclosed in which a metal material film is formed in such a way that it is in contact with the entire surface of the semiconductor substrate in the contact hole of the interlayer insulating film, and the contact area between the metal material film and the semiconductor substrate is silicided by heat treatment to form a heating reaction layer on the entire surface of the contact area in a self-aligned manner, by using etching to remove the unsilicided portion of the metal material film (the portion other than the heating reaction layer), so that only the portion of the metal material film that becomes the heating reaction layer remains.

[0026] Figure 36 This is a cross-sectional view showing an example of an ohmic electrode formed in self-alignment using a conventional silicon carbide semiconductor device manufacturing method. Figure 36 It is the following patent document 7 Figure 1 . Figure 36 The conventional silicon carbide semiconductor device 160 shown has a heating reaction layer in the contact hole 163a of the interlayer insulating film 163, which is a high-concentration impurity region 162 that is in contact with and electrically connected to the surface region of the semiconductor substrate 161 made of silicon carbide and the wiring layer 165 that is buried in the contact hole 163a of the interlayer insulating film 163.

[0027] The ohmic electrode 164 is formed in a self-aligned manner on the entire surface of the semiconductor substrate 161 within the contact hole 163a of the interlayer insulating film 163 using the self-aligned silicide process described in Patent Document 7, with the interlayer insulating film 163 as a mask. The ohmic electrode 164 is disposed within the contact hole 163a of the interlayer insulating film 163 in the surface region exposed on the surface of the semiconductor substrate 161 in the high-concentration impurity region 162, and protrudes from the front side of the semiconductor substrate 161 in a direction away from the front side of the semiconductor substrate 161.

[0028] Existing technical documents

[0029] Patent documents

[0030] Patent Document 1: Japanese Patent No. 5546759

[0031] Patent Document 2: Japanese Patent Application Publication No. 2008-282972

[0032] Patent Document 3: Japanese Patent Application Publication No. 2003-158259

[0033] Patent Document 4: Japanese Patent No. 4291875

[0034] Patent Document 5: Japanese Patent Application Publication No. Heisei 1-020616

[0035] Patent Document 6: Japanese Patent Application Publication No. 2017-175115

[0036] Patent Document 7: Japanese Patent Application Publication No. 2005-276978

[0037] Non-patent literature

[0038] Non-Patent Literature 1: N. Kiritani et al., Single Material Ohmic Contacts Simultaneously Formed on the Source / P-well / Gate of 4H-SiC VerticalMOSFETs, Materials Science Forum, Switzerland, Trans Tech Publications, 2003, Vol. 433-436, pp. 669-672. Summary of the Invention

[0039] Technical issues

[0040] However, even in order to improve the aforementioned conventional silicon carbide semiconductor device 140' (a silicon carbide diode with a JBS structure: see reference) Figure 33 , Figure 34 The surge current withstand capability is such that an ohmic electrode is provided between the semiconductor substrate 130 and the Schottky electrode (titanium film 131) that only contacts the p-type region 113. However, when the ohmic electrode is a nickel silicide film, the contact resistance between the p-type region 113 and the ohmic electrode cannot be sufficiently reduced, and therefore, the predetermined design value of the surge current withstand capability cannot be obtained.

[0041] In order to reduce the contact resistance between the p-type region 113 and the ohmic electrode, the junction area between the p-type region 113 and the ohmic electrode is increased. If the active region 110 is kept at the same surface area, the more the junction area between the p-type region 113 and the ohmic electrode is increased, the more likely n is to be lost. -The junction area between the type-type drift region 112 and the Schottky electrode becomes smaller. Therefore, under forward bias, from n - The electron current in the drift region 112 toward the Schottky electrode decreases, making it difficult to achieve a low forward voltage (Vf).

[0042] Therefore, in order to set the junction area of ​​the p-type region 113 and the ohmic electrode to the junction area required to achieve the predetermined surge current withstand capability, and to maximize n... - The junction area between the p-type drift region 112 and the Schottky electrode allows an ohmic electrode to be formed only on the p-type region 113, with an n-type electrode between adjacent p-type regions 113. - A Schottky electrode is formed on the entire surface of the p-type drift region 112. Furthermore, by using an aluminum / nickel laminate as the material for the ohmic electrode, the contact resistance between the p-type region 113 and the ohmic electrode can be reduced.

[0043] However, due to the width w101 of the p-type region 113 (refer to...) Figure 33 The width is less than a few μm, making it difficult to control the patterning of stacked films of two metals (aluminum and nickel) with different etching rates. Considering the process margin of mass production, this results in an ohmic electrode being formed with a width narrower than the width w101 of the p-type region 113. Therefore, an ineffective region is created where the p-type region 113 contacts the Schottky electrode without reducing the contact resistance, and sufficient characteristics for increasing the extraction amount of surge current cannot be obtained.

[0044] In the technology described in the aforementioned patent document 2, the metal film is patterned by photolithography and etching to leave an ohmic electrode 133' (see reference). Figure 35 This is part of the process. Therefore, the increased number of steps leads to increased costs. Furthermore, since the metal film can only be patterned with the smallest etching size, it is not suitable for miniaturization. In cases where miniaturization is not possible, the junction area of ​​the Schottky electrode within the surface of the semiconductor substrate 130 decreases, resulting in a lower forward voltage as described above.

[0045] Although the technology described in Patent Document 7 involves forming a finely patterned ohmic electrode 164 within the contact holes 163a of the interlayer insulating film 163 using the interlayer insulating film 163 as a mask, as described above, it has been confirmed that the contact resistance between the high-concentration impurity region 162 and the ohmic electrode 164 is not sufficiently reduced. Furthermore, it has been confirmed that if the conventional self-alignment technology described in Patent Documents 2 and 7 is applied to a laminated film made of aluminum and nickel films, the following problems arise.

[0046] For example, the case in which an ohmic electrode 133' is formed only on the p-type region 113 will be used as an example. Figure 30This is an explanatory diagram showing the state of the formation process of a conventional ohmic electrode. Figure 31 This is an explanatory diagram showing the state of a conventional ohmic electrode magnified. Figure 30 , Figure 31 The upper part schematically shows the state obtained by observing the ohmic electrode 133' using a scanning electron microscope (SEM), and the lower part shows a cross-sectional view near the ohmic electrode 133'.

[0047] like Figure 30 As shown, an n-type region covering the area between adjacent p-type regions 113 is formed on the front side of the semiconductor substrate 130. - The oxide mask 171 of the p-type drift region 112 is then formed. Next, a metal material film 172 is formed on the oxide mask 171 in such a way that it contacts the p-type region 113 within the opening 171a of the oxide mask 171. Then, the metal material film 172 and the semiconductor substrate 130 are reacted by heat treatment to silicideize and form a nickel silicide film that becomes the ohmic electrode 133'.

[0048] When the metal material film 172 is a laminate of aluminum and nickel films, during the heat treatment used to silicide the contact area between the metal material film 172 and the semiconductor substrate 130, aluminum atoms in the metal material film 172 penetrate into the oxide mask 171 and react, generating product 134 within the oxide mask 171. It has been confirmed that this product 134 remains between the semiconductor substrate 130 and the Schottky electrode 131' even after the device is completed (see reference). Figure 31 ), and become a source of leakage current.

[0049] In order to solve the problems of the prior art, the present invention aims to provide a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device, which is a silicon carbide diode with a JBS structure formed by mixing Schottky junction and pn junction, can maintain the low forward voltage of the SBD structure and improve the surge current tolerance.

[0050] Technical solution

[0051] To address the aforementioned issues and achieve the objective of this invention, the method for manufacturing a silicon carbide semiconductor device of this invention provides a method for manufacturing a silicon carbide semiconductor device comprising an active region, a terminal region surrounding the active region, an oxide film disposed on a first main surface of the semiconductor substrate in the terminal region, and a connection region disposed between the active region and the oxide film, characterized by the following steps: A first step is performed to form a first conductivity type region constituting the first main surface of the semiconductor substrate within the semiconductor substrate. A second step is performed to selectively form a first second conductivity type region in the active region on the surface region of the first conductivity type region located on the first main surface side of the semiconductor substrate.

[0052] A third step involves forming a second second conductive region on the surface region of the first conductive region located on the first main surface side of the semiconductor substrate, throughout the entire connection region. A fourth step involves forming an oxide film covering the first conductive region, the first second conductive region, and the second second conductive region on the first main surface of the semiconductor substrate. A fifth step involves selectively removing the oxide film to form a first opening exposing the first second conductive region and a second opening exposing the second second conductive region in the connection region.

[0053] A sixth step involves sequentially stacking an aluminum-containing metal film and a nickel film to form a metal material film, wherein the metal material film contacts a first main surface of the semiconductor substrate in the first and second openings of the oxide film. A seventh step involves reacting the metal material film with the semiconductor substrate through a first heat treatment, thereby self-aligning a compound layer to be formed on the first main surface of the semiconductor substrate located in the first and second openings of the oxide film, using the oxide film as a mask. An eighth step, following the seventh step, involves removing the remaining portion of the metal material film, excluding the compound layer.

[0054] Following the eighth step, a ninth step involves a second heat treatment at a higher temperature than the first heat treatment to generate nickel silicide within the compound layer, thereby forming a nickel silicide film that ohmically bonds to the semiconductor substrate. Following the ninth step, a tenth step involves removing the portion of the oxide film in the active region to form a contact hole connecting the first opening and the second opening. Inside the contact hole, an eleventh step involves sequentially stacking a titanium film that contacts the first conductivity region and forms a Schottky bond with it on the first main surface of the semiconductor substrate, thereby forming a first electrode. A twelfth step involves forming a second electrode on the second main surface of the semiconductor substrate.

[0055] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the fifth step, the oxide film is selectively removed by dry etching to form the first opening and the second opening in the oxide film.

[0056] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above invention, the metal film is an aluminum film.

[0057] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the seventh step of the invention, the temperature of the first heat treatment is set to 400°C or higher and 550°C or lower.

[0058] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above invention, the metal film is an aluminum-silicon film.

[0059] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the seventh step of the invention, the temperature of the first heat treatment is set to 400°C or higher and 800°C or lower.

[0060] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above invention, the thickness of the aluminum-silicon film is 5 nm or more and 300 nm or less.

[0061] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above invention, the silicon concentration of the aluminum silicon film is 0.1 wt% or more and 3 wt% or less.

[0062] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above invention, in the ninth step, the temperature of the second heat treatment is set to 900°C or higher and 1050°C or lower.

[0063] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above invention, the tenth step includes: a step of forming a photoresist mask covering the outer portion from the sidewall outside the second opening of the oxide film; and a step of removing the portion of the oxide film in the active region by wet etching using the photoresist mask as a mask.

[0064] Furthermore, in order to solve the above-mentioned problems and achieve the objectives of the present invention, the silicon carbide semiconductor device of the present invention has the following features: An active region and a terminal region surrounding the active region are provided on a semiconductor substrate made of silicon carbide. An oxide film is provided on a first main surface of the semiconductor substrate in the terminal region. A connection region is provided between the active region and the oxide film. A first conductivity type region exposed on the first main surface of the semiconductor substrate is provided inside the semiconductor substrate. In the active region, a first second conductivity type region is selectively provided between the first main surface of the semiconductor substrate and the first conductivity type region, in contact with the first conductivity type region. A second second conductivity type region in contact with the first conductivity type region is provided throughout the entire region of the connection region between the first main surface of the semiconductor substrate and the first conductivity type region.

[0065] The first silicide film is ohmically bonded to the first second conductivity type region. The second silicide film contacts the inner end of the oxide film and is ohmically bonded to the second second conductivity type region. The first electrode is formed by sequentially stacking a titanium film and an aluminum-containing metal electrode film on the first main surface of the semiconductor substrate. The titanium film contacts the first silicide film, the second silicide film, and the first conductivity type region, and is connected to the first silicide film and the second silicide film, and is Schottky bonded to the first conductivity type region. The second electrode is disposed on the second main surface of the semiconductor substrate.

[0066] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that the first silicide film contains nickel, silicon and aluminum.

[0067] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that the first silicide film contains carbon.

[0068] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that the second silicide film contains nickel, silicon and aluminum.

[0069] Furthermore, the silicon carbide semiconductor device of the present invention is characterized in that the second silicide film contains carbon.

[0070] Technical effect

[0071] According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device of the present invention, as a silicon carbide diode with a JBS structure formed by mixing a Schottky junction and a pn junction, a low-resistance ohmic electrode can be formed not only in the active region but also in the entire region of the connection region of the edge terminal region. Therefore, it has the effect of improving surge current tolerance while maintaining the low forward voltage of the SBD structure. Attached Figure Description

[0072] Figure 1 This is a top view showing the layout of the silicon carbide semiconductor device of Embodiment 1 as viewed from the front side of the semiconductor substrate.

[0073] Figure 2 This is a top view showing the layout of the silicon carbide semiconductor device of Embodiment 1 as viewed from the front side of the semiconductor substrate.

[0074] Figure 3 It is shown Figure 2 A cross-sectional view of the structure at the cutting line A-A'.

[0075] Figure 4 This is a flowchart illustrating an outline of the manufacturing method of the silicon carbide semiconductor device according to Embodiment 1.

[0076] Figure 5 This is a cross-sectional view showing the state during the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1.

[0077] Figure 6 This is a cross-sectional view showing the state during the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1.

[0078] Figure 7 This is a cross-sectional view showing the state during the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1.

[0079] Figure 8 This is a cross-sectional view showing the state during the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1.

[0080] Figure 9 This is a cross-sectional view showing the state during the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1.

[0081] Figure 10 This is a cross-sectional view showing the state during the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1.

[0082] Figure 11 This is a cross-sectional view showing the state during the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1.

[0083] Figure 12 This is a cross-sectional view showing the state during the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1.

[0084] Figure 13 This is a cross-sectional view showing the state during the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1.

[0085] Figure 14 This is a cross-sectional view showing the state during the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1.

[0086] Figure 15 This is a cross-sectional view showing the state during the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1.

[0087] Figure 16 This is a cross-sectional view schematically showing the state of the front electrode of the silicon carbide semiconductor device in Embodiment 1 during the manufacturing process.

[0088] Figure 17 This is a cross-sectional view schematically showing the state of the front electrode of the silicon carbide semiconductor device in Embodiment 1 during the manufacturing process.

[0089] Figure 18 This is a cross-sectional view schematically showing the state of the front electrode of the silicon carbide semiconductor device in Embodiment 1 during the manufacturing process.

[0090] Figure 19 This is a cross-sectional view schematically showing the state of the front electrode during the manufacturing process of Reference Example 1.

[0091] Figure 20 This is a top view showing an example of the layout of the silicon carbide semiconductor device of Embodiment 3 as viewed from the front side of the semiconductor substrate.

[0092] Figure 21 This is a top view showing an example of the layout of the silicon carbide semiconductor device of Embodiment 3 as viewed from the front side of the semiconductor substrate.

[0093] Figure 22 This is a schematic cross-sectional view showing the state obtained by observing the vicinity of the ohmic junction in Example 1.

[0094] Figure 23 This is a schematic cross-sectional view showing the state obtained by observing the ohmic junction near Reference Example 1.

[0095] Figure 24 It is Figure 22 A cross-sectional view shown as an enlarged portion.

[0096] Figure 25 This is a cross-sectional view schematically showing the state of the front electrode during the formation process of Reference Example 2.

[0097] Figure 26 This is a cross-sectional view schematically showing the state of the front electrode during the formation process of Reference Example 2.

[0098] Figure 27 This is a cross-sectional view schematically showing the state obtained by observing the structure of the front electrode of Reference Example 2.

[0099] Figure 28 This is a cross-sectional view schematically showing the state obtained by observing the structure of the front electrode of Reference Example 2.

[0100] Figure 29 This is a characteristic graph showing the relationship between the ohmic junction area and surge current withstand capability in Example 2.

[0101] Figure 30 This is an explanatory diagram showing the state of the formation process of a conventional ohmic electrode.

[0102] Figure 31 This is an explanatory diagram showing the state of a conventional ohmic electrode magnified.

[0103] Figure 32 This is a top view showing the state of a conventional silicon carbide semiconductor device as viewed from the front side of a semiconductor substrate.

[0104] Figure 33 This is a top view showing another example of a conventional silicon carbide semiconductor device viewed from the front side of a semiconductor substrate.

[0105] Figure 34 It is shown Figure 33 A cross-sectional view of the structure at the cutting line AA-AA'.

[0106] Figure 35 This is a cross-sectional view showing another example of a conventional silicon carbide semiconductor device.

[0107] Figure 36 This is a cross-sectional view showing an example of an ohmic electrode formed in self-alignment using a conventional silicon carbide semiconductor device manufacturing method.

[0108] Symbol Explanation

[0109] 10: Active region

[0110] 11:n + Type of starting substrate

[0111] 12:n - Type Drift Zone

[0112] 13, 72, 74: p-type regions constituting the JBS structure

[0113] 14: Front electrode

[0114] 15: Field Oxidation Film

[0115] 15': Covering the active region with n in the oxide film (oxide film mask) - Part of the drift zone

[0116] 15a: Contact pores of field oxide film

[0117] 16: Thermal Oxidation Film

[0118] 17: Deposited oxide film

[0119] 18: Passivation film

[0120] 18a: Opening of the passivation film

[0121] 19: Back electrode

[0122] 20: Edge Terminal Area

[0123] 20a: Connection area of ​​edge terminal region

[0124] 21: Field Limiting Loop (FLR)

[0125] 22: p that constitutes the JTE structure - Type area

[0126] 23: p that constitutes the JTE structure -- Type area

[0127] 24:n + Type of trench cut-off area

[0128] 30, 30': Semiconductor substrate

[0129] 31: Titanium film

[0130] 32: Aluminum alloy film

[0131] 33 (33a, 33b): Nickel silicide films (first nickel silicide film, second nickel silicide film)

[0132] 34: Remaining carbon

[0133] 40: Silicon carbide semiconductor devices

[0134] 41: Bonding pads

[0135] 42: Joint between bonding pad and lead

[0136] 50: Carbon protective film

[0137] 51: Oxide film (oxide film mask)

[0138] 51a, 51b: Openings of the oxide film (oxide film mask)

[0139] 52, 52': Metallic material film

[0140] 53: Aluminum film

[0141] 53': Silicon film

[0142] 54, 54': Nickel film

[0143] 55: Aluminum-nickel-silicon (Al-Ni-Si) compounds

[0144] 56: Aluminum-nickel compounds

[0145] 57: Resist film

[0146] 61-64: Thermal diffusion

[0147] 70, 70': Silicon carbide semiconductor device

[0148] 71, 73: p-type region

[0149] w1: Width of the p-type region constituting the JBS structure

[0150] w2a: Width of the first nickel silicide film

[0151] w2b: Width of the second nickel silicide film

[0152] w3: Width of the connection area in the edge terminal region Detailed Implementation

[0153] Hereinafter, preferred embodiments of the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device of the present invention will be described in detail with reference to the accompanying drawings. In this specification and the drawings, layers and regions prefixed with n or p respectively indicate that electrons or holes are the majority carriers. Furthermore, the + and - symbols marked with n or p respectively indicate that the impurity concentration is higher and lower than the impurity concentration in layers or regions not marked with + and -. It should be noted that in the following description of the embodiments and the accompanying drawings, the same symbols are used to denote the same structures, and repeated descriptions are omitted. It should be noted that in the notation of Miller indices, "-" indicates a horizontal line immediately following the index, and a negative index is indicated by marking "-" before the index.

[0154] (Implementation Method 1)

[0155] The structure of the silicon carbide semiconductor device of Embodiment 1 will be described. Figure 1 , Figure 2 This is a top view showing the layout of the silicon carbide semiconductor device of Embodiment 1 as viewed from the front side of the semiconductor substrate. Figure 1 The diagram shows an example of the layout of the p-type region (first second conductivity type region) 13 constituting the JBS structure. Figure 2 The middle figure shows an example of the layout of bonding pads 41 in various parts of the front side of a semiconductor substrate (semiconductor chip) 30 made of silicon carbide (SiC).

[0156] Figure 1 , Figure 2 The silicon carbide semiconductor device 40 of Embodiment 1 shown is a silicon carbide diode as follows: In the active region 10, a front electrode (first electrode) 14 (see reference 14) is mixed on the front side of the semiconductor substrate 30. Figure 3) and n - The SBD structure is composed of a Schottky structure in the p-type drift region (first conductivity type region) 12 and a p-type region 13 and n-type drift region 12. - The JBS structure is formed by the pn structure of the drift region 12.

[0157] n - The p-type drift region 12 and the p-type region 13 are arranged in a roughly identical pattern and are approximately equal in size within the surface of the active region 10. - The p-type drift region 12 and the p-type region 13 are, for example, configured as stripes extending in the same direction parallel to the front side of the semiconductor substrate 30, and are alternately and repeatedly configured in contact with each other in the short side direction orthogonal to the long side direction in which the stripes extend. - The p-type drift region 12 is exposed on the front side of the semiconductor substrate 30 between adjacent p-type regions 13.

[0158] The active region 10 is the area where current flows when the silicon carbide diode is in the on state. The active region 10 has, for example, a generally rectangular planar shape and is disposed approximately at the center of the semiconductor substrate 30. The edge termination region 20 is the region between the active region 10 and the end of the semiconductor substrate 30, and surrounds the active region 10. The edge termination region 20 is a buffer zone. - The drift region 12 is a region on the front side of the semiconductor substrate 30 that withstands the electric field and maintains a withstand voltage. Withstand voltage refers to the limit of voltage that will not cause malfunction and / or damage to the component.

[0159] The edge terminal area 20 is equipped with a junction termination extension (JTE) structure and other pressure-resistant structures (see reference). Figure 3 The JTE structure arranges multiple p-type regions with different impurity concentrations in a manner that increases as they move away from the inner side (central side of semiconductor substrate 30) to the outer side (end side of semiconductor substrate 30). Figure 3 The symbols 22 and 23) are configured in a roughly rectangular planar shape surrounding the active region 10 as a concentric circle pressure-resistant structure with the center of the active region 10 as the reference.

[0160] Furthermore, in the connection area 20a of the edge terminal area 20 (refer to...) Figure 3 The active region 10 is equipped with a field-limiting ring (FLR, second conductivity type region) 21. The FLR 21 is a roughly rectangular enclosure surrounding the active region 10. + Type region, and extends outward from the connection region 20a of the edge terminal region 20 and connects with p as described later. - Type 22 (refer to) Figure 3FLR21 can also contact p-type region 13 in the direction of the long side of the p-type region 13 extending in a stripe pattern.

[0161] The connection region 20a of the edge termination region 20 is the region between the active region 10 and the field oxide film 15 (described later), surrounding the active region 10 and connecting the active region 10 to the voltage-resistant structure of the edge termination region 20. The voltage-resistant structure of the edge termination region 20 is the portion of the edge termination region 20 extending from the inner end of the field oxide film 15 (described later) to the end of the semiconductor substrate (chip end), and is configured with a JTE structure and / or n... + Type 24 trench cutoff zone (refer to) Figure 3 (and other predetermined pressure-resistant structures.)

[0162] Front electrode 14 (reference) Figure 3 The active region 10 is disposed on the front side of the semiconductor substrate 30. The front electrode 14 and n - Type 12 drift region and p-type region 13 come into contact with n - The p-type drift region 12 and the p-type region 13 are electrically connected. A passivation film 18 is provided on the front side of the semiconductor substrate 30 (see reference). Figure 3 The passivation film 18 functions as a protective film for the component structure on the front side of the semiconductor substrate 30 and the front electrode 14.

[0163] An opening 18a is provided in the passivation film 18, exposing a portion of the front electrode 14. The portion of the front electrode 14 exposed in the opening 18a of the passivation film 18 functions as a bonding pad 41. The bonding pad 41 is, for example, disposed in the center of the semiconductor substrate 30. When current is supplied to the bonding pad 41, aluminum (Al) wires, which are the most common wiring connections, are bonded (joined) to the bonding pad 41.

[0164] Figure 2 The junction 42 between the bonding pad 41 and the aluminum wire (not shown) is shown in a circular planar shape. For example, when bonding an aluminum wire with a diameter of 500 μm to the bonding pad 41, the junction 42 between the bonding pad 41 and the aluminum wire needs to have a surface area of ​​approximately 1 mm square. The reason for this is that, depending on the voltage rating of the silicon carbide diode, the flow pattern of the surge current flowing in the forward direction when a surge voltage is applied in the plane of the semiconductor substrate 30 is different.

[0165] The bonding pad 41 is preferably disposed in the center of the semiconductor substrate 30, but as described above, due to n - The p-type drift region 12 and the p-type region 13 are arranged approximately equally in the plane of the active region 10 with approximately the same pattern. Therefore, even if the bonding pad 41 is not arranged in the center of the semiconductor substrate 30, it will not have an adverse effect on the electrical characteristics. Thus, the wire bonding has a high degree of freedom.

[0166] Next, the cross-sectional structure of the silicon carbide semiconductor device 40 of Embodiment 1 will be described. Figure 3 It is shown Figure 2 A cross-sectional view of the cross-sectional structure at the cutting line A-A'. As described above, the silicon carbide semiconductor device 40 of Embodiment 1 has an SBD structure and a JBS structure of a silicon carbide diode in the active region 10 of the semiconductor substrate 30 made of silicon carbide, and has a JTE structure as a voltage withstand structure in the edge terminal region 20.

[0167] Semiconductor substrate 30 is made of silicon carbide. + The front side of the type-starting substrate 11 is stacked to form n - Type drift region 12 of n - An epitaxial substrate formed by an epitaxial layer. + Type-starting substrate 11 is n + Type-n cathode region. Semiconductor substrate 30 will have n - The main surface on the 12th side of the drift region (becoming n) - Type drift region 12 of n - The surface of the epitaxial layer is taken as the front side, and n is used as the front side. + Main surface (n) on side of type starting substrate 11 + The back side of the type starting substrate 11 is used as the back side.

[0168] In the active region 10, one or more p-type regions 13 constituting a JBS structure are selectively disposed on the surface region of the front side of the semiconductor substrate 30. The p-type regions 13 are disposed on the front side of the semiconductor substrate 30 and the n-type region 13. - Between the n-type drift regions 12. The p-type region 13 is exposed on the front side of the semiconductor substrate 30 and is adjacent to the n-type drift region 12. - Type drift zone 12 contact.

[0169] In the edge terminal region 20, FLR 21 and one or more p-type regions (here, two p-type regions) constituting the JTE structure are selectively provided on the surface region of the front side of the semiconductor substrate 30. - Type 22 and p -- Type 23) and n + Type-shaped channel cutoff region 24. FLR21 is provided in the entire area of ​​the connection region 20a of the edge terminal region 20, and extends outward from the connection region 20a to connect with p. - Type 22 contact. The region further inside than FLR21 is the active region 10.

[0170] p - Type region 22 is disposed outside FLR 21 in a manner separate from the connection region 20a of edge terminal region 20, and adjacent to FLR 21. --Type 23 is set in p - The outer side of type region 22, and with p - Type region 22 is adjacent. + Type 24 truncation zone with p -- The type 23 is set in a way that is more than p -- The outermost position of type 23. + The channel cut-off region 24 is exposed at the end (chip end) of the semiconductor substrate 30.

[0171] FLR21, p - Type 22, p -- Type 23 and n + The channel cutoff region 24 is disposed on the front side of the semiconductor substrate 30 and the n - Type drift zone 12. FLR21, p - Type 22, p -- Type 23 and n + The channel cutoff region 24 is exposed on the front side of the semiconductor substrate 30 and is connected to the n-type channel cutoff region 24. - Type drift region 12 contact. FLR21, p - Type 22, p -- Type 23 and n + The depth of the p-type channel cutoff region 24 can, for example, be the same as the depth of the p-type region 13.

[0172] The front side of the semiconductor substrate 30 is covered by a field oxide film 15. The field oxide film 15 may be, for example, a laminated film formed by sequentially stacking a thermal oxide film 16 and a deposited oxide film 17. The thermal oxide film 16 can improve the tightness of the adhesion between the semiconductor substrate 30 and the field oxide film 15. Since the field oxide film 15 includes the deposited oxide film 17, the field oxide film 15 can be formed in a shorter time compared to the case where the field oxide film 15 is entirely a thermal oxide film 16.

[0173] The field oxide film 15 has contact holes 15a that expose approximately the entire front surface of the semiconductor substrate 30 in the active region 10. The sidewalls of the contact holes 15a (the inner side surfaces of the field oxide film 15) are, for example, approximately orthogonal to the front surface of the semiconductor substrate 30. The contact holes 15a of the field oxide film 15 are provided over the entire region from the active region 10 to the connection region 20a of the edge termination region 20.

[0174] The contact hole 15a of the on-site oxide film 15 will allow n in the active region 10 to pass through. - The inner portion of FLR21 in the p-type drift region 12, p-type region 13, and edge terminal region 20 is exposed. Inside the contact hole 15a of the field oxide film 15, on the front side of the semiconductor substrate 30, a front electrode 14 that functions as an anode electrode is provided along the front side of the semiconductor substrate 30.

[0175] The front electrode 14 has a stacked structure consisting of a titanium film 31 and an aluminum alloy film (a metal electrode film containing aluminum) 32 sequentially stacked. In addition, the front electrode 14 also has a bottommost nickel silicide (NiSi) film 33 (33a, 33b) selectively disposed between the front side of the semiconductor substrate 30 and the titanium film 31. The nickel silicide film 33 contains aluminum. The nickel silicide film 33 may also contain carbon (C). The front electrode 14 may extend outwards on the field oxide film 15.

[0176] A titanium film 31 is disposed inside the contact hole 15a over the entire front side of the semiconductor substrate 30, and is connected to n - Type drift region 12 contact. Titanium film 31 and n - The junction of type drift region 12 is formed with n - Schottky electrode of the Schottky junction in drift region 12. Titanium film 31 may extend outward on field oxide film 15 and terminate at, for example, a position opposite to FLR 21 in the depth direction.

[0177] The aluminum alloy film 32 covers the entire surface of the titanium film 31, is electrically connected to the titanium film 31, and is electrically connected to the nickel silicide film 33 through the titanium film 31. The aluminum alloy film 32 can extend on the field oxide film 15 to a position further outward than the titanium film 31, and terminates, for example, in the depth direction, with p - The opposite position of the type area 22. The aluminum alloy film 32 is, for example, an aluminum silicon (AlSi) film. Alternatively, an aluminum film can be used instead of the aluminum alloy film 32.

[0178] The nickel silicide film 33 has a first nickel silicide film 33a disposed between the p-type region 13 and the titanium film 31, and a second nickel silicide film 33b disposed between the FLR 21 and the titanium film 31. The first nickel silicide film 33a is an ohmic electrode that is ohmically bonded to the p-type region 13. The first nickel silicide film 33a has the function of increasing the amount of surge current (extraction amount) that is drawn from the semiconductor substrate 30 to the front electrode 14 when a surge voltage is applied, thereby improving the surge current withstand capability.

[0179] As described later, the first nickel silicide film 33a passes through the p-type region 13 and the metal material film 52 deposited on the front side of the semiconductor substrate 30 (see reference). Figure 10 The contact area between the two is formed by heat treatment to react the surface area of ​​the semiconductor substrate 30 with the metal material film 52. Therefore, the first nickel silicide film 33a is disposed on the surface area of ​​the front side of the semiconductor substrate 30, contacts the p-type region 13 in the depth direction, and protrudes from the front side of the semiconductor substrate 30 in a direction away from the front side of the semiconductor substrate 30.

[0180] The width w2a of the first nickel silicide film 33a is preferably approximately the same as, for example, the width w1 of the p-type region 13. By making the width w2a of the first nickel silicide film 33a the same as the width w1 of the p-type region 13, the p-type region 13 is not exposed on the front side of the semiconductor substrate 30. Therefore, since a high-resistance Schottky junction is not formed between the p-type region 13 and the titanium film 31, a lower forward voltage (Vf) of the silicon carbide diode can be achieved compared to the case where the p-type region 13 is exposed on the front side of the semiconductor substrate 30.

[0181] The width w2a of the first nickel silicide film 33a can be narrower than the width w1 of the p-type region 13. By making the width w2a of the first nickel silicide film 33a narrower than the width w1 of the p-type region 13, it is possible to obtain a mask used to improve the formation of the first nickel silicide film 33a (the remainder of the field oxide film 15 described later: see reference). Figure 10 The design margin for the positional alignment accuracy is such that the first nickel silicide film 33a can be positioned with good positional accuracy opposite to the p-type region 13 in the depth direction.

[0182] The second nickel silicide film 33b is an ohmic electrode that is ohmically bonded to the FLR 21. The second nickel silicide film 33b is disposed over almost the entire surface of the FLR 21 in the connection region 20a located in the edge terminal region 20. The second nickel silicide film 33b is in contact with the field oxide film 15 at the sidewall of the field oxide film 15. Similar to the first nickel silicide film 33a, the second nickel silicide film 33b has the function of increasing the surge current extraction rate and thus improving the surge current withstand capability.

[0183] By providing a second nickel silicide film 33b, an ohmic electrode with the same function as the first nickel silicide film 33a can be configured in the connection region 20a of the edge terminal region 20. Therefore, even when the chip size (the planar dimension parallel to the front side of the semiconductor substrate 30) becomes smaller, the combined area of ​​the first nickel silicide film 33a and the second nickel silicide film 33b with the semiconductor substrate 30 can sufficiently ensure the amount of ohmic junction area between the front electrode 14 and the semiconductor substrate 30 required to obtain the predetermined surge current withstand capacity.

[0184] Furthermore, by extending the second nickel silicide film 33b outward to the position where it contacts the field oxide film 15, the ohmic junction area between the FLR 21 and the second nickel silicide film 33b can be maximized. As a result, the width w2b of the second nickel silicide film 33b becomes approximately the same as the width w3 of the connection region 20a of the edge termination region 20, and as described above, the second nickel silicide film 33b can be disposed on almost the entire surface of the FLR 21 located in the connection region 20a of the edge termination region 20.

[0185] Furthermore, by making the width w2b of the second nickel silicide film 33b approximately the same as the width w3 of the connection region 20a of the edge terminal region 20, a low forward voltage can be achieved in the silicon carbide diode, similar to the case where the width w2a of the first nickel silicide film 33a is approximately the same as the width w1 of the p-type region 13. The width w2b of the second nickel silicide film 33b can be narrower than, for example, the width w3 of the connection region 20a of the edge terminal region 20. The reason is the same as the reason why the width w2a of the first nickel silicide film 33a can be narrower than the width w1 of the p-type region 13.

[0186] As described later, the second nickel silicide film 33b is formed by reacting the semiconductor substrate 30 with the metal material film 52 at the contact point between the FLR 21 and the metal material film 52 deposited on the front side of the semiconductor substrate 30 through heat treatment. The second nickel silicide film 33b is disposed on the surface region of the front side of the semiconductor substrate 30, contacts the FLR 21 in the depth direction, and protrudes from the front side of the semiconductor substrate 30 in a direction away from the front side of the semiconductor substrate 30.

[0187] The front side of the semiconductor substrate 30, except for the portion in contact with the front electrode 14, is covered by a field oxide film 15. A passivation film 18 made of polyimide is provided on the outermost surface of the front side of the semiconductor substrate 30. Here, n + The upper part of the truncated section 24 of the channel is set with n + The channel cut-off region 24 is in contact with and electrically connected to the channel cut-off electrode. The channel cut-off electrode may be an aluminum alloy film formed simultaneously with, for example, an aluminum alloy film 32.

[0188] The passivation film 18 is a protective film that protects the front electrode 14 and the field oxide film 15. The passivation film 18 has an opening 18a in the active region 10 that exposes a portion of the aluminum alloy film 32. The portion of the front electrode 14 exposed in the opening 18a of the passivation film 18 functions as a bonding pad 41. On the back side (n) of the semiconductor substrate 30... + A back electrode (second electrode) 19 is provided on the entire back surface of the type starting substrate 11, and is connected to n + The type-starting substrate 11 is electrically connected.

[0189] Next, the manufacturing method of the silicon carbide semiconductor device 40 according to Embodiment 1 will be described. Figure 4 This is a flowchart illustrating an outline of the manufacturing method of the silicon carbide semiconductor device according to Embodiment 1. Figures 5 to 15 This is a cross-sectional view showing the state during the manufacturing process of the silicon carbide semiconductor device according to Embodiment 1. Figures 16 to 18 This is a cross-sectional view schematically showing the state of the front electrode of the silicon carbide semiconductor device in Embodiment 1 during the manufacturing process. Figure 19This is a cross-sectional view schematically showing the state of the front electrode during the manufacturing process of Reference Example 1.

[0190] First, such as Figure 5 As shown, n + Type-starting substrate (semiconductor wafer) 11, prepared with, for example, 1×10⁻⁶ particles. 16 / cm 3 A four-layer periodic hexagonal (4H-SiC) substrate of nitrogen (N) silicon carbide. + The front side of the type-starting substrate 11 can have an offset angle of about 4° relative to, for example, the (0001) surface. Next, in n + n is grown on the front side of the type-starting substrate 11. - The drift region 12 is doped with, for example, 1.8 × 10⁻⁶. 16 / cm 3 The left and right nitrogen n - Type epitaxial layer (first process).

[0191] Become n + n-type cathode region + The thickness of the type-initiating substrate 11 can be, for example, around 350 μm. This becomes n - Type drift region 12 of n - The thickness of the epitaxial layer can be, for example, around 6 μm. Through the processes up to this point, an epitaxial layer is fabricated on the n-type layer. + The front side of the type starting substrate 11 is stacked with n - Type drift region 12 of n - A semiconductor substrate (semiconductor wafer) 30 with an epitaxial layer. As described above, the semiconductor substrate 30 has an n-type epitaxial layer. - The main surface of the 12-sided drift zone is the front, and it is marked with n + The main surface of the type starting substrate 11 is the back side.

[0192] Next, as Figure 6 As shown, through photolithography and first ion implantation of p-type impurities such as aluminum, in the active region 10 (reference) Figure 1 , Figure 3 In the process, one or more p-type regions 13 and FLR 21 constituting the JBS structure are selectively formed on the surface region of the front side of the semiconductor substrate 30 (step S1 (the first of the steps): the second process, the third process). Figure 6 In the middle, simplified to the ratio Figure 1 A small number (3 in this case) is shown in the diagram of p-type region 13 (in Figures 7-15 (The same applies to the middle). Multiple p-type regions 13 are arranged at equal intervals, for example, at intervals of about 2 μm, in a direction parallel to the front side of the semiconductor substrate 30.

[0193] At this time, while heating the semiconductor substrate 30 at a temperature of, for example, around 500°C, n is approached from the front side of the semiconductor substrate 30. - Type epitaxial layer (n) - A first ion implantation is performed in the drift region 12. In this first ion implantation, for example, the impurity concentration of the box profile extending from the front surface of the semiconductor substrate 30 to a depth of 500 nm is set to 2 × 10⁻⁶. 19 / cm 3 The method involves implanting p-type impurities into ions in multiple stages using different acceleration energies ranging from 30 keV to 350 keV.

[0194] Next, as Figure 7 As shown, under different conditions, a process consisting of photolithography and second ion implantation of impurities is repeatedly performed in the edge terminal region 20 (refer to...). Figure 3 In the process, p-type regions constituting the JTE structure are selectively formed on the surface region of the front side of the semiconductor substrate 30. - Type 22 and p -- Type 23) and n + Type 24 trench cutoff zone (refer to) Figure 3 (Step S1 (2)). The second ion implantation is, for example, the same as the first ion implantation, performed in multiple stages in such a way that the impurity concentration distribution forms a box-shaped profile.

[0195] Next, as Figure 8 As shown, after protecting the entire front side of the semiconductor substrate 30 by covering it with, for example, a carbon (C) protective film 50, the impurities implanted by the first and second ion implantations are activated by heat treatment (step S2). In step S2, for example, the semiconductor substrate 30 is inserted into the processing furnace of the heat treatment apparatus, and the atmosphere inside the processing furnace is drawn (vacuumed) to a depth of 1 × 10⁻⁶. -2 After a pressure below Pa, argon (Ar) gas is introduced into the processing furnace at a pressure of 1×10⁻⁶ Pa. 5 The mixture is subjected to heat treatment at a temperature of approximately 1700°C for about 5 minutes in an atmosphere with a pressure of approximately Pa.

[0196] Next, as Figure 9As shown, for example, an ashing process (ashing) apparatus is used to remove the carbon protective film 50 by ashing. For example, a reactive ion etching (RIE) apparatus is used as the ashing apparatus. After the processing furnace of the RIE apparatus is set to an oxygen (O2) atmosphere at a pressure of about 6 Pa, the carbon protective film 50 is removed by ashing for about 5 minutes in an oxygen atmosphere that has been plasmaized by applying a high-frequency (RF) power of about 500 W.

[0197] Next, as Figure 10 As shown, an oxide film 51 is formed on the entire front side of the semiconductor substrate 30 (step S3: fourth process). Next, the oxide film 51 is selectively removed by photolithography and etching to form openings (first opening, second opening) 51a and 51b (step S4: fifth process). In the process of step S4, multiple openings 51a are formed on the oxide film 51, exposing different p-type regions 13 respectively, and an opening 51b is formed in a generally rectangular shape that surrounds the active region 10 and exposes the inner side of the FLR 21.

[0198] Through the processing in step S4, the oxide film 51 is coated with n in the active region 10. - The portion 15' of the drift region 12 and the portion remaining in the edge end region 20 as the field oxide film 15. After the processing in step S4, the oxide film 51, including the portion that becomes the field oxide film 15, becomes entirely the oxide film mask used in the subsequent process to form the nickel silicide film 33. The oxide film 51 covers the active region 10 with n - Part 15' of the drift zone 12 does not remain in the product.

[0199] That is, in step S4, a field oxide film 15 and an oxide film mask for forming a nickel silicide film 33 are formed simultaneously. Therefore, the oxide film 51 has the same stacked structure as the field oxide film 15. Specifically, the oxide film 51 is formed by sequentially stacking a thermal oxide film 16 and a deposited oxide film 17 (see reference) based on, for example, thermal oxidation and chemical vapor deposition (CVD) methods. Figure 3 And a stacked oxide film with a thickness of about 500nm.

[0200] The process in step S4 can be performed using dry etching with high dimensional accuracy. This allows for the exposure of the p-type region 13 and FLR21 with good dimensional accuracy. Furthermore, the sidewall outside the opening 51b of the oxide film 51 becomes the sidewall of the contact hole 15a of the field oxide film 15. Therefore, by using dry etching to perform step S4, the contact hole 15a of the field oxide film 15 can be formed with good dimensional accuracy.

[0201] Next, a metal material film 52 is formed on the front surface (surface) of the semiconductor substrate 30 located within the openings 51a and 51b of the oxide film 51 by means of, for example, sputtering. The metal material film 52 is a stacked metal film consisting of an aluminum film (a metal film containing aluminum) 53 and a nickel film 54 sequentially laminated. Figure 16 ).exist Figure 10 In the diagram, aluminum film 53 and nickel film 54 are combined as a single layer of metal material film 52.

[0202] The nickel film 54 is a cap film used to prevent the aluminum film 53 from melting during the heat treatment in step S6 (described later). It has a thickness t2 of approximately 50 nm. The cap film is used because, without it, the aluminum film 53, which melts during the heat treatment in step S6, becomes granular and partially contacts the semiconductor substrate 30. In this case, it is impossible to uniformly form the Al-Ni-Si compound (compound layer) 55 (described later) across the entire front surface of the semiconductor substrate 30.

[0203] Subsequently, the metal film 52 is subjected to a first sintering process using heat treatment (step S6: seventh step), thereby generating an aluminum-nickel-silicon (Al-Ni-Si) compound 55 (refer to) within the openings 51a and 51b of the oxide film 51. Figure 11 The mechanism for generating Al-Ni-Si compound 55 using heat treatment (first sintering) will use... Figures 16 to 18 Please provide a detailed explanation.

[0204] Figure 16 Only the contact areas between the metal material film 52 within the openings 51a and 51b of the oxide film 51 and the semiconductor substrate 30 are shown, and illustrations of other parts are omitted. Figure 17 and Figure 18 The same applies to China). Although Figure 16 The diagram shows the state within one opening (51a, 51b) of the oxide film 51, but all openings 51a and 51b of the oxide film 51 are in harmony with the state of the oxide film 51. Figure 16 The states shown are the same. The thickness t1 of the aluminum film 53 can be set to, for example, 20 nm, and the thickness t2 of the nickel film 54 can be set to, for example, 50 nm.

[0205] Through the heat treatment in step S6, at the contact points between the metal film 52 and the semiconductor substrate 30 within the openings 51a and 51b of the oxide film 51, silicon atoms in the semiconductor substrate 30 undergo thermal diffusion 61 into the aluminum film 53. Aluminum atoms in the aluminum film 53 undergo thermal diffusion 62 into the nickel film 54. Nickel atoms in the nickel film 54 undergo thermal diffusion 63 into both the aluminum film 53 and the semiconductor substrate 30. Figure 17 ).

[0206] Through thermal diffusion 62 of aluminum atoms into the nickel film 54 and thermal diffusion 63 of nickel atoms into the aluminum film 53, an aluminum-nickel (AlNi) compound 56 is generated on the front side of the semiconductor substrate 30 located within the openings 51a and 51b of the oxide film 51 and on the surface of the oxide film 51. Further, through the reaction between this aluminum-nickel compound 56 and the semiconductor substrate 30, an Al-Ni-Si compound 55 is generated at the contact site between the metal material film 52 and the semiconductor substrate 30. Figure 18 ).

[0207] Al-Ni-Si compound 55 is formed by reacting a low-impurity portion of the p-type region 13 and FLR21, which are diffusion regions formed by ion implantation, with the metal film 52 at a relatively shallow depth of 20 nm to 30 nm from the front side of the semiconductor substrate 30. Therefore, the compound layer containing Al-Ni-Si compound 55 is self-aligned and formed by embedding itself into the interior of the semiconductor substrate 30 in the depth direction within the openings 51a and 51b of the oxide film 51, using the oxide film 51 as a mask.

[0208] Furthermore, the Al-Ni-Si compound 55 contacts a high-impurity portion of the semiconductor substrate 30, located at a depth greater than the low-impurity portion on the front side of the semiconductor substrate 30, where the p-type region 13 or the FLR 21 is formed. The Al-Ni-Si compound 55 forms a low-resistance ohmic junction with this high-impurity portion within the p-type region 13 or the FLR 21.

[0209] Within the Al-Ni-Si compound 55, residual carbon (C) (hereinafter referred to as residual carbon) remaining in the semiconductor substrate 30 due to the silicide phytochemical reaction between the Al-Ni-Si compound 55 and the semiconductor substrate 30 can precipitate out to a degree that does not form layers. The residual carbon is carbon atoms remaining in the semiconductor substrate 30 due to the consumption of silicon atoms in the semiconductor substrate 30 by the aforementioned silicide phytochemical reaction. Specifically, the residual carbon within the Al-Ni-Si compound 55 can precipitate and distribute in a granular form.

[0210] Considering the uniformity of the chemical reaction, the heat treatment time of step S6 can be, for example, 2 minutes or more; considering the mass production of the product, the heat treatment time of step S6 can be, for example, 1 hour or less. The heat treatment temperature of step S6 is preferably, for example, 400°C or higher and 550°C or lower. The reason is as follows: when the heat treatment temperature of step S6 exceeds 550°C, aluminum atoms in the aluminum film 53 penetrate into the silicon oxide (SiO2) film, i.e., the oxide film 51, and react, generating products within the oxide film 51 as described later. If these products remain in the field oxide film 15, they can cause leakage current problems under reverse bias.

[0211] Furthermore, because the heat treatment temperature in step S6 is less than 400°C, the semiconductor substrate 30 and the metal film 52 do not undergo the aforementioned reaction, the metal film 52 is not used, and all metal films 52 are removed in the subsequent step S7. Additionally, because the heat treatment temperature in step S6 is less than 600°C, aluminum atoms in the aluminum film 53 do not thermally diffuse into the semiconductor substrate 30. The heat treatment in step S6 is preferably performed using, for example, a heat treatment furnace where the heat treatment temperature can be easily and uniformly controlled. Temperature uniformity means approximately the same temperature within a range including errors allowed by process variations. The above is a detailed explanation related to the first sintering.

[0212] Next, as Figure 12 As shown, the remaining metal (residual portion) on the oxide film 51 and within the openings 51a and 51b of the oxide film 51 is removed (step S7: eighth step). The remaining metal is the metal generated from the metal material film 52, excluding the nickel silicide film 33; specifically, it is the aluminum-nickel compound 56, which does not contribute to the formation of the nickel silicide film 33. In the process of step S7, the entire front side of the semiconductor substrate 30 is etched using, for example, wet etching with phosphoric acid, nitric acid, and acetic acid. Through the process of step S7, Al-Ni-Si compound 55 remains in each opening 51a and 51b of the oxide film 51.

[0213] Next, as Figure 13 As shown, the Al-Ni-Si compound 55 undergoes a second sintering process via heat treatment (step S8: ninth step). Through the heat treatment in step S8, nickel silicide is generated within the Al-Ni-Si compound 55, transforming the Al-Ni-Si compound 55 into a nickel silicide film 33 that forms an ohmic bond with the semiconductor substrate 30. Consequently, nickel silicide films 33 that form an ohmic bond with the semiconductor substrate 30 are formed self-aligned within each opening 51a and 51b of the oxide film 51, using the oxide film 51 as a mask.

[0214] The heat treatment time for step S8 can be the same as that for step S6. The heat treatment temperature for step S8 is preferably above 900°C, where nickel silicide is formed within the Al-Ni-Si compound 55, and below 1050°C, which allows for low-cost processing using a vertical heat treatment furnace. The heat treatment for step S8 is preferably performed using, for example, a heat treatment furnace capable of uniformly controlling the heat treatment temperature.

[0215] Next, as Figure 14 As shown, contact holes 15a of the field oxide film 15 are formed by photolithography (refer to...). Figure 3 A resist film 57 is formed by opening the area of ​​the field oxide film 15. Next, using the resist film 57 as a mask, etching is performed to form a contact hole 15a that penetrates the field oxide film 15 along the depth direction (see reference). Figure 3 (Step S9: Tenth process). In this step S9, only the portion of the oxide film 51 that becomes the field oxide film 15 remains.

[0216] In the process of step S9, by covering the active region 10 with n in the oxide film 51 - The drift region 12 is completely removed, and the openings 51a and 51b of the oxide film 51 are completely connected, thereby revealing the contact hole 15a formed in step S4. During the process in step S9, the outer sidewall of the opening 51b of the oxide film 51 is completely covered by the resist film 57, therefore, the outer sidewall of the opening 51b of the oxide film 51 is not etched.

[0217] The contact holes 15a of the in-field oxide film 15 expose the entire surface of the active region 10 and the entire surface of the connection region 20a of the edge terminal region 20. Thus, the contact holes 15a of the in-field oxide film 15 expose all the nickel silicide films 33 (33a, 33b) and n - The portion of the drift region 12 sandwiched between adjacent nickel silicide films 33 is exposed.

[0218] When the width w2a of the first nickel silicide film 33a and the width w2b of the second nickel silicide film 33b are smaller than the width w1 of the p-type region 13 and the width w3 of the connection region 20a of the edge terminal region 20, respectively, the contact hole 15a of the field oxide film 15 will also expose the portions of the p-type region 13 and the surface of the FLR 21 that are not bonded to the nickel silicide film 33.

[0219] The processing in step S9 is preferably performed by wet etching. This is because if step S9 is performed by dry etching, plasma damage caused by dry etching may remain on the front side of the semiconductor substrate 30. Even if step S9 is performed by wet etching, the contact hole 15a can be formed in the field oxide film 15 with good dimensional accuracy. This is because, during the processing in step S4, the sidewall outside the opening 51b formed in the oxide film 51 with good dimensional accuracy by dry etching is formed by the sidewall of the contact hole 15a of the field oxide film 15.

[0220] In step S4, the covering n in the oxide film 51 is... - Part 15' of the drift region 12 and part of the residual field oxide film 15 (see reference) Figure 10 Therefore, after the processing in step S4, the coating n in the oxide film 51 - A portion 15' of the drift region 12 remains within the contact hole 15a of the field oxide film 15, and the outer sidewall of the opening 51b of the oxide film 51 is formed by the sidewall of the contact hole 15a of the field oxide film 15. During the processing in step S9, the outer sidewall of the opening 51b of the oxide film 51 is completely covered by the resist film 57 and is not etched. Therefore, after the processing in step S4, the position of the outer sidewall of the opening 51b of the oxide film 51 remains unchanged.

[0221] Thus, the dimensional accuracy of the contact hole 15a of the field oxide film 15 is the same as the dimensional accuracy of the opening 51b of the oxide film 51 formed by dry etching, and does not depend on the dimensional accuracy of the wet etching in step S9. Furthermore, after step S4, the position of the outer sidewall of the opening 51b of the oxide film 51 does not change. Therefore, the second nickel silicide film 33b, which is self-aligned and formed using the oxide film 51 as a mask, also remains in contact with the outer sidewall of the opening 51b of the oxide film 51 after step S9. That is, the second nickel silicide film 33b also remains in contact with the field oxide film 15 at the sidewall of the contact hole 15a after step S9.

[0222] For example, using existing technology (such as the aforementioned Patent Document 2, etc.) to produce Figure 19 The conventional silicon carbide semiconductor device 170 is shown. Figure 19 The conventional silicon carbide semiconductor device 170 shown is a silicon carbide diode (hereinafter referred to as Reference Example 1) that differs from the silicon carbide semiconductor device 40 of Embodiment 1 only in the configuration of the second nickel silicide film 133b. The configuration of Reference Example 1 is the same as that of the silicon carbide semiconductor device 40 of Embodiment 1, except for the second nickel silicide film 133b. Figure 19In the example, the hundreds digit of the symbols of the corresponding parts of the silicon carbide semiconductor device 40 of Embodiment 1 is set to 1 and marked in each part of Reference Example 1.

[0223] In Reference Example 1, the second nickel silicide film 133b, which is ohmically bonded to FLR 121, needs to be positioned away from the field oxide film 115. The reason is as follows. In Reference Example 1, when the metal material film 172 (see reference...) is... Figure 30 , Figure 31 After patterning and selectively depositing the metal material film 172 onto the p-type region 113 and FLR 121 respectively, the metal material film 172 is sintered to form a nickel silicide film 133. In this case, if the second nickel silicide film 133b comes into contact with the field oxide film 115, aluminum atoms penetrate from the aluminum film of the metal material film 172 into the field oxide film 115 and react, generating a product that becomes a leakage current source (equivalent to...). Figure 30 , Figure 31 (symbol 134).

[0224] The second nickel silicide film 133b is configured away from the field oxide film 115 in a manner that prevents the formation of this product. However, when the second nickel silicide film 133b is configured away from the field oxide film 115, a process margin is obtained for forming the second nickel silicide film 133b at a location away from the field oxide film 115, resulting in an invalid region 120b that neither forms an ohmic junction nor a Schottky junction. Therefore, it is not possible to ensure sufficient ohmic junction area for the surface area portion of the invalid region 120b in the connection region 120a of the edge termination region 120.

[0225] On the other hand, in Embodiment 1, as described above, the first nickel silicide film 33a and the second nickel silicide film 33b can be formed in a self-aligned manner using the oxide film 51 as a mask. Therefore, the first nickel silicide film 33a and the second nickel silicide film 33b can be formed with good precision on almost the entire surface area of ​​the p-type region 13 and the FLR 21, respectively. Furthermore, the second nickel silicide film 33b can be disposed in contact with the field oxide film 15 in almost the entire area of ​​the connection region 20a of the edge terminal region 20, and sufficient ohmic junction area can be ensured in the connection region 20a of the edge terminal region 20.

[0226] Next, as Figure 15As shown, a titanium film 31 is formed on the entire surface of the semiconductor substrate 30, from the surface of the field oxide film 15 to the front side located within the contact hole 15a, using a physical vapor deposition method such as sputtering. Next, by photolithography and etching, the titanium film 31 is left only within the contact hole 15a (step S10: eleventh step). The thickness of the titanium film 31 can be, for example, around 100 nm. The titanium film 31 can extend from within the contact hole 15a onto the field oxide film 15.

[0227] Next, the titanium film 31 is sintered by heat treatment at a temperature of approximately 500°C for about 10 minutes. Through this heat treatment, the titanium film 31 and n are formed. - A Schottky junction is formed between the drift regions 12. Next, an aluminum alloy film with a thickness of approximately 5 μm is formed over the entire surface from the surface of the titanium film 31 to the surface of the field oxide film 15 by physical vapor deposition, such as sputtering. Next, the aluminum alloy film is selectively removed by photolithography and etching, leaving an aluminum alloy film 32, which serves as the front electrode 14, on the surface of the titanium film 31.

[0228] Next, after protecting the front side of the semiconductor substrate 30 (semiconductor wafer) with a protective film (not shown), the semiconductor substrate 30 is thinned to the product thickness by grinding from the back side. Next, the back side (n) of the semiconductor substrate 30 is thinned using a physical vapor deposition method such as sputtering. + After nickel and titanium are formed on the entire back surface of the initial substrate 11, the back electrode 19 is formed by laser annealing (step S11: twelfth process). Subsequently, after removing the protective film on the front surface of the semiconductor substrate 30, the semiconductor substrate 30 is monolithically divided into individual chips by cutting (splitting), thereby completing the process. Figure 1 , Figure 3 The silicon carbide semiconductor device 40 shown.

[0229] As described above, according to Embodiment 1, by providing a second nickel silicide film as an ohmic electrode for ohmic bonding with the FLR in almost the entire area of ​​the connection region of the edge terminal region, a low-resistance ohmic electrode can be formed not only in the active region but also in the entire area of ​​the connection region of the edge terminal region. Therefore, it is possible to maintain n - A predetermined Schottky junction area between the drift region and the Schottky electrode maintains a low forward voltage (Vf), and the sum of the ohmic junction areas in the connection regions of the active region and the edge termination region ensures the amount of ohmic junction area required to achieve the predetermined surge current withstand capability. Therefore, even with smaller chip sizes, the ohmic junction area can be ensured to be large enough without compromising the forward voltage characteristics, thereby achieving the predetermined surge current withstand capability.

[0230] (Implementation Method 2)

[0231] Next, the manufacturing method of the silicon carbide semiconductor device according to Embodiment 2 will be described. The manufacturing method of the silicon carbide semiconductor device in Embodiment 2 differs from the manufacturing method of the silicon carbide semiconductor device 40 in that the aluminum film 53 (refer to...) used to form the metal material film 52 for forming the first nickel silicide film 33a and the second nickel silicide film 33b... Figure 16 The first nickel silicide film 33a and the second nickel silicide film 33b are formed by using a metal material film 52 formed by sequentially stacking an aluminum silicon film and a nickel film 54.

[0232] The thickness of the aluminum-silicon film of the metal material film 52 is preferably, for example, 5 nm or more and 300 nm or less. This is because if the thickness of the aluminum-silicon film of the metal material film 52 is less than 5 nm, the thickness is too thin, so even with subsequent processing, the predetermined contact resistance cannot be obtained. Furthermore, if the thickness of the aluminum-silicon film of the metal material film 52 exceeds 300 nm, the thickness is too thick, so the nickel film of the metal material film 52 does not react with the semiconductor substrate 30, and a nickel silicide film 33 is not formed, thus the predetermined contact resistance cannot be obtained.

[0233] The silicon concentration of the aluminum-silicon film of the metal material film 52 is preferably, for example, 0.1 wt% or more and 3 wt% or less. This is because by making the silicon concentration of the aluminum-silicon film of the metal material film 52 0.1 wt% or more, the silicide reaction between the nickel atoms in the nickel film 54 of the metal material film 52 and the silicon atoms in the aluminum-silicon film of the metal material film 52 is easier to occur than the silicide reaction between the nickel atoms in the nickel film 54 of the metal material film 52 and the silicon atoms in the semiconductor substrate 30. As a result, it is difficult for residual carbon to be generated in the semiconductor substrate 30, and it is possible to form a nickel silicide film 33 with less residual carbon precipitation from the semiconductor substrate 30 compared to Embodiment 1, or with no residual carbon precipitation from the semiconductor substrate 30.

[0234] Furthermore, when the silicon concentration of the aluminum-silicon film in the metal material film 52 exceeds 3 wt%, it becomes impossible to uniformly distribute silicon within the aluminum-silicon film during sputtering, resulting in areas with locally high silicon concentrations. In this case, it is impossible to achieve a predetermined silicon ratio in the aluminum-silicon film of the metal material film 52 across the entire area of ​​the film. The silicon concentration of the aluminum-silicon film in the metal material film 52 is optimized within the aforementioned preferred range, based on, for example, the respective thicknesses of the aluminum-silicon film of the metal material film 52 and the nickel film 54.

[0235] Furthermore, the manufacturing method of the silicon carbide semiconductor device in Embodiment 2 and the manufacturing method of the silicon carbide semiconductor device 40 in Embodiment 1 (see [reference]). Figure 4 The differences between the flowchart and the previous one are as follows: First, in step S5, as described above, a metal material film 52 formed by sequentially stacking an aluminum-silicon film and a nickel film 54 is used. Second, the heat treatment temperature in step S6 can be set higher than that in the manufacturing method of the silicon carbide semiconductor device 40 of Embodiment 1 described above.

[0236] The two differences mentioned above will be explained. In Embodiment 2, similarly to Embodiment 1, the aluminum-silicon film and the nickel film 54 are reacted through the heat treatment in step S6 to generate an aluminum-nickel compound 56, and the aluminum-nickel compound 56 is further reacted with the semiconductor substrate 30 to generate an Al-Ni-Si compound 55 (see reference). Figure 18 The heat treatment temperature in step S6 is preferably, for example, 400°C or higher and 800°C or lower, so that the upper limit is higher than the heat treatment temperature in embodiment 1.

[0237] In Embodiment 2, the heat treatment in step S6 can be performed at a high temperature higher than the upper limit of the heat treatment temperature in Embodiment 1 because even if the heat treatment in step S6 is performed at a high temperature higher than the upper limit of the heat treatment temperature in Embodiment 1, the aluminum-silicon film of the metal material film 52 and the oxide film 51 (refer to) serving as the oxide film mask... Figure 10 It is also difficult for a reaction to occur. The higher the temperature at which the heat treatment of step S6 is performed, the more likely a lower resistance ohmic junction can be formed between the nickel silicide film 33 and the semiconductor substrate 30 (p-type region 13).

[0238] The reason for setting the upper limit of the heat treatment temperature in step S6 to around 800°C is that if the heat treatment temperature in step S6 exceeds 800°C, the aluminum-nickel compound 56 reacts with the oxide film 51 to generate a product that becomes a leakage current source inside the oxide film 51 (equivalent to...). Figure 30 , Figure 31 (symbol 134). Since the product cannot be removed by wet etching in the subsequent step S7, it remains in the product. The reason for setting the lower limit of the heat treatment temperature in step S6 to about 400°C is the same as in embodiment 1.

[0239] Furthermore, during the heat treatment in step S6, silicon atoms are provided from the aluminum-silicon film of the metal material film 52, making it difficult to provide silicon atoms to the semiconductor substrate 30 and to precipitate residual carbon from the semiconductor substrate 30. Although the residual carbon reacts with aluminum atoms in the aluminum-nickel compound 56 to generate aluminum carbide (Al4C3) in the aluminum-nickel compound 56, which increases the contact resistance between the aluminum-nickel compound and the semiconductor substrate 30, the difficulty in precipitating residual carbon prevents the formation of aluminum carbide, thus suppressing the increase in contact resistance.

[0240] Furthermore, since it is difficult to deposit residual carbon within the nickel silicide film 33, the adhesion between the nickel silicide film 33 and the semiconductor substrate 30 can be improved, and peeling of the front electrode 14 can be suppressed. Additionally, since silicon atoms are provided from the aluminum-silicon film of the metal material film 52 during the formation of the nickel silicide film 33, the consumption of silicon carbide in the semiconductor substrate 30 can be reduced, and the ion implantation depth of the p-type region 13 constituting the JBS structure can be set shallower.

[0241] The structure of the silicon carbide semiconductor device in Embodiment 2, except that it has a nickel silicide film 33 with less residual carbon deposited from the semiconductor substrate 30 compared to Embodiment 1, or with no residual carbon deposited from the semiconductor substrate 30, is similar to that of the silicon carbide semiconductor device 40 in Embodiment 1 (see [reference]). Figures 1-3 )same.

[0242] As described above, according to Embodiment 2, the same effects as in Embodiment 1 can be obtained. Furthermore, according to Embodiment 2, the heat treatment temperature for the first sintering used to form the nickel silicide film as an ohmic electrode can be increased, and an ohmic junction with lower resistance can be formed. Furthermore, according to Embodiment 2, the contact resistance between the nickel silicide film as an ohmic electrode and the semiconductor substrate can be reduced. Furthermore, according to Embodiment 2, the peeling of the front electrode from the boundary between the ohmic electrode and the semiconductor substrate can be suppressed.

[0243] (Implementation Method 3)

[0244] Next, the structure of the silicon carbide semiconductor device of Embodiment 3 will be described. Figure 20 and Figure 21 This is a top view showing an example of the layout of the silicon carbide semiconductor device of Embodiment 3 as viewed from the front side of the semiconductor substrate.

[0245] The layout of the silicon carbide semiconductor devices 70 and 70' in Embodiment 3, as observed from the front side of the semiconductor substrate (semiconductor chip) 30, showing the p-type regions 72 and 74 constituting the JBS structure, is similar to that of the silicon carbide semiconductor device 40 in Embodiment 1 (see reference). Figures 1-3The difference is that in Embodiment 3, the first nickel silicide film and the second nickel silicide film (not shown: equivalent to) are configured in the same manner as in Embodiment 1, respectively, to ohmally bonded to the p-type regions 72, 74 and FLR21. Figure 3 Symbols 33a and 33b) are used as the front electrode (not shown: equivalent to Figure 3 The lowest layer of the symbol 14).

[0246] Therefore, although the illustration is omitted, the layout of the first nickel silicide film that forms an ohmic bond with the p-type regions 72 and 74 is the same as that of the p-type regions 72 and 74. In Embodiment 3, the p-type regions 72 and 74 are located at the front electrode and the lead (not shown: equivalent to...). Figure 2 The junction area between the junction and the first nickel silicide film is largest directly below the junction of the symbol 42), and the junction area between the junction and the first nickel silicide film becomes smaller as the junction is positioned further away from the junction of the front electrode and the lead.

[0247] Specifically, in Figure 20 In the silicon carbide semiconductor device 70 of Embodiment 3 shown, for example, a p-type region 71 is arranged in a generally rectangular planar shape directly below the junction of the front electrode and the lead (the center of the active region 10). Multiple p-type regions 72 constituting the JBS structure are arranged in a generally rectangular planar shape surrounding the p-type regions 71, and are arranged in concentric circles with reference to the center of the active region 10. All p-type regions 72 are electrically connected by p-type regions 73 that extend in a generally linear manner from the p-type regions 71 to the FLR 21 in a direction parallel to the front side of the semiconductor substrate 30.

[0248] On the front side of the semiconductor substrate 30, there is a titanium film (not shown: equivalent to) on the front electrode. Figure 3 Between the symbols 31), a first nickel silicide film (not shown: equivalent to) is arranged in the same planar shape and layout as in Embodiment 1, and is ohmically bonded to the p-type regions 71-73. Figure 3 (Symbol 33a). The ohmic junction area between the first nickel silicide film and each p-type region 71-73 is approximately the same as the surface area of ​​the p-type regions 71-73. The n-type junction area between p-type regions 71-73... - The drift region 12 forms a Schottky junction with the titanium film of the front electrode in the same manner as in Embodiment 1.

[0249] exist Figure 21 In the silicon carbide semiconductor device 70' of Embodiment 3 shown, n - The drift region 12 is located in the active region 10 and is exposed on the front side of the semiconductor substrate 30 in a generally rectangular shape, for example, separated from each other. - The portion of the type drift region 12 exposed on the front side of the semiconductor substrate 30 (hereinafter referred to as n) -The exposed portion of the drift region 12 is not positioned directly below the junction of the bonding pad and the lead. - The exposed portion of the drift region 12 becomes more densely packed the further away from the junction of the bonding pad and the lead. - The exposed portion of the drift region 12, similar to that in Embodiment 1, forms a Schottky junction with the titanium film of the front electrode.

[0250] The p-type region 74 that constitutes the JBS structure surrounds n - The exposed portion of the p-type drift region 12 is arranged around the entire front side of the semiconductor substrate 30 in the active region 10. The outer periphery of the p-type region 74 can contact the FLR 21. A titanium film (not shown: equivalent to) is present on the front side of the semiconductor substrate 30 along with the front electrode. Figure 3 Between the symbols 31), a first nickel silicide film (not shown: equivalent to) that is ohmically bonded to the p-type region 74 is arranged in the same planar shape and layout as in Embodiment 1. Figure 3 (symbol 33a). The area of ​​the ohmic junction between the first nickel silicide film and the p-type region 74 is approximately the same as the surface area of ​​the p-type region 74.

[0251] The manufacturing method of the silicon carbide semiconductor device 70, 70' in Embodiment 3 and the manufacturing method of the silicon carbide semiconductor device 40 in Embodiment 1 (see reference) Figures 4 to 18 The manufacturing method of the silicon carbide semiconductor devices 70 and 70' in Embodiment 3 is the same as that in Embodiment 2, except that the layout of the p-type regions 72 and 74 constituting the JBS structure can be changed.

[0252] As described above, according to Embodiment 3, the same effects as in Embodiment 1 can be achieved. Furthermore, generally, the current density is highest directly below the junction of the bonding pad and the lead, tending to generate more heat. According to Embodiment 3, since a first nickel silicide film (ohmic electrode) is disposed directly below the junction of the bonding pad and the lead, the ohmic junction area directly below the junction of the bonding pad and the lead is increased. This increases the surge current withstand capability at the location of highest current density and improves the overall surge current withstand capability of the semiconductor chip.

[0253] Furthermore, according to Embodiment 3, the ohmic junction area decreases towards the outer periphery of the semiconductor substrate. Therefore, even by increasing the ohmic junction area directly below the junction of the bonding pad and the lead to improve surge current withstand capability, the Schottky junction area of ​​the entire semiconductor chip can be maintained, and the forward voltage of the entire semiconductor chip can be maintained. Therefore, as a silicon carbide diode with a JBS structure that mixes the Schottky junction and pn junction on the front side of the semiconductor substrate, a predetermined low forward voltage can be maintained, and surge current withstand capability can be improved.

[0254] (Example 1)

[0255] Next, the silicon carbide semiconductor device 40 of Embodiment 1 was verified (see Figure 1). Figure 3 The area of ​​the Ohm junction. Figure 22 This is a schematic cross-sectional view showing the state obtained by observing the vicinity of the ohmic junction in Example 1. Figure 22 The image shows the state obtained by observing the bottommost first nickel silicide film 33a and second nickel silicide film 33b of the front electrode 14 of Example 1 using a scanning electron microscope (SEM).

[0256] Figure 23 This is a schematic cross-sectional view showing the state obtained by observing the ohmic junction near Reference Example 1. Figure 23 The image shows the observation of the above-mentioned Reference Example 1 (conventional silicon carbide semiconductor device 170) using a scanning electron microscope. Figure 19 The state obtained is the state of the bottommost first nickel silicide film 133a and second nickel silicide film 133b of the front electrode 114. Figure 24 It is Figure 22 A cross-sectional view shown as an enlarged portion. Figure 24 The second nickel silicide film 33b of Example 1 is shown.

[0257] according to Figure 23 The results shown confirm that in Reference Example 1, which applies the prior art, since the second nickel silicide film 133b is formed away from the field oxide film 115, no products that would become leakage current sources are generated inside the field oxide film 115.

[0258] On the other hand, according to Figure 22 The results show that in the silicon carbide diode (hereinafter referred to as Embodiment 1) manufactured according to the manufacturing method of the silicon carbide semiconductor device 40 of Embodiment 1, the second nickel silicide film 33b of the bottommost layer of the front electrode 14 can be formed in contact with the field oxide film 15, and the second nickel silicide film 33b can be ohmically bonded to the FLR 21 in almost the entire area of ​​the connection region 20a of the edge terminal region 20.

[0259] Furthermore, it was confirmed that in Example 1, at the contact site between the second nickel silicide film 33b and the field oxide film 15, no products that would become leakage current sources were generated inside the field oxide film 15 (equivalent to...). Figure 30 , Figure 31 (symbol 134). Therefore, it was confirmed that the leakage current could be maintained to the same extent as in Reference Example 1, and the ohmic junction area was better secured than in Reference Example 1.

[0260] In addition, according to Figure 22 , Figure 24 The results confirmed that, in Example 1, the residual carbon 34 generated in the semiconductor substrate 30 through the silicide reaction between the semiconductor substrate 30 and the nickel film 54 precipitates inside the nickel silicide film 33 and is distributed in a granular manner. Furthermore, it was confirmed that even if the residual carbon 34 precipitates inside the nickel silicide film 33, as long as it does not form a layer, the decrease in the tightness of the adhesion between the nickel silicide film 33 and the semiconductor substrate 30 can be suppressed.

[0261] Next, the residual carbon 34 that was generated by the silicide reaction between the semiconductor substrate 30 and the nickel film 54 and precipitated in the nickel silicide film 33 was verified. Figure 25 , Figure 26 This is a cross-sectional view schematically showing the state of the front electrode during the formation process of Reference Example 2. Figure 25 , Figure 26 The diagram shows the contact area between the semiconductor substrate 30' made of silicon carbide and the metal material film 52', and the diagrams of the parts formed inside the semiconductor substrate 30' before the metal material film 52' are omitted.

[0262] like Figure 25 As shown, a metal material film 52' is formed by sequentially stacking a nickel film 54' and a silicon film 53' on the front side of the semiconductor substrate 30'. Then, as... Figure 26 As shown, a silicide reaction is performed between the metal material film 52' and the semiconductor substrate 30' to form a nickel silicide film 33' that is ohmically bonded to the p-type region (not shown) constituting the JBS structure.

[0263] Using the method described above, two silicon carbide diodes (hereinafter referred to as Reference Example 2) were fabricated using metal material films 52' with different silicon concentrations of silicon film 53'. The structure of Reference Example 2 is the same as that of Reference Example 1, except for the layered structure of the front electrode. The states obtained by observing the front electrodes of the two Reference Examples 2 using a scanning electron microscope are shown below. Figure 27 , Figure 28 . Figure 27 , Figure 28 This is a cross-sectional view schematically showing the state obtained by observing the structure of the front electrode of Reference Example 2. Symbols 31' and 35' represent titanium and nickel films sequentially stacked on the nickel silicide film 33' after the formation of the nickel silicide film 33'.

[0264] In Reference Example 2, a nickel silicide film 33' formed by making the silicon concentration of the silicon film 53' of the metal material film 52' less than 1 wt% is shown. Figure 27A nickel silicide film 33' formed by making the silicon concentration of the silicon film 53' of the metal material film 52' within a preferred range of 1 wt% of the silicon concentration of the aluminum-silicon film of the metal material film 52 used in the manufacturing method of the silicon carbide semiconductor device of Embodiment 2 described above is shown. Figure 28 .

[0265] like Figure 27 As shown, it was confirmed that when the silicon concentration of the silicon film 53' of the metal material film 52' is less than 1 wt%, the semiconductor substrate 30' undergoes a silicide reaction with the nickel film 54', and the remaining carbon 34a' (shaded area) in the semiconductor substrate 30' precipitates in a layered manner in the nickel silicide film 33'. This layered remaining carbon 34a' causes a decrease in the tightness of the adhesion between the nickel silicide film 33' and the semiconductor substrate 30'.

[0266] On the other hand, such as Figure 28 As shown, it was confirmed that by setting the silicon concentration of the silicon film 53' of the metal material film 52' to 1 wt%, the remaining carbon 34b' (shaded area) in the semiconductor substrate 30' precipitates in the nickel silicide film 33' in a granular form and does not become layered. Therefore, it was confirmed that by optimizing the silicon concentration of the silicon film 53' of the metal material film 52', a nickel silicide film 33' without remaining carbon 34b' can be formed.

[0267] Specifically, although the illustrations are omitted, the inventors confirm that as long as the silicon concentration of the aluminum-silicon film of the metal material film 52 used in the manufacturing method of the silicon carbide semiconductor device in Embodiment 2 is within the preferred range, it is possible to achieve the desired result. Figure 28 The configuration shown is either in which the remaining carbon 34b' within the nickel silicide film 33' is distributed in a granular form, or in which no remaining carbon is deposited within the nickel silicide film 33'.

[0268] (Example 2)

[0269] Next, the surge current withstand capability (IFSM) of the silicon carbide semiconductor device 40 of Embodiment 1 was verified. Figure 29 This is a characteristic graph showing the relationship between the ohmic junction area and surge current withstand capability in Example 2. Figure 29 The horizontal axis represents the area of ​​the second nickel silicide film 33b (hereinafter referred to as the ohmic electrode area). Figure 29 The larger the horizontal axis, i.e. the ohmic electrode area, means that the width w2b of the second nickel silicide film 33b is wider. Figure 29 The vertical axis represents surge current withstand capability.

[0270] According to the manufacturing method of the silicon carbide semiconductor device 40 in Embodiment 1 described above, multiple silicon carbide diodes (hereinafter referred to as Embodiment 2) were fabricated by making various modifications to the width w2b of the second nickel silicide film 33b. The surge current withstand capability of these multiple Embodiment 2 was measured. The relationship between the ohmic junction area and the surge current withstand capability of Embodiment 2 is shown below. Figure 29 .

[0271] according to Figure 29 The results show that the larger the ohmic electrode area, the greater the surge current withstand capability. Since the surge current withstand capability can be increased by increasing the ohmic junction area regardless of the layout of the p-type region 13 constituting the JBS structure, it can be seen that the same results as in Example 2 can be obtained in Embodiments 2 and 3.

[0272] The present invention is not limited to the embodiments described above. Various modifications can be made without departing from the spirit of the present invention, and it can be applied to silicon carbide semiconductor devices having ohmic electrodes that are ohmically bonded to p-type regions arranged in a predetermined pattern.

[0273] Specifically, for example, the present invention addresses the use of p-type regions (or p-type regions disposed between the p-type region and the main surface of the semiconductor substrate) to reduce p-type regions. + Silicon carbide semiconductor devices with a structure that provides contact resistance between the p-type contact region and the ohmic electrode, and silicon carbide semiconductor devices with a structure in which the ohmic electrode and the oxide film are in contact, are useful.

[0274] Furthermore, in a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field effect transistor with an insulated gate composed of a metal-oxide-semiconductor three-layer structure) that integrates the SBD into the same semiconductor substrate, the present invention can be applied to the structure on the front side of the semiconductor substrate.

[0275] Furthermore, in the reverse-conducting IGBT (RC-IGBT), which integrates an IGBT (Insulated Gate Bipolar Transistor) and a FWD (Free Wheeling Diode) connected in reverse parallel with the IGBT on the same semiconductor chip, it can be applied to the p-type collector region formed on the back side of the semiconductor substrate. In other words, it can be applied to the entire back side of the semiconductor substrate.

[0276] Industrial availability

[0277] As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device of the present invention are useful for power semiconductor devices used in power conversion devices and / or power supply devices for various industrial machinery.

Claims

1. A method of manufacturing a silicon carbide semiconductor device, characterized by, A silicon carbide semiconductor device has a semiconductor substrate composed of silicon carbide, an active region, a termination region surrounding a periphery of the active region, an oxide film provided on a first main surface of the semiconductor substrate in the termination region, and a connection region provided between the active region and the oxide film, and a manufacturing method of the silicon carbide semiconductor device includes: a first step of forming a first conductive type region constituting a first main surface of the semiconductor substrate inside the semiconductor substrate; a second step of selectively forming a first second conductive type region in the active region in a surface region of the first conductive type region on the first main surface side of the semiconductor substrate; a third step of forming a second second conductive type region in a whole region of the connection region in a surface region of the first conductive type region on the first main surface side of the semiconductor substrate; a fourth step of forming the oxide film covering the first conductive type region, the first second conductive type region, and the second second conductive type region on the first main surface of the semiconductor substrate; a fifth step of selectively removing the oxide film to form a first opening portion exposing the first second conductive type region and a second opening portion exposing the second second conductive type region in the connection region in the oxide film; a sixth step of sequentially stacking a metal film containing aluminum and a nickel film to form a metal material film in contact with the first main surface of the semiconductor substrate in the first opening portion and the second opening portion of the oxide film; a seventh step of generating a compound layer self-aligned with the oxide film as a mask on the first main surface of the semiconductor substrate in the first opening portion and the second opening portion of the oxide film by a first heat treatment to react the metal material film with the semiconductor substrate; an eighth step of removing a remaining portion of the metal material film except for the compound layer after the seventh step; a ninth step of generating a nickel silicide in an inside of the compound layer by a second heat treatment at a higher temperature than the first heat treatment to form a nickel silicide film ohmic-joined with the semiconductor substrate after the eighth step; a tenth step of removing a portion of the oxide film in the active region to form a contact hole connecting the first opening portion and the second opening portion after the ninth step; an eleventh step of sequentially stacking a titanium film in contact with the first conductive type region to form a Schottky junction with the first conductive type region and a metal electrode film containing aluminum on the first main surface of the semiconductor substrate in the contact hole to form a first electrode; and a twelfth step of forming a second electrode on a second main surface of the semiconductor substrate.

2. The manufacturing method of a silicon carbide semiconductor device according to claim 1, wherein in the fifth step, the first opening portion and the second opening portion are formed in the oxide film by dry etching to selectively remove the oxide film.

3. The method for manufacturing a silicon carbide semiconductor device according to Claim 1, wherein the metal film is an aluminum film.

4. The manufacturing method of a silicon carbide semiconductor device according to claim 3, wherein In the seventh step, the first heat treatment is performed at a temperature of 400°C or higher and 550°C or lower.

5. The method for manufacturing a silicon carbide semiconductor device according to Claim 1, wherein The metal film is an aluminum-silicon film.

6. The method according to claim 5, wherein in the seventh step, the first heat treatment is performed at a temperature of 400°C or higher and 800°C or lower. The aluminum-silicon film has a thickness of 5 nm or more and 300 nm or less.

7. The method for manufacturing a silicon carbide semiconductor device according to Claim 5, wherein 8. The method according to claim 5, wherein in the seventh step, the first heat treatment is performed at a temperature of 400°C or higher and 800°C or lower. The aluminum-silicon film has a thickness of 5 nm or more and 300 nm or less.

8. The method according to claim 5, wherein in the seventh step, the first heat treatment is performed at a temperature of 400°C or higher and 800°C or lower. The aluminum-silicon film has a thickness of 5 nm or more and 300 nm or less.

9. The method according to claim 1, wherein in the ninth step, the second heat treatment is performed at a temperature of 900°C or higher and 1050°C or lower.

10. The method for manufacturing a silicon carbide semiconductor device according to any one of Claims 1 to 9, wherein The tenth step includes: a step of forming a resist mask that covers a portion of the oxide film on the outside of the second opening portion of the oxide film; and a step of removing, with the resist mask as a mask, a portion of the oxide film on the active region by wet etching.

11. A silicon carbide semiconductor device, characterized by comprising: provided with: an active region provided in a semiconductor substrate composed of silicon carbide; a terminal region provided in the semiconductor substrate and surrounding a periphery of the active region; an oxide film provided on a first main surface of the semiconductor substrate in the terminal region; a connection region provided between the active region and the oxide film; a first conductive type region provided inside the semiconductor substrate and exposed on the first main surface of the semiconductor substrate; a first second conductive type region selectively provided between the first main surface of the semiconductor substrate and the first conductive type region in the active region in contact with the first conductive type region; a second second conductive type region provided between the first main surface of the semiconductor substrate and the first conductive type region in an entire region of the connection region in contact with the first conductive type region; a first silicide film in ohmic junction with the first second conductive type region; a second silicide film in ohmic junction with the second second conductive type region in contact with an inner end of the oxide film; a first electrode in which a titanium film in Schottky junction with the first conductive type region and a metal electrode film containing aluminum are sequentially stacked on the first main surface of the semiconductor substrate in contact with the first silicide film and the second silicide film and connecting the first silicide film and the second silicide film; and a second electrode provided on a second main surface of the semiconductor substrate, the second silicide film contains nickel, silicon, and aluminum.

12. The silicon carbide semiconductor device according to claim 11, wherein the first silicide film contains nickel, silicon, and aluminum.

13. The silicon carbide semiconductor device according to claim 12, wherein the first silicide film contains carbon.

14. The silicon carbide semiconductor device according to claim 11, wherein the second silicide film contains carbon. ​

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