Semiconductor device including data storage pattern

Abstract

A semiconductor device including a data storage pattern is provided. The semiconductor device includes a lower structure, a stack structure including a gate layer and an interlayer insulating layer and having an opening, a vertical structure located in the opening, a contact structure located on the vertical structure, and a conductive line located on the contact structure. The vertical structure includes an insulating core region, a channel semiconductor layer covering side surfaces and a lower surface of the insulating core region, a data storage pattern located between the channel semiconductor layer and the gate layer and spaced apart from each other, a first dielectric layer, and a second dielectric layer. At least a portion of the first dielectric layer is located between the data storage pattern and the gate layer, at least a portion of the second dielectric layer is located between the data storage pattern and the channel semiconductor layer, and the insulating core region includes a first protrusion having an increased width in a region facing the gate layer.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2019-0110621, filed on September 6, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to semiconductor devices, and more specifically, to semiconductor devices including data storage patterns and methods for forming semiconductor devices. Background Technology

[0004] To enhance product price competitiveness, the demand for increasing the integration level of semiconductor devices is growing. To further improve the integration level of semiconductor devices, a semiconductor device with a three-dimensional array of memory cells instead of a two-dimensional array has been proposed. Summary of the Invention

[0005] One aspect of the present invention is to provide a semiconductor device that can improve integration.

[0006] One aspect of the present invention provides a method for forming a semiconductor device that can improve integration.

[0007] According to one aspect of the present invention, a semiconductor device includes: a lower structure; a stacked structure located on the lower structure and having an opening; a vertical structure located in the opening; a contact structure located on the vertical structure; and a conductive line located on the contact structure, wherein the stacked structure includes a plurality of gate layers and a plurality of interlayer insulating layers, wherein the vertical structure includes an insulating core region, a channel semiconductor layer, a plurality of data storage patterns, a first dielectric layer and a second dielectric layer, wherein the insulating core region extends in a vertical direction perpendicular to the upper surface of the lower structure, wherein the channel semiconductor layer covers the side surface and the lower surface of the insulating core region, wherein the plurality of data storage patterns are located between the channel semiconductor layer and the plurality of gate layers and are spaced apart from each other in the vertical direction, wherein at least a portion of the first dielectric layer is disposed between the plurality of data storage patterns and the plurality of gate layers, wherein at least a portion of the second dielectric layer is disposed between the plurality of data storage patterns and the channel semiconductor layer, and wherein the insulating core region includes a plurality of first protrusions having an increasing width in the region facing the plurality of gate layers.

[0008] According to an aspect of the inventive concept, a semiconductor device includes: a lower structure; a stack structure including an interlayer insulating layer and a gate layer sequentially stacked on the lower structure; and a vertical structure passing through the stack structure, wherein the vertical structure includes: an insulating core region passing through the interlayer insulating layer and the gate layer; a channel semiconductor layer covering at least a side surface of the insulating core region; a data storage pattern between the channel semiconductor layer and the gate layer; a first dielectric layer between at least the data storage pattern and the gate layer; and a second dielectric layer between at least the data storage pattern and the channel semiconductor layer, wherein the data storage pattern has a first side surface facing the gate layer and a second side surface facing the channel semiconductor layer, and wherein the second side surface of the data storage pattern has a recess.

[0009] According to an aspect of the inventive concept, a semiconductor device includes: a lower structure; a stack structure including an interlayer insulating layer and a gate layer sequentially stacked on the lower structure; and a vertical structure passing through the stack structure, wherein the vertical structure includes: an insulating core region passing through the interlayer insulating layer and the gate layer; a channel semiconductor layer covering at least a side surface of the insulating core region; a data storage pattern between the channel semiconductor layer and the gate layer; a first dielectric layer between at least the data storage pattern and the gate layer; and a second dielectric layer between at least the data storage pattern and the channel semiconductor layer, and wherein the insulating core region has at least two inflection points in a region facing the gate layer. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above and other aspects, features, and advantages of the inventive concept will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a plan view showing a portion of a semiconductor device according to an example embodiment of the inventive concept.

[0012] Figure 2 is a cross-sectional view showing an example of a semiconductor device according to an example embodiment of the inventive concept.

[0013] Figure 3 is a plan view showing a portion of a semiconductor device according to an example embodiment of the inventive concept. Figure 2 is a partial enlarged view of portion 'A' of

[0014] Figure 4 is a plan view showing a portion of a semiconductor device according to an example embodiment of the inventive concept.Figure 2 is a partial enlarged view of a portion "B" of FIG. 1.

[0015] Figure 5 is a partial enlarged view showing a modified example of a semiconductor device according to an example embodiment of the present inventive concept.

[0016] Figure 6 is a partial enlarged view showing a modified example of a semiconductor device according to an example embodiment of the present inventive concept.

[0017] Figure 7 is a partial enlarged view showing a modified example of a semiconductor device according to an example embodiment of the present inventive concept.

[0018] Figure 8A is a cross-sectional view showing a modified example of a semiconductor device according to an example embodiment of the present inventive concept.

[0019] Figure 8B is a partial enlarged view of a portion "A1" of FIG. 1. Figure 8A

[0020] Figure 9 is a partial enlarged view showing a modified example of a semiconductor device according to an example embodiment of the present inventive concept.

[0021] Figure 10 is a cross-sectional view showing a modified example of a semiconductor device according to an example embodiment of the present inventive concept.

[0022] Figure 11 is a cross-sectional view showing a modified example of a semiconductor device according to an example embodiment of the present inventive concept.

[0023] Figure 12 is a cross-sectional view showing a modified example of a semiconductor device according to an example embodiment of the present inventive concept.

[0024] Figures 13A-13F is a cross-sectional view showing an example of a method of forming a semiconductor device according to an example embodiment of the present inventive concept.

[0025] Figures 14A-14C is a cross-sectional view showing another example of a method of forming a semiconductor device according to an example embodiment of the present inventive concept. DETAILED DESCRIPTION

[0026] Hereinafter, example embodiments of the present inventive concept will be described with reference to the accompanying drawings. In the drawings, like reference numerals always denote like elements.

[0027] Figure 1 is a plan view showing a portion of a semiconductor device according to an example embodiment of the present inventive concept, Figure 2 is a cross-sectional view taken along​Figure 1 a cross-sectional view of a region taken by a cross line I-I' to show an example of a semiconductor device according to an example embodiment of the present inventive concept, Figure 3 is a partial enlarged view of a portion 'A' of Figure 2 Figure 4 is a partial enlarged view of a portion 'B' of Figure 2

[0028] Referring to Figures 1-4 , a stack structure 68 can be disposed on the lower structure 3. In an example, the lower structure 3 can include a semiconductor substrate. The stack structure 68 can include a plurality of interlayer insulating layers 22 and a plurality of gate layers 65 alternately stacked.

[0029] A horizontal connection structure 62 can be disposed between the lower structure 3 and the stack structure 68. The horizontal connection structure 62 can include a lower horizontal connection pattern 59 and an upper horizontal connection pattern 17 on the lower horizontal connection pattern 59. The lower horizontal connection pattern 59 and the upper horizontal connection pattern 17 can be formed of polysilicon having N-type conductivity.

[0030] An opening 30 can be disposed through the stack structure 68. A vertical structure 50 can be disposed in the opening 30. The vertical structure 50 can pass through the stack structure 68, can extend in a downward direction (e.g., toward the upper surface 3s of the lower structure 3), can pass through the horizontal connection structure 62, and can extend into the lower structure 3. When viewed in a top view, the vertical structure 50 can have a circular shape, an elliptical shape, an oval shape, or the like.

[0031] A first upper insulating layer 53 and a second upper insulating layer 75 can be disposed sequentially stacked on the stack structure 68 and the vertical structure 50. For example, the first upper insulating layer 53 can be formed on an upper surface of an uppermost interlayer insulating layer 22U among the interlayer insulating layers 22, and the second upper insulating layer 75 can be formed on an upper surface of the first upper insulating layer 53.

[0032] A separation structure 72 can be disposed through the first upper insulating layer 53 and the stack structure 68. Each separation structure 72 can include a separation spacer 72a and a separation pattern 72b. The separation spacer 72a can be disposed on a side surface of the separation pattern 72b to be in contact with the side surface of the separation pattern 72b. In an example, the separation spacer 72a can be formed of an insulating material, and the separation pattern 72b can be formed of a conductive material. In another example, the separation structure 72 can be formed of an insulating material. For example, the separation structure 72 can be formed of silicon oxide.

[0033] ​​The separation structure 72 can pass through the first upper insulating layer 53, can extend in a downward direction (e.g., toward the upper surface 3s of the lower structure 3), and can pass through the horizontal connection structure 62. The separation structure 72 can separate the stacked structure 68 in a first horizontal direction X. The separation structure 72 can have a linear shape extending in a second horizontal direction Y perpendicular to the first horizontal direction X. The first horizontal direction X and the second horizontal direction Y can be parallel to the upper surface 3s of the lower structure 3.

[0034] The conductive line 81 can be disposed on the second upper insulating layer 75. The contact plug 78 can be disposed between the conductive line 81 and the vertical structure 50.

[0035] The stacked structure 68 can include the interlayer insulating layer 22 and the gate layer 65 alternately and repeatedly stacked.

[0036] In an example, each of the plurality of gate layers 65 can include a first layer 66a and a second layer 66b. The first layer 66a can extend between the second layer 66b and the vertical structure 50 while covering a lower surface and an upper surface of the second layer 66b.

[0037] In an example, the second layer 66b can include a conductive material (e.g., doped polysilicon, TiN, TaN, WN, TiSi, TaSi, CoSi, WSi, Ti, Ta, W, etc.), and the first layer 66a can include a dielectric material. The dielectric material of the first layer 66a can be a high-k dielectric such as AlO or the like. In another example, the first layer 66a can be replaced by a conductive material (e.g., TiN, WN, etc.) different from the conductive material of the second layer 66b.

[0038] The plurality of gate layers 65 can include one or more lower gate layers 65L, a plurality of middle gate layers 65M on the one or more lower gate layers 65L, and one or more upper gate layers 65U on the plurality of middle gate layers 65M.

[0039] At least one of the one or more lower gate layers 65L can include a ground select gate electrode, and at least one of the one or more upper gate layers 65U can include a string select gate electrode. The plurality of middle gate layers 65M can include a word line. For example, the second layer 66b of the plurality of middle gate layers 65M can be a word line.

[0040] The interlayer insulating layers 22 can include a lowermost interlayer insulating layer 22L, an uppermost interlayer insulating layer 22U, and intermediate interlayer insulating layers 22M between the lowermost interlayer insulating layer 22L and the uppermost interlayer insulating layer 22U. Among the interlayer insulating layers 22, the thickness of the uppermost interlayer insulating layer 22U can be greater than the thickness of each of the remaining interlayer insulating layers 22. The interlayer insulating layers 22 can be formed of silicon oxide.

[0041] An insulating pattern 27 can be provided extending in a downward direction (e.g., toward the upper surface 3s of the lower structure 3) from the upper surface of the stacked structure 68 and through one or more of the upper gate layers 65U. The insulating pattern 27 can be formed of silicon oxide. The vertical structures 50 can be spaced apart from the insulating pattern 27. For example, the insulating pattern 27 can be provided between and space apart adjacent ones of the vertical structures 50. Dummy structures 50d can be provided contacting the insulating pattern 27 and passing through the stacked structure 68. Figure 1 ). Figure 1 The cross-sectional structure of the dummy structures 50d can be the same as that of the vertical structures 50. In some embodiments, the dummy structures 50d can be formed in the same process as the vertical structures 50 and can include the same materials as the vertical structures 50; however, the dummy structures 50d can not be operatively effective.

[0042] The enhancement patterns 36 can be arranged adjacent to the vertical structures 50. The enhancement patterns 36 can be formed of an insulating material such as silicon oxide.

[0043] In an example, the enhancement patterns 36 can be adjacent to side surfaces of the vertical structures 50 and can be spaced apart from each other in a vertical direction Z. The vertical direction Z can be a direction perpendicular to the upper surface 3s of the lower structure 3. The enhancement patterns 36 can be provided between the interlayer insulating layers 22 and the vertical structures 50. The enhancement patterns 36 can include lower enhancement patterns 36L interposed between the lowermost interlayer insulating layer 22L and the vertical structures 50 and extending between a portion of the horizontal connection structures 62 and the vertical structures 50. For example, the lower enhancement patterns 36L can be provided between the upper horizontal connection patterns 17 and the vertical structures 50. In addition, the enhancement patterns 36 can include upper enhancement patterns 36U interposed between the uppermost interlayer insulating layer 22U and the vertical structures 50 and intermediate enhancement patterns 36M interposed between the intermediate interlayer insulating layers 22M and the vertical structures 50.

[0044] Each intermediate reinforcing pattern 36M can be in contact with a corresponding intermediate interlayer insulating layer 22M. A vertical thickness of each intermediate reinforcing pattern 36M can be greater than a vertical thickness of each intermediate interlayer insulating layer 22M. In this case, the vertical thickness refers to a thickness in a vertical direction (Z direction). Each intermediate reinforcing pattern 36M can be recessed in a central portion of the intermediate reinforcing pattern 36M facing the vertical structure 50.

[0045] A substrate insulating layer 37 can be provided between the vertical structure 50 and the lower structure 3. The substrate insulating layer 37 can be located at a vertical height lower than that of the upper surface 3s of the lower structure 3. The substrate insulating layer 37 can be formed of silicon oxide.

[0046] In an example, the vertical structure 50 can include an insulating core region 46, a channel semiconductor layer 44, a plurality of data storage patterns 40, a first dielectric layer 38, a second dielectric layer 42, and a pad pattern 48.

[0047] The insulating core region 46 can extend in a vertical direction Z. The insulating core region 46 can include an insulating material. For example, the insulating core region 46 can be filled with an insulating material such as silicon oxide, or can be formed of an insulating material having a void therein.

[0048] The pad pattern 48 can be provided on the insulating core region 46, and can contact a top surface of the insulating core region 46. The pad pattern 48 can be formed of polysilicon having N-type conductivity.

[0049] At least a portion of the channel semiconductor layer 44 can cover side surfaces and a lower surface of the insulating core region 46 to contact the side surfaces and the lower surface of the insulating core region 46. The channel semiconductor layer 44 can be in contact with the pad pattern 48. For example, the channel semiconductor layer 44 can contact side surfaces of the pad pattern 48. Thus, the channel semiconductor layer 44 can be electrically connected to the pad pattern 48. The channel semiconductor layer 44 can be formed of polysilicon.

[0050] The plurality of data storage patterns 40 can be spaced apart from each other in the vertical direction Z while being disposed between the plurality of gate layers 65 and the channel semiconductor layer 44. The plurality of data storage patterns 40 can face the plurality of gate layers 65 in a one-to-one manner.

[0051] The plurality of data storage patterns 40 can be formed of a material capable of storing data. For example, when the semiconductor device according to an example embodiment of the present inventive concept is a memory device such as a NAND flash, the plurality of data storage patterns 40 can be formed of a material capable of trapping electric charges (for example, silicon nitride).

[0052] In example embodiments of the inventive concept, the material of the plurality of data storage patterns 40 is not limited to silicon nitride, and can be replaced by another material capable of storing data.

[0053] At least a portion of the first dielectric layer 38 can be disposed between the plurality of data storage patterns 40 and the plurality of gate layers 65. The first dielectric layer 38 can extend from the portion between the plurality of data storage patterns 40 and the plurality of gate layers 65 to cover the enhancement pattern 36. For example, a portion of the first dielectric layer 38 can be disposed between the enhancement pattern 36 and the second dielectric layer 42 to contact both the enhancement pattern 36 and the second dielectric layer 42.

[0054] At least a portion of the second dielectric layer 42 can be disposed between the plurality of data storage patterns 40 and the channel semiconductor layer 44 to contact both the plurality of data storage patterns 40 and the channel semiconductor layer 44. The second dielectric layer 42 can extend from the portion between the plurality of data storage patterns 40 and the channel semiconductor layer 44 to cover the first dielectric layer 38.

[0055] Between the channel semiconductor layer 44 and the plurality of gate layers 65, the plurality of data storage patterns 40 can be disposed between the first dielectric layer 38 and the second dielectric layer 42. The first dielectric layer 38 can cover a lower surface of the channel semiconductor layer 44, and can cover an outer side surface of the channel semiconductor layer 44. The second dielectric layer 42 can be disposed between the channel semiconductor layer 44 and the first dielectric layer 38.

[0056] The horizontal connection structure 62 can include one or more horizontal connection patterns. For example, the horizontal connection structure 62 can include a lower horizontal connection pattern 59 and an upper horizontal connection pattern 17 located on the lower horizontal connection pattern 59. The lower horizontal connection pattern 59 and the upper horizontal connection pattern 17 can be formed of polysilicon. For example, the lower horizontal connection pattern 59 and the upper horizontal connection pattern 17 can be formed of polysilicon having N-type conductivity. The upper horizontal connection pattern 17 can be spaced apart from the channel semiconductor layer 44. The lower horizontal connection pattern 59 can pass through the first dielectric layer 38 and the second dielectric layer 42, and can contact the channel semiconductor layer 44. The lower horizontal connection pattern 59 can further include a first extension portion 59E1 extending between the lower structure 3 and the channel semiconductor layer 44, and a second extension portion 59E2 extending between the upper horizontal connection pattern 17 and the channel semiconductor layer 44. In some embodiments, the first extension portion 59E1 can contact an upper surface of the substrate insulating layer 37, an upper surface of the first dielectric layer 38, and an upper surface of the second dielectric layer 42, and the second extension portion 59E2 can contact a lower surface of the lower enhancement pattern 36L, a lower surface of the first dielectric layer 38, and a lower surface of the second dielectric layer 42.

[0057] A vertical thickness of each of the plurality of data storage patterns 40 can be less than a vertical thickness of each of the plurality of gate layers 65.

[0058] Each of the plurality of data storage patterns 40 can have a lower surface 40L and an upper surface 40U. In each of the plurality of data storage patterns 40, at least one of the lower surface 40L and the upper surface 40U can have a concave shape. For example, in some embodiments, both the lower surface 40L and the upper surface 40U can have a concave shape.

[0059] Each of the plurality of data storage patterns 40 can include a first side surface 40S1 facing the plurality of gate layers 65 and a second side surface 40S2 facing the channel semiconductor layer 44. Each of the plurality of data storage patterns 40 can include a first portion 40p1 adjacent to the first side surface 40S1, a second portion 40p2 adjacent to the second side surface 40S2, and a minimum vertical thickness portion 40p3 between the first portion 40p1 and the second portion 40p2. A thickness of the minimum vertical thickness portion 40p3 can be less than a maximum vertical thickness of the first portion 40p1 and a maximum vertical thickness of the second portion 40p2.

[0060] In each of the plurality of data storage patterns 40, a distance between the minimum vertical thickness portion 40p3 and the first side surface 40S1 can be less than a distance between the minimum vertical thickness portion 40p3 and the second side surface 40S2. For example, the minimum vertical thickness portion 40p3 can be closer to the first side surface 40S1 than to the second side surface 40S2.

[0061] In each of the plurality of data storage patterns 40, the second side surface 40S2 can have a recess 40R. The second side surface 40S2 can have a curved shape above and below the recess 40R.

[0062] In an example, a distance between an upper end and a lower end of the first side surface 40S1 can be less than a distance between an upper end and a lower end of the second side surface 40S2.

[0063] The insulating core region 46 can include a plurality of first protrusions 46a1 having an increased width in a region facing the plurality of gate layers 65. The insulating core region 46 can include a plurality of second protrusions 46a2 having an increased width in a region facing the plurality of interlayer insulating layers 22, and recesses 46b1, 46b2 having a reduced width between the first protrusions 46a1 and the second protrusions 46a2. A width of each of the recesses 46b1 and 46b2 can be less than a width of each of the first protrusions 46a1 and the second protrusions 46a2.

[0064] Hereinafter, description will be made based on any one of the first protrusions 46al facing any one of the gate layers 65 for the convenience of description.

[0065] A portion of the insulating core region 46 can include any one of the first protrusions 46al, a first recess 46bl provided below the first protrusion 46al and having a width smaller than that of the first protrusion 46al, and a second recess 46b2 provided above the first protrusion 46al and having a width smaller than that of the first protrusion 46al. The portion of the insulating core region 46 can further include a second protrusion 46a2 provided below the first recess 46bl and having a width larger than that of the first recess 46bl. The portion having the smallest horizontal width in the first recess 46bl and the portion having the smallest horizontal width in the second recess 46b2 can face any one of the gate layers 65.

[0066] A distance between the portion having the smallest horizontal width in the first recess 46bl and the portion having the smallest horizontal width in the second recess 46b2 can be greater than the maximum vertical thickness of any one of the data storage patterns 40.

[0067] A distance between the portion having the smallest horizontal width in the first recess 46bl and the portion having the smallest horizontal width in the second recess 46b2 can be smaller than the vertical thickness of any one of the gate layers 65. For example, both the first recess 46bl and the second recess 46b2 can be at a vertical level higher than a lower surface of the adjacent gate layer 65 and at a vertical level lower than an upper surface of the adjacent gate layer 65.

[0068] A distance between the portion having the largest horizontal width in the second protrusion 46a2 and the portion having the smallest horizontal width in the first recess 46bl can be greater than a distance between the portion having the smallest horizontal width in the first recess 46bl and the portion having the largest horizontal width in the first protrusion 46al.

[0069] A distance between a first inflection point 46il located between a side surface of the first recess 46bl and a side surface of the first protrusion 46al and a second inflection point 46i2 located between the side surface of the first protrusion 46al and a side surface of the second recess 46b2 can be smaller than the vertical thickness of any one of the gate layers 65. The first inflection point 46il can be a point at which a concavity (or convexity) changes between the first protrusion 46al and the first recess 46bl, and the second inflection point 46i2 can be a point at which the concavity (or convexity) changes between the first protrusion 46al and the second recess 46b2.

[0070] A distance between a first inflection point 46i1 and a second inflection point 46i2 can be smaller than a maximum vertical thickness of any one data storage pattern 40, the first inflection point 46i1 being located between a side surface of the first recessed portion 46b1 and a side surface of the first protruded portion 46a1, the second inflection point 46i2 being located between the side surface of the first protruded portion 46a1 and a side surface of the second recessed portion 46b2.

[0071] The insulating core region 46 can further include a lower protruded portion 46c Figure 4 facing the lower horizontal connection pattern 59, a first lower recessed portion 46d1 Figure 4 disposed below the lower protruded portion 46c and having a width smaller than a width of the lower protruded portion 46c, and a second lower recessed portion 46d2 Figure 4 disposed above the lower protruded portion 46c and having a width smaller than the width of the lower protruded portion 46c.

[0072] In an example, the data storage patterns 40 can be spaced apart from each other in the vertical direction Z. Therefore, interference between the data storage patterns 40 adjacent to each other in the vertical direction Z can be prevented, and a phenomenon in which charges trapped in the data storage patterns 40 move to a region outside the data storage patterns 40 due to an operation of a NAND flash memory device can be prevented. Accordingly, in a semiconductor device such as a NAND flash memory device, a data retention characteristic can be improved.

[0073] Next, modification examples of the plurality of data storage patterns 40 will be described with reference to Figure 5 and Figure 6 respectively. Figure 5 and Figure 6 are partial enlarged sectional views corresponding to the partial enlarged sectional views of Figure 3 for describing modification examples of the plurality of data storage patterns 40. In this case, any one of the plurality of data storage patterns 40 will be mainly described.

[0074] In a modification example, with reference to Figure 5 at least a portion of the plurality of data storage patterns 40 can further include a void 40v located between the first side surface 40S1 and the second side surface 40S2. A distance between the void 40v and the first side surface 40S1 can be greater than a distance between the void 40v and the second side surface 40S2. For example, the void 40v can be closer to the second side surface 40S2 than the first side surface 40S1. In some embodiments, the void 40v can include air. The term “air” discussed herein can refer to atmospheric air or other gases that can be present during the manufacturing process.

[0075] In a modification example, with reference to Figure 6Any data storage pattern 40' may have a recessed upper surface 40U' and a recessed lower surface 40L' in a similar manner to those described above. The data storage pattern 40' may have a first side surface 40S1' facing any gate layer 65 and a second side surface 40S2' facing the channel semiconductor layer 44.

[0076] In the example, the distance between the upper and lower ends of the first side surface 40S1' can be greater than the distance between the upper and lower ends of the second side surface 40S2'.

[0077] The data storage pattern 40' may include: a first portion 40p1' adjacent to the first side surface 40S1', a second portion 40p2' adjacent to the second side surface 40S2', and a minimum vertical thickness portion 40p3' located between the first portion 40p1' and the second portion 40p2'. The thickness of the minimum vertical thickness portion 40p3' may be less than the maximum vertical thickness of the first portion 40p1' and the maximum vertical thickness of the second portion 40p2'.

[0078] The distance between the minimum vertical thickness portion 40p3' and the first side surface 40S1' can be greater than the distance between the minimum vertical thickness portion 40p3' and the second side surface 40S2'. For example, the minimum vertical thickness portion 40p3' can be closer to the second side surface 40S2' than the first side surface 40S1'.

[0079] The data storage pattern 40' may also include a gap 40v' located between the first side surface 40S1' and the second side surface 40S2'. The distance between the gap 40v' and the first side surface 40S1' may be smaller than the distance between the gap 40v' and the second side surface 40S2'. For example, the gap 40v' may be closer to the first side surface 40S1' than the second side surface 40S2'.

[0080] Next, we will refer to Figure 7 Here is a modified example to describe the above-mentioned insulating core region 46. Figure 7 Is with Figure 4 The partial enlarged cross-sectional view corresponding to the above-mentioned modified example of the insulating core region 46 is shown.

[0081] In the modified example, refer to Figure 7 The portion of the insulating core region 46' facing the horizontal connection structure 62 can have a substantially constant width. Therefore, the channel semiconductor layer 44' located between the horizontal connection structure 62 and the side surface of the insulating core region 46' can have a linear shape. In such an embodiment, the side surface of the lower horizontal connection pattern 59 adjacent to and in contact with the channel semiconductor layer 44' can be linear and substantially perpendicular to the upper surface 3s of the lower structure 3.

[0082] Next, we will refer to Figure 8A and Figure 8B To describe a modified example of a semiconductor device according to an exemplary embodiment of the present invention. Figure 8A This is a cross-sectional view illustrating a modified example of a semiconductor device according to an exemplary embodiment of the present invention. Figure 8B It is shown Figure 8A A magnified view of part 'A1'. (Refer to...) Figure 8A and Figure 8B When describing modified examples of semiconductor devices according to exemplary embodiments of the present invention, the description will primarily refer to... Figures 1-4 The modified components in the description can be omitted or the unmodified components can be directly referenced.

[0083] In the modified example, refer to Figure 8A and Figure 8B The vertical structure 50a can sequentially pass through the aforementioned stacked structure 68 and horizontal connecting structure 62, and can extend into the lower structure 3. The vertical structure 50a can be aligned with a reference... Figures 2-4 The substantially similar configuration includes a first dielectric layer 38, a data storage pattern 40, a second dielectric layer 42, a channel semiconductor layer 44, and a pad pattern 48. The vertical structure 50a may include a shape different from... Figures 2-4 The insulating core region 146 has a shape similar to the insulating core region 46. For example, the insulating core region 146 of the vertical structure 50a may have a protrusion 146a in the region facing the data storage pattern 40, and may not have a protrusion in the region facing the interlayer insulation layer 22. The insulating core region 146 may have a substantially constant width in the region facing the interlayer insulation layer 22. For example, the side surface of the insulating core region 146 adjacent to the interlayer insulation layer 22 may be linear and substantially perpendicular to the upper surface 3s of the lower structure 3.

[0084] One of the protrusions 146a in the insulating core region 146 may be formed between the first portion 146b1 and the second portion 146b2. The vertical thickness of the protrusion 146a (i.e., the distance between the first portion 146b1 and the second portion 146b2) may be less than the thickness of either gate layer 65. For example, the first portion 146b1 may be located at a vertical height higher than the lower surface of the adjacent gate layer 65, and the second portion 146b2 may be located at a vertical height lower than the upper surface of the adjacent gate layer 65.

[0085] The data storage pattern 40 may overlap with the interlayer insulating layer 22 in the vertical direction. (See reference...) Figures 2-4 The described enhancement pattern (e.g., Figures 2-4The enhanced pattern 36) can be modified to be formed on a surface of the interlayer insulating layer 22 facing the data storage pattern 40. Thus, the modified enhanced pattern 136 can be formed on the upper and lower surfaces of the interlayer insulating layer 22 facing the data storage pattern 40.

[0086] Next, a modified example of the semiconductor device according to the example embodiment of the present inventive concept will be described with reference to Figure 9 Figure 8A and Figure 8B described above with reference to Figure 9 Figure 8B is a partial enlarged sectional view corresponding to a partial enlarged sectional view of Figure 8A Figure 8B described above with reference to

[0087] In the modified example, with reference to Figure 9 , the enhanced pattern 236 having a circular shape can cover the side surface of any one of the interlayer insulating layers 22, and can extend to the upper and lower surfaces of the interlayer insulating layer 22. The insulating core region 246 can include a convex portion 246a facing the gate layer 65 and a concave portion 246b facing the interlayer insulating layer 22.

[0088] Next, a modified example of the semiconductor device according to the example embodiment of the present inventive concept will be described with reference to Figure 10 Figure 10 is a sectional view showing a modified example of the semiconductor device according to the example embodiment of the present inventive concept. In this case, a modified portion in the semiconductor device according to the example embodiment described above with reference to Figures 2-4 will be mainly described.

[0089] With reference to Figure 10 , the lower structure 3 and the horizontal connection structure 62 can be provided in substantially the same manner as described with reference to Figures 2-4 Figure 2 The stack structure (e.g., the stack structure 68) of Figure 2 can be modified to a stack structure 68' including a lower stack group 68a and an upper stack group 68b located on the lower stack group 68a. The lower stack group 68a can include lower interlayer insulating layers 22a and lower gate layers 65a which are alternately and repeatedly stacked. The upper stack group 68b can include upper interlayer insulating layers 22b and upper gate layers 65b which are alternately and repeatedly stacked. The lower interlayer insulating layers 22a and the upper interlayer insulating layers 22b can be formed of the same material (e.g., silicon oxide). The lower gate layers 65a and the upper gate layers 65b can be formed of the same material and structure. For example, each of the lower gate layers 65a and the upper gate layers 65b can include a first layer 66a and a second layer 66b. The first layer 66a and the second layer 66b can be the same as described with reference to​​​​​Figures 2-4 The first layer 66a and the second layer 66b described are substantially the same.

[0090] The vertical structure 50c can be provided to sequentially pass through the stacked structure 68' and the horizontal connection structure 62, and can extend into the lower structure 3.

[0091] The vertical structure 50c can include a lower portion 50c_L and an upper portion 50c_U located on the lower portion 50c_L.

[0092] In the vertical structure 50c, a width of a lower region of the upper portion 50c_U adjacent to the lower portion 50c_L can be less than a width of an upper region of the lower portion 50c_L adjacent to the upper portion 50c_U.

[0093] The vertical structure 50c can include substantially the same components as the vertical structure 50 described above with reference to Figures 2-4 The components (e.g., the components described above with reference to Figures 2-4 the vertical structure 50) described can be substantially the same components. For example, the vertical structure 50c can include the first dielectric layer 38, the data storage pattern 40, the second dielectric layer 42, the channel semiconductor layer 44, the insulating core region 46, and the pad pattern 48 described above with reference to Figures 2-4 A first upper insulating layer 53 and a second upper insulating layer 75 can be arranged to be sequentially stacked on the stacked structure 68'. A partition structure 172 can be provided to pass through the first upper insulating layer 53, the stacked structure 68', and the horizontal connection structure 62. The partition structure 172 can include an upper portion and a lower portion, and side surfaces of the upper portion and the lower portion of the partition structure 172 can be angled with respect to the upper surface 3s of the lower structure 3. The partition structure 172 can be formed of an insulating material such as silicon oxide.

[0094] Next, a modified example of a semiconductor device according to an example embodiment will be described with reference to

[0095] Figure 11 Figure 11 is a cross-sectional view illustrating a modified example of a semiconductor device according to an example embodiment of the present inventive concept.

[0096] With reference to Figure 11 , a stacked structure 568 can be provided on a lower structure 503. The lower structure 503 can include a semiconductor substrate. The stacked structure 568 can include interlayer insulating layers 522 and gate layers 565 which are alternately and repeatedly stacked.

[0097] The interlayer insulating layers 522 can include a first lower interlayer insulating layer 522L1, a second lower interlayer insulating layer 522L2 located on the first lower interlayer insulating layer 522L1, an intermediate interlayer insulating layer 522M located on the second lower interlayer insulating layer 522L2, and an upper interlayer insulating layer 522U located on the intermediate interlayer insulating layer 522M.​​

[0098] Each of the gate layers 565 can include a first layer 566a and a second layer 566b. The first layer 566a and the second layer 566b can correspond to the first layer 66a and the second layer 66b, respectively, described with reference to FIGS. 1 to 5. Figures 2-4 The gate layers 565 can be formed of substantially the same materials as the gate layers (e.g., the gate layers 65) described with reference to FIGS. 1 to 5, and can have substantially the same structures as the gate layers (e.g., the gate layers 65) described with reference to FIGS. 1 to 5. Figures 2-4 Figures 2-4 The gate layers 565 can be formed of substantially the same materials as the gate layers (e.g., the gate layers 65) described with reference to FIGS. 1 to 5, and can have substantially the same structures as the gate layers (e.g., the gate layers 65) described with reference to FIGS. 1 to 5. Figures 2-4 Figures 2-4 The gate layers 565 can be formed of substantially the same materials as the gate layers (e.g., the gate layers 65) described with reference to FIGS. 1 to 5, and can have substantially the same structures as the gate layers (e.g., the gate layers 65) described with reference to FIGS. 1 to 5.

[0099] The gate layers 565 can include a lower gate layer 565L between the first lower interlayer insulating layer 522L1 and the second lower interlayer insulating layer 522L2, an intermediate gate layer 565M on the lower gate layer 565L, and one or more upper gate layers 565U on the intermediate gate layer 565M.

[0100] An insulating pattern 527 extending in a downward direction (e.g., toward an upper surface of the lower structure 503) through the upper interlayer insulating layer 522U and the one or more upper gate layers 565U can be provided.

[0101] An opening 530 through the stack structure 568 and exposing the lower structure 503 can be provided. The vertical structure 550 can be provided in the opening 530. The vertical structure 550 can pass through the stack structure 568, and can extend into the lower structure 503.

[0102] The vertical structure 550 can include a lower semiconductor pattern 531, an insulating core region 546, a pad pattern 548, a channel semiconductor layer 544, a first dielectric layer 538, a second dielectric layer 542, and a data storage pattern 540.

[0103] The lower semiconductor pattern 531 can be in contact with the lower structure 503. The lower semiconductor pattern 531 can face the lower gate layer 565L, and can be provided at a lower level than the intermediate gate layer 565M. The insulating core region 546 can partially fill the opening 530 on the lower semiconductor pattern 531. The pad pattern 548 can be provided on the insulating core region 546. The channel semiconductor layer 544 can cover a lower surface and a side surface of the insulating core region 546, and can be connected to the pad pattern 548. The channel semiconductor layer 544 can be connected to the lower semiconductor pattern 531.

[0104] ​​The first dielectric layer 538 can be disposed between the channel semiconductor layer 544 and the stack structure 568 on the lower semiconductor pattern 531. The second dielectric layer 542 can be disposed between the channel semiconductor layer 544 and the first dielectric layer 538 on the lower semiconductor pattern 531. The data storage pattern 540 can face the middle gate layer 565M and the upper gate layer 565U on the lower semiconductor pattern 531, and can be disposed between the first dielectric layer 538 and the second dielectric layer 542.

[0105] The cross-sectional structure of the vertical structure 550 adjacent to the middle gate layer 565M and the upper gate layer 565U and the middle interlayer insulating layer 522M and the upper interlayer insulating layer 522U can be substantially the same as the cross-sectional structure of the vertical structure 50 adjacent to the gate layer 65 of, for example, Figure 2 Figure 2 the middle interlayer insulating layer 22M and the upper interlayer insulating layer 22U of, for example, Figure 2 Figure 2 Therefore, the cross-sectional structure of the vertical structure 550 can be substantially the same as the cross-sectional structure of the vertical structure 50 described with reference to FIGS. 2A and 2B, and wherein Figure 2 Figure 3 the 'A' portion of FIG. 2A is enlarged.

[0106] A reinforcement pattern 536 can be disposed adjacent to the vertical structure 550. The reinforcement pattern 536 can be formed of an insulating material such as silicon oxide. In an example, the reinforcement pattern 536 can include a lower reinforcement pattern 536L interposed between the second lower interlayer insulating layer 522L2 and the vertical structure 550 and contacting a portion of an upper surface of the lower semiconductor pattern 531, an upper reinforcement pattern 536U interposed between the upper interlayer insulating layer 522U and the vertical structure 550, and a middle reinforcement pattern 536M interposed between the middle interlayer insulating layer 522M and the vertical structure 550.

[0107] A first upper insulating layer 553 and a second upper insulating layer 575 can be sequentially disposed on the stack structure 568. A separation structure 572 can be disposed through the first upper insulating layer 553 and the stack structure 568. Each separation structure 572 can include a separation spacer 572a and a separation pattern 572b. The separation spacer 572a can be disposed on a side surface of the separation pattern 572b. In an example, the separation spacer 572a can be formed of an insulating material, and the separation pattern 572b can be formed of a conductive material. In another example, the separation structure 572 can be formed of an insulating material.

[0108] A conductive line 581 can be disposed on the second upper insulating layer 575. A contact plug 578 can be disposed between the conductive line 581 and the vertical structure 550. ​​​

[0109] Next, we will refer to Figure 12 Here is an example of a modification to the substructure 3 described above. Figure 12 This is a cross-sectional view illustrating a modified example of a semiconductor device according to an exemplary embodiment of the present invention.

[0110] In the modified example, refer to Figure 12 The above is in Figure 2 The substructure described in the text (e.g., Figure 2 The lower structure 3) can be replaced by a lower structure 3', which includes a lower substrate 5, a peripheral circuit region 7 located on the lower substrate 5, and an upper substrate 9 located on the peripheral circuit region 7. The lower substrate 5 may be a semiconductor substrate. The peripheral circuit region 7 may include peripheral circuit wiring 7a and a peripheral insulating layer 7b covering the peripheral circuit wiring 7a. The upper substrate 9 may be a conductive substrate. For example, the upper substrate 9 may include polycrystalline silicon and / or a metallic material having N-type conductivity.

[0111] Next, we will refer to Figures 13A-13F Examples of methods for forming semiconductor devices according to exemplary embodiments of the present invention will be described. Figures 13A-13F It shows along Figure 1 A cross-sectional view of the region intercepted by the transverse line I-I', used to illustrate an example of a method for forming a semiconductor device according to an exemplary embodiment of the present invention.

[0112] Reference Figure 1 and Figure 13A A lower horizontal molding layer 15 and an upper horizontal connecting pattern 17 can be sequentially formed on the lower structure 3. The lower horizontal molding layer 15 may include a first lower horizontal molding layer 15a, a second lower horizontal molding layer 15b, and a third lower horizontal molding layer 15c that are stacked sequentially.

[0113] In the example, the first lower horizontal molding layer 15a and the third lower horizontal molding layer 15c may be formed of a first material (e.g., silicon oxide), and the second lower horizontal molding layer 15b may be formed of a second material (e.g., silicon nitride or polysilicon) that is different from the materials of the first lower horizontal molding layer 15a and the third lower horizontal molding layer 15c.

[0114] The upper horizontal connection pattern 17 can be formed of polysilicon. For example, the upper horizontal connection pattern 17 can be formed of polysilicon with N-type conductivity.

[0115] A molded structure 20 can be formed on the upper horizontal connecting pattern 17.

[0116] The molded structure 20 can include a plurality of interlayer insulating layers 22 and a plurality of sacrificial gate layers 24 which are alternately and repeatedly stacked. The plurality of interlayer insulating layers 22 can include a lowermost interlayer insulating layer 22L, a plurality of intermediate interlayer insulating layers 22M on the lowermost interlayer insulating layer 22L, and an uppermost interlayer insulating layer 22U on the plurality of intermediate interlayer insulating layers 22M. The plurality of sacrificial gate layers 24 can be formed between the lowermost interlayer insulating layer 22L and the uppermost interlayer insulating layer 22U.

[0117] The plurality of interlayer insulating layers 22 can be formed of silicon oxide, and the plurality of sacrificial gate layers 24 can be formed of a material (for example, silicon nitride) having etching selectivity with respect to the plurality of interlayer insulating layers 22.

[0118] An insulating pattern 27 can be formed through the uppermost interlayer insulating layer 22U, extending in a downward direction (for example, toward the upper surface 3s of the lower structure 3), and through one or more upper sacrificial gate layers among the plurality of sacrificial gate layers 24. The insulating pattern 27 can be formed of silicon oxide.

[0119] An opening 30 can be formed through the molded structure 20, extending in a downward direction (for example, toward the upper surface 3s of the lower structure 3), sequentially through the upper horizontal connection pattern 17 and the lower horizontal molded layer 15, and extending into the lower structure 3. The opening 30 can be formed as a plurality (for example, a plurality of openings 30). In some embodiments, each opening 30 can have a circular shape, an elliptical shape, an oval shape, or the like when viewed in a top view.

[0120] Referring to Figure 1 and Figure 13B The interlayer insulating layer 22 can be etched, and a preliminary enhancement layer 33 can be formed on a side surface of the interlayer insulating layer 22. The preliminary enhancement layer 33 can be formed of polysilicon.

[0121] When the first lower horizontal molded layer 15a and the third lower horizontal molded layer 15c, as well as the interlayer insulating layer 22, are formed of the same material, the first lower horizontal molded layer 15a and the third lower horizontal molded layer 15c can be etched together with the etching of the interlayer insulating layer 22, a first lower preliminary enhancement layer 33L1 can be formed on a side surface of the first lower horizontal molded layer 15a, and a second lower preliminary enhancement layer 33L2 can be formed on a side surface of the third lower horizontal molded layer 15c.

[0122] Referring to Figure 1 and Figure 13C The sacrificial gate layer 24 can be selectively etched to form a recessed region 34.

[0123] In an example, when the second lower horizontal mold layer 15b and the sacrificial gate layer 24 are formed of the same material (e.g., silicon nitride), the second lower horizontal mold layer 15b can be etched together with the sacrificial gate layer 24 to form the lowermost recessed region 34L.

[0124] In another example, when the second lower horizontal mold layer 15b is formed of a different material (e.g., polysilicon) from the sacrificial gate layer 24, the second lower horizontal mold layer 15b can be substantially not etched during the selective etching of the sacrificial gate layer 24.

[0125] Hereinafter, for ease of description, examples in which the second lower horizontal mold layer 15b is formed of the same material as the sacrificial gate layer 24 will be mainly described.

[0126] Referring to Figure 1 and Figure 13D , an oxidation process can be performed to form the enhancement pattern 36 and the substrate insulating layer 37. The oxidation process can be a process of oxidizing silicon to form silicon oxide.

[0127] The oxidation process can be a process of oxidizing the preliminary enhancement layer (e.g., the preliminary enhancement layer 33 of Figure 13C ), the first lower preliminary enhancement layer and the second lower preliminary enhancement layer (e.g., the first lower preliminary enhancement layer 33L1 and the second lower preliminary enhancement layer 33L2 of Figure 13C ), the upper horizontal connection pattern 17, and the lower structure 3 to form silicon oxide.

[0128] The enhancement pattern 36 can include an upper enhancement pattern 36U, an intermediate enhancement pattern 36M, and a lower enhancement pattern 36L. The upper enhancement pattern 36U can be formed by oxidizing the preliminary enhancement layer (e.g., the preliminary enhancement layer 33 of Figure 13C ) on the side surface of the uppermost interlayer insulating layer 22U. The intermediate enhancement pattern 36M can be formed by oxidizing the preliminary enhancement layer (e.g., the preliminary enhancement layer 33 of Figure 13C ) on the side surface of the intermediate interlayer insulating layer 22M. The lower enhancement pattern 36L can be formed by oxidizing the preliminary enhancement layer (e.g., the preliminary enhancement layer 33 of Figure 13C ), the upper horizontal connection pattern 17, and the second lower preliminary enhancement layer (e.g., the second lower preliminary enhancement layer 33L2 of Figure 13C ). The substrate insulating layer 37 can be formed by oxidizing the surface of the lower structure 3 exposed by the opening 30 and the first lower preliminary enhancement layer (e.g., the first lower preliminary enhancement layer 33L1 of Figure 13C ).

[0129] Accordingly, the enhancement pattern 36 and the substrate insulating layer 37 described with reference to Figures 2-4 can be formed.

[0130] In another example, enhanced pattern 36 can be replaced with Figure 8A and Figure 8B Enhanced patterns (e.g., Figure 8A and Figure 8B The enhanced pattern 136) is formed. For example, in forming such a pattern Figure 13A The opening in (e.g., Figure 13A After the opening 30), the sacrificial gate layer can be etched (e.g., Figure 13C The sacrificial gate layer 24) is recessed, and the sacrificial gate layer can be etched (e.g., Figure 13C During the sacrificial gate layer 24), the surface of the interlayer insulating layer 22 exposed is formed as follows: Figure 8A and Figure 8B Enhanced patterns in (e.g.) Figure 8A and Figure 8B The enhanced pattern 136). This can be achieved by adding a sacrificial gate layer (e.g., Figure 13C The insulating byproducts generated by etching the sacrificial gate layer 24) are used to form Figure 8A and Figure 8B Enhanced pattern 136.

[0131] In another example, this can be achieved by replacing it with an enhanced pattern (e.g., Figure 9 The reinforcing pattern 36 is formed by (reinforcing pattern 236). For example, in forming such a... Figure 13A The opening in (e.g., Figure 13A After the opening 30), the sacrificial gate layer can be etched (e.g., Figure 13C The sacrificial gate layer 24) is recessed, and a layer with a covering etched sacrificial gate layer (e.g., Figure 13C A low-step covering oxide layer on the side surface of the interlayer insulating layer 22 exposed during the sacrificial gate layer 24) to form Figure 9 The described enhancement pattern (e.g., Figure 9 Enhanced pattern 236).

[0132] Reference Figure 1 and Figure 13E A vertical structure 50 can be formed in the opening 30 where the reinforcing pattern 36 and the substrate insulating layer 37 are formed. Forming the vertical structure 50 may include: forming a first dielectric layer 38 that conformally covers the inner wall of the opening 30; forming a plurality of data storage patterns 40 in a recessed region 34 defined on the first dielectric layer 38; conformally forming a second dielectric layer 42; conformally forming a channel semiconductor layer 44; forming an insulating core region 46 on the channel semiconductor layer 44 that partially fills the opening 30; and forming a pad pattern 48 on the insulating core region 46.

[0133] Forming multiple data storage patterns 40 may include: forming a data storage layer on a first dielectric layer 38 that covers the inner wall of the opening 30 and fills the recessed region 34; and partially etching the data storage layer to retain the data storage layer in the recessed region 34.

[0134] Reference Figure 1 and Figure 13F It can be used in molded structures (e.g., Figure 13E A first upper insulating layer 53 is formed on the molded structure 20. A lower horizontal connecting pattern 59 is used instead of the lower horizontal molded layer (e.g., Figure 13E When the lower horizontal molding layer 15 is formed, the lower horizontal connection pattern 59 can be connected to the channel semiconductor layer 44. For example, a molding structure (e.g., through the first upper insulating layer 53) can be formed. Figure 13E The molded structure 20), the upper horizontal connecting pattern 17 and the third lower horizontal molding layer (e.g., Figure 13E The third lower horizontal molding layer 15c) and expose the second lower horizontal molding layer (e.g., Figure 13E The preliminary trench of the second lower horizontal molding layer 15b) can form sacrificial spacers on the sidewalls of the preliminary trench, and the second lower horizontal molding layer (e.g., Figure 13E The second lower horizontal molding layer 15b). Then, the first lower horizontal molding layer can be etched sequentially (e.g., Figure 13E The first lower horizontal molding layer 15a), the third lower horizontal molding layer (e.g., Figure 13E The third lower horizontal molding layer 15c), and the layer provided in the lower horizontal molding layer (e.g., Figure 13E The first dielectric layer 38, data storage pattern 40, and second dielectric layer 42 between the lower horizontal molding layer 15 and the channel semiconductor layer 44 can be etched to remove a portion of the reinforcement pattern 36L and a portion of the substrate insulating layer 37, filling the space between the lower structure 3 and the upper horizontal connection pattern 17, forming a lower horizontal connection pattern 59 that contacts the channel semiconductor layer 44, and removing sacrificial spacers. The initial trench can be formed as a trench 56 exposing the lower structure 3.

[0135] In the example, the lower horizontal connection pattern 59 and the upper horizontal connection pattern 17 can form a horizontal connection structure 62.

[0136] Sacrificial gate layer (e.g., Figure 13E The sacrificial gate layer 24) can be exposed through trench 56. The sacrificial gate layer (e.g., ...) exposed through trench 56 can be... Figure 13E The sacrificial gate layer 24) is replaced with gate layer 65. Forming gate layer 65 may include: removing the sacrificial gate layer exposed through trench 56 (e.g., Figure 13Ea sacrificial gate layer 24) to form a void space; forming a first layer 66a conformally covering inner walls of the void space; and forming a second layer 66b filling the void space on the first layer 66a. Thus, each gate layer 65 can include the first layer 66a and the second layer 66b. In an example, the first layer 66a can be formed of an insulating material, and the second layer 66b can be formed of a conductive material. In another example, the first layer 66a and the second layer 66b can be formed of different conductive materials.

[0137] The gate layers 65 and the interlayer insulating layers 22 can constitute a stack structure 68.

[0138] Subsequently, a separation structure 72 filling the trenches 56 can be formed. The separation structure 72 can include separation spacers 72a on sidewalls of the trenches 56 and a separation pattern 72b filling the trenches 56.

[0139] Referring back to Figures 1-4 A second upper insulating layer 75 can be formed on the separation structure 72 and the first upper insulating layer 53. A contact plug 78 can be formed through the first upper insulating layer 53 and the second upper insulating layer 75. A conductive line 81 can be formed on the contact plug 78. The conductive line 81 can be a bit line. The conductive line 81 can be electrically connected to the pad pattern 48 of the vertical structure 50 through the contact plug 78.

[0140] Next, a method of forming a semiconductor device described with reference to Figures 14A-14C will be described. Figure 11 Figures 14A-14C is a cross-sectional view illustrating a method of forming a semiconductor device described with reference to Figure 11

[0141] Referring to Figure 14A A molding structure 520 can be formed on the lower structure 503. The molding structure 520 can include interlayer insulating layers 522 and sacrificial gate layers 524 stacked alternately and repeatedly. The interlayer insulating layers 522 can be formed of silicon oxide, and the sacrificial gate layers 524 can be formed of a material (e.g., silicon nitride) having etch selectivity with respect to the interlayer insulating layers 522.

[0142] ​​The interlayer insulating layers 522 can include a first lower interlayer insulating layer 522L1, a second lower interlayer insulating layer 522L2 located on the first lower interlayer insulating layer 522L1, an intermediate interlayer insulating layer 522M located on the second lower interlayer insulating layer 522L2, and an upper interlayer insulating layer 522U located on the intermediate interlayer insulating layer 522M. The sacrificial gate layers 524 can include a lower sacrificial gate layer 524L located between the first lower interlayer insulating layer 522L1 and the second lower interlayer insulating layer 522L2, an intermediate sacrificial gate layer 524M located on the lower sacrificial gate layer 524L, and one or more upper sacrificial gate layers 524U located on the intermediate sacrificial gate layer 524M.

[0143] An insulating pattern 527 can be formed through the upper interlayer insulating layer 522U, extending in a downward direction (e.g., toward the upper surface of the lower structure 503), and through the one or more upper sacrificial gate layers 524U.

[0144] An opening 530 can be formed through the molded structure 520 and exposing the lower structure 503.

[0145] An epitaxial growth process can be performed to form a lower semiconductor pattern 531 epitaxially grown from the lower structure 503. When the lower structure 503 is formed as a silicon substrate, the lower semiconductor pattern 531 can be formed of silicon by the epitaxial growth process. An upper surface of the lower semiconductor pattern 531 can be located at a vertical height lower than a vertical height of the intermediate sacrificial gate layer 524M.

[0146] Referring to Figure 14B On the lower semiconductor pattern 531, the interlayer insulating layers 522 exposed by the opening 530 can be etched, and a preliminary enhancement layer 533 can be formed on side surfaces of the interlayer insulating layers 522. The preliminary enhancement layer 533 can be formed of polysilicon.

[0147] The preliminary enhancement layer 533 can include a preliminary enhancement layer 533 in contact with the second lower interlayer insulating layer 522L2 exposed by the opening 530 located on the lower semiconductor pattern 531, a preliminary enhancement layer 533 in contact with the upper interlayer insulating layer 522U exposed by the opening 530, and a preliminary enhancement layer 533 in contact with the intermediate interlayer insulating layer 522M exposed by the opening 530.

[0148] Referring to Figure 14C An oxidation process can be performed to oxidize surfaces of the preliminary enhancement layer 533 and the lower semiconductor pattern 531 to form an enhancement pattern 536.

[0149] The enhancement pattern 536 can include a lower enhancement pattern 536L formed by oxidizing the preliminary enhancement layer 533 and the upper surface of the lower semiconductor pattern 531 in contact with the second interlayer insulating layer 522L2, an upper enhancement pattern 536U formed by oxidizing the preliminary enhancement layer 533 in contact with the upper interlayer insulating layer 522U, and an intermediate enhancement pattern 536M formed by oxidizing the preliminary enhancement layer 533 in contact with the intermediate interlayer insulating layer 522M.

[0150] Subsequently, a first dielectric layer 538 can be conformally formed. A data storage pattern 540 can be formed on the first dielectric layer 538. The data storage pattern 540 can be formed between the enhancement patterns 536 (e.g., between the enhancement patterns 536 adjacent in the Z direction). Forming the data storage pattern 540 can include forming a data storage layer on the first dielectric layer 538, and partially etching the data storage layer to leave the data storage layer between the enhancement patterns 536.

[0151] Referring back to Figure 11 A second dielectric layer 542 can be conformally formed on the data storage pattern 540, and a lower portion of the first dielectric layer 538 and a lower portion of the second dielectric layer 542 can be etched to expose at least a portion of the upper surface of the lower semiconductor pattern 531. A channel semiconductor layer 544 can be conformally formed covering the second dielectric layer 542 and the lower semiconductor pattern 531, an insulating core region 546 partially filling the opening 530 can be formed on the channel semiconductor layer 544, and a pad pattern 548 can be formed on the insulating core region 546. Thus, a vertical structure 550 including the lower semiconductor pattern 531, the first dielectric layer 538, the data storage pattern 540, the second dielectric layer 542, the channel semiconductor layer 544, the insulating core region 546, and the pad pattern 548 can be formed in the opening 530.

[0152] A first upper insulating layer 553 can be formed on the molded structure (e.g., the molded structure 520 of Figure 14C A trench can be formed through the first upper insulating layer 553 and the molded structure (e.g., the molded structure 520 of Figure 14C A sacrificial gate layer (e.g., the sacrificial gate layer 524 of Figure 14C The sacrificial gate layer exposed by the trench can be removed to form a void space, a gate layer 565 filling the void space can be formed, and a partition structure 572 filling the trench can be formed.

[0153] A second upper insulating layer 575 can be formed on the partition structure 572 and the first upper insulating layer 553. A contact plug 578 can be formed through the first upper insulating layer 553 and the second upper insulating layer 575 and electrically connected to the pad pattern 548 of the vertical structure 550. A conductive wire 581 can be formed on the contact plug 578.

[0154] According to an embodiment of the present inventive concept, a semiconductor device capable of improving integration and a method of forming the same can be provided. The semiconductor device according to an example embodiment can include data storage patterns isolated in a vertical direction. Since the data storage patterns are isolated in the vertical direction, a retention characteristic of charges trapped in the data storage patterns can be improved.

[0155] Although example embodiments have been shown and described above, it will be obvious to those skilled in the art that modifications and changes can be made without departing from the scope of the present inventive concept defined by the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: Lower structure; A stacked structure, which is situated on the lower structure and has an opening; A vertical structure located within the opening; A contact structure located on the vertical structure; as well as A conductive wire, the conductive wire being located on the contact structure. The stacked structure includes multiple gate layers and multiple interlayer insulating layers. The vertical structure includes an insulating core region, a channel semiconductor layer, multiple data storage patterns, a first dielectric layer, and a second dielectric layer. The insulating core region extends in a vertical direction, which is perpendicular to the upper surface of the lower structure. The channel semiconductor layer covers the side and bottom surfaces of the insulating core region. The plurality of data storage patterns are located between the channel semiconductor layer and the plurality of gate layers, and are spaced apart from each other in the vertical direction. In this configuration, at least a portion of the first dielectric layer is disposed between the plurality of data storage patterns and the plurality of gate layers. At least a portion of the second dielectric layer is disposed between the plurality of data storage patterns and the channel semiconductor layer. The insulating core region includes a plurality of first protrusions with increasing width in the region facing the plurality of gate layers, and In each of the plurality of data storage patterns, at least one of the upper and lower surfaces is a concave shape.

2. The semiconductor device according to claim 1, wherein, The insulating core region further includes: a plurality of second protrusions in the region facing the plurality of interlayer insulating layers and a recess located between the plurality of first protrusions and the plurality of second protrusions, the plurality of second protrusions having an increasing width and the recess having a decreasing width.

3. The semiconductor device according to claim 1, in, Each of the plurality of data storage patterns includes a first side surface and a second side surface, the first side surface facing a corresponding gate layer among the plurality of gate layers, and the second side surface facing the channel semiconductor layer. Each of the plurality of data storage patterns includes: a first portion adjacent to the first side surface, a second portion adjacent to the second side surface, and a minimum vertical thickness portion located between the first portion and the second portion. Wherein, the vertical thickness of the minimum vertical thickness portion is less than the maximum vertical thickness of the first portion and the maximum vertical thickness of the second portion.

4. The semiconductor device according to claim 3, wherein, The distance between the minimum vertical thickness portion and the first side surface is less than the distance between the minimum vertical thickness portion and the second side surface.

5. The semiconductor device according to claim 3, wherein, The distance between the minimum vertical thickness portion and the first side surface is greater than the distance between the minimum vertical thickness portion and the second side surface.

6. The semiconductor device according to claim 1, in, Each of the plurality of data storage patterns includes a first side surface and a second side surface, the first side surface facing a corresponding gate layer among the plurality of gate layers, and the second side surface facing the channel semiconductor layer. Wherein, at least a portion of the multiple data storage patterns further includes a gap located between the first side surface and the second side surface, and The distance between the gap and the first side surface is greater than the distance between the gap and the second side surface.

7. The semiconductor device according to claim 1, in, Each of the plurality of data storage patterns includes a first side surface and a second side surface, the first side surface facing a corresponding gate layer among the plurality of gate layers, and the second side surface facing the channel semiconductor layer. Wherein, at least a portion of the multiple data storage patterns further includes a gap located between the first side surface and the second side surface, and Wherein, the distance between the gap and the first side surface is less than the distance between the gap and the second side surface.

8. The semiconductor device according to claim 1, in, Each of the plurality of data storage patterns includes a first side surface and a second side surface, the first side surface facing a corresponding gate layer among the plurality of gate layers, and the second side surface facing the channel semiconductor layer. At least a portion of the second side surface is concave.

9. The semiconductor device according to claim 1, further comprising: A horizontal connection structure is provided, located between the lower structure and the stacked structure. The horizontal connection structure includes a lower horizontal connection pattern and an upper horizontal connection pattern located on the lower horizontal connection pattern. The vertical structure passes through the stacked structure, extends downwards through the horizontal connecting structure, and extends into the lower structure. Wherein, the upper horizontal connection pattern is spaced apart from the channel semiconductor layer of the vertical structure, and The lower horizontal connection pattern is in contact with the channel semiconductor layer of the vertical structure.

10. The semiconductor device according to claim 9, wherein, The insulating core region also includes a lower protrusion facing the lower horizontal connection pattern.

11. The semiconductor device according to claim 1, wherein, The insulating core region also includes a recess with a reduced width in the region facing the interlayer insulation layer.

12. The semiconductor device according to claim 1, wherein, The insulating core region has a constant width in the region facing the interlayer insulation layer.

13. A semiconductor device, said semiconductor device comprising: Lower structure; A stacked structure comprising an interlayer insulating layer and a gate layer sequentially stacked on the lower structure; as well as A vertical structure that passes through the stacked structure. The vertical structure includes: an insulating core region extending through the interlayer insulating layer and the gate layer; a channel semiconductor layer at least covering the side surface of the insulating core region; a data storage pattern located between the channel semiconductor layer and the gate layer; a first dielectric layer at least between the data storage pattern and the gate layer; and a second dielectric layer at least between the data storage pattern and the channel semiconductor layer. The data storage pattern has a first side surface facing the gate layer and a second side surface facing the channel semiconductor layer. Wherein, the second side surface of the data storage pattern has a recess, and The second side surface of the data storage pattern has a curved shape above or below the recess.

14. The semiconductor device according to claim 13, in, The insulating core region includes: a first recess; a first protrusion, the width of which is greater than the width of the first recess and is disposed on the first recess; and a second recess, the width of which is less than the width of the first protrusion and is disposed on the first protrusion. Wherein, the first protrusion faces the data storage pattern, and The portion of the first recess with the minimum horizontal width and the portion of the second recess with the minimum horizontal width face the gate layer.

15. The semiconductor device according to claim 14, wherein, In the vertical direction, the distance between the portion of the first recess having the minimum horizontal width and the portion of the second recess having the minimum horizontal width is less than the thickness of the gate layer and greater than the maximum thickness of the data storage pattern.

16. The semiconductor device according to claim 14, in, The insulating core region further includes a second protrusion, the width of which is greater than the width of the first recess and is disposed below the first recess. The second protrusion faces the interlayer insulation layer.

17. The semiconductor device according to claim 16, wherein, The distance between the portion of the second protrusion having the maximum horizontal width and the portion of the first concave portion having the minimum horizontal width is greater than the distance between the portion of the first concave portion having the minimum horizontal width and the portion of the first protrusion having the maximum horizontal width.

18. A semiconductor device, the semiconductor device comprising: Lower structure; A stacked structure comprising an interlayer insulating layer and a gate layer sequentially stacked on the lower structure; as well as A vertical structure that passes through the stacked structure. The vertical structure includes: an insulating core region extending through the interlayer insulating layer and the gate layer; a channel semiconductor layer at least covering the side surface of the insulating core region; a data storage pattern located between the channel semiconductor layer and the gate layer; a first dielectric layer at least between the data storage pattern and the gate layer; and a second dielectric layer at least between the data storage pattern and the channel semiconductor layer. The insulating core region has at least two inflection points in the portion facing the gate layer, and Wherein, at least one of the upper and lower surfaces of the data storage pattern is concave.

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