Semiconductor device including data storage structure

Abstract

A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction; a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening and a variable resistance material on the semiconductor layer, a vacancy concentration in the variable resistance material varying along a width thereof to have a higher concentration closer to a center of the channel structure than closer to the semiconductor layer; and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.

Description

[0001] Cross-references to related applications

[0002] Korean Patent Application No. 10-2019-0110620, entitled "Semiconductor Device Including Data Storage Structure", filed with the Korean Intellectual Property Office on September 6, 2019, is incorporated herein by reference in its entirety. Technical Field

[0003] The example embodiments relate to semiconductor devices, and more specifically, to a semiconductor device including a data storage structure and a method of manufacturing the same. Background Technology

[0004] To improve the price competitiveness of electronic products, the demand for increasing the integration density of semiconductor devices has increased. To further enhance this density, semiconductor devices with three-dimensional memory cell arrangements have been proposed to replace those with two-dimensional memory cell arrangements. However, when memory cells are arranged in three dimensions, the distribution properties of the memory cells may deteriorate. Summary of the Invention

[0005] According to one aspect of an embodiment, a semiconductor device may include: a stacked structure on a substrate, the stacked structure including alternating gate electrodes and insulating layers stacked along a first direction; a vertical opening through the stacked structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening and a variable resistance material on the semiconductor layer, the vacancy concentration in the variable resistance material varying along its width to have a higher concentration closer to the center of the channel structure rather than closer to the semiconductor layer; and an impurity region on the substrate, the semiconductor layer contacting the impurity region at the bottom of the channel structure.

[0006] According to another aspect of the embodiments, a semiconductor device may include: a stacked structure on a substrate, the stacked structure including alternating gate electrodes and insulating layers stacked along a first direction; a vertical opening through the stacked structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, a variable resistance material on the semiconductor layer, and a buffer layer between the first variable resistance material and the semiconductor layer, the entire buffer layer including a material having a structure containing grains smaller than the grains of the semiconductor layer; and an impurity region on the substrate, the semiconductor layer contacting the impurity region at the bottom of the channel structure.

[0007] According to another aspect of the embodiments, a semiconductor device may include: a stacked structure on a substrate, the stacked structure including alternating gate electrodes and insulating layers stacked along a first direction; a vertical opening through the stacked structure along the first direction, the vertical opening including a channel structure having a polycrystalline silicon semiconductor layer on an inner sidewall of the vertical opening, a variable resistance material on the semiconductor layer, and an amorphous silicon buffer layer between a first variable resistance material and the semiconductor layer; and an impurity region on the substrate, the semiconductor layer contacting the impurity region at the bottom of the channel structure. Attached Figure Description

[0008] The features will become apparent to those skilled in the art from the detailed description of the exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 A plan view of a semiconductor device according to an example embodiment is shown;

[0010] Figure 2A Show along Figure 1 A cross-sectional view of line I-I' in the diagram;

[0011] Figure 2B Show Figure 2A An enlarged view of part of the letter "A" in the image;

[0012] Figure 3A and Figure 3B A graph showing the vacancy concentration in the data storage structure of a semiconductor device according to an example embodiment;

[0013] Figure 3C Showing the settings and reset states Figure 3A or Figure 3B A conceptual diagram illustrating the change in vacancy concentration in the data storage structure shown.

[0014] Figure 4A A graph showing the vacancy concentration in the data storage structure of a semiconductor device according to another example embodiment;

[0015] Figure 4B Showing the settings and reset states Figure 4A A conceptual diagram illustrating the change in vacancy concentration in the data storage structure shown.

[0016] Figure 5A An enlarged cross-sectional view showing a modified example of a portion of the data storage structure of a semiconductor device according to an example embodiment;

[0017] Figure 5B An enlarged cross-sectional view showing a portion of a modified example of the data storage structure of a semiconductor device according to another example embodiment;

[0018] Figure 6A An enlarged view of a semiconductor device according to another example embodiment is shown;

[0019] Figures 6B to 6E A graph showing the vacancy concentration in the data storage structure of a semiconductor device according to an example embodiment;

[0020] Figure 6F An enlarged view of a semiconductor device according to another example embodiment is shown;

[0021] Figure 6G An enlarged view of a semiconductor device according to another example embodiment is shown;

[0022] Figure 7A A cross-sectional view of a semiconductor device according to another example embodiment is shown;

[0023] Figure 7B and Figure 7C Show respectively Figure 7A Enlarged images of parts "B" and parts "C" in the image;

[0024] Figure 8 Showing with Figure 7A Example of modification of the semiconductor device corresponding to part of "C";

[0025] Figure 9 Showing with Figure 7A Example of modification of the semiconductor device corresponding to part "B";

[0026] Figure 10 Showing with Figure 7A Another example of a modified semiconductor device corresponding to part "B";

[0027] Figure 11A A cross-sectional view of a semiconductor device according to another example embodiment is shown;

[0028] Figure 11B A cross-sectional view of a semiconductor device according to another example embodiment is shown;

[0029] Figure 12A A cross-sectional view of a semiconductor device according to another example embodiment is shown;

[0030] Figure 12B A cross-sectional view of a semiconductor device according to another example embodiment is shown;

[0031] Figure 12C A cross-sectional view of a semiconductor device according to another example embodiment is shown;

[0032] Figure 12D A cross-sectional view of a semiconductor device according to another example embodiment is shown;

[0033] Figure 12E A cross-sectional view of a semiconductor device according to another example embodiment is shown;

[0034] Figure 13 , Figure 14A and Figure 15 Cross-sectional views are shown of each stage in a method for manufacturing a semiconductor device according to an example embodiment; and

[0035] Figure 14B and Figure 14C A schematic diagram of each stage in a method for forming a data storage structure according to an example embodiment is shown. Detailed Implementation

[0036] The following is a description of an embodiment with reference to the accompanying drawings.

[0037] In the following description, reference will be made to Figure 1 A semiconductor device is described based on an example embodiment. Figure 1 This is a plan view showing a portion of the elements of a semiconductor device according to an example embodiment.

[0038] Reference Figure 1 In the example embodiment, the semiconductor device 1 may include a stacked structure 18, a separation structure 66 penetrating the stacked structure 18, a vertical structure 33 between the separation structures 66, and wires 79. The separation structures 66 may extend in a first direction D1 and may be spaced apart from each other in a second direction D2 perpendicular to the first direction D1. The wires 79 may extend in the second direction D2 and may be spaced apart from each other in the first direction D1.

[0039] The vertical structure 33 may be disposed within the stacked structure 18, for example, the vertical structure 33 penetrates the stacked structure 18. The vertical structure 33 may include a core region 55, a data storage structure 46 surrounding the side surface of the core region 55, a channel semiconductor layer 38 surrounding the outer surface of the data storage structure 46, and a gate dielectric layer 36 surrounding the outer surface of the channel semiconductor layer 38. For example, as... Figure 1 As shown, when viewed in a top view, each of the data storage structure 46, the channel semiconductor layer 38, and the gate dielectric layer 36 surrounds the entire perimeter of the core region 55. The vertical structure 33 may include a channel structure. The channel structure may include the gate dielectric layer 36, the channel semiconductor layer 38, the data storage structure 46, and the core region 55. The channel semiconductor layer 38 may be referred to as a "semiconductor layer".

[0040] In one example embodiment, the data storage structure 46 may include a variable resistance material. In another example embodiment, the data storage structure 46 may include a phase change material. In the following description, one or more example embodiments of the semiconductor device 1 will be described.

[0041] Reference Figure 2A and Figure 2B A semiconductor device is described based on an example embodiment. Figure 2A It shows along Figure 1 A cross-sectional view of the region of the semiconductor device intercepted by line I-I'. Figure 2B It is shown Figure 2A An enlarged view of part A in the image.

[0042] Reference Figure 1 , Figure 2A and Figure 2B The stacked structure 18 may be disposed on the lower structure 3. In an example embodiment, the lower structure 3 may include an impurity region 15. The impurity region 15 may be formed of, for example, polysilicon having N-type conductivity.

[0043] In an example embodiment, the lower structure 3 may include a lower substrate 5, a peripheral circuit region 6 disposed on the lower substrate 5, an upper substrate 13 disposed on the peripheral circuit region 6, and an impurity region 15 disposed on the upper substrate 13. The lower substrate 5 may be implemented as a semiconductor substrate formed of a semiconductor material (e.g., silicon). The lower substrate 5 may be a single-crystal silicon substrate. The peripheral circuit region 6 may include peripheral leads 9 and a lower insulating layer 11 covering the peripheral leads 9. The upper substrate 13 may include metal and / or metal silicide. For example, the upper substrate 13 may be formed of a conductive material layer including tungsten and tungsten silicide disposed on the tungsten. The impurity region 15 may be disposed on the upper substrate 13.

[0044] The stacked structure 18 may be located on the impurity region 15. The stacked structure 18 may include alternately stacked interlayer insulating layers 21 and gate layers 24.

[0045] The interlayer insulating layer 21 may include a lowermost interlayer insulating layer 21L and an uppermost interlayer insulating layer 21U. In the interlayer insulating layer 21 and the gate layer 24, the lowermost layer may be configured as the lowermost interlayer insulating layer 21L, and the uppermost layer may be configured as the uppermost interlayer insulating layer 21U. For example, the interlayer insulating layer 21 may be formed of an insulating material (e.g., silicon oxide).

[0046] In the example embodiment, gate layer 24 may be configured as a gate electrode. Therefore, in the following description, gate layer 24 will be referred to as the gate electrode.

[0047] In an example embodiment, a lower buffer layer 17 may be disposed between the stacked structure 18 and the lower structure 3. The lower buffer layer 17 may be formed of a material that has etch selectivity relative to the interlayer insulating layer 21. For example, the lower buffer layer 17 may be formed of an insulating material (e.g., alumina, etc.). In another example embodiment, the lower buffer layer 17 may not be provided.

[0048] A vertical structure 33 may be provided in a hole 30 penetrating the stacked structure 18. The hole 30 may be referred to as a "vertical opening" or "opening". The hole 30 may penetrate the stacked structure 18 and may extend downward, for example, in the vertical direction Z, and may penetrate the lower buffer layer 17. The hole 30 may expose a portion of the lower structure 3 (e.g., a portion of the impurity region 15). The vertical structure 33 may be formed in the hole 30 to penetrate the stacked structure 18 and the lower buffer layer 17.

[0049] The vertical structure 33 may include pad pattern 57 and Figure 1 The diagram shows the core region 55, data storage structure 46, channel semiconductor layer 38, and gate dielectric layer 36. For example, as... Figure 2A As shown, pad pattern 57 may be located on the top surface of core region 55 and data storage structure 46, while channel semiconductor layer 38 and gate dielectric layer 36 may extend (e.g., continuously) along the outer surface (e.g., the entire outer surface) of each of data storage structure 46 and pattern 57, so that, for example, the top surfaces of pad pattern 57, channel semiconductor layer 38 and gate dielectric layer 36 may be flush with each other.

[0050] Specifically, the core region 55 may be configured as an insulating pillar formed of an insulating material (e.g., silicon oxide). For example, the upper portion of the core region 55 adjacent to the pad pattern 57 may be formed of silicon oxide, and the lower portion of the core region 55 spaced apart from the pad pattern 57 may be formed of silicon oxide including voids, or may be formed of air gaps. The core region 55 may be spaced apart from the sidewalls of the via 30, the upper surface of the core region 55 may be disposed at a level higher than the uppermost gate electrode in the gate electrode 24, and the lower surface of the core region 55 may be disposed at a level lower than the lowermost gate electrode in the gate electrode 24.

[0051] The channel semiconductor layer 38 may cover the side and bottom surfaces of the core region 55. A gate dielectric layer 36 may be inserted between the outer surface of the channel semiconductor layer 38 and the gate electrode 24. In an example embodiment, the gate dielectric layer 36 may extend from the portion inserted between the outer surface of the channel semiconductor layer 38 and the gate electrode 24 to the space between the outer surface of the channel semiconductor layer 38 and the interlayer insulating layer 21.

[0052] Data storage structure 46 can be inserted between core region 55 and channel semiconductor layer 38, and can cover the side and bottom surfaces of core region 55. For example, as Figure 2A As shown, the data storage structure 46 can be continuous along the entire sidewall and bottom of the core region 55.

[0053] The pad pattern 57 may contact the upper surface of the core region 55. In an example embodiment, the pad pattern 57 may contact the upper surface of the data storage structure 46. In an example embodiment, the pad pattern 57 may contact the upper portion of the lateral side surface of the channel semiconductor layer 38. In an example embodiment, the pad pattern 57 may be formed of doped silicon (e.g., polysilicon) having N-type conductivity.

[0054] The gate electrode 24 may include a word line 24W and at least one select line 24S disposed on the word line 24W. An insulating pattern 27 may be arranged to isolate the at least one select line 24S of the gate electrode 24 from each other in a second direction D2. The insulating pattern 27, which isolates the at least one select line 24S in the second direction D2, may extend in the vertical direction Z and may penetrate the uppermost interlayer insulating layer 21U. In an example embodiment, the thickness of each of the at least one select line 24S may be greater than the thickness of each word line 24W (e.g., in the vertical direction Z).

[0055] The first upper insulating layer 60 and the second upper insulating layer 73 may be sequentially stacked and disposed on the stacked structure 18. The separation structure 66 may penetrate the first upper insulating layer 60 and the stacked structure 18. The separation structure 66 may have a linear form extending in the first direction D1, such as... Figure 1 As shown.

[0056] In an example embodiment, the separation structure 66 may be formed of an insulating material. In another example embodiment, the separation structure 66 may include both an insulating material and a conductive material. For example, each separation structure 66 may include a first isolation pattern 68 formed of an insulating material and a second isolation pattern 70 formed of a conductive material. The first isolation pattern 68 may be inserted between the second isolation pattern 70 and the stacked structure 18.

[0057] A contact plug 76 may be provided that penetrates the first upper insulating layer 60 and the second upper insulating layer 73 and is electrically connected to the vertical structure 33. The contact plug 76 may contact and be electrically connected to the pad pattern 57 of the vertical structure 33.

[0058] A wire 79 electrically connected to the contact plug 76 can be configured. The wire 79 can be configured as a bit line.

[0059] In an example embodiment, the data storage structure 46 includes a variable resistive material having a non-uniform vacancy concentration along its width. For example, the data storage structure 46 may include a variable resistive material with an increasing vacancy concentration in a direction from the channel semiconductor layer 38 toward the core region 55 orientation; for example, the vacancy concentration may increase in the radial direction as the distance from the outer surface of the core region 55 decreases. For example, if the variable resistive material in the data storage structure 46 is to be separated into a first portion 48 (i.e., the first variable resistive layer 48) disposed between the channel semiconductor layer 38 and the core region 55 (e.g., along the entire perimeter of the core region 55) and a second portion 50 (i.e., the second variable resistive layer 50) disposed between the first variable resistive layer 48 and the core region 55 (e.g., along the entire perimeter of the core region 55), the vacancy concentration in the second portion 50 (the portion closer to the core region 55) will be higher than the vacancy concentration in the first portion 48 (the portion farther from the core region 55). For ease of explanation, the variable resistive material in the data storage structure 46 will be discussed below based on the first part 48 and the second part 50 (or, interchangeably, based on "first variable resistive layer 48" and "second variable resistive layer 50"), to facilitate reference to the different vacancy concentrations along the radial direction of the vertical structure 33. The first variable resistive layer 48 may be referred to as the first variable resistive material layer, and the second variable resistive layer 50 may be referred to as the second variable resistive material layer.

[0060] In an example embodiment, the variable resistance material in the data storage structure 46 may include a first element and oxygen. For example, the variable resistance material in the data storage structure 46 may include a transition metal element and oxygen, such that the concentration of oxygen vacancies in the resulting transition metal oxide (e.g., hafnium oxide (HfO)) increases toward the core region 55.

[0061] For example, refer to Figure 2B The first variable resistivity layer 48 and the second variable resistivity layer 50 may jointly comprise a first element and oxygen. For example, the first element may be a metallic element, such as Al, Mg, Zr, Hf, etc. For example, both the first variable resistivity layer 48 and the second variable resistivity layer 50 may be formed of an HfO material comprising Hf and O, and the concentration of oxygen vacancies in the HfO material included in the second variable resistivity layer 50 may be higher than the concentration of oxygen vacancies in the HfO material included in the first variable resistivity layer 48. Therefore, the first variable resistivity layer 48 and the second variable resistivity layer 50 may be configured as material layers comprising the same element.

[0062] In another example, one of the first variable resistance layer 48 and the second variable resistance layer 50 may be configured as an oxide comprising a first element and oxygen, and the other of the first variable resistance layer 48 and the second variable resistance layer 50 may be configured as a material comprising a second element different from the first element and oxygen. At least one of the first element and the second element may be a transition metal element. The first variable resistance layer 48 may be formed of a first material comprising the first element, and the second variable resistance layer 50 may be formed of a second material comprising a second element different from the first element. For example, the first variable resistance layer 48 may be made of SiO2. x AlO x MgO x ZrO x HfO x and SiN x One of the materials is used to form the second variable resistance layer 50, which may be made of SiOx, AlO x MgO x ZrO x HfO x and SiN x The material is different from that of the first variable resistance layer 48.

[0063] In an example embodiment, each of the first variable resistance layer 48 and the second variable resistance layer 50 may include a material with switching properties, such as SiO2. x AlO x MgO x ZrO x HfO x and SiN x One of them. For example, the first variable resistor layer 48 can be made of HfO. x The second variable resistance layer 50 can be formed from AlO. x form.

[0064] The region of the side surface of the data storage structure 46 facing the word line 24W can be configured to store data and can be configured as a memory cell. In the example embodiment, the distribution characteristics of the memory cells can be improved by providing the data storage structure 46 including a first variable resistance layer 48 and a second variable resistance layer 50.

[0065] In detail, the data storage regions of the data storage structure 46 facing word lines 24W can be programmed. For example, programming operations may include selecting word lines of word lines 24W facing data storage regions of the data storage structure 46 that may need to be programmed, and deselecting other word lines. The selected word line WLa in word lines 24W can be turned off, and the unselected word lines WLb1 and WLb2 can be turned on. For example, programming operations may include applying 0V or a negative voltage to the selected word line WLa, applying a positive voltage above a threshold voltage (e.g., about 6V) to the unselected word lines WLb1 and WLb2, applying a voltage of about 5V to about 6V to the conductor 79 (i.e., the bit line), and grounding the impurity region 15 (i.e., the common source line).

[0066] Figure 2B The dashed line indicates the flow of current 100 when the above programming operation is performed (i.e., when the selected word line WLa is selected and cut off). That is, refer to... Figure 2B , Figure 2B The current 100 can flow along the channel semiconductor layer 38 facing the first unselected word line WLb1 disposed above the selected word line WLa, and is deflected into the data storage structure 46 facing the selected word line WLa due to the change in resistance caused by the applied bias voltage (i.e., flows through the data storage structure 46 in the region corresponding to the cut-off selected word line WLa), and then flows back to the channel semiconductor layer 38 facing the second unselected word line WLb2 disposed below the selected word line WLa.

[0067] An increase in vacancy concentration along the width of the data storage structure 46 in a direction oriented from the channel semiconductor layer 38 toward the center of the vertical structure 33 (e.g., compared to a uniform concentration along the width or a concentration varying in the opposite direction) allows the current 100 to be further shifted into the data storage structure 46, for example, flowing through the second variable resistor layer 50 instead of the first variable resistor layer 48 due to the lower resistance in the second variable resistor layer 50 relative to the first variable resistor layer 48, thereby improving the control and uniformity of current operation. Specifically, applying a bias voltage to the vertical structure 33 (which includes the data storage structure 46 with varying vacancy concentration) causes the vacancy concentration to be more uniformly distributed along the vertical direction Z within the data storage structure 46 at the region corresponding to the selected gate electrode WLa, and forms, for example, two depletion regions above and below the selected gate electrode WLa, such that the vertical distance between the outermost vacancy and the channel semiconductor layer 38 is reduced, thereby improving the control and uniformity of current operation through the channel semiconductor layer 38.

[0068] As described above, as current flows along the data storage structure 46 facing the selected word line WLa, the resistance of the data storage structure 46 changes, and the data storage area of ​​the data storage structure 46 facing the selected word line WLa can be configured to be in a set state. By performing the above programming operation, the resistance of the data storage structure 46 decreases.

[0069] In an example embodiment, the data storage structure 46 may form a single-level memory cell. For example, the data storage region of the data storage structure 46 facing the selected word line WLa may be configured to be in a first resistive state, and the data storage region of the data storage structure 46 in the first resistive state may form a single-level memory cell.

[0070] In another example embodiment, the data storage area of ​​the data storage structure 46 can form a multi-level memory cell. For example, depending on the applied programming operation, the data storage area of ​​the data storage structure 46 facing the selected word line WLa can be configured to be in a first resistive state or a second resistive state, in which the resistance is higher than that in the first resistive state. Therefore, when the data storage area of ​​the data storage structure 46 facing the selected word line WLa is configured to be in different resistive states, the data storage structure 46 can form a multi-level memory cell.

[0071] An erase operation can be performed on the data storage area of ​​the data storage structure 46 programmed as described above. Similar to the programming operation described above, the erase operation may include turning off the selected word line WLa, turning on the unselected word lines WLb1 and WLb2, applying an erase voltage (i.e., a voltage of approximately 5V to approximately 6V) to the impurity region 15 (i.e., the common source line), and grounding the conductor 79 (i.e., the bit line). Therefore, current can be applied in conjunction with... Figure 2B The flow moves in the opposite direction, allowing the magnetic field to change, and the data storage area of ​​the data storage structure 46 facing the selected word line WLa can be configured to be in a reset state. Through the erase operation, the resistance of the data storage area of ​​the data storage structure 46 increases. Therefore, the resistance of the data storage area of ​​the data storage structure 46 in the set state obtained by performing a programming operation may differ from the resistance in the reset state obtained by performing an erase operation. For example, the resistance in the set state of the data storage area of ​​the data storage structure 46 may be lower than the resistance in the reset state.

[0072] In an example embodiment, the data storage structure 46 may be included in a single-level memory cell. For example, the region of the data storage structure 46 opposite to the selected word line WLa may enter a first resistive state, and the region of the data storage structure in the first resistive state may be included in the single-level memory cell.

[0073] In another example, the data storage structure 46 may be included in a multi-level cell (MLC). For example, depending on the applied programming operation, the region of the data storage structure 46 opposite to the selected word line WL may be in a first resistance state or a second resistance state higher than the first resistance state. Therefore, the region of the data storage structure 46 opposite to the selected word line WL can be configured to be in different resistance states, and the data storage structure 46 may be included in a multi-level memory cell.

[0074] In the following description, reference will be made to Figure 3A and Figure 3B The description includes, for example, the vacancy concentration in a data storage structure 46 comprising a first variable resistance layer 48 and a second variable resistance layer 50. Figure 3A This is a graph illustrating an example of vacancy concentration in data storage structure 46. Figure 3B This is a graph illustrating an example of a modification to the vacancy concentration in data storage structure 46.

[0075] For example, refer to Figure 3A The data storage structure 46 may have a vacancy concentration that varies in a stepped manner. That is, the vacancy concentration along the width of the data storage structure 46 in the direction from the channel semiconductor layer 38 toward the core region 55 may increase along the stepped profile.

[0076] Specifically, for example, the first variable resistive layer 48 (i.e., the portion of the data storage structure 46 closer to the channel semiconductor layer 38) may have a first vacancy concentration C1, and the second variable resistive layer 50 (i.e., the portion of the data storage structure 46 closer to the core region 55) may have a second vacancy concentration C2 that is higher than the first vacancy concentration C1. The first vacancy concentration C1 may remain constant with variations in the thickness of the first variable resistive layer 48, and the second vacancy concentration C2 may remain constant with variations in the thickness of the second variable resistive layer 50.

[0077] In another example, refer to Figure 3B The data storage structure 46 may have a gradually changing vacancy concentration. For example, the vacancy concentration in the first variable resistor layer 48 may increase as the distance from the second variable resistor layer 50 increases. Similarly, the vacancy concentration in the second variable resistor layer 50 may decrease as the distance from the first variable resistor layer 48 increases.

[0078] For example, in the first variable resistance layer 48, the first variable resistance layer 48 and the channel semiconductor layer 38 ( Figure 2B The vacancy concentration in the contact portion of the first variable resistor layer 48 with the contact portion of the second variable resistor layer 50 can be higher than the vacancy concentration in the contact portion of the first variable resistor layer 48 with the core region 55. In the second variable resistor layer 50, the vacancy concentration in the contact portion of the second variable resistor layer 50 with the first variable resistor layer 48 can be higher than the vacancy concentration in the contact portion of the second variable resistor layer 50 with the core region 55. Figure 2BThe vacancy concentration in the contact area (in the middle). Therefore, the vacancy concentration of the second variable resistive layer 50 can be higher than that of the first variable resistive layer 48.

[0079] In the following description, reference will be made to Figure 3C The document describes the empty space concentration, programming operation method, and erase operation method of the data storage structure 46 in the set state and reset state. Figure 3C This is a conceptual diagram illustrating the change in the vacancy concentration of the data storage structure 46 in its set state and reset state, where the vacancy concentration is as follows: Figure 3A or Figure 3B The change is shown in a stepped manner.

[0080] exist Figure 3C In this diagram, element B1a is the first boundary surface B1a between the channel semiconductor layer 38 and the first variable resistor layer 48, and the set current flows from the first boundary surface B1a from the channel semiconductor layer 38 to the first variable resistor layer 48. Element B2a is the second boundary surface B2a, and the set current flows from the second boundary surface B2a from the first variable resistor layer 48 to the second variable resistor layer 50. Element B2b is the third boundary surface B2b, and the set current flowing in the second variable resistor layer 50 flows from the third boundary surface B2b to the first variable resistor layer 48. Element B1b is the fourth boundary surface B1b between the first variable resistor layer 48 and the channel semiconductor layer 38, and the current flowing through the first variable resistor layer 48 flows from the fourth boundary surface B1b to the channel semiconductor layer 38. Therefore, Figure 3C The arrangement of boundaries B1a, B2a, B2b, and B1b in the diagram schematically reflects the relationship with... Figure 2B The current path in the region corresponding to the selected word line WLa. The current can be a current generated through programming operations.

[0081] Reference Figure 3C In the region of the data storage structure 46 configured to be in a set state through programming, a first filament F1a can be formed in the first variable resistor layer 48 between the first boundary surface B1a and the second boundary surface B2a; a second filament F2a can be formed in the second variable resistor layer 50 between the second boundary surface B2a and the third boundary surface B2b; and a third filament F3a can be formed in the first variable resistor layer 48 between the third boundary surface B2b and the fourth boundary surface B1b. The first filament F1a, the second filament F2a, and the third filament F3a can be connected to each other. Therefore, a current path can be formed along the first filament F1a, the second filament F2a, and the third filament F3a connected sequentially in the data storage structure 46; that is, the first filament to the third filament reflects the actual current path through the data storage structure 46.

[0082] In the first filament F1a, the vacancy concentration in the region adjacent to the first boundary surface B1a may be higher than the vacancy concentration in the region adjacent to the second boundary surface B2a. In the second filament F2a, the vacancy concentration in the region adjacent to the second boundary surface B2a may be higher than the vacancy concentration in the region adjacent to the third boundary surface B2b. In the third filament F3a, the vacancy concentration in the region adjacent to the third boundary surface B2b may be higher than the vacancy concentration in the region adjacent to the fourth boundary surface B1b.

[0083] In the region of the data storage structure 46 configured to be in a reset state by an erase operation, a first deformable filament F1b can be formed in the first variable resistance layer 48 between the first boundary surface B1a and the second boundary surface B2a, a second deformable filament F2b can be formed in the second variable resistance layer 50 between the second boundary surface B2a and the third boundary surface B2b, and a third deformable filament F3b can be formed between the third boundary surface B2b and the fourth boundary surface B1b.

[0084] exist Figure 3C In this structure, the widths of the first to third filaments F1a, F2a, and F3a, and the first to third textured filaments F1b, F2b, and F3b, can indicate the vacancy concentration. For example, in the first to third filaments F1a, F2a, and F3a, and the first to third textured filaments F1b, F2b, and F3b, portions with relatively large widths can indicate a relatively high vacancy concentration, while portions with relatively small widths can indicate a relatively low vacancy concentration.

[0085] The first deformed filament F1b may contact the first boundary surface B1a and may be substantially spaced from the second boundary surface B2a. Compared to the second filament F2a, the vacancy concentration in the region of the second deformed filament F2b adjacent to the third boundary surface B2b may be reduced. The third deformed filament F3b may contact the third boundary surface B2b and may be substantially spaced from the fourth boundary surface B1b. Therefore, in the region of the data storage structure 46 in the reset state, the first deformed filament F1b may be disconnected from the second deformed filament F2b, and the third deformed filament F3b may be disconnected from the fourth boundary surface B1b.

[0086] As described above, the area of ​​the data storage structure 46 in the set state may include first filaments to third filaments F1a, F2a and F3a connected to each other, and the area of ​​the data storage structure 46 in the reset state may include first deformed filaments to third deformed filaments F1b, F2b and F3b, at least one of the first deformed filaments to third deformed filaments F1b, F2b and F3b is disconnected from the other.

[0087] In the following description, reference will be made to Figure 4A This describes an example of modifying the vacancy concentration in data storage structure 46 after it has been formed by a deposition process. Figure 4A This is a graph illustrating an example of a modification to the vacancy concentration in data storage structure 46.

[0088] In the modified example, according to Figure 4A The data storage structure 46 may have a continuously changing vacancy concentration. For example, in the data storage structure 46, the vacancy concentration may gradually increase from the first variable resistor layer 48 to the second variable resistor layer 50. Therefore, the vacancy concentration of the second variable resistor layer 50 may be higher than that of the first variable resistor layer 48.

[0089] In the following description, reference will be made to Figure 4B Describes the vacancy concentration of data storage structure 46 in the set state and reset state. Figure 4B This illustrates the change in the vacancy concentration of data storage structure 46 in the set state and the reset state. Figure 4B In the diagram, elements B1a, B2a, B2b, and B1b correspond to... Figure 3C The first boundary surface B1a, the second boundary surface B2a, the third boundary surface B2b, and the fourth boundary surface B1b are shown.

[0090] Reference Figure 4B In the region of the data storage structure 46 configured to be in a set state through programming, a first filament F1a' can be formed in the first variable resistor layer 48 between the first boundary surface B1a and the second boundary surface B2a, a second filament F2 can be formed in the second variable resistor layer 50 between the second boundary surface B2a and the third boundary surface B2b, and a third filament F3a' can be formed in the first variable resistor layer 48 between the third boundary surface B2b and the fourth boundary surface B1b. The first filament F1a', the second filament F2, and the third filament F3a' can be connected to each other. Therefore, a current path can be formed along the first filament F1a', the second filament F2, and the third filament F3a' that are connected sequentially in the data storage structure 46.

[0091] In the first filament F1a', the vacancy concentration in the region adjacent to the first boundary surface B1a may be lower than the vacancy concentration in the region adjacent to the second boundary surface B2a. In the second filament F2, the vacancy concentration in the region adjacent to the second boundary surface B2a may be substantially the same as the vacancy concentration in the region adjacent to the third boundary surface B2b. In the third filament F3a', the vacancy concentration in the region adjacent to the third boundary surface B2b may be lower than the vacancy concentration in the region adjacent to the fourth boundary surface B1b.

[0092] In the region of the data storage structure 46 configured to be in a reset state by an erase operation, a first deformable filament F1b' can be formed in the first variable resistance layer 48 between the first boundary surface B1a and the second boundary surface B2a, a second filament F2 can be substantially undeformed in the second variable resistance layer 50 between the second boundary surface B2a and the third boundary surface B2b, and a third deformable filament F3b' can be formed between the third boundary surface B2b and the fourth boundary surface B1b.

[0093] exist Figure 4B In this structure, the widths of the first to third filaments F1a', F2, and F3a', as well as the first textured filament F1b' and the third textured filament F3b', can indicate the vacancy concentration. For example, in the first to third filaments F1a', F2, and F3a', as well as the first textured filament F1b' and the third textured filament F3b', portions with relatively large widths can indicate a relatively high vacancy concentration, while portions with relatively small widths can indicate a relatively low vacancy concentration.

[0094] The first deformable filament F1b' can be spaced apart from and disconnected from the first boundary surface B1a, and can maintain a connection with the second filament F2. The third deformable filament F3b' can maintain a connection with the second filament F2 and can be spaced apart from and disconnected from the fourth boundary surface B1b. Therefore, in the reset region of the data storage structure 46, the first deformable filament F1b' can be disconnected from the first boundary surface B1a, and the third deformable filament F3b' can be disconnected from the fourth boundary surface B1b.

[0095] Return to reference Figure 1 , Figure 2A and Figure 2B The first variable resistance layer 48 and the second variable resistance layer 50 may, for example, have the same thickness along the second direction D2, but exemplary embodiments are not limited thereto. For example, the first variable resistance layer 48 and the second variable resistance layer 50 may be configured to have different thicknesses, for example, along the second direction D2. For example, the thickness of each of the first variable resistance layer 48 and the second variable resistance layer 50 may be from about 1 nm to about 5 nm. (Refer to...) Figure 5A and Figure 5B Describe an example configured as a variable resistance layer with different thicknesses. Figure 5A and Figure 5B This is an enlarged view showing a portion of the variable resistor layer configured with different thicknesses.

[0096] In the modified example, refer to Figure 5AThe data storage structure 46a may include a first variable resistor layer 48a and a second variable resistor layer 50a with a thickness less than that of the first variable resistor layer 48a. By configuring the thickness of the first variable resistor layer 48a to be greater than that of the second variable resistor layer 50a, the semiconductor device can operate with relatively low current, thereby reducing the power consumption of the semiconductor device. In another modified example, refer to... Figure 5B The data storage structure 46b may include a first variable resistance layer 48b and a second variable resistance layer 50b with a thickness less than that of the first variable resistance layer 48b. By configuring the thickness of the first variable resistance layer 48b to be less than that of the second variable resistance layer 50b, the distribution properties can be improved.

[0097] In the following description, reference will be made to Figure 6A Describe an example of a modified stacking structure. Figure 6A Is with Figure 2B The enlarged view corresponding to part A shown.

[0098] In the modified example, refer to Figure 6A The vertical structure 33b may include a data storage structure 46c and the gate dielectric layer 36, channel semiconductor layer 38, core region 55 and pad pattern 57 described in the above example embodiments.

[0099] Data storage structure 46c may include Figure 2A and Figure 2B The first variable resistance layer 48 and the second variable resistance layer 50 are shown. The data storage structure 46c may further include one or more additional variable resistance layers 52a and 52b disposed between the first variable resistance layer 48 and the second variable resistance layer 50. The vacancy concentration of the one or more additional variable resistance layers 52a and 52b may be higher than the vacancy concentration of the first variable resistance layer 48 and lower than the vacancy concentration of the second variable resistance layer 50.

[0100] In the example embodiment, one or more additional variable resistance layers 52a and 52b may be a single additional variable resistance layer.

[0101] In an example embodiment, a plurality of additional variable resistance layers 52a and 52b may be provided, and the plurality of additional variable resistance layers 52a and 52b may include a first additional variable resistance layer 52a and a second additional variable resistance layer 52b. The first additional variable resistance layer 52a may be inserted between the second additional variable resistance layer 52b and the first variable resistance layer 48.

[0102] The vacancy concentration of the first additional variable resistive layer 52a may be higher than that of the first variable resistive layer 48. The vacancy concentration of the second additional variable resistive layer 52b may be higher than that of the first additional variable resistive layer 52a and lower than that of the second variable resistive layer 50.

[0103] In the example embodiment, the first variable resistance layer 48 may be referred to as the first layer, the first additional variable resistance layer 52a may be referred to as the second layer, the second additional variable resistance layer 52b may be referred to as the third layer, and the second variable resistance layer 50 may be referred to as the fourth layer. In the example embodiment, by providing a data storage structure 46c including the first layer 48, the second layer 52a, the third layer 52b, and the fourth layer 52b, the distribution properties can be improved.

[0104] In the example embodiment, the data storage structure 46c can form a single-level memory cell. In the example embodiment, the data storage structure 46c can form a multi-level memory cell.

[0105] In the following description, reference will be made to Figure 6B , Figure 6C , Figure 6D and Figure 6E Describe the vacancy concentration of data storage structure 46c. Figure 6B , Figure 6C , Figure 6D and Figure 6E This is a graph illustrating one or more examples of vacancy concentration in data storage structure 46c. For example, Figure 6A This is a graph illustrating an example of vacancy concentration in data storage structure 46c. Figure 6B This is a graph illustrating an example of a modification to the vacancy concentration in data storage structure 46c. Figure 6C This is a graph illustrating another modified example of vacancy concentration in data storage structure 46c. Figure 6D This is a graph illustrating another modified example of vacancy concentration in data storage structure 46c. Figure 6E This is a graph illustrating another modified example of vacancy concentration in data storage structure 46c.

[0106] Reference Figure 6B ,and Figure 3A Similar to the example embodiment shown, the data storage structure 46c may have a vacancy concentration that varies with a stepped profile. For example, the data storage structure 46c may include a channel semiconductor layer 38 ( Figure 6A Core region 55 in (middle) Figure 6AA first variable resistor layer 48a, a first additional variable resistor layer 52a, a second additional variable resistor layer 52b, and a second variable resistor layer 50 are sequentially arranged in the direction of (center). The vacancy concentration of the first additional variable resistor layer 52a may be higher than that of the first variable resistor layer 48, the vacancy concentration of the second additional variable resistor layer 52b may be higher than that of the first additional variable resistor layer 52a, and the vacancy concentration of the second variable resistor layer 50 may be higher than that of the second additional variable resistor layer 52b. As described above, when neither the first additional variable resistor layer 52a nor the second additional variable resistor layer 52b is provided, the vacancy concentration of the other of the first additional variable resistor layer 52a and the second additional variable resistor layer 52b may be higher than that of the first variable resistor layer 48 and lower than that of the second variable resistor layer 50.

[0107] In the following description, although the data storage structure 46c that does not provide one of the first additional variable resistance layer 52a and the second additional variable resistance layer 52b is described as described above, the vacancy concentration of the data storage structure 46c that does not provide one of the first additional variable resistance layer 52a and the second additional variable resistance layer 52b can be understood based on the description of the vacancy concentration of the data storage structure 46c that includes both the first additional variable resistance layer 52a and the second additional variable resistance layer 52b.

[0108] In the modified example embodiment, refer to Figure 6C At least a portion of the data storage structure 46c may have a vacancy concentration distribution that tends to increase from the first variable resistance layer 48 toward the second variable resistance layer 50. For example, the vacancy concentration distribution of the first additional variable resistance layer 52a and the second additional variable resistance layer 52b may increase in the direction from the first variable resistance layer 48 toward the second variable resistance layer 50. The slope of the vacancy concentration at the boundary between the first variable resistance layer 48 and the first additional variable resistance layer 52a, and the slope of the vacancy concentration at the boundary between the first additional variable resistance layer 52a and the second additional variable resistance layer 52b, may be steeper than the slope of the vacancy concentration at the central portion of the first additional variable resistance layer 52a and the central portion of the second additional variable resistance layer 52b.

[0109] In the modified example embodiment, refer to Figure 6D Similar to Figure 3B In the example embodiment shown, the data storage structure 46 may have a vacancy concentration that varies with a stepped profile. For example, the first variable resistance layer 48 and the channel semiconductor layer 38 ( Figure 6AThe vacancy concentration in the adjacent portion of the first variable resistor layer 48 may be higher than the vacancy concentration in the portion of the first additional variable resistor layer 52a adjacent to the first additional variable resistor layer 52a. The vacancy concentration in the portion of the first additional variable resistor layer 52a adjacent to the first variable resistor layer 48 may be higher than the vacancy concentration in the portion of the first additional variable resistor layer 52a adjacent to the second additional variable resistor layer 52b. The vacancy concentration in the portion of the second additional variable resistor layer 52b adjacent to the first additional variable resistor layer 52a may be higher than the vacancy concentration in the portion of the second additional variable resistor layer 52b adjacent to the second variable resistor layer 50. The vacancy concentration in the portion of the second variable resistor layer 50 in contact with the second additional variable resistor layer 52b may be higher than the vacancy concentration in the portion of the second variable resistor layer 50 in contact with the core region 55. Figure 6A The vacancy concentration in the part in contact with the middle.

[0110] In the modified example, refer to Figure 6E Similar to Figure 4A In the example embodiment shown, data storage structure 46 may have a vacancy concentration that changes at a constant slope.

[0111] In the following description, reference will be made to Figure 6F Describe an example of a modified stacking structure. Figure 6F Is with Figure 2B The enlarged view corresponding to part A shown.

[0112] In the modified example, refer to Figure 6F The vertical structure 33c may include a dielectric structure 136, rather than the gate dielectric layer 36 described in the above example embodiments. Figure 2B (in the middle). Therefore, the vertical structure 33c may include the dielectric structure 136 and the channel semiconductor layer 38, core region 55, pad pattern 57 and data storage structure 46 described in the above example embodiments.

[0113] The dielectric structure 136 may include a first dielectric layer 136a, a data storage layer 136b, and a second dielectric layer 136c. The data storage layer 136b may be a charge trapping layer for trapping charge. The first dielectric layer 136a may be formed of, for example, silicon oxide or nitrogen-doped silicon oxide. The data storage layer 136b may be formed of a charge trapping material (e.g., silicon nitride). The second dielectric layer 136c may include, for example, silicon oxide and a high-k dielectric.

[0114] The data storage layer 136b in the dielectric structure 136 can be used as a data storage area for NAND flash memory, and the data storage structure 46 can be used as a data storage area for a variable resistance memory device. Since the data storage areas can be disposed on both sides of the channel semiconductor layer 38, the data storage density can be increased.

[0115] In the following description, reference will be made to Figure 6GDescribe an example of a modified stacking structure. Figure 6G Is with Figure 2B The enlarged view corresponding to part A shown.

[0116] In the modified example, refer to Figure 6G The vertical structure 33d may include the data storage structure 146 and the gate dielectric layer 36, channel semiconductor layer 38, core region 55 and pad pattern 57 described in the above example embodiments.

[0117] The data storage structure 146 may include multiple separate layers and multiple data storage layers that are alternately stacked. Each of the multiple data storage layers may include a phase change material.

[0118] Multiple data storage layers may include a first phase change material layer 148 and a second phase change material layer 150. Multiple separation layers may include a first separation layer 147 disposed between the first phase change material layer 148 and the channel semiconductor layer 38, and a second separation layer 149 disposed between the first phase change material layer 148 and the second phase change material layer 150. The thickness of each of the first phase change material layer 148 and the second phase change material layer 150 may be greater than the thickness of each of the first separation layer 147 and the second separation layer 149.

[0119] Each of the plurality of phase change material layers 148 and 150 may be formed of a phase change memory material, such as a chalcogenide material including Ge, Sb and / or Te. Alternatively, each of the plurality of phase change material layers 148 and 150 may be formed of a phase change memory material including, for example, at least one of Te and Se and at least one of Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O, N and In.

[0120] Multiple phase change material layers 148 and 150 may collectively include a first element, and the concentration of the first element in the second phase change material layer 150 may be higher than the concentration of the first element included in the first phase change material layer 148. The first element may be Sb or Te. Multiple separation layers 147 and 149 may be formed of metal nitrides (e.g., TiN).

[0121] In the example embodiment, the distribution properties can be improved by providing a data storage structure 146 that includes multiple separation layers 147 and 149 and multiple phase change material layers 148 and 150.

[0122] In the following description, reference will be made to Figure 7A , Figure 7B and Figure 7C Description Reference Figure 1 A modified example of the described vertical structure 33. Figure 7A It shows along Figure 1 A cross-sectional view of the region intercepted by line I-I' in the diagram. Figure 7B It is shown Figure 7A A magnified view of part B in the image. Figure 7C It is shown Figure 7A A magnified view of part C in the image.

[0123] Reference Figure 7A , Figure 7B and Figure 7C The vertical structure 33e may include a data storage structure 46d and a buffer semiconductor layer 39, as well as the gate dielectric layer 36, channel semiconductor layer 38, core region 55, and pad pattern 57 described in the example embodiments above. In the example embodiments, the data storage structure 46d may be configured as a single variable resistance layer. The buffer semiconductor layer 39 may be referred to as a buffer layer.

[0124] A buffer semiconductor layer 39 may be inserted between the data storage structure 46d and the channel semiconductor layer 38. The buffer semiconductor layer 39 may, for example, be integrally formed of a material having a grain size smaller than that of the channel semiconductor layer 38.

[0125] For example, the channel semiconductor layer 38 may be formed of polysilicon, and the buffer semiconductor layer 39 may be formed of amorphous silicon. In another example, the channel semiconductor layer 38 may be formed of first polysilicon, and the buffer semiconductor layer 39 may be formed of second polysilicon with grains smaller than those of the first polysilicon.

[0126] For example, when the buffer semiconductor layer 39 is formed of a material having a structure with grains smaller than those of the channel semiconductor layer 38, for example, when the buffer semiconductor layer 39 is formed of amorphous silicon, the filament formed through the buffer semiconductor layer 39 (e.g., as previously referred to) when a bias voltage is applied... Figure 3C and Figure 4B The described grains can be more easily aligned with the grain boundaries of smaller grains, thereby improving the uniformity of the vacancy distribution along the vertical Z direction. In other words, smaller grains facilitate a straighter current path through the grain boundaries (i.e., via filaments).

[0127] In an example embodiment, the thickness of the buffer semiconductor layer 39 may be less than the thickness of the channel semiconductor layer 38. For example, the thickness of the buffer semiconductor layer 39 may be from about 0.5 nm to about 2 nm, and the thickness of the channel semiconductor layer 38 may be from about 2 nm to about 10 nm.

[0128] The pad pattern 57 can directly contact the channel semiconductor layer 38. The pad pattern 57 can directly contact the upper end of the data storage structure 46d and the upper end of the buffer semiconductor layer 39. In the example embodiment, the upper surface of the pad pattern 57 can be coplanar with the upper surface of the channel semiconductor layer 38.

[0129] In the example embodiment, the distribution properties can be improved by providing a vertical structure 33e including a channel semiconductor layer 38 and a buffer semiconductor layer 39.

[0130] In the following description, reference will be made to Figure 8 Description Reference Figure 7A and Figure 7C Example of a modified pad pattern described. Figure 8 Is with Figure 7C The magnified view corresponding to C in the magnified section.

[0131] In the modified example, refer to Figure 8 The pad pattern 57a ​​may cover the upper surface of the channel semiconductor layer 38a. For example, the pad pattern 57a ​​may have a lower surface that covers the upper end of the data storage structure 46d and the upper end of the buffer semiconductor layer 39 and covers the upper surface of the channel semiconductor layer 38a.

[0132] In the following description, reference will be made to Figure 9 Description Reference Figures 7A to 7C Example of a modified data storage structure. Figure 9 Is with Figure 7B The magnified image corresponding to section B in the image.

[0133] In the modified example, refer to Figure 9 The vertical structure 33f may include the data storage structure 46 and, in the above example embodiment, reference to Figures 7A to 7C The gate dielectric layer 36, the channel semiconductor layer 38, the buffer semiconductor layer 39, the core region 55, and the pad pattern 57 are described.

[0134] Data storage structure 46 may include Figure 2A and Figure 2B The first variable resistor layer 48 and the second variable resistor layer 50 are shown. The first variable resistor layer 48 may contact the buffer semiconductor layer 39, and the second variable resistor layer 50 may contact the core region 55.

[0135] In the example embodiment, the distribution properties can be improved by providing a vertical structure 33f that includes a channel semiconductor layer 38, a buffer semiconductor layer 39, and a data storage structure 46.

[0136] In the following description, reference will be made to Figure 10 Description Reference Figure 9 Example of a modified data storage structure. Figure 10 Is with Figure 9 The enlarged image in the image corresponds to the enlarged image in the image.

[0137] In the modified example, refer to Figure 10 The vertical structure 33g may also include an interface layer 41 and Figure 9 The diagram shows the gate dielectric layer 36, channel semiconductor layer 38, buffer semiconductor layer 39, core region 55, and pad pattern 57. Figure 7A(in Chinese) and data storage structure 46.

[0138] In an example embodiment, data storage structure 46 may include a reference. Figure 2A and Figure 2B The first variable resistance layer 48 and the second variable resistance layer 50 are described. In another example embodiment, the data storage structure 46a may be configured as a single variable resistance layer.

[0139] The interface layer 41 may be formed of an oxide of the channel semiconductor layer 38, which is formed by oxidizing the surface of the channel semiconductor layer 38 facing the core region 55. For example, when the channel semiconductor layer 38 is formed of polysilicon, the interface layer 41 may be formed of silicon oxide, which is formed by oxidizing the polysilicon.

[0140] Interface layer 41 can be inserted between channel semiconductor layer 38 and buffer semiconductor layer 39. The thickness of interface layer 41 can be less than the thickness of data storage structure 46b.

[0141] In the example embodiment, the distribution properties can be improved by providing a vertical structure 33g that includes a channel semiconductor layer 38, an interface layer 41, a buffer semiconductor layer 39, and a data storage structure 46.

[0142] In the following description, reference will be made to Figure 11A and Figure 11B A modified example of the vertical structure described in the above example embodiments is described. Figure 11A and Figure 11B Corresponding to along Figure 1 A cross-sectional view of line I-I'.

[0143] In the modified example, refer to Figure 11A The vertical structure 33h may further include a barrier layer 56 disposed between the pad pattern 57 and the data storage structure 46, as well as a gate dielectric layer 36, a channel semiconductor layer 38, a core region 55, and the pad pattern 57. The barrier layer 56 may be inserted between the pad pattern 57 and the data storage structure 46, and may also be inserted between the core region 55 and the pad pattern 57. In an example embodiment, the barrier layer 56 may be formed of an insulating material (e.g., silicon oxide). The barrier layer 56 may be referred to as a barrier insulating layer.

[0144] Barrier layer 56 blocks the current path from pad pattern 57 to data storage structure 46. That is, barrier layer 56 ensures that the current path flows from pad pattern 57 to channel semiconductor layer 38 before flowing to data storage structure 46 (i.e., there is no direct flow between pad pattern 57 and data storage structure 46), thus improving current flow control (via channel semiconductor layer 38). Therefore, the switching properties of the select transistor, including select line 24S, are improved.

[0145] In another modified example, refer to Figure 11B The vertical structure 33i may include pad pattern 157 and the gate dielectric layer 36, channel semiconductor layer 38, data storage structure 46 and core region 55 described in the above example embodiments.

[0146] The pad pattern 157 may include a first pad layer 157a and a second pad layer 157b. The first pad layer 157a may cover the lower surface and side surface of the second pad layer 157b. The second pad layer 157b may be formed of polysilicon with N-type conductivity. A first portion 157a_1 of the first pad layer 157a adjacent to the second pad layer 157b may be formed of polysilicon with N-type conductivity, and a second portion 157a_2 disposed below the second pad layer 157b and in contact with the data storage structure 46 may be formed of undoped polysilicon. The second portion 157a_2 of the first pad layer 157a may significantly reduce the current path from the pad pattern 157 to the data storage structure 46, thereby improving the switching properties of the selection transistor including the selection line 24S.

[0147] In the following description, reference will be made to Figures 12A to 12E Description Reference Figure 2A and Figure 2B One or more examples of modifications to the described semiconductor device. See below for reference. Figures 12A to 12E In the description of one or more modified examples of the described semiconductor device, the modified elements will be described primarily, while those not described in the modified examples will be omitted. Figures 12A to 12E The elements in can be understood based on the elements described in the above example embodiments.

[0148] Reference Figure 12A Description Reference Figure 2A and Figure 2B Example of a modified stacking structure described. Figure 12A Corresponding to along Figure 1 The cross-sectional view taken from line I-I' in the diagram.

[0149] In the modified example, refer to Figure 12A The lower buffer layer 17 may be disposed on the lower structure 3 as described above. The stacked structure 118 may be disposed on the lower buffer layer 17. The stacked structure 118 may include alternately stacked interlayer insulating layers 21 and gate electrodes 124. As described above, the interlayer insulating layer 21 may include a lowermost interlayer insulating layer 121L and an uppermost interlayer insulating layer 121U, and among the interlayer insulating layers 21 and the gate electrode 124, the lowermost layer may be configured as the lowermost interlayer insulating layer 121L and the uppermost layer may be configured as the uppermost interlayer insulating layer 121U.

[0150] Can be set and referenced Figure 2AThe described separation structure 66 is essentially the same as the separation structure 66. The separation structure 66 can penetrate the stacked structure 118 and the lower buffer layer 17.

[0151] A vertical structure 33 can be configured to penetrate the stacked structure 118 and the lower buffer layer 17. The cross-sectional structure of the vertical structure 33 can be compared with a reference. Figures 2A to 10 The cross-sectional structures of one of the vertical structures 33b, 33c, 33d, 33e, 33f, and 33g described are substantially the same. Therefore, vertical structure 33 can also be replaced by one of the vertical structures 33b, 33c, 33d, 33e, 33f, and 33g described in the above example embodiments.

[0152] Each gate electrode 124 may include a first gate portion 124a adjacent to the vertical structure 33 and a second gate portion 124b adjacent to the split structure 66. The first gate portion 124a may surround the side surface of the vertical structure 33.

[0153] The first gate portion 124a may be formed of doped polysilicon, and the second gate portion 124b may be formed of metal silicide (e.g., Wsi, TiSi, etc.), metal nitride (e.g., WN, TiN, etc.) and / or metal (e.g., W, etc.).

[0154] Since each gate electrode 124 includes a second gate portion 124b, the electrical characteristics of the gate electrode 124 can be improved. Therefore, a semiconductor device with improved electrical characteristics can be provided.

[0155] In the following description, reference will be made to Figure 12B Description Reference Figure 2A and Figure 2B Example of a modified substructure described. Figure 12B Corresponding to along Figure 1 The cross-sectional view taken from line I-I' in the diagram.

[0156] In the modified example, refer to Figure 12B The lower structure 113 may include a semiconductor substrate 105 and an impurity region 115 disposed on the semiconductor substrate 105. The semiconductor substrate 105 may be configured as a single-crystal silicon substrate. The impurity region 115 may be formed by doping the single-crystal silicon substrate to N-type. Therefore, the impurity region 115 may have N-type conductivity.

[0157] Reference Figure 12C Modification examples of semiconductor devices are described based on exemplary embodiments. Figure 12C This is a cross-sectional view showing a modified example of a semiconductor device.

[0158] Reference Figure 12CA first chip region 203 and a second chip region 503 disposed on the first chip region 203 can be configured. The first chip region 203 may include a substrate 205 and a peripheral circuit structure 207 disposed on the substrate 205. The peripheral circuit structure 207 may include a peripheral transistor PTR and peripheral leads 209 included in the peripheral circuit, a substrate insulating layer 211 covering the peripheral transistor PTR and peripheral leads 209, and a substrate bonding pad 214 disposed in the substrate insulating layer 211 and electrically connected to the peripheral leads 209. The peripheral transistor PTR may include a peripheral gate PG and a peripheral source / drain PSD. The substrate bonding pad 214 and the substrate insulating layer 211 may have upper surfaces that are coplanar with each other. The substrate bonding pad 214 and the peripheral leads 209 may be electrically connected to each other through a substrate plug 212.

[0159] The second chip region 503 may include a plurality of stacked structures 318 and 418 and a plurality of vertical structures 333 and 433 stacked sequentially. Each of the plurality of stacked structures 318 and 418 may be coupled with... Figure 2A The stacked structures 18 shown are substantially the same. For example, multiple stacked structures 318 and 418 may include a first stacked structure 318 and a second stacked structure 418 disposed on the first stacked structure 318. The first stacked structure 318 may include alternately stacked first interlayer insulating layers 321 and multiple first gate electrodes 324. The second stacked structure 418 may include alternately stacked second interlayer insulating layers 421 and multiple second gate electrodes 424.

[0160] The second chip region 503 may include a first conductive structure 379 disposed between the first stacked structure 318 and the first chip region 203, a second conductive structure 500 disposed between the first stacked structure 318 and the second stacked structure 418, and a third conductive structure 410 disposed on the second stacked structure 418.

[0161] The first conductive structure 379 may be formed of a metallic material (e.g., tungsten, copper, etc.). The second conductive structure 500 may include a first conductive layer 315 adjacent to the first stacked structure 318 and a second conductive layer 479 adjacent to the second stacked structure 418. The third conductive structure 410 may include a third conductive layer 415 adjacent to the second stacked structure 418 and a fourth conductive layer 413 disposed on the third conductive layer 415. The first conductive layer 315 and the third conductive layer 415 may be formed of polycrystalline silicon having N-type conductivity. The second conductive layer 479 and the fourth conductive layer 413 may be formed of a metallic material (e.g., tungsten and / or tungsten silicide, etc.).

[0162] The second chip region 503 may further include an insulating layer 411 disposed on the third conductive structure 410. The second chip region 503 may further include a contact insulating layer 382 that contacts and combines with the substrate insulating layer 211 of the first chip region 203 between the first chip region 203 and the first conductive structure 379, a chip bonding pad 390 disposed in the contact insulating layer 382 and contacts and combines with the substrate bonding pad 214, and a via 385 disposed in the contact insulating layer 382 and electrically connects the chip bonding pad 390 and the first conductive structure 379.

[0163] The second chip region 503 may further include a first upper insulating layer 360 disposed between the first stacked structure 318 and the first conductive structure 379, a second upper insulating layer 370 disposed between the first upper insulating layer 360 and the first conductive structure 379, and a first buffer layer 317 disposed between the first stacked structure 318 and the second conductive structure 500.

[0164] The second chip region 503 may further include a third upper insulating layer 460 disposed between the second stacked structure 418 and the second conductive structure 500, a fourth upper insulating layer 470 disposed between the third upper insulating layer 460 and the second conductive structure 500, and a second buffer layer 417 disposed between the second stacked structure 418 and the third conductive structure 410.

[0165] The multiple vertical structures 333 and 433 may include a first vertical structure 333 and a second vertical structure 433. The first vertical structure 333 penetrates the first stacked structure 318 and the first buffer layer 317 and is electrically connected to the second conductive structure 500. The second vertical structure 433 penetrates the second stacked structure 418 and the second buffer layer 417 and is electrically connected to the third conductive structure 410.

[0166] Each of the multiple vertical structures 333 and 433 may have a reference Figures 1 to 11B The structure is identical to that of one of the described vertical structures 33. For example, when the semiconductor device including the second chip region 503 is rotated 180 degrees, each of the first vertical structure 333 and the second vertical structure 433 in the second chip region 503 may have the same structure as... Figure 2A The vertical structure 33 shown has the same structure. For example, each of the first vertical structure 333 and the second vertical structure 433 may include a structure that is respectively connected to the gate dielectric layer 36 ( Figure 2A (middle), channel semiconductor layer 38 ( Figure 2A (Chinese), data storage structure 46 ( Figure 2A (Middle), Core Area 55 ( Figure 2A (middle) and pad pattern 57 ( Figure 2AThe corresponding gate dielectric layers 336 and 436, channel semiconductor layers 338 and 438, data storage structures 346 and 446, core regions 355 and 455, and pad patterns 357 and 457 are shown in the middle.

[0167] The pad pattern 357 of the first vertical structure 333 can be electrically connected to the first conductive structure 379 via contact plugs 376 that penetrate the first upper insulating layer 360 and the second upper insulating layer 370. The pad pattern 357 of the first vertical structure 333 can be formed of polysilicon with N-type conductivity.

[0168] The channel semiconductor layer 338 of the first vertical structure 333 can be electrically connected to the first conductive layer 315 of the second conductive structure 500, and the pad pattern 457 of the second vertical structure 433 can be electrically connected to the second conductive layer 479e of the second conductive structure 500 through contact plugs 476 that penetrate the third upper insulating layer 460 and the fourth upper insulating layer 470. Multiple second conductive structures 500 can be provided.

[0169] The channel semiconductor layer 438 of the second vertical structure 433 can be electrically connected to the third conductive layer 415 of the third conductive structure 410.

[0170] The first conductive structure 379 can be configured as a first common source line, the second conductive structure 500 can be configured as a bit line, and the third conductive structure 410 can be configured as a second common line. Therefore, the second conductive structure 500 (bit line) can be disposed between the first vertical structure 333 and the second vertical structure 433. By providing the first vertical structure 333 and the second vertical structure 433 in the vertical direction, and by providing the second conductive structure 500 (bit line) between the first vertical structure 333 and the second vertical structure 433, the integration density of the semiconductor device can be improved.

[0171] Reference Figure 12D This section will describe a modified example of a semiconductor device. Figure 12D This is a cross-sectional view showing a modified example of a semiconductor device.

[0172] Reference Figure 1 and Figure 12D It can provide Figure 2A The lower structure 3 is shown. In another example, the lower structure 3 may be replaced by a semiconductor substrate.

[0173] The horizontal structure 614 may be disposed on the lower structure 3. The horizontal structure 614 may include a first horizontal pattern 610 and a second horizontal pattern 612 on the first horizontal pattern 610.

[0174] In an example embodiment, the horizontal structure 614 may be formed of polysilicon. For example, each of the first horizontal pattern 610 and the second horizontal pattern 612 may be formed of polysilicon.

[0175] In an example embodiment, at least one of the first horizontal pattern 610 and the second horizontal pattern 612 may be formed of polysilicon having N-type conductivity. For example, the first horizontal pattern 610 and the second horizontal pattern 612 may be formed of polysilicon having N-type conductivity.

[0176] The stacking structure 618 may be disposed on the horizontal structure 614. The stacking structure 618 may include a first group 618a and a second group 618b on the first group 618a.

[0177] The first group 618a may include alternatingly stacked first interlayer insulating layers 621a and first gate layers 624a. The lowest layer of the first interlayer insulating layer 621a and the first gate layer 624a may be the lowest first interlayer insulating layer, and the highest layer may be the highest first interlayer insulating layer.

[0178] The second group 618b may include a second interlayer insulating layer 621b and a second gate layer 624b. The lowest layer of the second interlayer insulating layer 621b and the second gate layer 624b may be the lowest second interlayer insulating layer, and the highest layer may be the highest second interlayer insulating layer. It can be configured with... Figure 2A The insulating pattern 27 is essentially the same. For example, the insulating pattern 27 may penetrate the second gate layer 624b, which is used as a select line in the second gate layer.

[0179] Vertical structures 633 may be provided that penetrate the stacked structure 618. Each vertical structure 633 may include a lower portion 633a of a first group 618a penetrating the stacked structure 618 and an upper portion 633b of a second group 618b penetrating the stacked structure 618 on the lower portion 633a. In an example embodiment, the width of the upper region of the lower portion 633a adjacent to the upper portion 633b may be greater than the width of the lower region of the upper portion 633b adjacent to the lower portion 633a.

[0180] Each vertical structure 633 may include a gate dielectric layer 636, a core region 655, a data storage structure 646, a channel semiconductor layer 638, and a pad pattern 657.

[0181] The core region 655 may extend in a vertical direction Z perpendicular to the upper surface of the lower structure 3, and may penetrate at least the first gate layer 624a and the second gate layer 624b. A pad pattern 657 may be disposed on the core region 655. A channel semiconductor layer 638 may cover the lower surface and side surfaces of the core region 655, and may extend to the side surfaces of the pad pattern 657. The channel semiconductor layer 638 may be in direct contact with the pad pattern 657. A data storage structure 646 may be inserted between the channel semiconductor layer 638 and the core region 655, and may be disposed below the pad pattern 657. The data storage structure 646 may include a first variable resistance layer 648 and a second variable resistance layer 650 with different vacancy concentrations. A gate dielectric layer 636 may surround the outer surface of the channel semiconductor layer 638. Furthermore, the gate dielectric layer 636 may cover the bottom surface of the channel semiconductor layer 638.

[0182] At least a portion of the horizontal structure 614 can penetrate the gate dielectric layer 636 and can contact the channel semiconductor layer 638. For example, a first horizontal pattern 610 of the horizontal structure 614 can penetrate the gate dielectric layer 636 and can contact the channel semiconductor layer 638.

[0183] In the vertical structure 633, the channel semiconductor layer 638, the data storage structure 646, and the core region 655 can respectively correspond to the channel semiconductor layer 38 ( Figure 2A and Figure 2B (Chinese), data storage structure 46 ( Figure 2A and Figure 2B (middle) and core area 55 ( Figure 2A and Figure 2B (in the middle). However, its exemplary embodiments are not limited thereto; the vertical structure 633 may be as described with reference to Figures 5A to 11B Modified as described in the example embodiments. For example, each vertical structure 633 may include references Figure 6A The first additional variable resistor layer 52a and the second additional variable resistor layer 52b are described. Figure 6A (Middle). As another example, each vertical structure 633 may also include a reference. Figures 7A to 9 The described buffer semiconductor layer 39 ( Figures 7A to 9 In this case, in each vertical structure 633, the buffer semiconductor layer 39 described in the above example embodiment ( Figures 7A to 9 (The middle) can be inserted between the channel semiconductor layer 638 and the data storage structure 646. As another example, each vertical structure 633 may also include a reference. Figure 10 The described buffer semiconductor layer 39 ( Figure 10 (middle) and interface layer 41 ( Figure 10 (Middle). As another example, each vertical structure 633 may also include a reference. Figure 11A The described barrier layer 56 ( Figure 11A middle).

[0184] In the following description, reference will be made to Figure 12E Describe an example of a modification to a semiconductor device. Figure 12E This is a cross-sectional view showing a modified example of a semiconductor device.

[0185] Reference Figure 1 and Figure 12E The stacked structure 718 can be disposed on the lower structure 703. The lower structure 703 can be... Figure 2A The lower structure 3 shown Figure 2A (Middle). The stacked structure 718 may include a first group 718a and a second group 718b on the first group 718a. The first group 718a may include alternatingly stacked first interlayer insulating layers 721a and first gate layers 724a. The lowest layer of the first interlayer insulating layer 721a and the first gate layer 724a may be the lowest first interlayer insulating layer, and the highest layer may be the highest first interlayer insulating layer. The second group 718b may include alternatingly stacked second interlayer insulating layers 721b and second gate layers 724b. The lowest layer of the second interlayer insulating layer 721b and the second gate layer 724b may be the lowest second interlayer insulating layer, and the highest layer may be the highest second interlayer insulating layer. It can be configured with... Figure 2B The insulating pattern 27 is substantially the same. For example, the insulating pattern 27 may penetrate the second gate layer 724b, which is used as a select line in the second gate layer.

[0186] A vertical structure 733 can be provided that penetrates the stacked structure 718. Each vertical structure 733 may include a lower portion 733a of a first group 718a that penetrates the stacked structure 718 and an upper portion 733b of a second group 718b that penetrates the stacked structure 718 on the lower portion 733a.

[0187] In the example embodiment, the width of the upper region of the lower part 733a adjacent to the upper part 733b may be greater than the width of the lower region of the upper part 733b adjacent to the lower part 733a.

[0188] The lower part 733a of the vertical structure 733 may include a semiconductor pattern 716, a first gate dielectric layer 736a disposed on the semiconductor pattern 716, a first core region 755a, a first data storage structure 746a, a first channel semiconductor layer 738a, and a first pad pattern 757a.

[0189] In the lower portion 733a of the vertical structure 733, the semiconductor pattern 716 can penetrate the lowest first gate layer of the first gate layer 724a. The first core region 755a can extend vertically in the Z direction on the semiconductor pattern 716 and can penetrate the other first gate layers of the first gate layer 724a. The first pad pattern 757a can be disposed on the first core region 755a. The first channel semiconductor layer 738a can cover the lower surface and side surface of the first core region 755a and can extend to the side surface of the first pad pattern 757a. The first data storage structure 746a can be inserted between the first channel semiconductor layer 738a and the first core region 755a and can be disposed below the first pad pattern 757a. The first gate dielectric layer 736a can surround the outer surface of the first channel semiconductor layer 738a. The first data storage structure 746a may include a first variable resistance layer 748 and a second variable resistance layer 750 with different vacancy concentrations.

[0190] In the example, semiconductor pattern 716 may be an epitaxial silicon layer grown from substrate 703.

[0191] In the example, the lower gate dielectric layer 717 may be disposed between the lowest first gate layer in the first gate layer 724a and the semiconductor pattern 716.

[0192] In the example, the first channel semiconductor layer 738a may be in contact with the semiconductor pattern 716.

[0193] In another example, the semiconductor pattern 716 may not be provided. When the semiconductor pattern 716 is not provided, the first channel semiconductor layer 738a may extend downward and may contact the substrate 703.

[0194] In the upper portion 733b of the vertical structure 733, a second core region 755b extends vertically in the Z direction on the first pad pattern 757a and penetrates the second gate layer 724b. The second pad pattern 757b is disposed on the second core region 755b. A second channel semiconductor layer 738b covers the lower and side surfaces of the second core region 755b and extends to the side surface of the second pad pattern 757b. A second data storage structure 746b is inserted between the second channel semiconductor layer 738b and the second core region 755b and is disposed below the second pad pattern 757b. The second gate dielectric layer 736b surrounds the outer surface of the second channel semiconductor layer 738b. The second data storage structure 746b can be formed of the same material as the first data storage structure 746a.

[0195] In the vertical structure 733, the first channel semiconductor layer 738a and the second channel semiconductor layer 738b, the first data storage structure 746a and the second data storage structure 746b, and the first core region 755a and the second core region 755b can respectively correspond to references. Figure 2A and Figure 2B The described channel semiconductor layer 38 ( Figure 2A and Figure 2B (Chinese), data storage structure 46 ( Figure 2A and Figure 2B (middle) and core area 55 ( Figure 2A and Figure 2B (in the middle). However, its exemplary embodiments are not limited thereto, and each of the lower part 733a and the upper part 733b of the vertical structure 733 may be referred to as Figures 5A to 11B Modified as described in the example embodiments above.

[0196] In the following description, reference will be made to Figures 13 to 15 A method for manufacturing a semiconductor device is described based on an example embodiment. Figure 13 , Figure 14A and Figure 15 It shows along Figure 1 A cross-sectional view of the region intercepted by line I-I' in the diagram. Figure 14B and Figure 14C This is a schematic diagram of each stage in the method of forming the data storage structure 46 according to the example embodiment.

[0197] Reference Figures 1 to 13 A lower buffer layer 17 and a stacked structure 18 may be sequentially formed on the lower structure 3. Forming the lower structure 3 may include: forming a peripheral circuit region 6 on a lower substrate 5, and then sequentially forming an upper substrate 13 and an impurity region 15 on the peripheral circuit region 6. The peripheral circuit region 6 may include peripheral leads 9 and a lower insulating layer 11 covering (e.g., embedding) the peripheral leads 9. The lower substrate 5 may be implemented as a monocrystalline silicon substrate, and the upper substrate 13 may be formed of, for example, metal, metal silicide, or polycrystalline silicon.

[0198] In another example embodiment, forming the lower structure 3 may include, for example, directly on the semiconductor substrate 105 ( Figure 12B Impurity region 115 (middle) is formed on the upper part. Figure 12B (in Chinese), such as Figure 12B As shown.

[0199] Forming the stacked structure 18 may include alternately and repeatedly forming interlayer insulating layers 21 and gate electrodes 24. The interlayer insulating layers 21 may include a lowermost interlayer insulating layer 21L and an uppermost interlayer insulating layer 21U. Of the interlayer insulating layers 21 and gate electrodes 24, the lowermost layer may be configured as the lowermost interlayer insulating layer 21L, and the uppermost layer may be configured as the uppermost interlayer insulating layer 21U. An insulating pattern 27 may be formed that penetrates the uppermost interlayer insulating layer 21U and extends downwards, and penetrates the upper gate electrode 24 (e.g., at least one select line 24S) in the gate electrode 24. The insulating pattern 27 may be formed of, for example, silicon oxide.

[0200] A hole 30 may be formed that penetrates the stacked structure 18 and the lower buffer layer 17. Forming the hole 30 may include: exposing the lower buffer layer 17 by etching the stacked structure 18, and exposing the lower structure 3 by etching the lower buffer layer 17.

[0201] Reference Figures 1 to 14A A vertical structure 33 can be formed in the hole 30. The vertical structure 33 can be formed as a reference. Figures 2A to 11B One of the vertical structures 33 to 33i is described. For example, vertical structure 33 may be as shown in reference to Figure 2A and Figure 2B The formation, for example, may include: forming a gate dielectric layer 36 on the sidewall of the hole 30, forming a channel semiconductor layer 38 in the hole 30 that covers the gate dielectric layer 36 and contacts the impurity region 15, forming a data storage structure 46 in the hole 30 that covers the channel semiconductor layer 38, forming a core region 55 that fills a portion of the hole 30, and forming a pad pattern 57 on top of the core region 55 to completely fill the hole 30.

[0202] The data storage structure 46 may include sequentially forming references Figure 2A and Figure 2B The first variable resistor layer 48 and the second variable resistor layer 50 are described. That is, reference will be made below. Figure 14B and Figure 14C An example describing the formation of the variable resistance material in data storage structure 46.

[0203] For example, refer to Figure 14B A first transition metal (e.g., Hf) can be deposited on the channel semiconductor layer 38, for example, via atomic layer deposition (ALD) to form a first transition metal layer 44. Then, a mixture of oxygen and an additional gas (e.g., hydrogen or nitrogen) can be deposited on the deposited first transition metal layer 44, for example, via ALD, to form a mixture layer 47a. The deposition of the first transition metal layer 44 and the mixture layer 47a can be repeated multiple times; for example, at least three ALD cycles can be performed to deposit a total of at least three transition metal layers 44 alternating with three mixture layers 47a. Figure 14BAs shown, the amount of additional gas (e.g., hydrogen) can be increased relative to the amount of oxygen during each deposition cycle, such that the amount of additional gas (e.g., hydrogen) can be gradually increased in each additional deposition mixture layer 47a. For example, refer to Figure 14B In the first deposition cycle, the amount of oxygen in the deposited mixture may be greater than the amount of hydrogen, while in the final deposition cycle, the amount of hydrogen in the deposited mixture may be greater than the amount of oxygen.

[0204] Once the first transition metal layer 44 and the mixture layer 47a have been deposited, they are processed to remove the additional gas, thereby forming (e.g., retaining) vacancies 45 to replace the removed atoms of the additional gas. Because the amount of additional gas increases in each deposition cycle, the amount of vacancies obtained after processing also increases with increasing distance from the channel semiconductor layer 38. Therefore, the increase in vacancy concentration with increasing distance from the channel semiconductor layer 38 refers to an increase in the amount of vacancies in the material obtained after removing the atoms of the additional gas.

[0205] For example, if the additional gas is hydrogen, the first transition metal layer 44 and the mixture layer 47a are treated with chlorine to remove hydrogen atoms from the mixture layer 47a, such that vacancies replace the removed hydrogen atoms. The resulting mixture layer 47a' with vacancies is then heated to form a data storage structure 46 on the channel semiconductor layer 38, such that along the path from the channel semiconductor layer 38 towards the vertical structure 33... Figure 14A The concentration of vacancy in the center-oriented direction of the mixture increases. Heating the mixture layer 47a' with vacancy may include, for example, annealing at about 650°C for about 360 seconds or at about 1100°C for about 1 second.

[0206] In another example, if the additional gas is nitrogen, the first transition metal layer 44 and the mixture layer 47a can be chemically treated (e.g., with phosphoric acid) to remove nitrogen atoms from the mixture layer 47a and create a vacancy concentration on the channel semiconductor layer 38 along the path from the channel semiconductor layer 38 toward the vertical structure 33. Figure 14A The data storage structure 46 is increased by center orientation (in the middle).

[0207] For example, the vacancy concentration in the data storage structure 46 can be adjusted by regulating the amount of additional gas in the mixture layer 47a. For example, the deposition time of the individual transition metal layers 44 and the mixture layer 47a can be controlled to adjust the vacancy concentration distribution, for example, by controlling the cycle length to have a constant profile (stepped profile of individual or multiple layers) or a gradually increasing profile (very short cycles, and increasing concentrations that provide a gradually increasing concentration profile).

[0208] In another example, refer to Figure 14CA first transition metal oxide (e.g., HfO) can be deposited on the channel semiconductor layer 38, for example, via atomic layer deposition (ALD) to form a first transition metal oxide layer 44', followed by, for example, deposition of an amorphous silicon layer 47b via ALD. The resulting structure is then heated, causing oxygen atoms to transfer from the first transition metal oxide layer 44' to the amorphous silicon layer 47b. The oxygen atoms removed from the first transition metal oxide layer 44' form vacancies in the first transition metal oxide layer 44', while the amorphous silicon layer 47b transforms into silicon oxide 47b'. The silicon oxide 47b' is removed, for example, via hydrofluoric acid (e.g., completely etched away) to expose the first transition metal oxide layer with vacancies, such that the resulting exposed first transition metal oxide layer with vacancies defines a data storage structure 46 on the channel semiconductor layer 38. For example, multiple cycles can be performed to gradually increase the vacancy concentration (e.g., repeated cycles of deposition, heating, and removal).

[0209] Reference Figure 1 and Figure 15 A first upper insulating layer 60 can be formed covering the vertical structure 33 and the stacked structure 18. An isolation trench 63 can be formed penetrating the first upper insulating layer 60, the stacked structure 18 and the lower buffer layer 17.

[0210] In another example embodiment, in order to form a reference Figure 12A The described gate electrode 124 ( Figure 12A In the middle), an isolation trench 63 can be formed that penetrates the stacked structure 18. A recess can be formed by partially etching the gate electrode 24 exposed through the isolation trench 63. The recess can be filled with a metallic material, and the lower structure 3 can be exposed by etching the lower buffer layer 17. The partially etched gate electrode 24 can be defined as the first gate portion 124a. Figure 12A (in the middle), and the metal material filling the depression can be defined as the second gate portion 124b ( Figure 12A middle).

[0211] Reference Figure 1 , Figure 2A and Figure 2B A separation structure 66 can be formed to fill the isolation trench 63. In an example embodiment, forming the separation structure 66 may include forming a first isolation pattern 68 covering the sidewalls of the isolation trench 63 and forming a second isolation pattern 70 filling each isolation trench 63. The first isolation pattern 68 may be inserted between the second isolation pattern 70 and the stacked structure 18. The first isolation pattern 68 may be formed of an insulating material, and the second isolation pattern 70 may be formed of a conductive material. In another example embodiment, the separation structure 66 may be formed of an insulating material.

[0212] A second upper insulating layer 73 may be formed on the separation structure 66 and the first upper insulating layer 60. A contact plug 76 may be formed that penetrates the first upper insulating layer 60 and the second upper insulating layer 73 and is electrically connected to the vertical structure 33. A wire 79 electrically connected to the contact plug 76 may be formed on the contact plug 76.

[0213] According to the above example embodiments, a semiconductor device including memory cells with improved distributed properties can be provided.

[0214] This document discloses exemplary embodiments, and although specific terminology is used, it is used and interpreted in a general and descriptive sense only and is not intended to be limiting. In some instances, as will be apparent to those skilled in the art since the filing of this application, unless otherwise specifically indicated, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: A stacked structure on a substrate, the stacked structure comprising alternating gate electrodes and insulating layers stacked along a first direction; A vertical opening extending through the stacked structure along the first direction, the vertical opening comprising a channel structure having: The core region spaced apart from the inner sidewall of the vertical opening; The semiconductor layer located between the inner wall of the vertical opening and the core region, and A variable resistive material located between the semiconductor layer and the core region, wherein the vacancy concentration in the variable resistive material varies along the width of the variable resistive material, such that the vacancy concentration of the portion of the variable resistive material closer to the core region is higher than the vacancy concentration of the portion of the variable resistive material closer to the semiconductor layer; and In the impurity region on the substrate, the semiconductor layer contacts the impurity region at the bottom of the channel structure.

2. The semiconductor device according to claim 1, wherein, The variable resistance material has a vacancy concentration that increases along its width in a direction from the semiconductor layer toward the center orientation of the channel structure.

3. The semiconductor device according to claim 2, wherein, The variable resistance material has a vacancy concentration that gradually increases along its width in a direction from the semiconductor layer toward the center orientation of the channel structure.

4. The semiconductor device according to claim 2, wherein, The increased vacancy concentration of the variable resistive material has a stepped profile along the width of the variable resistive material in a direction from the semiconductor layer toward the center orientation of the channel structure.

5. The semiconductor device according to claim 1, wherein, The variable resistance material includes transition metal oxides.

6. The semiconductor device according to claim 5, wherein, The variable resistance material includes aluminum oxide and hafnium oxide.

7. The semiconductor device of claim 1, further comprising a pad pattern on top of the channel structure, the pad pattern electrically connecting the semiconductor layer to a bit line, and the pad pattern at least covering the top surface of the variable resistivity material.

8. The semiconductor device according to claim 7, further comprising: A barrier insulating layer is located between the bottom of the pad pattern and the top surface of the variable resistivity material.

9. The semiconductor device according to claim 7, further comprising: A barrier insulating layer that directly contacts each of the bottom of the pad pattern and the top surface of the variable resistor material.

10. The semiconductor device of claim 1, further comprising a buffer layer between the variable resistance material and the semiconductor layer, the buffer layer comprising amorphous silicon.

11. The semiconductor device according to claim 1, wherein: In the variable resistance material, the vacancy concentration increases in the direction from the semiconductor layer to the core region orientation.

12. The semiconductor device according to claim 11, wherein, When viewed from above, the vacancy concentration in the variable resistive material and each of the semiconductor layers surrounds the entire perimeter of the core region, with the concentration increasing in the radial direction from the semiconductor layer to the core region.

13. A semiconductor device, comprising: A stacked structure on a substrate, the stacked structure comprising alternating gate electrodes and insulating layers stacked along a first direction; A vertical opening extending through the stacked structure along the first direction, the vertical opening comprising a channel structure having: The core region spaced apart from the inner sidewall of the vertical opening, The semiconductor layer located between the inner wall of the vertical opening and the core region. A variable resistive material located between the semiconductor layer and the core region, wherein the vacancy concentration in the variable resistive material varies along the width of the variable resistive material, such that the vacancy concentration of the portion of the variable resistive material closer to the core region is higher than the vacancy concentration of the portion of the variable resistive material closer to the semiconductor layer, and A buffer layer between the variable resistance material and the semiconductor layer, wherein the entire buffer layer comprises a material having a structure containing grains smaller than those of the semiconductor layer; as well as In the impurity region on the substrate, the semiconductor layer contacts the impurity region at the bottom of the channel structure.

14. The semiconductor device according to claim 13, wherein, The buffer layer comprises amorphous silicon.

15. The semiconductor device according to claim 14, wherein, The variable resistance material comprises a transition metal oxide, and the semiconductor layer comprises polycrystalline silicon.

16. The semiconductor device according to claim 13, wherein, The buffer layer comprises a first polycrystalline silicon, the variable resistance material comprises a transition metal oxide, and the semiconductor layer comprises a second polycrystalline silicon whose grains are larger than those of the first polycrystalline silicon.

17. The semiconductor device according to claim 13, wherein, The thickness of the buffer layer is less than the thickness of the semiconductor layer.

18. The semiconductor device of claim 13, further comprising an interface layer between the buffer layer and the semiconductor layer, the interface layer comprising an oxidized surface of the semiconductor layer.

19. A semiconductor device, comprising: A stacked structure on a substrate, the stacked structure comprising alternating gate electrodes and insulating layers stacked along a first direction; A vertical opening extending through the stacked structure along the first direction, the vertical opening comprising a channel structure having: The core region spaced apart from the inner sidewall of the vertical opening, A polycrystalline silicon semiconductor layer located between the inner wall of the vertical opening and the core region. A variable resistive material located between the polycrystalline silicon semiconductor layer and the core region, wherein the vacancy concentration in the variable resistive material varies along the width of the variable resistive material, such that the vacancy concentration of the portion of the variable resistive material closer to the core region is higher than the vacancy concentration of the portion of the variable resistive material closer to the polycrystalline silicon semiconductor layer, and An amorphous silicon buffer layer between the variable resistance material and the polycrystalline silicon semiconductor layer; as well as In the impurity region on the substrate, the polycrystalline silicon semiconductor layer contacts the impurity region at the bottom of the channel structure.

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