Imaging system having a successive approximation register (SAR) analog-to-digital converter with reduced nonlinearity

Abstract

The present disclosure relates to an imaging system having a successive approximation register (SAR) analog-to-digital converter with reduced nonlinearity. An image sensor may include an array of imaging pixels arranged in rows and columns. Each column of imaging pixels may be coupled to an analog-to-digital converter for converting an analog imaging signal from the pixel into a digital signal. The analog-to-digital converter may be implemented as a separate successive approximation register (SAR) analog-to-digital converter (ADC). The separate SAR ADC may include a coarse segment and a fine segment. During a reset sampling phase, a reset level is sampled while a predetermined blanking pulse value is applied to the coarse segment and the fine segment. During the reset conversion, a reset code is obtained. During the signal sampling phase, the signal level is sampled using only the inverse phase of the reset code of the fine segment. During the signal conversion, a signal code is obtained. Operating in this manner, the differential nonlinearity of the ADC is minimized.

Description

Technical Field

[0001] This relates generally to analog-to-digital converters, and more particularly to image sensors having successive approximation register (SAR) analog-to-digital converters. Background Art

[0002] Modern electronic devices, such as cell phones, cameras, and computers, often use digital image sensors. An image sensor (sometimes called an imager) can be formed from an array of two-dimensional image sensing pixels. The array of image sensing pixels is typically arranged into rows and columns of pixels. Each pixel includes a photosensitive layer that receives incident photons (light) and converts the photons into an electrical charge. Column sensing circuitry is typically coupled to each pixel column to read out an image signal from the image pixel.

[0003] Image sensors typically include analog-to-digital conversion circuitry for converting the analog signals generated by image pixels into digital signals. In one configuration, image sensors are equipped with a successive approximation register (SAR) analog-to-digital converter (ADC). Conventional SAR ADCs typically include a capacitive digital-to-analog converter (DAC) array that is divided into coarse and fine segments to make the ratio of capacitors more manageable in terms of area and layout.

[0004] However, because the gain ratio or scaling factor of the two sections may depend on the parasitic capacitance of the fine array, this split SAR architecture introduces differential nonlinearity (DNL) errors at the coarse bit transitions. In practice, even in low-light conditions between the reset and signal transition phases, coarse bit transitions may still occur, which will lead to undesirable visual artifacts. Even without a split array, DNL may also worsen towards the most significant bit (MSB) code transition.

[0005] The implementation plan of this article emerges in this context. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram of an illustrative electronic device according to one embodiment.

[0007] Figure 2 is a schematic diagram of an exemplary image pixel array in an image sensor according to one embodiment.

[0008] Figure 3A and Figure 3B is a circuit diagram of an illustrative analog-to-digital converter (ADC) that may be included in an image sensor according to some embodiments.

[0009] Figure 4 To show the operation Figure 3A A timing diagram of the ADC is shown in FIG.

[0010] Figure 5 Schematic diagram showing how a small pixel signal traverses a coarse digital-to-analog (DAC) range, leading to differential nonlinearity (DNL) errors, where the LSB DAC range is repeated across the full ADC DAC range.

[0011] Figure 6 To illustrate the operation according to the embodiment Figure 3A The timing diagram of the ADC shown is another way to ensure that there are no coarse bit transitions when the signal level reaches the full-scale value of the fine bit.

[0012] Figure 7 For operation according to the embodiment Figure 3A or Figure 3B Flowchart of illustrative steps for minimizing DNL in an ADC of the type shown.

[0013] Figure 8 Schematic diagram showing how the pixel signal is kept within the fine DAC range to remove the undesirable effects of DNL according to an embodiment. DETAILED DESCRIPTION

[0014] Embodiments of the present invention relate to image sensors, and more particularly, to analog-to-digital conversion within image sensors. Those skilled in the art will recognize that the exemplary embodiments of the present invention may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail to avoid unnecessarily obscuring the embodiments of the present invention.

[0015] Figure 1 is a schematic diagram of an exemplary electronic device according to one embodiment of the present invention. Figure 1 As shown, imaging system 10 can be a portable imaging system such as a camera, an automotive imaging system, a mobile phone, a video camera, a video surveillance system, or any other imaging device desired to capture digital image data. System 10 can include a camera module 12 for converting incident light into digital image data. Camera module 12 can include a lens array 14 and a corresponding image sensor 16. Lenses 14 and image sensors 16 can be mounted in the same package and can provide image data to processing circuitry 18. Image sensor 16 can include one or more image sensors, and lens array 14 can include one or more corresponding lenses.

[0016] Processing circuitry 18 may include one or more integrated circuits (e.g., image processing circuitry, a microprocessor, storage devices such as random access memory and non-volatile memory, etc.) and may be implemented using components that are separate from and / or form part of camera module 12 (e.g., circuitry that forms part of an integrated circuit that includes image sensor array 16 or that forms part of an integrated circuit within camera module 12 associated with image sensor array 16). If desired, image data captured and processed by camera module 12 may be further processed and stored using processing circuitry 18. If desired, the processed image data may be provided to an external device (e.g., a computer or other device) using a wired and / or wireless communication path coupled to processing circuitry 18.

[0017] Each pixel in image sensor 16 can receive light of a given color by providing a color filter for each image pixel. The color filters used for the image sensor pixels in the image sensor can be, for example, a red filter, a blue filter, and a green filter. Other color filters can also be used, such as a white filter, a dual-band IR-cut filter (e.g., a filter that allows transmission of visible light as well as a certain range of infrared light emitted by an LED light), and the like.

[0018] Figure 2 FIG is a schematic diagram of an exemplary image pixel array in an image sensor. Figure 2 As shown, the image sensor (e.g., Figure 1 Image sensor 16 may include a pixel array 202 having a plurality of pixels 201 (sometimes referred to herein as image pixels 201 or image sensor pixels 201) and row control circuitry 204 coupled to image pixel array 202. Row control circuitry 204 may provide pixel control signals (e.g., row select signals, pixel reset signals, charge transfer signals, etc.) to pixels 201 via corresponding row control lines 203 to control the capture and readout of images using the image sensor pixels in array 202.

[0019] The image sensor 16 may include column control and readout circuitry 212 and control and processing circuitry 208, which are coupled to the row control circuitry 204 and the column circuitry 212. The column control circuitry 212 may be coupled to the array 202 via a plurality of column lines 211. For example, each column of pixels 201 in the array 202 may be coupled to a corresponding column line 211. A corresponding analog-to-digital converter (ADC) 214 and column amplifier 216 may be inserted on each column line 211 to amplify the analog signals captured by the array 202 and convert the captured analog signals into corresponding digital pixel data. The column control and readout circuitry 212 may be coupled to external hardware, such as processing circuitry. The column control and readout circuitry 212 may perform column readout based on signals received from the control and processing circuitry 208. The column control and readout circuitry 212 may include column ADC circuitry 214 and column amplifier 216.

[0020] Amplifier 216 can be configured to receive an analog signal (e.g., an analog reset or image signal) from pixel array 202 and amplify the analog signal. The analog signal can include data from a single column of pixels or from multiple columns of pixels, depending on the application. ADC 214 can receive the amplified analog signal from amplifier 216 and perform an analog-to-digital conversion operation on the analog signal to generate digital data. The digital data can be transmitted to column control and readout circuitry 212 for processing and readout.

[0021] Figure 3A FIG. 2 is a circuit diagram of an exemplary analog-to-digital converter (ADC) circuit 214 that may be included in an image sensor. Figure 3A As shown, ADC 214 may include a comparator circuit 302, an ADC controller 304 configured to receive a signal from comparator 302, a first digital-to-analog converter (DAC) section 310, and a second DAC section 312. Comparator 302 may have a first (+) input that receives a common-mode input voltage Vcm and a second (-) input coupled to first DAC section 310. The common-mode voltage is a direct current (DC) voltage that may be set equal to a reset level (as an example) so that ADC 214 outputs zero when reset.

[0022] The first DAC section 310 may include a first array of capacitors C6-C12, each of which is selectively coupled to a low voltage Vlo or a high voltage Vhi via a corresponding switch. For example, the bottom plate of capacitor C12 may be coupled to Vhi by activating control bit b12 to turn on the corresponding Vhi switch, or may be coupled to Vlo by deactivating control bit b12 to turn on the corresponding Vlo switch. Similarly, the bottom plate of capacitor C6 may be coupled to Vhi by activating control bit b6 to turn on the corresponding Vhi switch, or may be coupled to Vlo by deactivating control bit b6 to turn on the corresponding Vlo switch. Voltages Vlo and Vhi may generally be independent of the common-mode voltage Vcm. The top plates of capacitors C6-C12 may be coupled to the second (-) terminal of comparator 302. The first section 310 may sometimes be referred to as a most significant bit (MSB) DAC or a "coarse" DAC section.

[0023] An input voltage Vin can be selectively applied to the top plate of the MSB capacitor via input switch 306. Input switch 306 can be activated by asserting input control signal Vs1. Input voltage Vin can be equal to Vsig when reading out an image signal from a selected image sensor pixel, or can be equal to reset voltage Vrst when reading out a reset level from a selected image pixel.

[0024] The second DAC section 312 may include a second array of capacitors C0-C5, each of which is selectively coupled to a low voltage Vlo or a high voltage Vhi via a corresponding switch. For example, the bottom plate of capacitor C5 can be coupled to Vhi by asserting control bit b5 to turn on the corresponding Vhi switch, or can be coupled to Vlo by deasserting control bit b5 to turn on the corresponding Vlo switch. Similarly, the bottom plate of capacitor C0 can be coupled to Vhi by asserting control bit b0 to turn on the corresponding Vhi switch, or can be coupled to Vlo by deasserting control bit b0 to turn on the corresponding Vlo switch. The top plates of capacitors C6-C12 can be coupled to the coarse section via coupling capacitor Cc. The use of coupling capacitor Cc can help make the size ratio of the capacitors between the two sections more manageable in terms of area and layout. The second section 312 is sometimes referred to as the least significant bit (LSB) DAC or "fine" DAC section. As the names suggest, the MSB DAC section exhibits coarser resolution, while the LSB DAC section exhibits finer resolution.

[0025] A reference voltage, Vref_top, can be selectively applied to the top plate of the LSB capacitor via reference switch 308. Reference switch 308 can be activated by asserting reference control signal Vs2. The top plate of the LSB capacitor can also be coupled to a ballast capacitor, Cballast, which can include parasitic capacitance of nearby interconnect wiring. ADC 214 configured in this manner is sometimes referred to as a "split SAR" ADC circuit. Figure 3A The ADC 214 of FIG. 214 (where the coarse segment includes seven bits of resolution and the fine segment includes six bits of resolution) is illustrative only and is not intended to limit the scope of the present embodiment. If desired, the ADC 214 can have a split architecture where the MSB and LSB DACs can display any suitable resolution.

[0026] Figure 4 To show the operation Figure 3A A timing diagram of one embodiment of an ADC 214 of the type shown is shown. At time t1, with the input voltage Vinput at the reset level Vrst and the bottom plate of the LSB DAC set at the pedestal level, control signals Vs1 and Vs2 are pulsed high. The pedestal level is a programmable preset value that is typically used to correct for inherent offsets that may be associated with the comparator 302. By applying a reference voltage Vref_top to the top plate of the fine segment while selectively enabling a predetermined pattern of control bits b0-b5, the pedestal value can be loaded into the LSB DAC. Even though the MSB DAC may have a non-zero pedestal value, this value will remain constant from reset to signal transition.

[0027] At time t2 , a reset conversion operation may be performed to read out the reset voltage level from the selected image pixel (ie, ADC 214 may output a digital code indicative of the reset voltage level Vrst received at time t1 ).

[0028] At time t3, the selected image pixel can output an image signal, which changes the ADC input voltage Vinput to the Vsig level. At time t4, the control signal Vs1 is pulsed high to pass Vsig to the MSB top plate, while the bottom plate of the LSB DAC is set to a predetermined pedestal level. The pedestal level provided to the LSB DAC bottom plate may be the same at times t1 and t4.

[0029] At time t5 , a signal conversion operation may be performed to read out the image signal level from the selected image pixel (ie, ADC 214 may output a digital code indicative of the signal voltage level V sig received at time t4 ).

[0030] use Figure 4An ADC operating in steps of 100 can introduce differential nonlinearity (DNL) errors at the transition between the fine LSB and coarse MSB bits because the gain ratio of these two sections depends on the parasitic capacitance of the fine DAC array (see Cballast). This creates inherent matching challenges between the fine LSB DAC and the coarse MSB DAC in a split SAR array. DNL can cause undesirable visual artifacts in the image sensor, especially in darkness or very low-light conditions.

[0031] Still refer to Figure 4 During the sampling of Vrst and Vref_top at time t1, the switches of the capacitive DAC are configured to a blanking pulse value, which is an offset value typically used to improve the input operating voltage range of the ADC. The blanking pulse value is typically a fraction of the ADC full-scale value and typically has a non-zero bit in the coarse region. For example, in a 7-MSB / 6-LSB split DAC array, such as Figure 3A In the array of split SAR ADCs shown in , if the blanking pulse value is 1 / 32 of the full-scale value, the coarse value of the reset transition will be non-zero. Even when the signal is very close to the reset value (i.e., even in very low light conditions), there is a high probability that some coarse bits of the signal transition will differ from the coarse bits of the reset transition due to dark current and other noise sources.

[0032] For example, consider the case where the reset value is "0010101111110" and the signal value is "0010110000001". Even though the reset value and the signal value differ by only three LSBs, the change still propagates to the 8th bit, which crosses into the coarse MSB segment. Figure 5 5 shows a pixel signal with increased pedestal offset that may cross the MSB and LSB DAC separation 500. As described above, this crossover can potentially introduce significant noise into the decremented value of the correlated double sampling (CDS) operation due to the DNL associated with the coarse bit transitions. This noise is exacerbated in low noise conditions where noise accounts for a significant portion of the difference between the signal value and the reset value.

[0033] According to an embodiment, a method of operating a split SAR ADC is provided that addresses this problem by ensuring that the coarse MSB bit does not change between the reset value and the signal value for all net (signal minus reset) values ​​up to approximately the full-scale value of the fine segment. This can be achieved by dynamically setting the offset value to a level at which the LSB DAC range is maximized when converting small pixel signal values ​​to avoid flipping the coarse bit in the MSB DAC. In a suitable arrangement, the programmable offset value can be set to an inverted version of the reset ADC value (rather than the blanking pulse value) during the pixel signal conversion phase. Additional margin can also be provided to account for random noise. Doing so will ensure that DNL caused by coarse bit conversions is prevented in low light conditions where image quality is most susceptible to noise.

[0034] Figure 6 To show the operation Figure 3A A timing diagram of an exemplary method for an ADC 214 of the type shown, which ensures that there are no coarse bit transitions for signal levels approximately reaching the full-scale value of the fine bits. Prior to time t1, the blanking pulse value should be set. There is generally a certain amount of flexibility in the level of the blanking pulse value, but the fine bits of the blanking pulse should correspond to the maximum fine value minus the small value noise_offset. For example, if the fine segment is 6 bits and noise_offset is equal to 5, the fine blanking pulse value should be set to 63 minus 5 (equal to 58). Therefore, the total blanking pulse value can be equal to (m*64+58), where the parameter m is adjusted for optimal performance. This optimized blanking pulse value can be loaded into the SARDAC by selectively enabling a predetermined pattern of control bits b0-b12.

[0035] At time t1 during the auto-zero phase, when the input voltage Vinput is at the reset level Vrst and the bottom plate of the LSB DAC is set at the optimized blanking pulse level, the control signals Vs1 and Vs2 can be pulsed high. Configured in this manner, the top plate of the coarse segment is sampled using the reset signal Vrst, while the top plate of the fine segment is sampled using the predetermined reference voltage Vref_top.

[0036] At time t2, a reset conversion operation may be performed to read out the reset voltage level from the selected image pixel (e.g., ADC 214 may output a digital code indicative of the reset voltage level Vrst received at time t1). The final digital value should be close to the pedestal level, but the fine value may have some deviation due to noise, charge injection, offset, etc. The final fine value (referred to herein as the fine reset code "fr") can range from zero to its full-scale value, which is 63 in the 6-bit LSB DAC example.

[0037] At time t3, the selected image pixel may output an image signal that changes the ADC input voltage Vinput to the Vsig level. At time t4, the control signal Vs1 is pulsed high to pass Vsig to the MSB top plate, while setting the fine segment using the inverted version of fr obtained during the reset transition (see arrow 600). In other words, the inverted reset transition value is based on, depends on, or is a function of fr. This performs an analog domain subtraction on the fine bits. The bits of the coarse segment should remain the same as the blanking pulse value at time t1. Figure 4 In the example shown, the reference voltage Vref_top is sampled onto the top plate of the fine segment (e.g., also by pulsing the high control signal Vs2) to keep the voltage of the Vs2 switch in phase with the reset sampling to minimize DNL caused by the voltage dependence of the junction capacitance of the switch. This is optional. If the voltage dependence of the junction capacitance of the switch is sufficiently small, there is no need to activate the Vs2 switch at time t4.

[0038] At time t5 , a signal conversion operation may be performed to read out the image signal level from the selected image pixel (ie, ADC 214 may output a digital code indicative of the signal voltage level V sig received at time t4 ).

[0039] Figure 7 For operation Figure 3A FIG2 is a flow chart illustrating exemplary steps for minimizing DNL using an ADC of the type shown. At step 700, the floor of the coarse and fine segments is set using predetermined blanking pulse values, where the fine blanking pulse value is set equal to the maximum fine value minus noise_offset. At step 702, a comparator autozero phase is performed while Vrst is sampled onto the top plate of the MSB DAC capacitor and the reference voltage Vref_top is sampled onto the top plate of the LSB DAC capacitor.

[0040] At step 704, the ADC performs a reset conversion to obtain the corresponding digital fine value fr. At step 706, the image signal Vsig is sampled while maintaining the same coarse blanking pulse value but setting the fine blanking pulse value based on fr, but with all bits inverted. The top plate of the LSB capacitor can optionally be resampled using the reference voltage Vref_top to minimize DNL. At step 708, the ADC performs a signal conversion to obtain the signal code.

[0041] Typically, the converted coarse and fine bits are simply concatenated and considered the output of the ADC. In conventional digital correlated double sampling (DCDS), the concatenated value of the reset conversion is simply subtracted from the concatenated value of the signal conversion.

[0042] However, in step 710, the reset transition fine bits should not be subtracted from the signal transition fine bits due to the change in the LSB DAC bit during the signal sampling phase. The blanking pulse adjustment of the inverted version of fr effectively simulates this subtraction, but is implemented in the analog domain. Therefore, post-processing only needs to perform partial DCDS by: (1) subtracting only the reset transition coarse bits from the signal transition coarse bits, (2) subtracting only noise_offset from the signal transition fine bits (i.e., from the fine bits of the signal code), and (3) adding the results from (1) and (2) to obtain the final ADC output. In other words, digital correlated double sampling is performed only on the coarse DAC section and not on the fine DAC section. If noise_offset is zero, the fine bits can be concatenated to the subtracted coarse bits. If noise_offset is not zero, this subtraction can be performed later in the fine signal transition bits because it is constant in the pixel column, which can help simplify the column logic circuit.

[0043] Operating the ADC using this scheme helps ensure that the coarse bits of the MSB DAC array do not change between the reset transition and the signal transition for (signal – reset) values ​​between –noise_offset and (LSB full-scale value – noise_offset). Figure 8 This improvement is shown in FIG, where the pixel signal with the increased noise-_offset is prevented from crossing the MSB and LSB DAC separation 500. Effectively, the ADC transfer curve is shifted downward from the reset transition phase to the signal transition phase by a value equal to (fr minus noise_offset) so that the signal level is exactly the same as the reset level and the fine output after the signal conversion will be equal to noise_offset. Figure 8 In the example, noise_offset' can represent the sum of the MSB bits of the blanking pulses with noise_offset, while noise-_offset' can represent the MSB bit of noise_offset' because the LSB portion has been subtracted. By preventing the coarse bit from transitioning between the reset transition and the signal transition, the DNL associated with the coarse bit is avoided, which results in better image quality in low light conditions. The value of noise_offset should be a small fraction of the LSB range to cover any noise and the worst-case DNL of the ADC. For example, if the RMS (root mean square) noise is 2LSB and the worst-case DNL is 4LSB, then noise_offset can be three times the RMS noise (in other words, 3 sigma) plus the worst-case DNL, ​​or 10LSB. Setting noise_offset too high relative to the total LSB range will reduce the positive range of the final output, for which the coarse bit will not change.

[0044] In some embodiments, the reference voltage Vref_top should be selected to allow swing on the top plate of the fine segment without turning on any diffused junctions or parasitic metal oxide semiconductor devices. In the case where Vs2 pulses high during T4, the reference voltage Vref_top should be at least the full-scale voltage (Vhi minus Vlo) away from either supply voltage, ignoring noise_offset. Therefore, if the positive supply voltage is 3V and (Vhi-Vlo) is 1V, then Vref_top can be any value between 1V and 2V (i.e., 3-1=2).

[0045] in Figures 6 to 8 The technology is applied to Figure 3A The device configuration of ADC 214 is merely illustrative and is not intended to limit the scope of the present embodiment. If desired, the improved scheme for minimizing DNL can be applied to devices such as Figure 3B Other ADC architectures (e.g., other SAR ADCs or split SAR ADC arrangements) are shown. Figure 3B As shown, ADC 214' uses a split reference instead of coupling capacitor Cc (e.g., the top plate terminal of the fine section is directly connected to the top plate terminal of the coarse section). The coarse section will still use reference voltages Vlo and Vhi, but the fine section will now use attenuated reference voltages Vlo' and Vhi'. The range (Vhi'-Vlo') is only a fraction of (Vhi-Vlo), and can be 1 / 2, 1 / 4, 1 / 8, 1 / 16, etc. Using a smaller reference voltage range for the LSB DAC section simulates the attenuation achieved using coupling capacitor Cc. Removing coupling capacitor Cc also eliminates the need for the Vs2 sampling switch.

[0046] According to an embodiment, an image sensor is provided, comprising a plurality of image sensor pixels, output lines coupled to the plurality of image sensor pixels, and a data converter configured to receive signals from the output lines, wherein the data converter comprises a coarse digital-to-analog converter (DAC) section having a first array of capacitors and a fine digital-to-analog converter (DAC) section having a second array of capacitors, wherein the fine DAC section is configured to receive a blanking pulse value during a reset sampling phase and to receive a dynamically adjustable value different from the blanking pulse value during a signal sampling phase to reduce differential nonlinearity at the data converter.

[0047] According to another embodiment, the data converter is optionally further configured to perform a reset conversion operation to obtain a reset code.

[0048] According to another embodiment, the dynamically adjustable value is optionally a function of a reset code.

[0049] According to another embodiment, the dynamically adjustable value is optionally an inverted version of the reset code.

[0050] According to another embodiment, the coarse DAC section is optionally configured to receive the same blanking pulse value during the reset sampling phase and the signal sampling phase.

[0051] According to another embodiment, the data converter is optionally configured to output a first coarse bit during a reset conversion operation and a second coarse bit during a signal conversion operation, and the image sensor is configured to calculate a difference between the first coarse bit and the second coarse bit.

[0052] According to another embodiment, the blanking pulse value has a fine bit, which is optionally equal to the difference between the maximum value of the fine DAC segment minus the noise offset value.

[0053] According to another embodiment, the data converter is optionally further configured to perform a signal conversion operation to obtain a signal code, and the image sensor is configured to subtract the noise offset value from only the fine bits of the signal code.

[0054] According to another embodiment, the data converter is optionally a successive approximation register (SAR) digital-to-analog converter.

[0055] According to another embodiment, the fine DAC section is coupled to the coarse DAC section, optionally via a coupling capacitor, and a reference voltage is selectively applied to a top plate terminal of the fine DAC section.

[0056] According to another embodiment, the fine DAC section is optionally directly connected to the coarse DAC section, wherein a first range of voltages is selectively applied to the bottom plate terminal of the coarse DAC section, and wherein a second range of voltages, optionally only a portion of the first range, is selectively applied to the bottom plate terminal of the fine DAC section.

[0057] According to an embodiment, a method of operating an image sensor including a data converter having a split architecture with a most significant bit (MSB) segment and a least significant bit (LSB) segment is provided, the method including sampling a reset signal, providing a fine blanking pulse value to the LSB segment when sampling the reset signal, performing a reset conversion to obtain a fine reset code for the LSB segment, sampling an image signal, and providing an adjustable value different from the fine blanking pulse value to the LSB segment when sampling the image signal to minimize differential nonlinearity of the data converter.

[0058] According to another embodiment, wherein providing the adjustable value optionally includes providing the value as an inverted version of the fine reset code.

[0059] According to another embodiment, the method optionally further includes providing a coarse blanking pulse value to the MSB segment when sampling the reset signal, and providing a coarse blanking pulse value to the MSB segment when sampling the image signal.

[0060] According to another embodiment, the method optionally further includes performing a reset conversion to obtain a coarse reset code for the MSB segment, performing a signal conversion to obtain a coarse signal code for the MSB segment and a fine signal code for the LSB segment, subtracting the coarse reset code from the coarse signal code, and subtracting only the noise offset value from the fine signal code without subtracting the fine reset code from the fine signal code.

[0061] According to an embodiment, an analog-to-digital converter circuit is provided, the analog-to-digital converter circuit including a comparator having an input, a coarse digital-to-analog converter (DAC) portion coupled to the input of the comparator, and a fine digital-to-analog converter (DAC) portion coupled to the input of the comparator, wherein different offset values ​​are applied to the fine DAC portion during a reset sampling phase and during a signal sampling phase such that there is no coarse bit conversion between a reset conversion operation after the reset sampling phase and a signal conversion operation after the signal sampling phase.

[0062] According to another embodiment, a blanking pulse offset value is optionally applied to the fine DAC portion during the reset sampling phase, and a dynamically adjustable offset value different from the blanking pulse offset value is optionally applied to the fine DAC portion during the signal sampling phase.

[0063] According to another embodiment, the reset conversion operation optionally outputs a fine reset value for the fine DAC portion, and the dynamically adjustable offset value is optionally set based on the fine reset value obtained from the reset conversion operation.

[0064] According to another embodiment, digital correlated double sampling is optionally performed only on the coarse DAC part and not on the fine DAC part.

[0065] According to another embodiment, the signal conversion operation outputs a fine signal value for the fine DAC portion, and no digital subtraction of the fine reset value from the fine signal value is required because the subtraction of the fine reset value is already performed in the analog domain via applying different offset values ​​to the fine DAC portion.

[0066] The foregoing is merely an illustrative description of the principles of the present invention, and those skilled in the art may make various modifications. The above embodiments may be implemented individually or in any combination.

Claims

1. An image sensor, comprising: multiple image sensor pixels; an output line coupled to the plurality of image sensor pixels; and a data converter configured to receive a signal from the output line, wherein the data converter comprises: a coarse digital-to-analog converter (DAC) section having a first array of capacitors; and a fine digital-to-analog converter DAC section having a second array of capacitors, wherein the fine digital-to-analog converter DAC section is configured to receive a blanking pulse value during a reset sampling phase and to receive a dynamically adjustable value different from the blanking pulse value during a signal sampling phase to reduce differential nonlinearity of the data converter. 2 . The image sensor of claim 1 , wherein the data converter is further configured to perform a reset conversion operation to obtain a reset code, and wherein the dynamically adjustable value is an inverted version of the reset code. 3 . The image sensor of claim 1 , wherein the coarse digital-to-analog converter (DAC) section is configured to receive the same blanking pulse value during the reset sampling phase and the signal sampling phase.

4. The image sensor of claim 1 , wherein the data converter is configured to output a first coarse bit during a reset conversion operation and to output a second coarse bit during a signal conversion operation, and wherein the image sensor is configured to calculate a difference between the first coarse bit and the second coarse bit.

5. The image sensor of claim 1 , wherein the blanking pulse value has fine bits, the fine bits being equal to a maximum value of the fine digital-to-analog converter (DAC) section minus a noise offset value, wherein the data converter is further configured to perform a signal conversion operation to obtain a signal code, and wherein the image sensor is configured to subtract the noise offset value only from the fine bits of the signal code. 6 . The image sensor of claim 1 , wherein the data converter comprises a Successive Approximation Register (SAR) digital-to-analog converter.

7. A method of operating an image sensor, the image sensor including a data converter having a split architecture, the split architecture having a most significant bit (MSB) segment and a least significant bit (LSB) segment, the method comprising: Sampling the reset signal; providing a fine blanking pulse value to the least significant bit (LSB) section when sampling the reset signal; performing a reset conversion to obtain a fine reset code of the least significant bit (LSB) segment; Sampling the image signal; and An adjustable value different from the fine blanking pulse value is provided to the least significant bit (LSB) section when sampling the image signal to minimize differential nonlinearity of the data converter.

8. The method according to claim 7, further comprising: providing a coarse blanking pulse value to the most significant bit (MSB) section when sampling the reset signal; providing the coarse blanking pulse value to the most significant bit (MSB) section when sampling the image signal; performing the reset conversion to obtain a coarse reset code for the most significant bit (MSB) segment; performing signal conversion to obtain a coarse signal code of the MSB segment and a fine signal code of the LSB segment; subtracting the coarse reset code from the coarse signal code; and Only a noise offset value is subtracted from the fine signal code without subtracting the fine reset code from the fine signal code.

9. An analog-to-digital converter circuit, comprising: a comparator having an input; a coarse digital-to-analog converter (DAC) section coupled to the input of the comparator; and a fine digital-to-analog converter (DAC) portion coupled to the input of the comparator, wherein different offset values ​​are applied to the fine digital-to-analog converter (DAC) portion during a reset sampling phase and during a signal sampling phase such that there is no coarse bit transition between a reset conversion operation after the reset sampling phase and a signal conversion operation after the signal sampling phase.

10. The analog-to-digital converter circuit according to claim 9, wherein: applying a blanking pulse offset value to the fine digital-to-analog converter (DAC) portion during the reset sampling phase; applying a dynamically adjustable offset value different from the blanking pulse offset value to the fine digital-to-analog converter (DAC) portion during the signal sampling phase; The reset conversion operation outputs a fine reset value of the fine digital-to-analog converter DAC portion; setting the dynamically adjustable offset value based on the fine reset value obtained from the reset conversion operation; and Digital correlated double sampling is performed only on the coarse digital-to-analog converter DAC portion and not on the fine digital-to-analog converter DAC portion.

Images