Interface circuit, storage device, storage equipment and method for operating storage device

Abstract

An interface circuit, a storage device, a storage apparatus, and a method for operating a storage device are provided. An interface circuit of a storage device including a plurality of memory dies includes: a plurality of registers corresponding to the plurality of memory dies, each of the plurality of registers being configured to store command information related to a data operation command; a demultiplexer circuit configured to: provide input command information to a register selected from among the plurality of registers according to at least one of a first address or a first chip selection signal, the input command information being received from outside the interface circuit; and a multiplexer circuit configured to: receive output command information from a register selected from among the plurality of registers according to at least one of a second address or a second chip selection signal, and output the output command information.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0113012 filed on September 11, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to an interface circuit, a storage device, a storage apparatus and / or a method of operating a storage device, and more particularly, to an interface circuit for processing a command, a storage device including the interface circuit and / or a method of operating a storage device. Background Art

[0004] Semiconductor memory devices can be divided into volatile memory devices, which lose the data stored therein when the power is turned off, and non-volatile memory devices, which do not lose the data stored therein when the power is turned off. Volatile memory devices have fast read and write speeds, but when the external power supply is interrupted, the data stored in the volatile memory device disappears. In contrast, non-volatile memory devices have slower read and write speeds than volatile memory devices, but retain the data stored therein even when the external power supply is interrupted.

[0005] Non-volatile memory devices such as flash memory are widely used in various fields due to advantages such as high capacity, low noise and low power consumption. For example, solid state hard disks or solid state drives (SSDs) based on flash memory are used as large-capacity storage devices in personal computers, notebooks, workstations, servers, etc. SSD devices are usually connected to computing systems based on serial advanced technology attachment (SATA) interfaces or peripheral component interconnect (PCI)-express interfaces. However, recently, with the increase in data processed by computing systems, the larger amount of data to be processed tends to cause bottlenecks in data processing compared to the data bandwidth or communication speed of the interface connected to the SSD device. This phenomenon leads to performance degradation of computing systems. Therefore, various technologies for improving performance are being developed to solve this problem. Summary of the invention

[0006] The inventive concept provides an interface circuit, a memory device, a memory apparatus, a method of operating a memory device, and / or a method and apparatus for reducing data communication time and increasing an operating speed of a memory device and a memory apparatus.

[0007] According to an example embodiment conceived by the present invention, an interface circuit of a storage device including a plurality of memory dies includes: a plurality of registers corresponding to the plurality of memory dies, respectively, the plurality of registers being configured to store command information related to a data operation command; a demultiplexer circuit configured to: provide input command information to a register selected from among the plurality of registers according to at least one of a first address or a first chip selection signal, the input command information being received from outside the interface circuit; and a multiplexer circuit configured to: receive output command information from a register selected from among the plurality of registers according to at least one of a second address or a second chip selection signal, and output the output command information.

[0008] According to an example embodiment conceived in the present invention, a method of operating a storage device including a first memory die and a second memory die includes: in response to input of a first command, performing a first data operation on the first memory die; storing first command information related to the first command in a first register corresponding to the first memory die; stopping the first data operation; performing a second data operation on the second memory die in response to input of a second command; and performing remaining data operations on the first memory die based on the first command information stored in the first register without receiving an additional recovery command, the remaining data operations not being performed during the first data operation.

[0009] According to an example embodiment of the inventive concept, a memory device includes: a plurality of memory dies including a first memory die and a second memory die; an interface circuit configured to store a plurality of command information, the plurality of command information respectively corresponding to the plurality of memory dies, the interface circuit further configured to selectively output at least one of the plurality of command information; and a control logic configured to: perform a first data operation on the first memory die according to a first selection signal and a first command, stop the first data operation on the first memory die in response to input of a second selection signal and a second command for the second memory die during the execution of the first data operation, control the memory device to perform a second data operation corresponding to the second command on the second memory die, and control the memory device to perform a remaining data operation of the first data operation on the first memory die based on first command information among the plurality of command information in response to input of the first selection signal again, the first command information among the plurality of command information being related to the first command received from the interface circuit.

[0010] According to an example embodiment conceived in the present invention, a storage device includes: a storage device, the storage device including a first memory die, a second memory die and an interface circuit; and a memory controller, configured to provide a first data operation command for the first memory die and a second data operation command for the second memory die, wherein the interface circuit can be configured to store at least one of the first data operation command or a first data operation control signal in response to the first data operation command, the first data operation control signal being generated based on the first data operation command, and the storage device can be configured to: in response to completing a second data operation on the second memory die according to the second data operation command, perform a first data operation on the first memory die based on the first data operation command or the at least one of the first data operation command or the first data operation control signal, the at least one of the first data operation command or the first data operation control signal having been stored in the interface circuit.

[0011] According to an example embodiment conceived in the present invention, a storage device includes: a first memory die; a second memory die; and an interface circuit, the interface circuit including: a plurality of registers including a first register and a second register, the first register corresponding to the first memory die, the second register corresponding to the second memory die, wherein the interface circuit can be configured to: based on at least one of an address and a chip selection signal, select a register corresponding to the first memory die or the second memory die from among the plurality of registers, and store a command input from outside the storage device in the selected one of the registers. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 A data processing system according to an example embodiment is shown;

[0014] Figure 2 shows a storage device according to an example embodiment;

[0015] Figure 3 shows a storage device according to an example embodiment;

[0016] Figure 4 An interface circuit according to an example embodiment is shown;

[0017] Figure 5 is a flowchart of a method of operating a storage device according to an example embodiment;

[0018] Figure 6is a flowchart of a method of operating a storage system according to an example embodiment;

[0019] Fig. 7A and Figure 7B shows a path selection circuit according to some example embodiments;

[0020] Figure 8 shows a storage device according to an example embodiment;

[0021] Fig. 9 shows a storage device according to an example embodiment;

[0022] Fig.10 shows a storage device according to an example embodiment;

[0023] Fig.11 shows a storage device according to an example embodiment;

[0024] Fig.12 A solid state disk or solid state drive (SSD) system is shown according to an example embodiment. DETAILED DESCRIPTION

[0025] Hereinafter, some example embodiments will be described with reference to the accompanying drawings.

[0026] Figure 1 A data processing system 10 according to an example embodiment is shown. The data processing system 10 may include a host 100 and a storage system 400. The storage system 400 may include a memory controller 200 and a storage device 300. The data processing system 10 may be applied to any of various computing systems such as an ultra mobile personal computer (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, an Internet tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, and a digital camera.

[0027] The host 100, the memory controller 200, and the storage device 300 may be provided as a single chip, a single package, a single module, etc. However, example embodiments are not limited thereto. For example, the memory controller 200 and the storage device 300 may be provided together as a storage system 400 or a storage device in a single chip, a single package, a single module, etc.

[0028] The storage system 400 may be formed as a PC card (formerly known as a PCMCIA card), a compact flash (CF) card, a smart media (SM) card (SMC), a memory stick, a multimedia card (MMC), a reduced-size MMC (RS-MMC), an MMCmicro card, a secure digital (SD) card, a miniSD card, a microSD card, or a universal flash memory (UFS). In some example embodiments, the storage system 400 may be formed as a solid state hard disk or a solid state drive (SSD).

[0029] The host 100 may send a data operation request REQ and an address ADDR to the memory controller 200, and may exchange data DATA with the memory controller 200. For example, the host 100 may exchange data DATA with the memory controller 200 based on at least one interface protocol selected from various interface protocols (e.g., a universal serial bus (USB) protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a mobile industry processor interface (MIPI) protocol, or a UFS protocol).

[0030] The memory controller 200 may control the memory device 300. For example, the memory controller 200 may control the memory device 300 in response to the data operation request REQ to read the data DATA stored in the memory device 300 or write the data DATA to the memory device 300. For example, the memory controller 200 may control the memory device 300 by providing the address ADDR, the command CMD, and the control signal (not shown) to the memory device 300. Figure 1 300), to control the write operation, read operation and erase operation of the memory device 300. Data DATA may be exchanged between the memory controller 200 and the memory device 300 for the operation. In an example embodiment, the memory controller 200 may provide a read enable signal to the memory device 300.

[0031] The storage device 300 may include at least one memory die. For example, the storage device 300 may include a plurality of memory dies. For example, the storage device 300 may include a first memory die 340_1 to an Nth memory die 340_N, where N is a natural number of at least 2. The memory die may be referred to as a storage path. The first memory die 340_1 to the Nth memory die 340_N may each include at least one memory cell array. The memory cell array may include a plurality of memory cells located at intersections between a plurality of word lines and a plurality of bit lines. The memory cell may include a non-volatile memory cell. Each memory cell may be a multi-level cell (MLC) storing at least two bits of data. For example, each memory cell may be a 2-bit MLC storing two bits of data, a three-level cell (TLC) storing three bits of data, a four-level cell (QLC) storing four bits of data, or an MLC storing at least five bits of data. However, example embodiments are not limited thereto. For example, some memory cells may be single-level cells (SLCs) storing one bit of data per cell, while other memory cells may be MLCs. The memory device 300 may include a NAND flash memory, a vertical NAND (VNAND) flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FRAM), a spin transfer torque RAM (STT-RAM), or a combination thereof. In an example embodiment, the memory device 300 may have a stacked structure including at least 100 layers. In an example embodiment, the memory device 300 may have a cell-on-peri or cell-over-peri structure. The memory device 300 may perform operations (e.g., write operations, read operations, and erase operations) on the data DATA in response to a signal from the memory controller 200. In an example embodiment, the memory device 300 may generate a data strobe signal based on a read enable signal from the memory controller 200, and provide the data strobe signal generated based on the read enable signal to the memory controller 200.

[0032] In example embodiments, the operating frequency of the memory device 300 may be at least 1 GHz.

[0033] The memory device 300 may include an interface circuit 320. The interface circuit 320 may buffer at least one signal input from the outside of the memory device 300. For example, the interface circuit 320 may store a command CMD from the memory controller 200 and / or a data operation control signal generated based on the command CMD. Alternatively, the interface circuit 320 may include a buffer chip or a buffer circuit. Here, the buffer chip may be configured to buffer a signal input from the outside of the memory device 300.

[0034] In an example embodiment, the interface circuit 320 may include a plurality of registers. The register may store a plurality of command information for each of the plurality of memory dies. Here, the plurality of command information refers to information about the command CMD provided from the memory controller 200, and may include the command CMD and / or a data operation control signal generated in the memory device 300 based on the command CMD. The data operation control signal may include a control signal required for data operations (e.g., write operations, read operations, and erase operations) of the memory device 300. For example, the data operation control signal may include at least one control signal selected from various control signals including, for example, a voltage control signal, a row decoder control signal, a column decoder control signal, and a data input / output control signal.

[0035] For example, the interface circuit 320 may include first to Nth registers ( Figure 1 The first register may store command information corresponding to the first memory die 340_1 among the plurality of command information, and the Nth register may store command information corresponding to the Nth memory die 340_N among the plurality of command information.

[0036] In an example embodiment, when a command CMD for a specific memory die is input from the memory controller 200, the interface circuit 320 may select a register corresponding to the specific memory die among a plurality of registers, and store corresponding command information about the command CMD among a plurality of command information in the selected register. For this operation, in an example embodiment, the interface circuit 320 may include a demultiplexer circuit ( Figure 4 322 in the figure), the demultiplexer circuit selects a register to store corresponding command information from multiple registers.

[0037] In an example embodiment, the memory device 300 may perform memory interleaving. For example, when the plurality of memory dies in the memory device 300 further includes a second memory die ( Figure 2 340_2 in the memory device 300, the memory device 300 that is executing the first data operation on the first memory die 340_1 may stop the first data operation and execute the second data operation on the second memory die in response to the data operation command for the second memory die. In response to the completion of the second data operation, the memory device 300 may execute the remaining data operations that have not yet been executed in the first data operation on the first memory die 340_1 in response to the address ADDR and / or the chip selection signal both indicating the selection of the first memory die 340_1.

[0038] In the comparative example, during the above-mentioned memory cross access, the interface circuit of the storage device only stores the command most recently input from the memory controller. Therefore, in order to perform the remaining data operations of the first data operation after the second data operation is completed, the storage device needs to additionally receive a command (e.g., a data operation command or a restore command) regarding the first data operation from the memory controller. Because it takes additional time to receive the command, in the comparative example, the data operation time of the storage device increases.

[0039] However, according to an example embodiment, in the interface circuit 320 of the memory device 300, each of the plurality of registers corresponding to each of the plurality of memory dies stores corresponding command information for the corresponding memory die among the plurality of command information, and therefore, the memory device 300 can perform the remaining data operations of the first data operation based on the corresponding command information about the first data operation stored in the interface circuit 320 among the plurality of command information without additionally receiving a command. In this case, the interface circuit 320 can select a register corresponding to a desired memory die among the registers based on the address ADDR and / or the chip select signal, receive corresponding command information about the command CMD among the plurality of command information from the selected register, and output corresponding command information among the plurality of command information. For these operations, in an example embodiment, the interface circuit 320 may include a multiplexer circuit ( Figure 4 326 in the multiplexer circuit), the multiplexer circuit selects a register that provides corresponding command information among multiple command information from among multiple registers.

[0040] In other words, in the data processing system 10 according to the present exemplary embodiment, the interface circuit 320 stores corresponding command information among the plurality of pieces of command information in each of the plurality of registers corresponding to the respective memory dies among the plurality of memory dies, and therefore, during memory interleaving access, etc., the storage device 300 can resume the data operation that has been stopped without receiving an additional command. Therefore, the time spent on input of an additional command and / or command decoding can be saved, and the time spent on data communication between the storage device 300 and the storage system 400 can be reduced. Furthermore, as the time spent on data communication is reduced, the operating speed of the storage device 300 and the storage system 400 can be increased.

[0041] Figure 2 A storage device 300 according to an example embodiment is shown. Figure 2 The storage device 300 may be configured to correspond to Figure 1 The storage device 300 in the embodiment will be omitted. Figure 1 Redundant description given.

[0042] The memory device 300 may include a control logic 310, an interface circuit 320, a data operation control circuit 330, and a plurality of memory dies. The memory dies may include a first memory die 340_1 and second to N-th memory dies 340_2 to 340_N.

[0043] The control logic 310 may control various functions of the storage device 300. For example, the control logic 310 may be based on Figure 1 The control logic 310 receives the command CMD, address ADDR and control signal from the memory controller 200 in the memory die, and generates various internal control signals for writing data to or reading data from the memory cell array included in the memory die. In an example embodiment, the control logic 310 can control the interface circuit 320. In order to control the interface circuit 320, the control logic 310 can provide the interface circuit control signal CTRL_INT to the interface circuit 320. The control logic 310 may include: a processing circuit such as hardware including a logic circuit; a hardware / software combination such as a processor that executes software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0044] The interface circuit 320 may store a plurality of pieces of command information regarding the command CMD input from the outside of the memory device 300. For example, the interface circuit 320 may include a plurality of registers, each register corresponding to a corresponding memory die, and each register may store corresponding command information for the corresponding memory die among the plurality of pieces of command information. According to some example embodiments, each of the plurality of pieces of command information may be the command CMD itself, may include a data operation control signal generated based on the command CMD, or may include both the command CMD and the data operation control signal. Figure 2 The operation of each register of the interface circuit 320 configured to store a command CMD for a corresponding memory die is described.

[0045] In example embodiments, when a first command for a first memory die is received from a memory controller, the interface circuit 320 may select a first register corresponding to the first memory die among registers based on an address ADDR and / or a chip select signal, and may store the first command in the first register.

[0046] In an example embodiment, the interface circuit 320 may select one of the registers and thus be provided with a command from the selected register. Here, the command is referred to as a selected command CMD_s. The interface circuit 320 may provide the selected command CMD_s to the data operation control circuit 330.

[0047] For example, the memory device 300 may perform memory interleaving. When the memory device 300 receives a second command for the second memory die 340_2 while performing a first data operation in response to a first command for the first memory die 340_1, the memory device 300 may stop the first data operation and perform the second data operation on the second memory die 340_2 in response to the input of the second command. After the second data operation on the second memory die 340_2 is completed, the interface circuit 320 may output the first command for the first memory die 340_1 stored in the first register as the selected command CMD_s.

[0048] The data operation control circuit 330 may control the data operation of at least one memory die based on the command CMD and / or the selected command CMD_s. For example, the data operation control circuit 330 may generate at least one data operation control signal related to the data operation. The data operation control circuit 330 may be implemented in various forms. According to example embodiments, the data operation control circuit 330 may be implemented by hardware or a combination of hardware and software. When the data operation control circuit 330 is implemented by hardware, the data operation control circuit 330 may include a circuit for generating a data operation control signal based on the command CMD and / or the selected command CMD_s. When the data operation control circuit 330 is implemented by a combination of hardware and software, the data operation control signal may be generated by using the control logic 310 in the storage device 300 or the processor to execute the program and / or instruction loaded into the memory in the storage device 300. For example, the data operation control circuit 330 may be firmware. However, example embodiments are not limited thereto.

[0049] In an example embodiment, as described above, the memory device 300 may resume the first data operation stopped in order to perform the second data operation during memory interleaving access. For this operation, the interface circuit 320 may provide the first command stored in the first register corresponding to the first memory die 340_1 as the selected command CMD_s to the data operation control circuit 330. The data operation control circuit 330 may generate a data operation control signal related to the first data operation on the first memory die 340_1 based on the selected command CMD_s. The data operation control circuit 330 may perform the remaining data operations of the first data operation on the first memory die 340_1 using the data operation control signal.

[0050] In the storage device 300 according to the present example embodiment, the interface circuit 320 stores a plurality of pieces of command information in a plurality of registers corresponding to a plurality of memory dies, respectively, so the storage device 300 can resume the stopped data operation during memory cross access, etc., without receiving an additional command. Therefore, the time spent on input of an additional command and / or command decoding can be saved, and the time spent on data communication of the storage device 300 can be reduced. In addition, as the time spent on data communication is reduced, the operating speed of the storage device 300 can be increased.

[0051] Figure 3 A storage device 300 according to an example embodiment is shown. Figure 3 It is shown that the combination of hardware and software is implemented Figure 2 The memory device 300 is described with emphasis on the data operation control circuit 330 of the memory device 300. Figure 3 The storage device 300 and Figure 2 The difference between the storage device 300 and the storage device 300 is shown in FIG.

[0052] The memory device 300 may include a control logic 310, an interface circuit 320, and a plurality of memory dies. The memory dies may include a first memory die 340_1 and second to N-th memory dies 340_2 to 340_N.

[0053] The interface circuit 320 may include a plurality of registers corresponding to the plurality of memory dies, respectively, and each register may store a command CMD for a corresponding memory die. The interface circuit 320 may select one of the registers and output a selected command CMD_s from the selected register. The interface circuit 320 may provide the selected command CMD_s to the control logic 310.

[0054] The control logic 310 may be based on external (eg, Figure 1 The memory controller 200 in the embodiment of the present invention may provide a command CMD and / or a selected command CMD_s to control the data operation of at least one memory die. For example, the control logic 310 may generate a data operation control signal for data operation based on the selected command CMD_s. In other words, Figure 2 compared to, Figure 3 The control logic 310 may also perform Figure 2 The function of the data operation control circuit 330.

[0055] Figure 4 An interface circuit 320 is shown according to an example embodiment. Figure 4 The interface circuit 320 may correspond to Figures 1 to 3 The interface circuit 320 will be omitted. Figures 1 to 3A redundant description is given. Reference will be made to Figure 2 and Figure 3 To describe Figure 4 .

[0056] The interface circuit 320 may include a demultiplexer circuit 322 , a plurality of registers 324 , a multiplexer circuit 326 , and a way selection circuit 328 .

[0057] The register 324 may include a first register 325_1 and a second register 325_2 to an N-th register 325_N. The first register 325_1 to the N-th register 325_N may correspond to the first memory die 340_1 to the N-th memory die 340_N, respectively. For example, the first register 325_1 may store corresponding command information related to a command for the first memory die 340_1 among a plurality of command information. The corresponding command information among the plurality of command information may include the command itself and / or a data operation control signal generated based on the command. In an example embodiment, the command may include a data operation command related to a data operation.

[0058] The demultiplexer circuit 322 may receive the command information CI and provide it to a register selected from among the registers 324. In other words, the demultiplexer circuit 322 may select one register from among the registers 324 and provide the command information CI to the selected register. At this time, when the command information CI is related to the first memory die 340_1, the demultiplexer circuit 322 may provide the command information CI to the first register 325_1 corresponding to the first memory die 340_1. Similarly, when the command information CI is related to the second memory die 340_2, the demultiplexer circuit 322 may provide the command information CI to the second register 325_2 corresponding to the second memory die 340_2. At this time, in an example embodiment, the demultiplexer circuit 322 may select one register from among the registers 324 based on the demultiplexer control signal CTRL_D provided from the path selection circuit 328.

[0059] The multiplexer circuit 326 may select a register among the registers 324, receive the selected command information CI_s from the selected register, and output the selected command information CI_s. Figure 2 and Figure 3 In contrast, in an example embodiment, the selected command information CI_s may include the selected command CMD_s. At this time, in an example embodiment, the multiplexer circuit 326 may select a register among the registers 324 based on the multiplexer control signal CTRL_M provided from the path selection circuit 328. The multiplexer circuit 326 may provide the selected command information CI_s to the control logic 310 or the data operation control circuit 330.

[0060] The path selection circuit 328 may specify a register to be selected from the registers 324 for the demultiplexer circuit 322 and the multiplexer circuit 326 based on the address ADDR and / or the chip selection signal. For example, when a first command for the first memory die 340_1 is input to the memory device 300, the path selection circuit 328 may provide the demultiplexer circuit 322 with a demultiplexer control signal CTRL_D indicating selection of the first register 325_1, so that the demultiplexer circuit 322 selects the first register 325_1 from the registers 324. Similarly, when the memory device 300 resumes data operation on the first memory die 340_1, the path selection circuit 328 may provide the multiplexer circuit 326 with a multiplexer control signal CTRL_M indicating selection of the first register 325_1, so that the multiplexer circuit 326 selects the first register 325_1 from the registers 324.

[0061] Figure 5 is a flowchart of a method of operating a storage device according to an example embodiment. Figures 2 to 4 To describe Figure 5 .

[0062] In operation S120 , the memory device 300 may perform a first data operation on the first memory die 340_1 in response to a first command with respect to the first memory die 340_1 .

[0063] In operation S140, the memory device 300 may store corresponding command information related to the first command among the plurality of command information in the first register 325_1 corresponding to the first memory die 340_1. For example, the path selection circuit 328 may provide the demultiplexer control signal CTRL_D to the demultiplexer circuit 322 based on the address ADDR and / or the chip selection signal, so that the demultiplexer circuit 322 selects the first register 325_1. The demultiplexer circuit 322 may provide corresponding command information related to the first command among the plurality of command information to the first register 325_1 according to the demultiplexer control signal CTRL_D generated by the path selection circuit 328 based on the address ADDR and / or the chip selection signal. The first register 325_1 may store corresponding command information among the plurality of command information. In example embodiments, the corresponding command information among the plurality of command information may include the first command itself and / or a data operation control signal generated based on the first command.

[0064] In operation S160, the memory device 300 may stop the first data operation on the first memory die 340_1 in response to the second command, and perform the second data operation on the second memory die 340_2. In example embodiments, the memory device 300 may stop the first data operation on the first memory die 340_1 in response to input of the second command, and may perform the second data operation on the second memory die 340_2 based on the second command. In some example embodiments, the first command is a data read command for the first memory die 340_1, and the second command may be a data write command for the second memory die 340_2.

[0065] In operation S180, the memory device 300 may perform the remaining data operations of the first data operation on the first memory die 340_1 based on the corresponding command information related to the first command stored in the first register 325_1 among the plurality of command information. In an example embodiment, the memory device 300 may perform at least a portion of the remaining data operations of the first data operation in response to input of the address ADDR and / or the chip selection signal both indicating selection of the first memory die 340_1. In an example embodiment, the path selection circuit 328 may provide the multiplexer control signal CTRL_M to the multiplexer circuit 326 based on the address ADDR and / or the chip selection signal so that the multiplexer circuit 326 selects the first register 325_1. The multiplexer circuit 326 may output the corresponding command information related to the first command stored in the first register 325_1 among the plurality of command information according to the multiplexer control signal CTRL_M generated by the path selection circuit 328 based on the address ADDR and / or the chip selection signal. For example, the multiplexer circuit 326 may provide a plurality of command information to the control logic 310 or the data operation control circuit 330. In an example embodiment, when the plurality of command information includes a first command, the control logic 310 or the data operation control circuit 330 may generate various data operation control signals based on the first command, thereby controlling the remaining data operations of the first data operation. However, example embodiments are not limited thereto. When the plurality of command information includes a data operation control signal generated based on the first command, the control logic 310 or the data operation control circuit 330 may control the remaining data operations of the first data operation based on the data operation control signal. In an example embodiment, the storage device 300 may perform the remaining data operations of the first data operation in response to the completion of the second data operation. In an example embodiment, the storage device 300 may perform the remaining data operations of the first data operation based on the first command stored in the interface circuit 320 without receiving an additional command (e.g., a restore command) from the outside of the storage device 300.

[0066] Figure 6is a flowchart of a method of operating a storage system according to an example embodiment. Figures 1 to 4 To describe Figure 6 . Figure 6 An example of a method of operating the memory device 300 when the data operation control circuit 330 is implemented in the control logic 310 is shown.

[0067] In operation S210 , the memory controller 200 may transmit a first command CMD1 for the first memory die 340_1 to the interface circuit 320 and the control logic 310 .

[0068] In operation S220 , the control logic 310 may control a first data operation on the first memory die 340_1 in response to the first command CMD1 .

[0069] In operation S230, the interface circuit 320 may store first command information related to the first command CMD1. For example, the first register corresponding to the first memory die 340_1 may store the first command information. The first command information may include at least one selected from the first command CMD1 and a data operation control signal generated based on the first command CMD1.

[0070] In operation S240 , the control logic 310 may stop the first data operation on the first memory die 340_1 .

[0071] In operation S250, the memory controller 200 may send a second command CMD2 for the second memory die 340_2 to the interface circuit 320 and the control logic 310. Figure 6 Operation S240 is performed before operation S250, but example embodiments are not limited thereto. According to example embodiments, operation S240 may be performed in response to operation S250.

[0072] In operation S260 , the control logic 310 may control a second data operation on the second memory die 340_2 in response to the second command CMD2 .

[0073] In operation S270, when the address ADDR and / or the chip selection signal both indicating selection of the first memory die 340_1 are input to the memory device 300, the interface circuit 320 may select the first command information stored in the first register, thereby providing the first command information as the selected command information CI_s to the control logic 310. Figure 6 As shown in FIG. 2 , but before operation S270 , the memory controller 200 may provide the interface circuit 320 with an address ADDR and / or a chip select signal both indicating selection of the first memory die 340_1 .

[0074] In operation S280 , the control logic 310 may control remaining data operations of the first data operation on the first memory die 340_1 based on the first command information provided from the interface circuit 320 .

[0075] Fig. 7A and Figure 7B Path selection circuits 328a and 328b are shown according to some example embodiments.

[0076] Reference Fig. 7A , the path selection circuit 328a may include an address comparator circuit 328_1a and a control signal generation circuit 328_2a.

[0077] The address comparator circuit 328_1a may detect one memory die among the plurality of memory dies based on the address ADDR. For example, the address comparator circuit 328_1a may store a lookup table including memory die information corresponding to the address ADDR or an address range, compare the received address ADDR with the lookup table, and detect the memory die corresponding to the address ADDR. The address comparator circuit 328_1a may provide the memory die information MDI to the control signal generation circuit 328_2a based on the detected memory die.

[0078] The control signal generating circuit 328_2a may generate a control signal based on the memory die information MDI. For example, the control signal generating circuit 328_2a may generate a demultiplexer control signal CTRL_D and a multiplexer control signal CTRL_M based on the memory die information MDI.

[0079] The address comparator circuit 328_1a and the control signal generating circuit 328_2a may be implemented in various forms. According to example embodiments, the address comparator circuit 328_1a and the control signal generating circuit 328_2a may be implemented by hardware or a combination of hardware and software.

[0080] Reference Figure 7B , the path selection circuit 328b may include a control signal generation circuit 328_2b. The control signal generation circuit 328_2b may generate a control signal based on a chip selection signal CS. For example, the chip selection signal CS may represent a selection signal indicating one of a plurality of memory dies, a selection signal indicating one of a plurality of memory chips, and a selection signal indicating one of a plurality of storage paths. For example, the control signal generation circuit 328_2b may generate a demultiplexer control signal CTRL_D and a multiplexer control signal CTRL_M based on the chip selection signal CS.

[0081] Figure 8 A storage device 300 according to an example embodiment is shown. Figure 8The configuration of the interface circuit 320 of the storage device 300 according to the example embodiment is specifically shown. Figure 8 and Figure 4 The difference.

[0082] The memory device 300 may include a path selection circuit 328 and an interface circuit 320. The interface circuit 320 may include a register 324, a demultiplexer circuit 322, and a multiplexer circuit 326. Figure 4 In contrast, the path selection circuit 328 may be implemented outside the interface circuit 320 .

[0083] The path selection circuit 328 may be implemented in various forms. For example, the path selection circuit 328 may be implemented by hardware or a combination of hardware and software. In an example embodiment, when the path selection circuit 328 is implemented by a combination of hardware and software, the path selection circuit 328 may be implemented as Figure 2 and Figure 3 Part of the control logic 310 in.

[0084] Fig. 9 A storage device 300 according to an example embodiment is shown. The description will focus on Fig. 9 The storage device 300 is similar to the above reference Figure 2 and Figure 3 The differences of the storage device 300 are described.

[0085] The memory device 300 may include a control logic 310, a data operation control signal generating circuit 315, an interface circuit 320, and a plurality of memory dies. The memory dies may include a first memory die 340_1 and second to Nth memory dies 340_2 to 340_N.

[0086] exist Figure 2 and Figure 3 In the example, the interface circuit 320 stores the command CMD itself. Fig. 9 In the embodiment, the interface circuit 320 stores the data operation control signal DCTRL.

[0087] The data operation control signal generation circuit 315 may generate a data operation control signal DCTRL based on the command CMD. The data operation control signal DCTRL may include at least one of various control signals for data operation according to the command CMD in the memory device 300. The data operation control signal generation circuit 315 may provide the data operation control signal DCTRL to the interface circuit 320.

[0088] The data operation control signal generating circuit 315 can be implemented in various forms. In an example embodiment, the data operation control signal generating circuit 315 can be implemented by hardware or a combination of hardware and software. When the data operation control signal generating circuit 315 is implemented by hardware, the data operation control signal generating circuit 315 may include a circuit for generating a data operation control signal DCTRL based on the command CMD. When the data operation control signal generating circuit 315 is implemented by a combination of hardware and software, the data operation control signal DCTRL can be generated by using the control logic 310 in the storage device 300 or the processor to execute the program and / or instruction loaded into the memory in the storage device 300. For example, the data operation control signal generating circuit 315 can be firmware. However, example embodiments are not limited thereto.

[0089] The interface circuit 320 may store the data operation control signal DCTRL in a register corresponding to one memory die selected from the memory dies according to the address ADDR and / or the chip selection signal. In addition, the interface circuit 320 may provide the stored data operation control signal DCTRL to the memory die or element during the memory cross access for use in the data operation in the memory device 300, thereby controlling the data operation on at least one memory die.

[0090] Fig.10 A storage device 300 according to an example embodiment is shown. Fig.10 Specifically shown is the control logic 310 including Fig. 9 The memory device 300 will be described with emphasis on the function of the data operation control signal generating circuit 315 of the memory device 300. Fig.10 The storage device 300 and Fig. 9 The difference between the storage device 300 and the storage device 300 is shown in FIG.

[0091] The memory device 300 may include a control logic 310, an interface circuit 320, and a plurality of memory dies. The memory dies may include a first memory die 340_1 and second to N-th memory dies 340_2 to 340_N.

[0092] The control logic 310 may generate a data operation control signal DCTRL based on the command CMD input thereto, and provide the data operation control signal DCTRL to the interface circuit 320. Fig. 9 In contrast, control logic 310 may also execute Fig. 9 The data in the control signal generation circuit 315 operates the function.

[0093] Fig.11A memory device 300 according to an example embodiment is shown. The memory device 300 may include a control logic 310, an interface circuit 320, a command selection circuit 350, and a plurality of memory dies. The memory dies may include a first memory die 340_1 and a second memory die 340_2 to an Nth memory die 340_N. The description will focus on Fig.11 The storage device 300 and Figure 3 The difference between the storage device 300 and the storage device 300 is shown in FIG.

[0094] The interface circuit 320 may store the command CMD input thereto in a register selected from among a plurality of registers therein, and may output a selected command CMD_s from the selected register when requested. The interface circuit 320 may provide the selected command CMD_s to the command selection circuit 350 .

[0095] The command selection circuit 350 may select a command from among the selected command CMD_s and the command CMD, and provide the second selected command CMD_s2 to the control logic 310. For this operation, the command selection circuit 350 may include a multiplexer. Unlike the case where the command selection circuit 350 is omitted, when the command selection circuit 350 is present, the data operation of the memory device 300 may be controlled based on the command CMD input from the outside to the memory device 300 (e.g., input from the outside of the memory device 300 to the memory device 300) and the requested command among the selected command CMD_s that has been stored in the interface circuit 320 and transmitted from the interface circuit 320.

[0096] Fig.12 1 shows an SSD system 1000 according to an example embodiment. The SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 may exchange signals with the host 1100 through a signal connector SIG and may receive power through a power connector PWR. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and flash memory devices 1230, 1240, and 1250 (e.g., Fig.12 FLASH 1, FLASH 2, and FLASH n shown in the figure). At this time, you can use Figures 1 to 11 The illustrated example embodiment implements SSD 1200 .

[0097] according to Figures 1 to 11In the example embodiment shown, each of the flash memory devices 1230, 1240, and 1250 may include a voltage regulator (not shown). Therefore, each of the flash memory devices 1230, 1240, and 1250 may include an interface circuit and a plurality of memory dies. The interface circuit may include a plurality of registers, each of which may store corresponding command information for a memory die corresponding to the register in a plurality of command information. Each of the flash memory devices 1230, 1240, and 1250 may complete the stopped data operation based on corresponding command information in a plurality of command information stored in the interface circuit during memory cross access, etc. Therefore, the SSD controller 1210 does not need to provide additional commands such as a recovery command to the flash memory devices 1230, 1240, and 1250. Therefore, the data communication time between the flash memory devices 1230, 1240, and 1250 and the SSD 1200 may be reduced, and further, the operating speed thereof may be increased.

[0098] While the inventive concept has been particularly shown and described with reference to certain exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An interface circuit of a storage device, the storage device comprising a plurality of memory dies, the interface circuit comprising: a plurality of registers corresponding to the plurality of memory dies respectively, the plurality of registers being each configured to store command information related to a data operation command; a demultiplexer circuit configured to: provide input command information to a register selected from among the plurality of registers according to at least one of a first address or a first chip select signal, the input command information being received from outside the interface circuit; as well as A multiplexer circuit is configured to: receive output command information from a register selected from the plurality of registers according to at least one of a second address or a second chip selection signal, and output the output command information, wherein, the plurality of memory dies comprising a first memory die and a second memory die; The plurality of registers include a first register storing first command information corresponding to the first memory die and a second register storing second command information corresponding to the second memory die, wherein the command information related to the data operation command includes the first command information and the second command information; The demultiplexer circuit is configured to: in response to input of a first data operation command for the first memory die, provide the first command information to the first register, wherein the first command information is related to the first data operation command, and The interface circuit is configured to, in response to a second data operation on the second memory die, cause the first data operation on the first memory die to stop and resume according to the first data operation command.

2. The interface circuit according to claim 1, further comprising: The path selection circuit is configured to generate a demultiplexer control signal for controlling a first register selection of the demultiplexer circuit and a multiplexer control signal for controlling a second register selection of the multiplexer circuit based on at least one of the first address or the first chip selection signal.

3. The interface circuit according to claim 2, wherein: The path selection circuit is further configured to: comparing the first address with a lookup table stored in the path selection circuit, selecting a memory die among the plurality of memory dies based on a result of the comparing, and The demultiplexer control signal and the multiplexer control signal are generated such that the demultiplexer circuit and the multiplexer circuit select a register corresponding to the selected memory die from among the plurality of registers.

4. The interface circuit according to claim 2, wherein: The path selection circuit is further configured to: selecting a memory die corresponding to the first chip select signal from among the plurality of memory dies, and The demultiplexer control signal and the multiplexer control signal are generated so that the demultiplexer circuit and the multiplexer circuit select one register corresponding to the selected memory die from among the plurality of registers.

5. The interface circuit according to claim 1, wherein: The multiplexer circuit is further configured to select and output the first command information in response to input of at least one of an address or a chip select signal both indicating selection of the first memory die, the first command information being stored in the first register.

6. The interface circuit according to claim 1, wherein: The first command information includes at least one of the first data operation command or a data operation control signal generated based on the first data operation command.

7. A method of operating a memory device, the memory device comprising a first memory die and a second memory die, the method comprising: In response to input of a first command, performing a first data operation on the first memory die; storing first command information related to the first command in a first register corresponding to the first memory die; stopping the first data operation in response to a second command directed to the second memory die; performing a second data operation on the second memory die in response to input of the second command; as well as In response to completion of the second data operation on the second memory die, performing remaining data operations on the first memory die based on the first command information stored in the first register without receiving additional resume commands, the remaining data operations not being performed during the first data operation.

8. The method according to claim 7, wherein: The memory device also includes an interface circuit including a plurality of registers, each of the plurality of registers storing command information corresponding to a respective memory die of a plurality of memory dies including the first memory die and the second memory die.

9. The method according to claim 8, wherein: The storing first command information related to the first command in a first register corresponding to the first memory die includes: storing the first command information in the first register corresponding to the first memory die among the plurality of registers.

10. The method according to claim 7, wherein: The executing the remaining data operations includes executing the remaining data operations of the first data operation in response to at least one of an address or a chip selection signal input, both indicating selection of the first memory die.

11. The method according to claim 7, wherein: The first command information includes at least one of the first command or a first data operation control signal generated based on the first command.

12. The method according to claim 11, wherein: The storing of first command information related to the first command in a first register corresponding to the first memory die includes storing the first command, and The execution of the remaining data operation includes: generating a second data operation control signal based on the first command that has been stored, the second data operation control signal being related to the first command, and The remaining data operations of the first data operation are performed using the second data operation control signal.

13. The method according to claim 11, wherein: The storing of the first command information includes: generating the first data operation control signal based on the first command, and storing the first data operation control signal, The executing the remaining data operations includes: executing the remaining data operations of the first data operation using the first data operation control signal that has been stored.

14. A storage device, comprising: a plurality of memory dies including a first memory die and a second memory die; an interface circuit, the interface circuit being configured to store a plurality of command information, the plurality of command information respectively corresponding to the plurality of memory dies, and the interface circuit being further configured to selectively output at least one command information of the plurality of command information; as well as A control logic configured to: performing a first data operation on the first memory die according to a first selection signal and a first command, During the execution of the first data operation, in response to input of a second selection signal and a second command for the second memory die, stopping the first data operation on the first memory die, controlling the storage device to perform a second data operation corresponding to the second command on the second memory die, and In response to completion of the second data operation on the second memory die and in response to re-input of the first selection signal, the memory device is controlled to perform remaining data operations of the first data operation on the first memory die based on first command information among the multiple command information, wherein the first command information among the multiple command information is related to the first command received from the interface circuit.

15. The storage device according to claim 14, wherein: The interface circuit comprises: a plurality of registers, the plurality of registers storing the plurality of command information respectively, the plurality of command information corresponding to the plurality of memory dies respectively; a demultiplexer circuit configured to: provide input command information to a register selected from among the plurality of registers according to at least one of a first address or a first chip select signal, the input command information being received from outside the memory device; and The multiplexer circuit is configured to receive output command information from a register selected from among the plurality of registers according to at least one of a second address or a second chip selection signal, and output the output command information.

16. The storage device according to claim 15, wherein: The interface circuit further includes a path selection circuit, wherein the path selection circuit is configured to: generating a demultiplexer control signal for controlling a first register selection of the demultiplexer circuit based on the at least one of the first address or the first chip select signal, and A multiplexer control signal for controlling a second register selection of the multiplexer circuit is generated based on the at least one of the second address or the second chip select signal.

17. The storage device according to claim 14, wherein: The interface circuit is further configured to store a plurality of data operation commands, the plurality of data operation commands respectively corresponding to the plurality of memory dies, and The control logic is further configured to: generating a data operation control signal based on the first command, and The memory device is controlled to perform the remaining data operations of the first data operation based on the data operation control signal.

18. The storage device according to claim 17, wherein: The control logic is further configured to: selecting one of the first command or a third command, the third command being input from outside the storage device, and The data operation control signal is generated based on the selected one of the commands.

19. The storage device according to claim 14, wherein: the interface circuit storing a data operation control signal generated based on a data operation command corresponding to each of the plurality of memory dies, The control logic is further configured to, in response to completion of the second data operation, control the storage device to perform the remaining data operations of the first data operation on the first memory die based on a first data operation control signal corresponding to the first command.

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