Computer system and computer system control method

Abstract

The present invention provides a computer system and a computer system control method, wherein the computer system includes a central processing unit, a persistent storage-level memory, a custom open channel SSD, a memory bus, an expansion bus, and a bridge, wherein the memory bus is connected to the expansion bus via a bridge, the central processing unit and the persistent storage-level memory are respectively connected to the memory bus, and the custom open channel SSD is connected to the expansion bus; a maintenance program of the custom open channel SSD is solidified in the persistent storage-level memory, and during the operation of the computer system, the central processing unit executes the maintenance program in the persistent storage-level memory to perform data access operations on the custom open channel SSD. The present invention does not need to rewrite the maintenance program of the custom open channel SSD when the system is powered off and restarted, thereby reducing the time consumed by the system power off and restart.

Description

Technical Field

[0001] The present invention relates to the field of computers, and more specifically, to a computer system and a computer system control method. Background Art

[0002] In computer systems, the access performance of memory (i.e. DRAM) is significantly better than that of external storage. Putting data into memory can provide faster reading efficiency. On the Internet, 80% of the access volume is concentrated on 20% of hot data. Therefore, by introducing a cache component and putting high-frequency access data into the cache, the data reading speed, system expansion capability and overall carrying capacity can be greatly improved, while also achieving a lower response delay. However, from mechanical hard disks to SSDs (Solid State Drives) to memory, the speed is getting faster and the price is getting more expensive, and the price per unit capacity is also getting higher.

[0003] An open-channel SSD is a special solid-state drive that does not implement a flash translation layer (FTL) in the drive's firmware, but instead offloads the management of physical solid-state storage to the computer's operating system. In existing systems that use open-channel SSDs, by caching hot data in memory, the central processing unit can reduce data access to the SSD, and centralized bad block management can be achieved, greatly improving data access efficiency.

[0004] However, in the above-mentioned system using open channel SSD, since the memory needs to store the file management system, the cache files required by the system, and update the data to the SSD in blocks at the same time, the memory capacity requirement is large, and the central processing unit needs to consume resources to maintain the file management system. In addition, when the system is powered on again, the file management system and the data to be cached need to be rewritten from the SSD to the memory, which is time-consuming. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a new computer system and a computer system control method in view of the problem that the system using the open channel SSD requires a large amount of memory.

[0006] The technical solution of the present invention to solve the above technical problems is to provide a computer system, including a central processing unit, a persistent storage-level memory, a custom open channel SSD, a memory bus, an expansion bus and a bridge, and the memory bus is connected to the expansion bus through a bridge, the central processing unit and the persistent storage-level memory are respectively connected to the memory bus, and the custom open channel SSD is connected to the expansion bus; a maintenance program of the custom open channel SSD is solidified in the persistent storage-level memory, and during the operation of the computer system, the central processing unit executes the maintenance program in the persistent storage-level memory to perform data access operations on the custom open channel SSD.

[0007] Preferably, the persistent storage class memory comprises a memory interface, a DRAM chipset, a control chip, a flash memory and an internal bus integrated into the same substrate, and the control chip is connected to the memory interface, the DRAM chipset and the flash memory respectively through the internal bus, and the memory interface is connected to the memory bus;

[0008] The control chip responds to the read and write requests of the central processing unit connected to the memory interface, obtains the instruction set from the DRAM chipset and transmits the instruction set to the central processing unit through the memory interface and writes the execution result data of the central processing unit to the DRAM chipset;

[0009] The maintenance program is fixed in the flash memory, and the control chip moves the maintenance program in the flash memory to the DRAM chipset when the persistent storage-level memory is powered on.

[0010] Preferably, an embedded operating system program is solidified in the flash memory, and when the persistent storage-level memory is powered on, the control chip moves the embedded operating system program in the flash memory to the DRAM chipset.

[0011] Preferably, the computer system further comprises a persistent memory in which an embedded operating system program is stored, and when the computer system is started, the embedded operating system program in the persistent memory is moved to the DRAM chipset of the persistent storage class memory.

[0012] Preferably, when the control chip in the DRAM chipset is waiting for the instruction set read by the central processing unit to meet a preset condition, it obtains a subsequent instruction set of the instruction set in the DRAM chipset from the flash memory through the memory interface and stores the subsequent instruction set in the DRAM chipset.

[0013] An embodiment of the present invention further provides a computer system control method, the method being applied to the computer system, the computer system comprising a central processing unit, a persistent storage-level memory, a custom open channel SSD, a memory bus, an expansion bus, and a bridge, wherein the memory bus is connected to the expansion bus via a bridge, and the memory bus is connected to the expansion bus via a bridge, the central processing unit and the persistent storage-level memory are respectively connected to the memory bus, and the custom open channel SSD is connected to the expansion bus; a maintenance program of the custom open channel SSD is solidified in the persistent storage-level memory, and the method comprises:

[0014] During the operation of the computer system, the central processing unit executes the maintenance program in the persistent storage-level memory and performs data access operations on the custom open channel SSD.

[0015] Preferably, the persistent storage-level memory includes a memory interface, a DRAM chipset, a control chip, a flash memory and an internal bus integrated into the same substrate, and the control chip is connected to the memory interface, the DRAM chipset and the flash memory respectively through the internal bus, and the memory interface is connected to the memory bus; the method further includes:

[0016] When the persistent storage-level memory is powered on, the control chip moves the maintenance program solidified in the flash memory to the DRAM chipset;

[0017] The control chip responds to the read and write requests of the central processing unit connected to the memory interface, obtains an instruction set from the DRAM chipset and transmits the instruction set to the central processing unit through the memory interface and writes the execution result data of the central processing unit to the DRAM chipset.

[0018] Preferably, an embedded operating system program is solidified in the flash memory, and the method further comprises:

[0019] When the persistent storage-level memory is powered on, the control chip moves the embedded operating system program in the flash memory to the DRAM chipset.

[0020] Preferably, the computer system further comprises a persistent memory, wherein an embedded operating system program is stored in the persistent memory, and the method comprises:

[0021] When the computer system is started, the central processing unit moves the embedded operating system program in the persistent memory to the DRAM chipset of the persistent storage class memory.

[0022] Preferably, the method further comprises:

[0023] When the control chip in the DRAM chipset waits for the instruction set read by the central processing unit to meet a preset condition, the control chip obtains a subsequent instruction set of the instruction set in the DRAM chipset from the flash memory through the memory interface and stores the subsequent instruction set in the DRAM chipset.

[0024] The computer system and computer system control method of the present invention fix the maintenance program of the custom open channel SSD in the persistent storage-level memory, so that when the system is powered off and restarted, there is no need to rewrite the maintenance program of the custom open channel SSD, thereby reducing the time consumed by the system power off and restart. In addition, the present invention can reduce storage costs and reduce the occupation of the central processing unit by file system maintenance. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram of a computer system provided by an embodiment of the present invention;

[0026] Figure 2 is a schematic diagram of a persistent storage-level memory in a computer system provided by an embodiment of the present invention;

[0027] Figure 3 It is a flowchart of a computer system control method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0029] like Figure 1 , is a schematic diagram of a computer system provided by an embodiment of the present invention, which can be used as an Internet server (cloud server) host and respond to client requests. The computer system of this embodiment includes a central processing unit 11, a persistent storage class memory 12, a custom open channel SSD 13, a memory bus 141, an expansion bus 142, and a bridge 143, and the memory bus 141 is connected to the expansion bus 142 through the bridge 143, the central processing unit 11 and the persistent storage class memory 12 are respectively connected to the memory bus 141, and the custom open channel SSD 13 is connected to the expansion bus 142. The above-mentioned custom open channel SSD 13 only includes a flash memory chip for data storage, and does not include a part for managing physical solid-state storage.

[0030] Specifically, the above-mentioned memory bus 141 can be a DRAM bus, which is used to achieve high-speed data transmission between the central processing unit 11 and the persistent storage level memory 12; the expansion bus 142 can be a PCIe bus, and is used to connect devices with slower data transmission speeds, such as persistent storage (including SSDs and hard disks, etc.); the bridge 143 is used to achieve data conversion between the memory bus 141 and the expansion bus 142. Through the bridge 143, the central processing unit 11 connected to the memory bus 141 can access the device connected to the expansion bus 142 (such as a custom open channel SSD 13).

[0031] In this embodiment, the maintenance program of the custom open channel SSD 13 is solidified in the persistent storage class memory 12 (that is, the maintenance program of the custom open channel SSD 13 is still retained when the computer system is powered off and does not disappear), and during the operation of the computer system, the central processing unit 11 executes the maintenance program in the persistent storage class memory 12 to perform data access operations on the custom open channel SSD 13. The maintenance program of the custom open channel SSD 13 includes a file system and a management system, such as a block mapping table, a bad block management table, a cache file, and a FAT table for managing blocks in the custom open channel SSD 13.

[0032] The above-mentioned computer system, by solidifying the maintenance program of the custom open channel SSD 13 in the persistent storage-level memory 12, does not need to read data (including data that the central processing unit 11 needs to access) from the custom open channel SSD 13 when the system is powered off and restarted, thereby reducing the time consumed by the system power off and restart and the need to read the data that the central processing unit 11 needs to frequently access and store in the custom open channel SSD 13 again.

[0033] Combination Figure 2 As shown, in one embodiment of the present invention, the above-mentioned persistent storage class memory 12 includes a memory interface (not shown in the figure), a DRAM chipset 122, a control chip 121, a flash memory 123 and an internal bus (not shown in the figure) integrated into the same substrate, and the control chip 121 is connected to the memory interface, the DRAM chipset 122, and the flash memory 123 through the internal bus, respectively, and the memory interface is also connected to the memory bus, so that the internal bus can be connected to the memory bus 141 through the memory interface, and the central processing unit 11 can access the control chip 121 through the memory bus 141, the memory interface, and the internal bus and perform data transmission. Since the cost of the flash memory 123 is much lower than that of the DRAM chipset 122, the storage capacity of the flash memory 123 can be much larger than the storage capacity of the DRAM chipset 122.

[0034] The control chip 121 can respond to read and write requests from the central processing unit 11 connected to the memory interface (via the memory bus 141), obtain an instruction set (such as an instruction set of a maintenance program for a custom open channel SSD) from the DRAM chipset 122 and transmit the instruction set to the central processing unit 11 through the memory interface and write the execution result data of the central processing unit 11 to the DRAM chipset 122.

[0035] The maintenance program of the custom open channel SSD 13 is solidified in the flash memory 123, and the control chip 121 moves the maintenance program of the custom open channel SSD 13 in the flash memory 123 to the DRAM chipset 122 when the persistent storage-level memory 12 is powered on, thereby ensuring that the central processing unit 11 can quickly access the maintenance program of the custom open channel SSD 13.

[0036] Since the maintenance program of the custom open channel SSD 13 in the flash memory 123 is directly written by the control chip 121 to the DRAM chipset 122 without the involvement of the central processing unit 11, the corresponding instruction transmission is avoided and the resources of the central processing unit 11 are not occupied.

[0037] Furthermore, when the control chip 121 waits in the DRAM chipset 122 for the instruction set read by the central processing unit 11 to meet the preset conditions, the control chip 121 obtains the subsequent instruction set of the instruction set in the DRAM chipset 122 from the flash memory 123 through the flash memory interface, and stores the subsequent instruction set in the DRAM chipset 122. In the above manner, the control chip 121 can directly predict the subsequent instruction set that the central processing unit 11 needs to execute based on the instruction set being executed, and update the content in the DRAM chipset 122 based on the prediction result, so that the DRAM chipset 122 can be automatically updated according to the operating status of the central processing unit 11, so that the storage capacity of the DRAM chipset 122 is close to infinite (equivalent to the capacity of the cheap flash memory 123), and during the prediction and update process, the central processing unit 11 does not need to interact with the flash memory 123, so that the central processing unit 11 can always be in an efficient operating state, which is suitable for fields with high requirements for computing resources such as cloud computing, and can greatly improve the operating efficiency of the system.

[0038] In one embodiment of the present invention, the DRAM chipset 122 includes two logical storage areas which are a main mapping area and a backup mapping area. The two logical storage areas are respectively a section of storage space in the DRAM chipset 122, and respectively store instruction sets for the central processing unit 11 to process, and the central processing unit 11 also writes the execution results of the instruction sets into the above logical storage areas. The logical storage area where the instruction set currently read by the central processing unit 11 is located is the main mapping area, and the other logical storage area is the backup mapping area, and the two logical storage areas can switch the main mapping area and the backup mapping area according to the jump instruction executed by the central processing unit 11 (i.e., the jump code in the instruction code). The instruction sets stored in the main mapping area and the backup mapping area are respectively from the flash memory 123, and the instruction sets stored therein correspond to a certain section of the instruction set in the flash memory 123, that is, the main mapping area and the backup mapping area are equivalent to two "windows" of the flash memory 123, and the central processing unit 11 can obtain the instruction set stored in the flash memory 123 through the two "windows". The content displayed in the "window" is controlled by the control chip 121.

[0039] Specifically, the central processing unit 11 obtains the instruction set from the main mapping area through the control chip 121 according to the program address specified by the program counter. Under normal circumstances, after the program counter executes each instruction set, it automatically increases the original address by 1 as the program address of the next instruction set, so that the central processing unit 11 obtains the next instruction set from the main mapping area according to the updated program address; if the central processing unit 11 executes a jump instruction, the program counter increases the original address by +n or -n according to the jump value n as the program address of the next instruction set, and the central processing unit 11 obtains the next instruction set from the main mapping area according to the updated program address. When the program address specified by the program counter is located in the backup mapping area, the main mapping area and the backup mapping area are switched.

[0040] Of course, in actual applications, the DRAM chipset 122 may include more logical storage areas, and one of the logical storage areas is a primary mapping area, and the other logical storage areas are backup mapping areas.

[0041] Specifically, the control chip 121 can update the content in the DRAM chipset 122 in the following manner: when the number of instruction sets in the main mapping area waiting to be read by the central processing unit 11 is less than a preset value, or the execution time of the instruction sets in the main mapping area waiting to be read in the central processing unit is less than a preset time, the control chip 121 obtains the subsequent instruction set of the instruction set in the DRAM chipset 122 from the flash memory 123, and stores the subsequent instruction set in the DRAM chipset 122 (at the same time, adjust the pointer according to the instruction set in the main mapping area and the updated instruction set in the backup mapping area, so that the central processing unit 11 can read the instruction set in sequence). In the above manner, the instruction set in the DRAM chipset 122 can be updated in time, so as not to affect the instruction execution of the central processing unit 11.

[0042] Preferably, the control chip 121 can store the subsequent instruction set of the instruction set in the main mapping area obtained from the flash memory 123 to the backup mapping area when the instruction set waiting to be read by the central processing unit 11 in the DRAM chipset 122 meets the preset conditions, for example, the number of instruction sets waiting to be read by the central processing unit 11 in the main mapping area is less than the preset value, or the execution time of the instruction set waiting to be read in the main mapping area in the central processing unit 11 is less than the preset time. In this way, by controlling the preset conditions, the efficient operation of the central processing unit 11 will not be affected when the capacity of the logical storage area is small, and the resources of the DRAM chipset 122 can be saved.

[0043] Specifically, when the instruction set in the DRAM chipset 122 waiting to be read by the central processing unit 11 does not include a jump instruction, or the instruction set in the DRAM chipset 122 waiting to be read by the central processing unit 11 includes a jump instruction and the instruction set pointed to by the jump instruction is still in the DRAM chipset 122, the subsequent instruction set takes the next instruction of the last instruction in the main mapping area of ​​the DRAM chipset 122 as the starting point; when the instruction set in the DRAM chipset 122 waiting to be read by the central processing unit includes a jump instruction and the instruction set pointed to by the above jump instruction is not in the DRAM chipset 122, the subsequent instruction set takes the instruction pointed to by the above jump instruction as the starting point.

[0044] For ease of management, the sizes of the two logical storage areas may be equal (ie, the storage spaces are equal), and the subsequent instruction set obtained by the control chip 121 is equal to the size of the logical storage area. By the above method, the access efficiency of the control chip 121 can be improved.

[0045] Since the central processing unit 11 writes the execution result to the logical storage area when executing the instruction set, before storing the subsequent instruction set of the instruction set in the main mapping area into the backup mapping area, if the content of the backup mapping area has been updated (i.e., the central processing unit 11 has written the execution result of the instruction set), the control chip 121 needs to write the content in the backup mapping area (the result updated by the central processing unit 11) back to the original address of the flash memory 123. That is, before storing the subsequent instruction set of the instruction set in the main mapping area into the backup mapping area, the control chip 121 first determines whether the content of the backup mapping area has been updated. If it has not been updated, the subsequent instruction set is directly stored in the backup mapping area. Otherwise, the content in the backup mapping area (i.e., the updated content) is first written back to the original address of the flash memory 123, and then the subsequent instruction set is stored in the backup mapping area.

[0046] The above-mentioned flash memory 123 also has an embedded operating system program solidified therein, which is used for execution by the central processing unit 11. When the persistent storage level memory 12 is powered on, the control chip 121 moves the embedded operating system program in the flash memory 123 to the DRAM chipset 122 for the central processing unit 11 to call.

[0047] In addition, in another embodiment of the present invention, in order to be compatible with existing computer systems, the computer system may further include a persistent memory independent of the custom open channel SSD 13, the persistent memory may be an SSD or a hard disk, and the persistent memory is connected to the expansion bus 142. The persistent memory stores an embedded operating system program, and when the computer system is started, under the control of the central processing unit 11, the embedded operating system program in the persistent memory is moved to the DRAM chipset 122 of the persistent storage class memory 12 for subsequent calling by the central processing unit 11.

[0048] like Figure 3 As shown, the embodiment of the present invention also provides a computer system control method, which is applied to a computer system, combined with Figure 1 As shown, the computer system includes a central processing unit, a persistent storage-level memory, a custom open channel SSD, a memory bus, an expansion bus, and a bridge, and the memory bus is connected to the expansion bus through a bridge, the memory bus is connected to the expansion bus through a bridge, the central processing unit and the persistent storage-level memory are connected to the memory bus respectively, and the custom open channel SSD is connected to the expansion bus; the maintenance program of the custom open channel SSD is solidified in the persistent storage-level memory. The method of this embodiment includes the following steps performed during the operation of the computer system:

[0049] Step S31: The central processing unit obtains the maintenance program from the persistent storage class memory. The maintenance program of the above-mentioned custom open channel SSD includes a file system and a management system, such as a block mapping table, a bad block management table, a cache file and a FAT table for managing blocks in the custom open channel SSD 13.

[0050] Step S32: The central processing unit uses the maintenance program to perform data access operations on the custom open channel SSD, for example, obtaining data from the flash memory chip of the custom open channel SSD and caching the data to the persistent storage class memory.

[0051] Specifically, the above-mentioned persistent storage-level memory includes a memory interface, a DRAM chipset, a control chip, a flash memory and an internal bus integrated into the same substrate, and the control chip is connected to the memory interface, the DRAM chipset and the flash memory through the internal bus respectively, and the memory interface is connected to the memory bus; accordingly, the computer system control method also includes:

[0052] The control chip moves the maintenance program solidified in the flash memory to the DRAM chipset when the persistent storage-level memory is powered on;

[0053] The control chip responds to the read and write requests of the central processing unit connected to the memory interface, obtains the instruction set from the DRAM chipset and transmits the instruction set to the central processing unit through the memory interface and writes the execution result data of the central processing unit to the DRAM chipset.

[0054] Since the maintenance program of the custom open channel SSD is solidified in the flash memory, and the control chip moves the maintenance program of the custom open channel SSD in the flash memory to the DRAM chipset when the persistent storage-level memory is powered on, thereby ensuring that the central processing unit can quickly access the maintenance program of the custom open channel SSD.

[0055] In one embodiment of the present invention, the computer system control method further includes:

[0056] When the control chip in the DRAM chipset waits for the instruction set read by the central processing unit to meet the preset condition, the control chip obtains the subsequent instruction set of the instruction set in the DRAM chipset from the flash memory through the memory interface and stores the subsequent instruction set in the DRAM chipset.

[0057] This process does not require the involvement of the central processing unit, so the DRAM chipset is nearly infinitely large relative to the central processing unit (comparable to the capacity of flash memory).

[0058] In particular, the above-mentioned flash memory has an embedded operating system program solidified therein, and accordingly, the above-mentioned method may further include:

[0059] When the persistent storage-level memory is powered on, the control chip moves the embedded operating system program in the flash memory to the DRAM chipset for the central processing unit to call.

[0060] In addition, in order to be compatible with existing computer systems, the computer system further includes a persistent memory, in which an embedded operating system program is stored. In this case, the method further includes:

[0061] When the computer system is started, the central processing unit moves the embedded operating system program in the persistent memory to the DRAM chipset of the persistent storage class memory.

[0062] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A computer system, characterized in that: Includes central processing unit, persistent storage-class memory, custom open channel SSD 、 A memory bus, an expansion bus and a bridge, wherein the memory bus is connected to the expansion bus via the bridge, the central processing unit and the persistent storage class memory are respectively connected to the memory bus, and the custom open channel SSD is connected to the expansion bus; a maintenance program of the custom open channel SSD is solidified in the persistent storage class memory, and during the operation of the computer system, the central processing unit executes the maintenance program in the persistent storage class memory to perform data access operations on the custom open channel SSD; The persistent storage-level memory includes a memory interface, a DRAM chipset, a control chip, a flash memory and an internal bus integrated into the same substrate, and the control chip is connected to the memory interface, the DRAM chipset and the flash memory through the internal bus respectively, and the memory interface is connected to the memory bus; The control chip responds to the read and write request of the central processing unit connected to the memory interface, obtains the instruction set from the DRAM chipset and transmits the instruction set to the central processing unit through the memory interface, and writes the execution result data of the central processing unit into the DRAM chipset; the DRAM chipset includes two logical storage areas, a main mapping area and a backup mapping area, and the control chip controls the content stored in the main mapping area and the backup mapping area; the central processing unit obtains the instruction set from the main mapping area through the control chip according to the program address specified by the program counter, and the program counter The sequence counter automatically increases the original address by 1 as the program address of the next instruction set when the central processing unit completes executing each non-jump instruction set, and the central processing unit obtains the next instruction set from the main mapping area according to the updated program address; when the central processing unit executes a jump instruction, the program counter increases the original address by n or -n as the program address of the next instruction set according to the jump value n, and the central processing unit obtains the next instruction set from the main mapping area according to the updated program address, wherein n is a positive integer; when the program address specified by the program counter is located in the backup mapping area, the main mapping area and the backup mapping area are switched; The custom open channel SSD only includes a flash memory chip for data storage, and a maintenance program for managing the flash memory chip of the custom open channel SSD is solidified in the flash memory, and the control chip moves the maintenance program in the flash memory to the DRAM chipset when the persistent storage-level memory is powered on; the maintenance program of the custom open channel SSD includes a file system and a management system, and the file system and the management system include a block mapping table, a bad block management table, a cache file and a FAT table for managing blocks in the custom open channel SSD.

2. The computer system according to claim 1, characterized in that The flash memory has an embedded operating system program fixed therein, and when the persistent storage-level memory is powered on, the control chip moves the embedded operating system program in the flash memory to the DRAM chipset.

3. The computer system according to claim 1, characterized in that: The computer system also includes a persistent memory in which an embedded operating system program is stored. When the computer system is started, the embedded operating system program in the persistent memory is moved to the DRAM chipset of the persistent storage class memory.

4. The computer system according to claim 1, wherein: When the control chip in the DRAM chipset waits for the instruction set read by the central processing unit to meet a preset condition, the control chip obtains a subsequent instruction set of the instruction set in the DRAM chipset from the flash memory through the memory interface and stores the subsequent instruction set in the DRAM chipset.

5. A computer system control method, characterized in that: The method is applied to the computer system, which includes a central processing unit, a persistent storage class memory, and a custom open channel SSD. 、 A memory bus, an expansion bus and a bridge, wherein the memory bus is connected to the expansion bus through the bridge, the central processing unit and the persistent storage class memory are respectively connected to the memory bus, and the custom open channel SSD is connected to the expansion bus; the custom open channel SSD only includes a flash memory chip for data storage, the persistent storage class memory is solidified with a maintenance program of the custom open channel SSD, the maintenance program of the custom open channel SSD includes a file system and a management system, and the file system and the management system include a block mapping table, a bad block management table, a cache file and a FAT table for managing blocks in the custom open channel SSD; the method includes: During the operation of the computer system, the central processing unit executes the maintenance program in the persistent storage class memory to perform data access operations on the custom open channel SSD; The persistent storage-level memory includes a memory interface, a DRAM chipset, a control chip, a flash memory, and an internal bus integrated into the same substrate, and the control chip is connected to the memory interface, the DRAM chipset, and the flash memory through the internal bus, respectively, and the memory interface is connected to the memory bus; the method further includes: When the persistent storage-level memory is powered on, the control chip moves the maintenance program solidified in the flash memory to the DRAM chipset; The control chip responds to the read and write requests of the central processing unit connected to the memory interface, obtains the instruction set from the DRAM chipset and transmits the instruction set to the central processing unit through the memory interface and writes the execution result data of the central processing unit to the DRAM chipset; The DRAM chipset includes two logical storage areas, which are a main mapping area and a backup mapping area, and the control chip controls the contents stored in the main mapping area and the backup mapping area; the central processing unit obtains the instruction set from the main mapping area through the control chip according to the program address specified by the program counter, and the program counter automatically increases the original address by 1 as the program address of the next instruction set each time the central processing unit executes a non-jump instruction set, and the central processing unit obtains the next instruction set from the main mapping area according to the updated program address; when the central processing unit executes a jump instruction, the program counter increases the original address by +n or -n according to the jump value n as the program address of the next instruction set, and the central processing unit obtains the next instruction set from the main mapping area according to the updated program address, and n is a positive integer; when the program address specified by the program counter is located in the backup mapping area, the main mapping area and the backup mapping area are switched.

6. The computer system control method according to claim 5, characterized in that: The flash memory has an embedded operating system program solidified therein, and the method further includes: When the persistent storage-level memory is powered on, the control chip moves the embedded operating system program in the flash memory to the DRAM chipset.

7. The computer system control method according to claim 5, characterized in that: The computer system further includes a persistent memory, wherein an embedded operating system program is stored in the persistent memory, and the method includes: When the computer system is started, the central processing unit moves the embedded operating system program in the persistent memory to the DRAM chipset of the persistent storage class memory.

8. The computer system control method according to claim 5, characterized in that: The method further comprises: When the control chip in the DRAM chipset waits for the instruction set read by the central processing unit to meet a preset condition, the control chip obtains a subsequent instruction set of the instruction set in the DRAM chipset from the flash memory through the memory interface and stores the subsequent instruction set in the DRAM chipset.

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