High resistivity silicon-on-insulator substrate and method for forming the same

Abstract

In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate and a method for forming the same. The high-resistivity silicon-on-insulator substrate includes a first polysilicon layer, a second polysilicon layer, a third polysilicon layer, an insulator layer, and an active semiconductor layer disposed on a semiconductor substrate. The second polysilicon layer is disposed on the first polysilicon layer, and the third polysilicon layer is disposed on the second polysilicon layer. The active semiconductor layer located on the insulator layer may be disposed on the third polysilicon layer. The second polysilicon layer has a higher oxygen concentration than the first polysilicon layer and the third polysilicon layer.

Description

Technical Field

[0001] The embodiment of the present invention relates to a high-resistivity silicon-on-insulator substrate and a method for forming the same. Background Art

[0002] Integrated circuits (ICs) are traditionally formed on bulk semiconductor substrates. In recent years, semiconductor-on-insulator (SOI) substrates have emerged as an alternative to bulk semiconductor substrates. SOI substrates include a semiconductor substrate, an insulator layer overlying the semiconductor substrate, and a device layer overlying the insulator layer. In addition, SOI substrates result in reduced parasitic capacitance, reduced leakage current, reduced latch-up, and improved semiconductor device performance (e.g., lower power consumption and higher switching speed). Summary of the invention

[0003] An embodiment of the present invention provides a high-resistivity silicon-on-insulator substrate, which includes a semiconductor substrate, a first polysilicon layer, a second polysilicon layer, a third polysilicon layer, an insulator layer, and an active semiconductor layer. The first polysilicon layer is disposed on the semiconductor substrate. The second polysilicon layer is disposed on the first polysilicon layer. The third polysilicon layer is disposed on the second polysilicon layer. The insulator layer is disposed on the third polysilicon layer. The active semiconductor layer is disposed on the insulator layer. The second polysilicon layer has a higher oxygen concentration than the first polysilicon layer and the third polysilicon layer.

[0004] An embodiment of the present invention provides a high-resistivity silicon-on-insulator substrate, which includes a semiconductor substrate, an insulator layer, and a trap-enriched polysilicon structure. The insulator layer is located on the semiconductor substrate. The trap-enriched polysilicon structure is configured between the insulator layer and the semiconductor substrate. The trap-enriched polysilicon structure includes a lower polysilicon layer, a lower oxygen-doped polysilicon layer, an upper polysilicon layer, an upper oxygen-doped polysilicon layer, and a cap polysilicon layer. The lower polysilicon layer has a first thickness and is configured on the semiconductor substrate. The lower oxygen-doped polysilicon layer has a second thickness and is configured on the lower polysilicon layer. The upper polysilicon layer has a third thickness and is configured on the lower oxygen-doped polysilicon layer. The upper oxygen-doped polysilicon layer has a fourth thickness and is configured on the upper polysilicon layer. The cap polysilicon layer has a fifth thickness and is configured on the upper oxygen-doped polysilicon layer. The first thickness and the third thickness are each greater than the second thickness and the fourth thickness, and the fifth thickness is greater than the first thickness and the third thickness.

[0005] An embodiment of the present invention provides a method for forming a high-resistivity silicon-on-insulator substrate, which includes: depositing a first layer of polysilicon on a semiconductor substrate in a chamber; forming a first layer of oxygen-doped polysilicon in the chamber; depositing a second layer of polysilicon on the first layer of oxygen-doped polysilicon in the chamber; forming a second layer of oxygen-doped polysilicon in the chamber; and depositing a polysilicon cap layer on the second layer of oxygen-doped polysilicon in the chamber. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A Cross-sectional views of some embodiments of a high-resistivity silicon-on-insulator (SOI) substrate are shown, which includes a polysilicon layer and an oxygen-doped polysilicon layer between an insulator and a semiconductor substrate.

[0008] Figure 1B , Figure 1C , Figure 1D and Figure 1E Schematic diagrams showing some embodiments of a polysilicon layer and a grain structure of an oxygen-doped polysilicon layer having grain boundaries to trap free charge carriers.

[0009] Figure 2 Cross-sectional views of some additional embodiments of a high-resistivity SOI substrate including a polysilicon layer and an oxygen-doped polysilicon layer between a radio frequency (RF) device and a semiconductor substrate are shown.

[0010] Figures 3 to 8 Cross-sectional views of some embodiments of methods of forming an oxygen-doped polysilicon layer between polysilicon layers to form a high-resistivity SOI substrate are shown.

[0011] Figures 9 to 11 Show Explanation Figures 3 to 8 Flowcharts of some embodiments of the method. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed by itself.

[0013] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0014] Silicon-on-insulator (SOI) substrates are often used for radio frequency (RF) applications. For example, an SOI substrate for RF applications may include an insulator layer disposed on a semiconductor substrate having a high resistivity and a device layer located on the insulator layer. For example, the device layer may include semiconductor materials and embedded semiconductor devices such as transistors, inductors, and / or micro-electromechanical system devices.

[0015] Since the semiconductor substrate is usually silicon, the semiconductor substrate may suffer from parasitic surface conduction (PSC). Fixed charges in the insulator layer attract free charge carriers in the semiconductor substrate, thereby forming a low-resistivity region along the top surface of the semiconductor substrate that is originally intended to have high resistivity to reduce RF losses and crosstalk between different devices in the device layer. For example, RF signals (e.g., RF signals from different devices in the device layer) may induce the formation of eddy currents in the low-resistivity region. Eddy currents may dissipate RF signals and cause RF losses. In addition, eddy currents may reflect RF signals, thereby increasing crosstalk and reducing linearity (e.g., increasing second / third harmonic distortion).

[0016] Therefore, in some RF SOI substrates, a trap-rich polysilicon layer is provided between the insulator and the semiconductor substrate to prevent free charge carriers from accumulating in the semiconductor substrate by trapping free charge carriers in the grain boundaries of the trap-rich polysilicon layer. In order to improve the effectiveness of the trap-rich polysilicon layer in trapping free charge carriers, the average grain size of the trap-rich polysilicon layer may be reduced by adjusting the parameters for forming the trap-rich polysilicon layer to increase the number of grain boundaries. However, even with a smaller grain size, parasitic surface conduction may still exist in the semiconductor substrate.

[0017] Various embodiments of the present application relate to embedding oxygen-doped polysilicon layers between polysilicon layers. In some embodiments, a polysilicon layer is formed in a chamber on a native oxide located on a semiconductor substrate. Then, a low concentration of oxygen is introduced into the chamber and the oxygen diffuses into the top surface of the polysilicon layer, thereby forming a thin oxygen-doped polysilicon layer on the polysilicon layer. The above steps can be repeated to increase the effectiveness of oxygen-doped polysilicon in reducing the PSC effect in the semiconductor substrate. The oxygen-doped polysilicon layer may have an average grain size smaller than that of the polysilicon layer, thereby providing more grain boundaries to capture free charge carriers. In addition, by introducing oxygen into the polysilicon structure, dangling bonds that can capture free charge carriers are formed. Therefore, the oxygen-doped polysilicon layer provides more mechanisms for capturing free charge carriers, thereby reducing the PSC effect in the semiconductor substrate. By reducing the PSC effect, crosstalk, RF loss, and second / third harmonic distortion, for example, can be alleviated.

[0018] Figure 1AA cross-sectional view 100A of some embodiments of a high-resistivity silicon-on-insulator (SOI) substrate having multiple layers of oxygen-doped polysilicon is shown.

[0019] The high resistivity SOI substrate in the cross-sectional view 100A includes a semiconductor substrate 102. In some embodiments, the semiconductor substrate 102 has a low doping concentration to increase the resistivity of the semiconductor substrate 102, wherein the doping concentration is between about 10 μm / cm3 and about 10 μm / cm3. 10 atoms per cubic centimeter and about 10 11 atoms. In some embodiments, a native oxide layer 103 is disposed on the semiconductor substrate 102. A multi-layer polysilicon structure 104 is disposed on the native oxide layer 103. The multi-layer polysilicon structure 104 may include oxygen-doped polysilicon layers 108 alternately stacked with polysilicon layers 106, wherein the oxygen-doped polysilicon layers 108 have a higher oxygen concentration than the polysilicon layers 106. The oxygen-doped polysilicon layers 108 may include oxygen in a range of between about 10% and about 20% atomic percentage. Therefore, the oxygen-doped polysilicon layers 108 do not include a structure in which the stoichiometry of silicon and oxygen is equal to silicon dioxide. The oxygen in the oxygen-doped polysilicon layers 108 forms dangling bonds, which may help capture free charge carriers and prevent the free charge carriers from damaging the high resistivity in the semiconductor substrate 102.

[0020] In some embodiments, a cap polysilicon layer 110 may be disposed on the topmost layer of the oxygen-doped polysilicon layer 108. The oxygen-doped polysilicon layer 108 also has a higher oxygen concentration than the cap polysilicon layer 110. In some embodiments, each of the polysilicon layers 106 has a first thickness t1 and each of the oxygen-doped polysilicon layers 108 has a second thickness t2 that is less than the first thickness t1. In addition, in some embodiments, the cap polysilicon layer 110 has a third thickness t3 that is greater than the first thickness t1 and the second thickness t2. In other embodiments, the third thickness t3 may be approximately equal to the first thickness t1.

[0021] In some embodiments, an insulator layer 112 may be disposed on the cap polysilicon layer 110, and a device layer 114 may be disposed on the insulator layer 112. In some embodiments, the device layer 114 may include an RF device located in and / or on the active semiconductor layer (see, e.g. Figure 2 In some embodiments, the high resistivity of the semiconductor substrate 102 can prevent crosstalk and RF loss between RF devices in the device layer 114 .

[0022] exist Figure 1AIn the cross-sectional view 100A of FIG. 1 , the multi-layer polysilicon structure 104 includes three oxygen-doped polysilicon layers 108 and three polysilicon layers 106. However, in other embodiments, the multi-layer polysilicon structure 104 may include up to fifty oxygen-doped polysilicon layers 108 and up to fifty polysilicon layers 106, wherein each of the polysilicon layers 106 is covered by one of the oxygen-doped polysilicon layers 108. Increasing the total number of oxygen-doped polysilicon layers 108 in the multi-layer polysilicon structure 104 may increase the manufacturing time of the high-resistivity SOI substrate, but may also increase the effectiveness of the multi-layer polysilicon structure 104 in capturing free charge carriers, thereby maintaining the high resistivity of the semiconductor substrate 102.

[0023] Figure 1B Show Figure 1A Schematic diagram 100B of some embodiments of a grain structure in region A of the polysilicon layer 106 .

[0024] Figure 1B The schematic diagram 100B shows microscopically Figure 1A The polysilicon layer 106 has grains 106g separated by grain boundaries 106b. The grain boundaries 106b capture the insulator layer ( Figure 1A 112) and semiconductor substrate ( Figure 1A 102) between the free charge carriers to maintain the semiconductor substrate ( Figure 1A 102) of high resistivity, resulting in a more reliable device layer ( Figure 1A For example, in some embodiments, the average grain size is used to quantify the number of grain boundaries 106b in a region such as region A. In some embodiments, region A is relative to Figure 1A The cross-sectional view 100A is taken from a cross section of the polysilicon layer 106 perpendicular to the page. As the average grain size decreases, the number of grain boundaries 106b increases. For example, the average grain size can be calculated from the microstructure image using various techniques (such as linear intercept method, grain size per area method and other software methods). However, the average grain size can be quantified as an average grain diameter. In addition, for example, many factors (such as processing methods, process conditions (such as temperature, pressure, etc.), and composition) can affect the average grain size of the material.

[0025] In some embodiments, Figure 1B The schematic diagram 100B may have a large (relative to Figure 1C , Figure 1D and Figure 1EIn some embodiments, the first average grain size d1 of the polysilicon layer 106 may be in a range between about 100 nanometers and about 200 nanometers.

[0026] Figure 1C Shown in the Figure 1B Schematic diagram 100B of the grain structure formed on the polysilicon layer 106 Figure 1A Schematic diagram 100C of some embodiments of the grain structure in region B of the oxygen-doped polysilicon layer 108 .

[0027] It should be understood that Figure 1B and Figure 1D The area A is equal to Figure 1C and Figure 1E In some embodiments, region B is relative to Figure 1A The cross-sectional view 100A is taken from a cross section perpendicular to the page of the oxygen-doped polysilicon layer 108. In some embodiments, Figure 1A The oxygen-doped polysilicon layer 108 is formed by implanting oxygen into Figure 1A In some embodiments, Figure 1A The oxygen-doped polysilicon layer 108 has a crystal grain 108g, and the crystal grain 108g has a Figure 1B In some embodiments, the second average grain size d2 may be, for example, in a range between about 20 nanometers and about 40 nanometers. Therefore, in some embodiments, doping the polysilicon layer 106 with oxygen may reduce the average grain size from the first average grain size d1 to the second average grain size d2.

[0028] Figure 1D Show Figure 1A Some embodiments of another grain structure in region A of the polysilicon layer 106 are schematically shown in FIG. 100D.

[0029] Figure 1D Schematic diagram 100D has a die 106g, and the die 106g has a ratio Figure 1B The first average particle size d1 is smaller than the third average particle size d3. Figure 1B and Figure 1D The schematic diagrams in both cases include the same materials, thus forming Figure 1A The process conditions (eg, temperature, pressure, etc.) of the polysilicon layer 106 may cause a difference between the first average grain size d1 and the third average grain size d3. In some embodiments, the third average grain size d3 may be in a range between about 15 nanometers and about 22 nanometers.

[0030] Figure 1E Shown in the Figure 1DSchematic diagram 100D in which a grain structure is formed on the polysilicon layer 106 Figure 1A Schematic diagram 100E of some embodiments of a grain structure in region B of the oxygen-doped polysilicon layer 108 .

[0031] Figure 1E Schematic diagram 100E has a die 108g, and the die 108g has a ratio Figure 1D In some embodiments, Figure 1A The fourth average grain size d4 of the oxygen-doped polysilicon layer 108 may be in a range between, for example, about 1 nanometer and about 10 nanometers. Therefore, in some embodiments, doping the polysilicon layer 106 with oxygen may reduce the average grain size from the third average grain size d3 to the fourth average grain size d4. In addition, in some embodiments, the fourth average grain size d4 may be less than Figure 1C Different factors (such as oxygen concentration, process conditions (such as temperature, pressure, etc.), and / or Figure 1A The oxygen-doped polysilicon layer 108 is associated with Figure 1A The initial grain size of the polysilicon layer 106 may cause this difference.

[0032] Figure 2 A cross-sectional view 200 of some other embodiments of a high-resistivity silicon-on-insulator (SOI) substrate having multiple layers of oxygen-doped polysilicon is shown.

[0033] The high resistivity SOI substrate in the cross-sectional view 200 includes a multi-layer polysilicon structure 104 having seventeen oxygen-doped polysilicon layers 108 and seventeen polysilicon layers 106. Each of the polysilicon layers 106 is covered by each of the oxygen-doped polysilicon layers 108, so that the multi-layer polysilicon structure 104 has an alternating structure of oxygen-doped polysilicon layers 108 and polysilicon layers 106. In some embodiments, the multi-layer polysilicon structure 104 may have a fourth thickness t4, which is measured from the top surface of the topmost oxygen-doped polysilicon layer 108 to the bottom surface of the bottommost polysilicon layer 106. In some embodiments, the fourth thickness t4 may be in a range between, for example, about 180 nanometers and about 1 micrometer. The cap polysilicon layer 110 may have a fifth thickness t5, and in some embodiments, the fifth thickness t5 depends on the fourth thickness t4. For example, in some embodiments, the sum of the fourth thickness t4 and the fifth thickness t5 is about 2 micrometers. Therefore, in such an embodiment, the fifth thickness t5 may be within a range between about 1.82 micrometers and about 1 micrometer.

[0034] In some embodiments, the device layer 114 located above the insulator layer 112 may include an active semiconductor layer 202 and devices such as transistors 204. Other devices in the active semiconductor layer 202 may include, for example, inductors or RF MEMS devices. The transistors 204 may each include a source / drain region 206 located within the active semiconductor layer 202. A gate barrier layer 208 may be disposed between the source / drain regions 206 and above the active semiconductor layer 202. The transistors 204 may each also include a gate electrode 210 disposed on the gate barrier layer 208. In some embodiments, there is more than one transistor 204 in the device layer 114. For example, a multi-layer polysilicon structure 104 is used to capture free charge carriers to maintain a high resistivity SOI substrate in the cross-sectional view 200, thereby reducing crosstalk and RF losses between the transistors 204. By increasing the number of oxygen-doped polysilicon layers 108 in the multi-layer polysilicon structure 104 , more free charge carriers may be trapped in the multi-layer polysilicon structure 104 , thereby increasing the reliability of the transistor 204 .

[0035] Figures 3 to 8 Cross-sectional views 300 to 800 illustrate some embodiments of methods of forming a high resistivity SOI substrate. Figures 3 to 8 This is an explanation of a method, but it should be understood that Figures 3 to 8 The structure disclosed in the invention is not limited to this method, but can be used alone as a structure independent of the method.

[0036] like Figure 3 As shown in the cross-sectional view 300 of FIG. 1 , a semiconductor substrate 102 is provided. In some embodiments, the semiconductor substrate 102 may include silicon of a doping type (e.g., n-type or p-type) with a low doping concentration so that the semiconductor substrate 102 has a high resistivity. Therefore, as the doping concentration decreases, the resistivity of the semiconductor substrate 102 increases. In some embodiments, the doping concentration is between about 10 cm3 and about 10 cm3. 10 atoms per cubic centimeter and about 10 11 In some embodiments, due to a residual effect of the process, a native oxide layer 103 may be formed on the semiconductor substrate 102. The native oxide layer 103 may include, for example, silicon dioxide. In some embodiments, the native oxide layer 103 has a sixth thickness t6 in a range between about 0.1 nanometers and about 1 nanometer.

[0037] like Figure 4As shown in the cross-sectional view 400 of FIG. 4 , the semiconductor substrate 102 may be loaded into the epitaxial chamber 402. In some embodiments, the epitaxial chamber may be a low pressure chemical vapor deposition (LPCVD) chamber. A polysilicon deposition process 404 may be performed at a first temperature in the epitaxial chamber 402 for a first time using a first precursor to deposit a first polysilicon layer 406 on the native oxide layer 103. In some embodiments, the native oxide layer 103 causes the first polysilicon layer 406 to include polysilicon instead of further growing the semiconductor substrate 102 through an epitaxial process. For example, assuming that the semiconductor substrate 102 is single crystal silicon, if the native oxide layer 103 is omitted, a single crystal silicon layer will be grown instead of the first polysilicon layer 406. Therefore, due to the presence of the native oxide layer 103, the first polysilicon layer 406 is different from the semiconductor substrate 102. In some embodiments, the first polysilicon layer 406 grows to a seventh thickness t7 that may be in a range of, for example, between about 20 nanometers and about 60 nanometers. In some embodiments, the first polysilicon layer 406 has a top surface that appears wavy or non-planar, while in other embodiments, the first polysilicon layer 406 may have a substantially planar top surface (eg, Figure 1A ).

[0038] For example, in some embodiments, such as in a variable temperature deposition method, the polysilicon deposition process 404 may use a first precursor including dichlorosilane (DCS) and be performed in the epitaxial chamber 402 at a first temperature between about 650 degrees Celsius and about 875 degrees Celsius for a first time of about 20 seconds, so that the seventh thickness t7 is within a range between about 55 nanometers and about 65 nanometers. For example, in some embodiments, the first temperature may be approximately equal to 850 degrees Celsius and the seventh thickness t7 may be approximately equal to 60 nanometers. In some embodiments, the variable temperature deposition may be performed using a pressure of about 80 torr. In other embodiments, the first time may be increased to increase the seventh thickness t7 of the first polysilicon layer 406. Under the aforementioned conditions of the variable temperature deposition method, the first polysilicon layer 406 may have a thickness of about 100 nm to about 100 nm. Figure 1B The grain structure of the first polysilicon layer 406 is similar to the grain structure of the schematic diagram 100B in FIG. 1 , and the grain structure has a first average grain size d1 in a range between about 100 nanometers and about 200 nanometers. In some embodiments, the first average grain size d1 of the first polysilicon layer 406 is relative to Figure 4 The cross-sectional view 400 is measured from a cross section perpendicular to the page.

[0039] For example, in other embodiments, such as in a constant temperature deposition method, the polysilicon deposition process 404 may be performed for a first time of about 40 seconds at a first temperature between about 650 degrees Celsius and about 750 degrees Celsius in the epitaxial chamber 402 using a first precursor including silane, so that the seventh thickness t7 is within a range between about 15 nanometers and about 25 nanometers. For example, in some embodiments, the first temperature may be approximately equal to 690 degrees Celsius, and the seventh thickness t7 may be approximately equal to 20 nanometers. In some embodiments, the constant temperature deposition method is performed using a pressure of about 30 Torr. Although the first time of the constant temperature deposition method is greater than the first time of the variable temperature deposition method, since the first temperature of the constant temperature deposition method is lower than the first temperature of the variable temperature deposition method, the seventh thickness t7 of the constant temperature deposition method may be less than the seventh thickness t7 of the variable temperature deposition method. However, the first time, the first temperature and / or the first precursor conditions may be adjusted to adjust the seventh thickness t7 of the first polysilicon layer 406 to a desired value.

[0040] Under the aforementioned conditions of the constant temperature deposition method, the first polysilicon layer 406 may have a thickness similar to Figure 1D 100D, the grain structure has a third average grain size d3 in a range between about 15 nanometers and about 22 nanometers. Since the constant temperature deposition method utilizes a first temperature that is smaller than the first temperature of the variable temperature deposition method, the third average grain size d3 may be smaller than the first average grain size d1. Therefore, in some embodiments, the lower first temperature reduces grain growth and, therefore, provides more grain boundaries to capture free charge carriers.

[0041] like Figure 5 As shown in the cross-sectional view 500 of FIG. 5 , an oxygen doping process 502 is performed in the epitaxial chamber 402 at a second temperature for a second time using a second precursor to form a first oxygen-doped polysilicon layer 508 on the first polysilicon layer 406. In some embodiments, the oxygen doping process 502 dopes the top surface of the first polysilicon layer 406 to a second thickness t2. In some embodiments, the second thickness t2 may be in a range between about 1 nanometer and about 2 nanometers. Therefore, after forming the first oxygen-doped polysilicon layer 508, the first polysilicon layer 406 and the first oxygen-doped polysilicon layer 508 together have a thickness equal to or approximately equal to t2. Figure 4 The seventh thickness t7 is the eighth thickness t8.

[0042] In some embodiments, the oxygen doping process 502 is performed in the epitaxial chamber 402 using a mixture of helium and oxygen as a second precursor. To prevent reactions in the epitaxial chamber 402 using hydrogen used for purging, the oxygen concentration in the second precursor is low. For example, in some embodiments, the second precursor includes between about 0.1 atomic percent and about 1 atomic percent oxygen mixed with helium. In some embodiments, the mixture of helium and oxygen is premixed and can enter the epitaxial chamber 402 at a flow rate of 500 standard cubic centimeters per minute. In some embodiments, hydrogen flows into the epitaxial chamber 402 at a flow rate of 50 standard liters per minute. Therefore, the oxygen concentration in the epitaxial chamber 402 can be 10 parts per million of the hydrogen concentration in the epitaxial chamber 402. In addition, in some embodiments, the second time can be about 20 seconds, and the second temperature can be in a range between about 650 degrees Celsius and about 700 degrees Celsius. After the oxygen doping process 502, a purge step may be performed to clean the epitaxial chamber 402. The purge step may include hydrogen gas at a flow rate of 50 standard liters per minute.

[0043] For example, in some embodiments, such as in a variable temperature deposition method, the oxygen doping process 502 may be performed in the epitaxial chamber 402 at a second temperature in a range between about 550 degrees Celsius and about 750 degrees Celsius. For example, in some embodiments, the second temperature may be approximately equal to about 650 degrees Celsius. In some embodiments of the variable temperature deposition method, the first polysilicon layer 406 may have a thickness of about 1000 nm. Figure 1B The first oxygen-doped polysilicon layer 508 may have a grain structure similar to that of the schematic diagram 100B in FIG. Figure 1C The grain structure similar to the schematic diagram 100C in FIG. 100C has a second average grain size d2 in the range between about 20 nanometers and about 40 nanometers. In some embodiments, the second average grain size d2 of the first oxygen-doped polysilicon layer 508 is relative to Figure 5 The cross-sectional view 500 is measured from a cross section perpendicular to the page. In addition, in the variable temperature deposition method, the second temperature of the oxygen doping process 502 is lower than Figure 4 The first temperature of the polysilicon deposition process 404 is set to 404. In some embodiments, the first time and the second time of the variable temperature deposition method may be equal.

[0044] For example, in other embodiments, such as in a constant temperature deposition method, the oxygen doping process 502 may be performed in the epitaxial chamber 402 at a second temperature between about 550 degrees Celsius and about 750 degrees Celsius. For example, in some embodiments, the second temperature may be about equal to about 690 degrees Celsius. In some embodiments of the constant temperature deposition method, the first polysilicon layer 406 may have a thickness of about 1000 nm. Figure 1D The first oxygen-doped polysilicon layer 508 may have a grain structure similar to that of the schematic diagram 100D in FIG. Figure 1E The grain structure is similar to that of the schematic diagram 100E, Figure 1E The grain structure similar to the schematic diagram 100E in FIG. 1 has a fourth average grain size d4 in the range between about 1 nanometer and about 10 nanometers. In addition, in the constant temperature deposition method, the second temperature of the oxygen doping process 502 is approximately equal to Figure 4 The first temperature of the polysilicon deposition process 404 is set to 404. In some embodiments of the constant temperature method, the first time is greater than the second time.

[0045] In some embodiments of the constant or variable temperature deposition method, the oxygen concentration in the first oxygen-doped polysilicon layer 508 may be in a range between 10% and about 20% due to the low concentration of oxygen in the second precursor and / or the second time. Therefore, the first oxygen-doped polysilicon layer 508 is polysilicon with a small amount of oxygen, rather than silicon dioxide. The composition of the first oxygen-doped polysilicon layer 508 may produce an atomic structure with dangling bonds that can collect free charge carriers. Therefore, the first oxygen-doped polysilicon layer 508 has a smaller average grain size than the first polysilicon layer 406 and also has dangling bonds, thereby providing two mechanisms for capturing free charge carriers, thereby maintaining a high resistivity of the semiconductor substrate 102. Although the first oxygen-doped polysilicon layer 508 provides more mechanisms as a trap-rich layer for free charge carriers than the first polysilicon layer 406, the oxygen doping process 502 is time-consuming. Therefore, in some embodiments, throughput constraints may limit the second thickness t2 of the first oxygen-doped polysilicon layer 508.

[0046] like Figure 6 As shown in the cross-sectional view 600 of Figure 4 Polysilicon deposition process 404, Figure 5 The oxygen doping process 502, and the purge step are repeated multiple times to form a multi-layer polysilicon structure 104 including a plurality of oxygen-doped polysilicon layers 108 and a plurality of polysilicon layers 106 alternately stacked together. For example, the number of oxygen-doped polysilicon layers 108 and the number of polysilicon layers 106 in the multi-layer polysilicon structure 104 may depend on various factors, such as the desired overall size (e.g., thickness) of the high-resistivity SOI substrate, the number of oxygen-doped polysilicon layers 108 that can effectively capture free charge carriers, and / or the yield. In some embodiments, the multi-layer polysilicon structure 104 may include 3 oxygen-doped polysilicon layers 108 to 50 oxygen-doped polysilicon layers 108. In addition, in some embodiments, the ratio of the total number of oxygen-doped polysilicon layers 108 to the total number of polysilicon layers 106 in the multi-layer polysilicon structure 104 is one to one.

[0047] In addition, in some embodiments, the Figure 4 The first polysilicon layer 406 and Figure 5 The first oxygen-doped polysilicon layer 508 Figure 4 Polysilicon deposition process 404, Figure 5 The oxygen doping process 502 and the purge step are classified into one cycle. Figure 6 , five cycles are required to be performed. All cycles can be performed in-situ (e.g., in the same chamber) in the epitaxial chamber 402. In some embodiments of the variable temperature deposition method, each cycle can take about 4 minutes, while in some embodiments of the constant temperature deposition method, each cycle can take about 1.3 minutes. Since temperature ramping is required between each step in the cycle of the variable temperature deposition process, the variable temperature deposition process may have a longer cycle time. Therefore, the constant temperature deposition process may have a higher yield of forming a high resistivity SOI substrate than the variable temperature deposition process.

[0048] In addition to trapping free charge carriers, the oxygen-doped polysilicon layer 108 also slows down the growth of grains in the polysilicon layer 106 during high temperature processes because grains are often prone to grow at high temperatures. Thus, by slowing down grain growth, the oxygen-doped polysilicon layer 108 protects the grains in the polysilicon layer 106 and prevents a reduction in the number of grain boundaries that exist for trapping free charge carriers. For example, in some embodiments, the presence of the oxygen-doped polysilicon layer 108 can increase the resistivity of the semiconductor substrate 102 from about 30 ohm-cm to about 120 ohm-cm.

[0049] like Figure 7 As shown in the cross-sectional view 700 of , a cap deposition process 702 is performed in the epitaxial chamber 402 to form a cap polysilicon layer 110 on the topmost layer 108t of the oxygen-doped polysilicon layer 108. Therefore, the cap polysilicon layer 110 can be performed in situ (for example, in the same chamber) with the multi-layer polysilicon structure 104. In some embodiments, the cap deposition process 702 is performed at a third temperature for a third time using a first precursor to form a cap polysilicon layer 110 of a third thickness t3. For example, in a variable temperature deposition process, the first precursor may include DCS, and in a constant temperature deposition process, the first precursor may include silane. In some embodiments, the cap polysilicon layer 110 is thicker than any of the underlying polysilicon layers 106. Therefore, the cap deposition process 702 can be performed at a third temperature than the first temperature. Figure 4The third time of the cap deposition process 702 may be longer than the first time of the polysilicon deposition process 404. In some embodiments, the third time of the cap deposition process 702 may depend on the third thickness t3 and may be in a range of, for example, between about 20 minutes and about 25 minutes. To increase the third thickness t3, the third time may be increased. In some embodiments, the third temperature may be greater than the first temperature, while in other embodiments, the third temperature may be approximately equal to the first temperature.

[0050] For example, in some embodiments of the variable temperature deposition process, the third temperature may be equal to about 850 degrees Celsius, and therefore, is approximately equal to the first temperature. Therefore, the cap polysilicon layer 110 and the polysilicon layer 106 may have the same average grain size. In addition, in some embodiments of the constant temperature deposition process, the third temperature may be equal to about 720 degrees Celsius, and therefore, is greater than the first temperature and the second temperature. Therefore, in such embodiments, the cap polysilicon layer 110 may have an average grain size larger than the polysilicon layer 106, and the cap polysilicon layer 110 may have a higher growth rate (e.g., thickness per unit time) than the polysilicon layer 106. To reduce the third time to increase the yield, in some embodiments, the third temperature is increased. However, the cap polysilicon layer 110 may capture free charge carriers, and then the multilayer polysilicon structure 104 may further capture free charge carriers to protect the semiconductor substrate 102.

[0051] like Figure 8 As shown in the cross-sectional view 800 of , an insulator layer 112 may be formed on the cap polysilicon layer 110, and a device layer 114 may be formed on the insulator layer 112. In some embodiments, the insulator layer 112 may include a high dielectric constant dielectric, an oxide (e.g., silicon dioxide), or some other insulator material. The insulator layer 112 may be formed in a furnace to a thickness ranging between about 1 nanometer and about 2 microns. The device layer 114 may include an active semiconductor layer including a semiconductor material and / or an RF device (see Figure 2 ). Furthermore, in some embodiments, before depositing the insulator layer 112 , the cap polysilicon layer 110 may undergo a planarization process (eg, chemical mechanical planarization) to ensure that the device layer 114 is substantially planar.

[0052] Fig. 9 , Fig.10 and Fig.11 Flowcharts illustrating some embodiments of methods 900 , 1000 , and 1100 of forming a high-resistivity SOI substrate.

[0053] Although method 900, method 1000, method 1100 are shown and described as a series of actions or events below, it should be understood that the order of these actions or events should not be interpreted as having a restrictive meaning. For example, some actions can occur in different orders, and / or can occur simultaneously with other actions or events other than the actions or events shown and / or described herein. In addition, when implementing one or more aspects or embodiments described herein, all shown actions may not be needed. In addition, one or more actions in the actions described herein can be implemented in one or more separate actions and / or stages.

[0054] Fig. 9 A flow chart illustrating some embodiments of a method 900 of forming a high resistivity SOI substrate having an oxygen-doped polysilicon layer using a variable temperature deposition process.

[0055] At act 902, a first layer of polysilicon is deposited over a substrate in a chamber at a first temperature. Figure 4 Cross-sectional view 400 of some embodiments is shown corresponding to act 902. For example, in some embodiments, a first layer of polysilicon may be formed using a first precursor comprising DCS at a first temperature approximately equal to 850 degrees Celsius in an epitaxial chamber for approximately 20 seconds.

[0056] At act 904 , oxygen is introduced into the chamber to dope a top surface of the first layer of polysilicon at a second temperature that is lower than the first temperature to form a first layer of oxygen-doped polysilicon over the first layer of polysilicon. Figure 5 Cross-sectional view 500 of some embodiments is shown corresponding to act 904. For example, in some embodiments, a second precursor comprising a mixture of oxygen and helium can be used in the epitaxial chamber at a second temperature approximately equal to 650 degrees Celsius for approximately 20 seconds to form a first layer of oxygen-doped polysilicon.

[0057] At act 906, a second layer of polysilicon is deposited over the first layer of oxygen-doped polysilicon in a chamber at a first temperature. For example, in some embodiments, a first precursor including DCS may be used in an epitaxial chamber at a first temperature of approximately 850 degrees Celsius for approximately 20 seconds to form the second layer of polysilicon.

[0058] At act 908 , oxygen is introduced into the chamber to dope a top surface of the second layer of polysilicon at a second temperature to form a second layer of oxygen-doped polysilicon over the second layer of polysilicon. Figure 6 Cross-sectional view 600 of some embodiments is shown corresponding to acts 906 and 908. For example, in some embodiments, a second precursor comprising a mixture of oxygen and helium can be used in the epitaxial chamber at a second temperature of approximately 650 degrees Celsius for approximately 20 seconds to form a second layer of oxygen-doped polysilicon.

[0059] At act 910, a polysilicon cap layer is deposited over a second layer of oxygen-doped polysilicon at a first temperature in a chamber. Figure 7 Cross-sectional view 700 of some embodiments is shown corresponding to act 910. For example, in some embodiments, a first precursor including DCS may be used at a first temperature approximately equal to 850 degrees Celsius for approximately 20 minutes in an epitaxial chamber to form a polysilicon cap layer.

[0060] Fig.10 A flow chart illustrating some embodiments of a method 1000 of forming a high resistivity SOI substrate having an oxygen-doped polysilicon layer using a constant temperature deposition process.

[0061] At act 1002, a first layer of polysilicon is deposited over a substrate in a chamber at a first temperature for a first time. Figure 4 Cross-sectional view 400 of some embodiments is shown corresponding to act 1002. For example, in some embodiments, a first layer of polysilicon may be formed in an epitaxial chamber at a first temperature of approximately 690 degrees Celsius for a first time of approximately 40 seconds using a first precursor comprising silane.

[0062] At act 1004 , oxygen is introduced into the chamber to dope a top surface of the first layer of polysilicon at a first temperature for a second time less than the first time to form a first layer of oxygen-doped polysilicon over the first layer of polysilicon. Figure 5 Cross-sectional view 500 of some embodiments is shown corresponding to act 1004. For example, in some embodiments, a first layer of oxygen-doped polysilicon may be formed in an epitaxial chamber at a first temperature of approximately 690 degrees Celsius using a second precursor comprising a mixture of oxygen and helium for a second time of approximately 20 seconds.

[0063] At act 1006, a second layer of polysilicon is deposited over the first layer of oxygen-doped polysilicon at a first temperature in the chamber for a first time. For example, in some embodiments, a first precursor comprising silane may be used in the epitaxial chamber at a first temperature of approximately 690 degrees Celsius for a first time of approximately 40 seconds to form the second layer of polysilicon.

[0064] At act 1008, oxygen is introduced into the chamber to dope a top surface of the second layer of polysilicon at the first temperature for a second time to form a second layer of oxygen-doped polysilicon over the second layer of polysilicon. Figure 6Cross-sectional view 600 of some embodiments is shown corresponding to act 1006 and act 1008. For example, in some embodiments, a second layer of oxygen-doped polysilicon may be formed in the epitaxial chamber at a first temperature of approximately 690 degrees Celsius using a second precursor comprising a mixture of oxygen and helium for a second time of approximately 20 seconds.

[0065] At act 1010, a polysilicon cap layer is deposited over the second layer of oxygen-doped polysilicon in a chamber at a second temperature greater than the first temperature for a third time greater than the first time. Figure 7 Cross-sectional view 700 of some embodiments is shown corresponding to act 1010. For example, in some embodiments, a polysilicon cap layer may be formed using a first precursor comprising silane at a second temperature of approximately 720 degrees Celsius in an epitaxial chamber for a third time of approximately 25 minutes.

[0066] Fig.11 A flow chart illustrating some other embodiments of a method 1100 for forming a high-resistivity SOI substrate having an oxygen-doped polysilicon layer.

[0067] At act 1102, a first layer of polysilicon is deposited over a substrate in a chamber. Figure 4 Cross-sectional view 400 of some embodiments corresponding to act 1102 is shown.

[0068] At act 1104, a first layer of oxygen-doped polysilicon is formed over the first layer of polysilicon. Figure 5 Cross-sectional view 500 of some embodiments corresponding to act 1104 is shown.

[0069] At act 1106 , a second layer of polysilicon is deposited in the chamber over the first layer of oxygen-doped polysilicon.

[0070] At act 1108, a second layer of oxygen-doped polysilicon is formed over the second layer of polysilicon. Figure 6 Cross-sectional view 600 of some embodiments corresponding to acts 1106 and 1108 is shown.

[0071] At act 1110 , a polysilicon cap layer is deposited in a chamber over the second layer of oxygen-doped polysilicon. Figure 7 Cross-sectional view 700 of some embodiments corresponding to act 1110 is shown.

[0072] Therefore, the present disclosure is directed to a high-resistivity SOI substrate including an oxygen-doped polysilicon layer between polysilicon layers to prevent free charge carriers from concentrating in a region of the semiconductor substrate, thereby maintaining the reliability of an RF device configured on the high-resistivity SOI substrate.

[0073] Therefore, in some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, which includes: a semiconductor substrate; a first polysilicon layer configured on the semiconductor substrate; a second polysilicon layer configured on the first polysilicon layer; a third polysilicon layer configured on the second polysilicon layer; an insulator layer configured on the third polysilicon layer; and an active semiconductor layer configured on the insulator layer, wherein the second polysilicon layer has a higher oxygen concentration than the first polysilicon layer and the third polysilicon layer.

[0074] In some embodiments, the high-resistivity silicon-on-insulator substrate further includes: a native oxide layer located between the semiconductor substrate and the first polysilicon layer.

[0075] In some embodiments, in the high-resistivity silicon-on-insulator substrate described above, the first polysilicon layer has a first thickness, and wherein the second polysilicon layer has a second thickness that is smaller than the first thickness.

[0076] In some embodiments, in the high-resistivity silicon-on-insulator substrate described above, the third polysilicon layer has a third thickness that is greater than the first thickness and greater than the second thickness.

[0077] In some embodiments, in the high-resistivity silicon-on-insulator substrate, the first polysilicon layer has a first average grain size, and the second polysilicon layer has a second average grain size that is smaller than the first average grain size.

[0078] In some embodiments, the high-resistivity silicon-on-insulator substrate further includes: a transistor device, which is configured on the active semiconductor layer.

[0079] In other embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, which includes: a semiconductor substrate; an insulator layer located on the semiconductor substrate; a trap-enriched polysilicon structure configured between the insulator layer and the semiconductor substrate, the trap-enriched polysilicon structure including: a lower polysilicon layer having a first thickness and configured on the semiconductor substrate; a lower oxygen-doped polysilicon layer having a second thickness and configured on the lower polysilicon layer; an upper polysilicon layer having a third thickness and configured on the lower oxygen-doped polysilicon layer; an upper oxygen-doped polysilicon layer having a fourth thickness and configured on the upper polysilicon layer; and a cap polysilicon layer having a fifth thickness and configured on the upper oxygen-doped polysilicon layer, wherein the first thickness and the third thickness are each greater than the second thickness and the fourth thickness, and wherein the fifth thickness is greater than the first thickness and the third thickness.

[0080] In some embodiments, the high-resistivity silicon-on-insulator substrate further includes: a native oxide layer located between the semiconductor substrate and the lower polysilicon layer of the trap-enriched polysilicon structure.

[0081] In some embodiments, in the above-mentioned high-resistivity silicon-on-insulator substrate, the lower polysilicon layer of the trap-enriched polysilicon structure directly contacts the native oxide layer, wherein the upper oxygen-doped polysilicon layer directly contacts the top polysilicon layer, and wherein the top polysilicon layer directly contacts the insulator layer.

[0082] In some embodiments, in the above-mentioned high-resistivity silicon-on-insulator substrate, the trap-enriched polysilicon structure also includes: one or more intermediate polysilicon layers, located between the lower oxygen-doped polysilicon layer and the upper polysilicon layer; and one or more intermediate oxygen-doped polysilicon layers, located between the lower oxygen-doped polysilicon layer and the upper polysilicon layer, wherein the one or more intermediate polysilicon layers and the one or more intermediate oxygen-doped polysilicon layers are alternately stacked together.

[0083] In some embodiments, in the high-resistivity silicon-on-insulator substrate described above, an atomic percentage of oxygen to polysilicon in each of the lower oxygen-doped polysilicon layer and the upper oxygen-doped polysilicon layer is between about 10% and about 20%.

[0084] In some embodiments, in the high-resistivity silicon-on-insulator substrate, the lower oxygen-doped polysilicon layer has a first average grain size, and wherein the lower polysilicon layer has a second average grain size that is larger than the first average grain size.

[0085] In some embodiments, in the high-resistivity silicon-on-insulator substrate, the capping polysilicon layer has a third average grain size that is larger than the second average grain size.

[0086] In yet other embodiments, the present disclosure relates to a method for forming a high-resistivity silicon-on-insulator (SOI) substrate, the method comprising: depositing a first layer of polysilicon over a semiconductor substrate in a chamber; forming a first layer of oxygen-doped polysilicon in the chamber; depositing a second layer of polysilicon over the first layer of oxygen-doped polysilicon in the chamber; forming a second layer of oxygen-doped polysilicon in the chamber; and depositing a polysilicon top layer over the second layer of oxygen-doped polysilicon in the chamber.

[0087] In some embodiments, in the above method of forming a high-resistivity silicon-on-insulator substrate, the first layer of oxygen-doped polysilicon and the second layer of oxygen-doped polysilicon are formed by diffusing oxygen into the top surface of the first layer of polysilicon and the top surface of the second layer of polysilicon, respectively.

[0088] In some embodiments, in the above method of forming a high-resistivity silicon-on-insulator substrate, the diffusion of oxygen includes introducing a premixed gas into the chamber, the premixed gas comprising less than 1 atomic percent of oxygen mixed in helium.

[0089] In some embodiments, in the above-mentioned method of forming a high-resistivity silicon-on-insulator substrate, the chamber is an epitaxial chamber, and wherein the method further includes: cleaning the chamber using hydrogen after forming the second layer of oxygen-doped polysilicon and before depositing the polysilicon top cap layer.

[0090] In some embodiments, in the above-mentioned method of forming a high-resistivity silicon-on-insulator substrate, the first layer of polysilicon, the first layer of oxygen-doped polysilicon, the second layer of polysilicon and the second layer of oxygen-doped polysilicon are respectively formed at a first temperature for a first time, at a second temperature for a second time, at a third temperature for a third time and at a fourth temperature for a fourth time, wherein the first temperature and the third temperature are respectively greater than the second temperature and the fourth temperature, wherein the third temperature is approximately equal to the first temperature, wherein the first time, the second time, the third time and the fourth time are approximately equal, and wherein the third time is greater than the first time.

[0091] In some embodiments, in the above-mentioned method of forming a high-resistivity silicon-on-insulator substrate, the first layer of polysilicon, the first layer of oxygen-doped polysilicon, the second layer of polysilicon, the second layer of oxygen-doped polysilicon and the polysilicon cap layer are respectively formed at a first temperature for a first time, at a second temperature for a second time, at a third temperature for a third time, at a fourth temperature for a fourth time and at a fifth temperature for a fifth time, wherein the first temperature, the second temperature, the third temperature and the fourth temperature are approximately equal, wherein the fifth temperature is greater than the first temperature, wherein the first time is greater than the second time, wherein the third time is greater than the fourth time, and wherein the fifth time is greater than the first time and the third time.

[0092] In some embodiments, the method for forming a high-resistivity silicon-on-insulator substrate further includes: depositing an insulator layer on the polysilicon cap layer; and depositing a semiconductor layer on the insulator layer.

[0093] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A high resistivity silicon-on-insulator substrate, comprising: Semiconductor substrate; A first polysilicon layer, disposed on the semiconductor substrate; a second polysilicon layer, disposed on the first polysilicon layer; a third polysilicon layer, disposed on the second polysilicon layer; a fourth polysilicon layer, disposed on the third polysilicon layer; A cap polysilicon layer, disposed on the fourth polysilicon layer; An insulator layer, disposed on the cap polysilicon layer; as well as an active semiconductor layer, disposed on the insulating layer, wherein the second polysilicon layer and the fourth polysilicon layer have a higher oxygen concentration than each of the first polysilicon layer, the third polysilicon layer and the cap polysilicon layer, Compared with each of the first polysilicon layer, the third polysilicon layer and the cap polysilicon layer, the second polysilicon layer and the fourth polysilicon layer have more dangling bonds and smaller grain sizes.

2. The high-resistivity silicon-on-insulator substrate according to claim 1, further comprising: A native oxide layer is located between the semiconductor substrate and the first polysilicon layer. 3 . The high-resistivity silicon-on-insulator substrate of claim 1 , wherein the first polysilicon layer has a first thickness, and wherein the second polysilicon layer has a second thickness that is smaller than the first thickness. 4 . The high-resistivity silicon-on-insulator substrate of claim 3 , wherein the third polysilicon layer has a third thickness that is greater than the first thickness and greater than the second thickness. 5 . The high-resistivity silicon-on-insulator substrate of claim 1 , wherein the first polysilicon layer has a first average grain size, and wherein the second polysilicon layer has a second average grain size that is smaller than the first average grain size.

6. The high-resistivity silicon-on-insulator substrate according to claim 1, further comprising: The transistor device is arranged on the active semiconductor layer.

7. A high resistivity silicon-on-insulator substrate, comprising: Semiconductor substrate; an insulator layer, located on the semiconductor substrate; A trap-enriched polysilicon structure is disposed between the insulator layer and the semiconductor substrate, and the trap-enriched polysilicon structure comprises: a lower polysilicon layer having a first thickness and disposed on the semiconductor substrate; a lower oxygen-doped polysilicon layer having a second thickness and disposed on the lower polysilicon layer; an upper polysilicon layer having a third thickness and disposed on the lower oxygen-doped polysilicon layer; an upper oxygen-doped polysilicon layer having a fourth thickness and disposed on the upper polysilicon layer; and a cap polysilicon layer having a fifth thickness and disposed on the upper oxygen-doped polysilicon layer, wherein the first thickness is greater than the second thickness and the fourth thickness, and the third thickness is greater than the second thickness and the fourth thickness, and wherein the fifth thickness is greater than the first thickness and the third thickness, and Compared with each of the lower polysilicon layer, the upper polysilicon layer and the cap polysilicon layer, the lower oxygen-doped polysilicon layer and the upper oxygen-doped polysilicon layer have a higher oxygen concentration, more dangling bonds and smaller grain size.

8. The high-resistivity silicon-on-insulator substrate according to claim 7, further comprising: A native oxide layer is located between the semiconductor substrate and the lower polysilicon layer of the trap-enriched polysilicon structure.

9. The high-resistivity silicon-on-insulator substrate of claim 8, wherein the lower polysilicon layer of the trap-enriched polysilicon structure directly contacts the native oxide layer, wherein the upper oxygen-doped polysilicon layer directly contacts the cap polysilicon layer, and wherein the cap polysilicon layer directly contacts the insulator layer.

10. The high-resistivity silicon-on-insulator substrate according to claim 7, wherein the trap-enriched polysilicon structure further comprises: one or more intermediate polysilicon layers located between the lower oxygen-doped polysilicon layer and the upper polysilicon layer; as well as One or more intermediate oxygen-doped polysilicon layers are located between the lower oxygen-doped polysilicon layer and the upper polysilicon layer, wherein the one or more intermediate polysilicon layers and the one or more intermediate oxygen-doped polysilicon layers are alternately stacked together.

11. The high-resistivity silicon-on-insulator substrate of claim 7, wherein an atomic percentage of oxygen to polysilicon in each of the lower oxygen-doped polysilicon layer and the upper oxygen-doped polysilicon layer is between 10% and 20%.

12. The high-resistivity silicon-on-insulator substrate of claim 7, wherein the lower oxygen-doped polysilicon layer has a first average grain size, and wherein the lower polysilicon layer has a second average grain size that is larger than the first average grain size. 13 . The high-resistivity silicon-on-insulator substrate of claim 12 , wherein the capping polysilicon layer has a third average grain size that is larger than the second average grain size.

14. A method for forming a high-resistivity silicon-on-insulator substrate, the method comprising: depositing a first layer of polysilicon over a semiconductor substrate in a chamber; forming a first layer of oxygen-doped polysilicon in the chamber; depositing a second layer of polysilicon on the first layer of oxygen-doped polysilicon in the chamber; forming a second layer of oxygen-doped polysilicon in the chamber; as well as depositing a polysilicon cap layer on the second layer of oxygen-doped polysilicon in the chamber, The first layer of oxygen-doped polysilicon and the second layer of oxygen-doped polysilicon include polycrystalline grains and have a higher oxygen concentration than the first layer of polysilicon and the second layer of polysilicon and the polysilicon top cap layer, wherein the first layer of oxygen-doped polysilicon is formed by diffusing oxygen into the top surface of the first layer of polysilicon, wherein the diffusion of oxygen includes introducing a premixed gas of oxygen and helium into the chamber at a flow rate of 500 standard cubic centimeters per minute, wherein the premixed gas contains less than 1 atomic percent of oxygen, and wherein the first layer of oxygen-doped polysilicon and the second layer of oxygen-doped polysilicon contain an oxygen concentration between 10% and 20%.

15. The method of forming a high-resistivity silicon-on-insulator substrate according to claim 14, wherein the second layer of oxygen-doped polysilicon is formed by diffusing oxygen into a top surface of the second layer of polysilicon.

16. The method of forming a high-resistivity silicon-on-insulator substrate according to claim 14, wherein the chamber is an epitaxial chamber, and wherein the method further comprises: After forming the second layer of oxygen-doped polysilicon and before depositing the polysilicon cap layer, the chamber is cleaned using hydrogen gas.

17. The method for forming a high-resistivity silicon-on-insulator substrate according to claim 14, wherein the first layer of polysilicon is formed at a first temperature for a first time, the first layer of oxygen-doped polysilicon is formed at a second temperature for a second time, the second layer of polysilicon is formed at a third temperature for a third time, and the second layer of oxygen-doped polysilicon is formed at a fourth temperature for a fourth time, wherein the first temperature and the third temperature are respectively greater than the second temperature and the fourth temperature, wherein the third temperature is equal to the first temperature, wherein the first time, the second time, the third time and the fourth time are equal, and wherein the third time is greater than the first time.

18. The method for forming a high-resistivity silicon-on-insulator substrate according to claim 14, wherein the first layer of polysilicon is formed at a first temperature for a first time, the first layer of oxygen-doped polysilicon is formed at a second temperature for a second time, the second layer of polysilicon is formed at a third temperature for a third time, the second layer of oxygen-doped polysilicon is formed at a fourth temperature for a fourth time, and the polysilicon capping layer is formed at a fifth temperature for a fifth time, wherein the first temperature, the second temperature, the third temperature and the fourth temperature are equal, wherein the fifth temperature is greater than the first temperature, wherein the first time is greater than the second time, wherein the third time is greater than the fourth time, and wherein the fifth time is greater than the first time and the third time.

19. The method for forming a high-resistivity silicon-on-insulator substrate according to claim 14, further comprising: depositing an insulator layer over the polysilicon cap layer; as well as A semiconductor layer is deposited over the insulator layer.

20. A high resistivity silicon-on-insulator substrate, comprising: Semiconductor substrate; an insulator layer, located on the semiconductor substrate; A trap-enriched polysilicon structure is disposed between the insulator layer and the semiconductor substrate, wherein the trap-enriched polysilicon structure comprises: a lower polysilicon layer; a lower oxygen-doped polysilicon layer, disposed on the lower polysilicon layer; an upper polysilicon layer disposed on the lower oxygen-doped polysilicon layer, wherein the lower oxygen-doped polysilicon layer has a smaller average grain size than the lower polysilicon layer and the upper polysilicon layer; an upper oxygen-doped polysilicon layer disposed on the upper polysilicon layer and having a higher oxygen concentration than the upper polysilicon layer; and a cap polysilicon layer, disposed on the upper oxygen-doped polysilicon layer, an active semiconductor layer disposed on the insulator layer and the trap-enriched polysilicon structure; and The semiconductor device is configured on and / or within the active semiconductor layer.

21. The high-resistivity silicon-on-insulator substrate of claim 20, wherein the lower oxygen-doped polysilicon layer is thinner than the lower polysilicon layer and the upper polysilicon layer.

22. The high-resistivity silicon-on-insulator substrate of claim 20, wherein the lower oxygen-doped polysilicon layer has a higher oxygen concentration than the lower polysilicon layer and the upper polysilicon layer.

23. The high-resistivity silicon-on-insulator substrate according to claim 20, further comprising: A native oxide layer is located between the semiconductor substrate and the trap-enriched polysilicon structure.

24. A high-resistivity silicon-on-insulator substrate according to claim 20, wherein the cap polysilicon layer has a larger average grain size than the upper oxygen-doped polysilicon layer and the lower oxygen-doped polysilicon layer, and wherein the cap polysilicon layer is thicker than the upper oxygen-doped polysilicon layer, the lower oxygen-doped polysilicon layer, the lower polysilicon layer and the upper polysilicon layer.

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