A high resistivity well-diffused low-voltage diode and its fabrication method

Abstract

A high-resistivity trap-diffused low-voltage diode and its fabrication method are disclosed. This invention relates to semiconductor devices. The invention involves selective diffusion on a high-resistivity CZ silicon substrate to fabricate a low-resistivity P+ substrate. Deoxidation treatment is performed on both the high-resistivity substrate and the highly doped low-resistivity P+ substrate to reduce the oxygen content of the device substrate and lower the product's IR. High oxygen content in the substrate easily leads to more load centers, resulting in more defects during production and causing high reverse leakage current. Therefore, the oxygen content should be less than 1 x 10⁻⁶. 17 pcs / cm 3 At the same time, by combining the trap technology, the breakdown point of the diode junction under high current is changed from the edge to the central region, thereby improving the overall withstand voltage capability and reliability of the product.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device, in particular to a high-resistivity well diffusion low-voltage diode and a preparation method. BACKGROUND

[0002] The most important thing for a low-voltage diode is to have a low and stable reverse breakdown voltage and a low reverse leakage current IR, and the high and low resistivity of the substrate determines the reverse breakdown voltage of the diode, and the substrate doping concentration and oxygen content determine the IR of the product. At present, low-voltage diode products generally use low-resistivity wafers for process production, and such process is limited to:

[0003] 1) Low-resistance epitaxial wafers have uniform and stable electrical properties, but the cost is high;

[0004] 2) It is difficult to produce ordinary CZ ultra-low resistivity wafers, and the voltage stability is poor and the IR is large, which increases the power consumption of the circuit in application, cannot meet the low-power requirement of the circuit, and the product reliability is also affected, resulting in the decline of product quality. SUMMARY

[0005] The present application provides a high-resistivity well diffusion low-voltage diode with small leakage current, low cost and high reliability, and a preparation method.

[0006] The technical scheme of the present application is: a high-resistivity well diffusion low-voltage diode, comprising:

[0007] A P substrate silicon wafer;

[0008] A P+ substrate region extending downward from the top surface of the P substrate silicon wafer;

[0009] A P deoxidation region extending downward from the top surface of the P substrate silicon wafer;

[0010] A P+ deoxidation region extending downward from the top surface of the P+ substrate region; the downward extension depth of the P+ deoxidation region is less than the downward extension depth of the P deoxidation region;

[0011] An N+ well region located outside the P+ deoxidation region and extending downward from the top surface of the P deoxidation region;

[0012] An N+ main junction region extending downward from the top surface of the P+ deoxidation region;

[0013] An oxide passivation layer located above the N+ main junction region and the N+ well region; and

[0014] A metal layer provided on the upper surface and the lower surface of the diode.

[0015] Specifically, the depth of the P+ substrate region is 4-40 um.

[0016] Specifically, the depth of the P and P+ deoxidation region is 5-50 um.

[0017] Specifically, the depth of the N+ well region is 3-40 um.

[0018] Specifically, the depth of the N+ main junction region is 2-30 um.

[0019] A preparation method of a high-resistivity well diffusion low-voltage diode, comprising the following steps:

[0020] S001: P substrate selection;

[0021] S002: first oxidation;

[0022] An oxide film is grown on the wafer surface, and the oxide film thickness is required to be 15000-30000 angstroms;

[0023] S003: first front P+ diffusion region selective lithography;

[0024] The P+ substrate region to be diffused is reserved on the oxide film, and the rest is protected with a photoresist;

[0025] S004: oxide film removal;

[0026] The oxide film above the P+ substrate region to be diffused is removed, exposing the front diffusion region;

[0027] S005: P+ substrate region boron pre-deposition and diffusion;

[0028] The boron impurities are deposited on the surface of the P+ substrate region, and through high-temperature diffusion, a low-resistance P+ substrate region is formed. The substrate region produced in this step is the real substrate region of the low-voltage diode, and its concentration determines the size of the reverse breakdown voltage of the diode;

[0029] S006: high-resistance silicon substrate and low-resistance P+ substrate (diffusion formed) deoxidation treatment, forming P deoxidation region and P+ deoxidation region;

[0030] S007: second front N+ diffusion well region selective lithography;

[0031] The semi-circular arc-shaped well channel region to be diffused is reserved on the upper surface of both sides of the P+ substrate region, and the rest is protected with a photoresist;

[0032] S008: oxide film removal;

[0033] The oxide film above the semi-circular arc-shaped well channel region to be diffused is removed, exposing the front N+ well region to be diffused;

[0034] S009: Phosphorus pre-deposition and propulsion in the N+ well region;

[0035] Phosphorus impurities are deposited on the surface of the semi-circular trap channel region to be diffused, and then diffused at high temperature to form an N+ trap region.

[0036] S010: Selective photolithography of the N+ main junction region to be diffused on the front side three times;

[0037] N+ main junction regions to be diffused are reserved on the upper surface of the P+ deoxidation region and in part of the N+ well region, and the rest are protected with photoresist.

[0038] S011: Oxide film removal;

[0039] Remove the oxide film above the N+ main junction region to be diffused to expose the N+ main junction region to be diffused on the front side;

[0040] S012: Phosphorus pre-deposition and advancement in the N+ main junction region

[0041] Phosphorus impurities are deposited on the silicon surface to be diffused, and then diffused at high temperature to form an N+ main junction region;

[0042] S013: Four selective photolithography steps on the front side to remove the oxide layer on the electrode surface;

[0043] The oxide film at the junction of the N+ main junction region and the N+ well region is covered with photoresist, while the remaining areas are exposed. The surface oxide passivation layer is removed by a wet etching process.

[0044] S014: Metal evaporation: Double-sided evaporation of Ag metal.

[0045] This invention selectively diffuses to create a low-resistivity P+ substrate on a high-resistivity CZ silicon substrate. By deoxidizing both the high-resistivity substrate and the heavily doped low-resistivity P+ substrate, the oxygen content of the device substrate is reduced, thus lowering the product's IR. High oxygen content in the substrate easily leads to more load centers, resulting in more defects during production and causing high reverse leakage current. Therefore, the oxygen content should be less than 1 x 10⁻⁶. 17 pcs / cm 3 At the same time, by combining the trap technology, the breakdown point of the diode junction under high current is changed from the edge to the central region, thereby improving the overall withstand voltage capability and reliability of the product. Attached Figure Description

[0046] Figure 1 This is a structural schematic diagram of step S001 of the present invention.

[0047] Figure 2 This is a structural schematic diagram of step S002 of the present invention.

[0048] Figure 3 This is a structural schematic diagram of step S003 of the present invention.

[0049] Figure 4 is a structural schematic diagram of step S004 of the present application,

[0050] Figure 5 is a structural schematic diagram of step S005 of the present application,

[0051] Figure 6 is a structural schematic diagram of step S006 of the present application,

[0052] Figure 7 is a structural schematic diagram of step S007 of the present application,

[0053] Figure 8 is a structural schematic diagram of step S008 of the present application,

[0054] Figure 9 is a structural schematic diagram of step S009 of the present application,

[0055] Figure 10 is a structural schematic diagram of step S010 of the present application,

[0056] Figure 11 is a structural schematic diagram of step S011 of the present application,

[0057] Figure 12 is a structural schematic diagram of step S012 of the present application,

[0058] Figure 13 is a structural schematic diagram of step S013 of the present application Figure 1 ,

[0059] Figure 14 is a structural schematic diagram of step S013 of the present application Figure 2 ,

[0060] Figure 15 is a structural schematic diagram of a finished device of the present application;

[0061] In the figure, 100 is a P substrate silicon wafer, 200 is a P deoxidation region, 300 is a P+ deoxidation region, 400 is an N+ well region, 500 is an N+ main junction region, 600 is an oxide passivation layer, and 700 is a metal layer. DETAILED DESCRIPTION

[0062] Embodiments of the present application are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout the drawings denote the same or similar elements or elements having the same or similar functions. The embodiments described below by reference to the drawings are exemplary only, and are used only to explain the present application, and cannot be understood as limiting the present application.

[0063] The present application is as follows Figures 1-15A high resistivity well diffusion low voltage diode, comprising:

[0064] A P substrate silicon wafer 100;

[0065] A P+ substrate region extending downward from a top surface of the P substrate silicon wafer 100;

[0066] A P deoxidation region extending downward from the top surface of the P substrate silicon wafer;

[0067] A P+ deoxidation region extending downward from the top surface of the P+ substrate region; the P+ deoxidation region extends to a depth less than that of the P deoxidation region;

[0068] An N+ well region 400 located outside the P+ deoxidation region 300 and extending downward from the top surface of the P deoxidation region 200;

[0069] An N+ main junction region 500 extending downward from the top surface of the P+ deoxidation region 300;

[0070] An oxide passivation layer 600 located above the N+ main junction region 500 and the N+ well region 400; and

[0071] A metal layer 700 provided on the upper and lower surfaces of the diode.

[0072] Further defined, the depth of the P+ substrate region is 4-40um

[0073] Further defined, the depth of the P deoxidation region 200 is 5-50um.

[0074] Further defined, the depth of the N+ well region 400 is 3-40um.

[0075] The depth of the P+ substrate region is determined by the depth of the N+ main junction region 500, which is generally 3-10um deeper than the N+ base region, and the N+ well region 400 is generally 5-10um deeper than the diffusion region of the N+ main junction region 500 to be diffused in S012;

[0076] Further defined, the depth of the N+ main junction region 500 is 2-30um.

[0077] A method for manufacturing a high resistivity well diffusion low voltage diode, characterized in that it comprises the following steps:

[0078] S001: Selecting a P substrate;

[0079] Select a P substrate silicon wafer 100 with different resistivity according to the voltage requirement of different products, generally 0.01-1Ω;

[0080] S002: One oxidation;

[0081] Growth of oxide film on the wafer surface, oxide film thickness requirement 15000-30000 angstrom;

[0082] S003: One positive P+ diffusion area selective lithography;

[0083] Reserve P+ substrate area for diffusion on the oxide film, the rest is protected by photoresist; P+ substrate area width: different product size, different reserved area, generally remove S007 step N+ trap area 400 width (50-150um) and cutting width (50-100um), P+ substrate area width selection to ensure maximum utilization of device area, to ensure product forward, reverse and other capabilities.

[0084] S004: Oxide film removal;

[0085] Remove the oxide film above the P+ substrate area to be diffused, exposing the front surface of the diffusion area;

[0086] S005: P+ substrate area boron pre-deposition and diffusion;

[0087] Deposition of a certain concentration of boron impurities on the surface of P+ substrate area, doping concentration determined by product reverse breakdown voltage (conventional 5-10V material substrate resistivity is 0.002-0.01Ω.cm, corresponding to the doping concentration is generally: 3E19~5E20 / cm 3 ), through high temperature diffusion, form a low resistance P+ substrate area; The P+ substrate area produced in this step is the real substrate area of low voltage diode, its concentration and uniformity determine the reverse breakdown voltage of diode and electrical consistency;

[0088] S006: High resistance silicon substrate and low resistance P+ substrate (diffusion formed) deoxidation treatment, forming P deoxidation area 200 and P+ deoxidation area;

[0089] Silicon substrate deoxidation treatment in high temperature furnace, P+ substrate area depth is different, deoxidation zone depth is also different, generally in 5-50um, the temperature requirement is 1000-1250℃, the time is 30-400min;

[0090] S007: Secondary positive N+ diffusion well area selective lithography;

[0091] Reserve half-circular arc-shaped well channel area to be diffused on both sides of the upper surface of P+ substrate area, the rest is protected by photoresist, N+ trap area 400 width is generally 50-150um;

[0092] S008: Oxide film removal;

[0093] The oxide film above the semicircular arc-shaped well channel region to be diffused is removed, and the N+ well region 400 to be diffused on the front surface is exposed;

[0094] S009: N+ well region 400 phosphorus pre-deposition and promotion;

[0095] Phosphorus impurities are deposited on the surface of the semicircular arc-shaped well channel region to be diffused, and the concentration of this region is lighter than that of the N+ main junction region 500 to be diffused in S012, generally 1E19~4E20 / cm 3 , through high-temperature diffusion, forming N+ well region 400, in order to ensure that the N+ well region 400 has higher voltage resistance than the N+ main junction region 500, the N+ well region 400 is generally 5-10um deeper than the N+ main junction region 500 to be diffused in S012; This step changes the breakdown point of the junction under high current from the edge to the central region, improves the overall voltage resistance of the product, and improves the reliability of the product.

[0096] S010: Three times of front surface N+ main junction region 500 to be diffused selective lithography;

[0097] Reserve N+ main junction region 500 to be diffused on the surface of P+ substrate region and part of N+ well region 400, and the rest is protected with photoresist;

[0098] S011: Oxide film removal;

[0099] The oxide film above the N+ main junction region 500 to be diffused is removed, and the N+ main junction region 500 to be diffused on the front surface is exposed;

[0100] S012: N+ main junction region 500 phosphorus pre-deposition (or ion implantation) and promotion;

[0101] Phosphorus impurities are deposited on the surface of the silicon to be diffused (the diffusion concentration is determined according to the voltage rating of the device, generally 5E20~1E21 / cm 3） Through high-temperature diffusion, forming N+ main junction region 500, the depth is generally 2-30um, the diffusion depth is determined according to the required reverse breakdown voltage rating, the reverse breakdown voltage of the diode is determined by the doping concentration of the substrate and N+ main junction region 500 on both sides of the PN junction, when the surface doping concentration is the same, the deeper the junction depth, the lower the doping concentration at the junction, and the higher the voltage;

[0102] The breakdown voltage calculation formula of the single-sided abrupt junction (this formula is also applicable to the gradual change junction) is:

[0103] V BR =(Ɛs*E 2 Crit ) / (2e*N B )

[0104] Where Ɛs is the dielectric constant of silicon, E CritThe critical electric field of silicon is slowly increased with the increase of the doping concentration, NB is the doping concentration of the low-doped side of the single-sided junction, e is the electronic charge, and it can be seen from the formula that the breakdown voltage is reduced with the increase of the doping concentration.

[0105] S013: four times of front surface selective photolithography, removing the oxide layer of the electrode surface;

[0106] Referring to Figures 13-14 As shown in the figure, the oxide film at the connection between the N+ main junction area 500 and the N+ well area 400 is covered with a photoresist, and the remaining area is exposed, and the surface oxide passivation layer 600 is removed by a wet etching process;

[0107] The oxide film between the upper surface of the N+ main junction area 500 and the outer edge of the N+ well area 400 is covered with a photoresist, and the remaining area is exposed;

[0108] The width of the reserved oxide film on the upper surface of the crystal grain determines the size of the available soldering surface, the narrower the reserved width, the larger the available area of the crystal grain, and the better the performance, but due to the limitation of exposure accuracy, the reserved width should not be too narrow, and the range of 20-40um is the best.

[0109] S014: metal evaporation: double-sided evaporation of Ag metal.

[0110] S015: electrode surface photolithography: selective photolithography, removing the glass layer and the metal on the cutting path surface; S016: metal etching: using a metal etching solution to etch and remove the exposed metal on the wafer surface.

[0111] The present application selectively diffuses a low-resistance P+ substrate on a high-resistivity CZ silicon substrate, and deoxidizes the high-resistivity wafer substrate and the high-doped low-resistance P+ substrate to reduce the oxygen content of the device substrate and reduce the product IR. 17 3 At the same time, combined with the well process, the breakdown point of the diode junction is changed from the edge to the central area when the current is large, the overall voltage resistance of the product is improved, the product reliability is improved, and the product reliability is improved.

[0112] The present application diffuses a low-resistance P+ deoxidized substrate area on a P substrate, and produces a diode product on the low-resistance P+ deoxidized substrate area, realizes the preparation of a low-voltage or even super-low-voltage diode product from a high-resistivity wafer, and ensures the consistency of the electrical properties of the product.

[0113] For the content disclosed in the present application, the following points need to be explained:

[0114] ​(1), the disclosed embodiment of the present case only involves the structure involved in the disclosed embodiment of the present case, and other structures can be referred to the general design;

[0115] (2), in the case of no conflict, the disclosed embodiments and the features in the embodiments can be combined to obtain new embodiments;

[0116] The above is only a specific embodiment disclosed in the present case, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A high resistivity well diffused low voltage diode, characterized in that, Comprise: P substrate silicon wafer; P+ substrate region, which extends downward from the top surface of the P substrate silicon wafer; P deoxidation region, which extends downward from the top surface of the P substrate silicon wafer; P+ deoxidation region, which extends downward from the top surface of the P+ substrate region; The P+ deoxidation region extends downward to a depth less than the P deoxidation region; N+ well region, which is located outside the P+ deoxidation region and extends downward from the top surface of the P deoxidation region; N+ main junction region, which extends downward from the top surface of the P+ deoxidation region; Oxide passivation layer, which is located above the N+ main junction region and N+ well region; And Metal layer, which is provided on the upper and lower surfaces of the diode; The low resistance P+ substrate region is selectively diffused on high resistivity P substrate silicon wafer. The oxygen content of the device substrate is reduced by deoxidizing the high resistivity P substrate silicon wafer and the highly doped low resistance P+ substrate region, thereby reducing the reverse leakage current of the product. The oxygen content is less than 1x10 17 3 In combination with the well process, the breakdown point of the diode junction is changed from the edge to the central region when the current is large, thereby improving the overall voltage resistance of the product.​ 2. A high resistivity well diffused low voltage diode as defined in claim 1, wherein, The depth of the P+ substrate region is 4-40um.

3. A high resistivity well diffused low voltage diode as defined in claim 1, wherein, The depth of the P deoxidation region is 5-50um.

4. A high resistivity well diffused low voltage diode as defined in claim 1, wherein, The depth of the N+ well region is 3-40um.

5. A high resistivity well diffused low voltage diode as defined in claim 1, wherein, The depth of the N+ main junction region is 2-30um.

6. A method of fabricating a high resistivity well diffused low voltage diode, characterized by, Comprise the following steps: S001: P substrate selection; S002: first oxidation; Grow an oxide film on the wafer surface, with a thickness requirement of 15000-30000 angstroms; S003: first front P+ to be diffused region selective lithography; Reserve the P+ substrate region to be diffused on the oxide film, and the rest is protected with photoresist; S004: oxide film removal; Remove the oxide film above the P+ substrate region to be diffused, exposing the front surface to be diffused; S005: P+ substrate region boron pre-deposition and diffusion; Depositing boron impurities on the surface of the P+ substrate region, and forming a low resistance P+ substrate region through high temperature diffusion; S006: high resistance silicon substrate and low resistance P+ substrate region deoxidation treatment, forming P deoxidation region and P+ deoxidation region; S007: second front N+ to be diffused well region selective lithography; Reserve the semicircular well channel region to be diffused on the upper surface of both sides of the P+ substrate region, and the rest is protected with photoresist; S008: oxide film removal; Remove the oxide film above the semicircular well channel region to be diffused, exposing the front surface to be diffused; S009: N+ well region phosphorus pre-deposition and promotion; Depositing phosphorus impurities on the surface of the semicircular well channel region to be diffused, and forming an N+ well region through high temperature diffusion; S010: third front to be diffused N+ main junction region selective lithography; Reserve the N+ main junction region to be diffused on the upper surface of the P+ substrate region and part of the N+ well region, and the rest is protected with photoresist; S011: oxide film removal; Remove the oxide film above the N+ main junction region to be diffused, exposing the front surface to be diffused; S012: N+ main junction region phosphorus pre-deposition and promotion Depositing phosphorus impurities on the surface of the silicon to be diffused, and forming an N+ main junction region through high temperature diffusion; S013: fourth front selective lithography, removing the oxide layer of the electrode surface; Cover the oxide film at the junction of the N+ main junction region and the N+ well region with photoresist, expose the rest of the area, and remove the surface oxide passivation layer through wet etching process; S014: metal evaporation: double-sided evaporation of Ag metal; The low-resistance P+ substrate region is selectively diffused on a high-resistance P substrate wafer. The oxygen content of the device substrate is reduced by deoxidizing the high-resistance P substrate wafer and the highly-doped low-resistance P+ substrate region, thereby reducing the reverse leakage current of the product. The oxygen content is less than 1x10 17 cm 3 In combination with the well process, the breakdown point of the diode junction is changed from the edge to the central region when the current is large, thereby improving the overall voltage resistance of the product.

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