Double-sided circuit connection

Abstract

The semiconductor device includes a top side and a bottom side opposite the top side. Comprising a semiconductor substrate is arranged between the top side and the bottom side. A component is disposed in the central portion in contact with the semiconductor substrate. The component includes a first electrical connection from the top side and a second electrical connection from the bottom side.

Description

Background Technology

[0001] The present invention relates generally to semiconductor devices and processing methods, and more specifically to semiconductor devices having front and back wiring for double-sided connections that contact the device or device components from opposite sides.

[0002] Integrated circuit devices are constructed by forming diffusion regions in a substrate and then building wiring connections from the substrate to the back-end interconnect (BEOL) structure. Such devices have diffusion regions (e.g., source / drain regions) formed on one side of the device within the substrate, and contacts are deposited (dropped down) to connect to the diffusion regions. Metal lines connect to the contacts and are themselves connected by other contacts and metal lines to form a metal structure according to the chip design. In the case of stacked field-effect transistor (FET) structures where FETs are stacked on top of each other, the device is again built from the substrate. Even if the wafer or substrate is flipped to process the opposite side, the contacts are deposited facing the substrate.

[0003] In devices employing large-stacked gate structures, such as nanosheet stacks, the gate resistance limits the switching capability of the gate-controlled transistor due to the large size of the gate, such as the large distance between the top and bottom of the gate. Gate resistance is introduced at the far bottom of the gate due to contact with the top of the large gate structure.

[0004] Asymmetry in the metal structure with respect to the substrate can lead to parasitic resistance and wiring resistance across the chip or device.

[0005] Therefore, a more balanced wiring layout is needed to address gate resistance issues, area constraints, and parasitic losses in integrated circuits. Multiple connections are also required for the same component to reduce contact resistance and current density through the connecting metal structures. Summary of the Invention

[0006] According to an embodiment of the present invention, a semiconductor device includes a top side and a bottom side opposite to the top side. A central portion includes a semiconductor substrate disposed between the top side and the bottom side. A component disposed in the central portion contacts the semiconductor substrate. The component includes a first electrical connection from the top side and a second electrical connection from the bottom side. By using the first and second electrical connections with the component, resistance caused by insufficient connection surface area is mitigated. As a result of using dual connections, problems such as gate resistance or contact resistance are greatly reduced. Furthermore, the use of another wiring side according to an embodiment of the present invention opens up many possibilities in terms of circuit layout, thereby saving area space and reducing the current density through the electrical connections.

[0007] According to another embodiment of the present invention, a semiconductor device includes: a top-side wiring including metal lines and contacts; and a bottom-side wiring including metal lines and contacts, disposed opposite to the top-side wiring. A central portion includes a semiconductor substrate disposed between the top-side wiring and the bottom-side wiring. A component is formed on the semiconductor substrate and disposed in the central portion. The component includes a first electrical connection from the top-side wiring and a second electrical connection from the bottom-side wiring. The first and second electrical connections can reduce resistance caused by insufficient connection surface area. With a significant reduction in resistance, device performance is improved. Furthermore, the use of another wiring side according to embodiments of the present invention opens up many possibilities in terms of circuit layout, thereby saving area space and reducing the current density through the electrical connections.

[0008] According to another embodiment of the present invention, a semiconductor device includes: a top-side wiring including metal lines and contacts; and a bottom-side wiring including metal lines and contacts, disposed opposite to the top-side wiring. A central portion includes a semiconductor substrate disposed between the top-side wiring and the bottom-side wiring. A first component is formed on the semiconductor substrate and disposed in the central portion. The first component includes a first electrical connection from the top-side wiring and a second electrical connection from the bottom-side wiring. A second component is formed on the semiconductor substrate and disposed in the central portion. The second component includes a first electrical connection from the top-side wiring and a second electrical connection from the bottom-side wiring. In addition to reducing resistance, a bridging member also connects the first electrical connection of the first component to the first electrical connection of the second component. By using a bridging member to connect sub-circuits across the device, top and bottom metal structures can be used in a single circuit spanning the top, bottom, and central regions of the device.

[0009] According to another embodiment of the present invention, a semiconductor device includes: a top-side wiring including metal lines and contacts; and a bottom-side wiring including metal lines and contacts, and disposed opposite to the top-side wiring. A central portion includes a semiconductor substrate disposed between the top-side wiring and the bottom-side wiring. A first circuit is disposed in the top-side wiring and the bottom-side wiring. The first circuit has a first component including a first electrical connection from the top-side wiring and a second electrical connection from the bottom-side wiring. A second circuit is disposed in the top-side wiring and the bottom-side wiring. The second circuit includes a second component having a first electrical connection from the top-side wiring and a second electrical connection from the bottom-side wiring. A bridging member connects the first circuit to the second circuit to form a single circuit spanning the top-side wiring, the bottom-side wiring, and the central portion, wherein the top-side wiring is a mirror image of the bottom-side wiring relative to the central portion. In addition to reducing resistance, the bridging member also connects the first electrical connection of the first component to the first electrical connection of the second component. By using the bridging member to connect sub-circuits across the device, top and bottom metal structures can be used in a single circuit spanning the top, bottom, and central regions of the device.

[0010] These and other features and advantages of the invention will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0011] The following description will provide details of preferred embodiments with reference to the following figures, in which:

[0012] Figure 1 A schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention is shown. The semiconductor device has a central portion with a substrate and includes a metal structure in the top side and a metal structure in the bottom side, wherein the metal structures in the top side and the bottom side provide dual connections with components, and the metal structures in the top side and the bottom side are mirror images of each other in one or more dimensions.

[0013] Figure 2 A schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention is shown. The semiconductor device has a central portion with a substrate and includes a metal structure in the top side and a metal structure in the bottom side, wherein the metal structures in the top side and the bottom side provide dual connections and have similar metal densities, but are not completely mirror images of each other.

[0014] Figure 3 A top layout view of a semiconductor device according to an embodiment of the present invention is shown, wherein the semiconductor device includes a metal structure in the top side and a metal structure in the bottom side, wherein the metal structures in the top side and the bottom side provide dual connections and are mirror images of each other in one or more dimensions;

[0015] Figure 4 An embodiment of the invention is shown in Figure 3 Three schematic cross-sectional views of a semiconductor device, taken at section lines A, B, and E, wherein the semiconductor device includes a metal structure in the top side and a metal structure in the bottom side, wherein the metal structures in the top side and the bottom side provide dual connections and are mirror images of each other in one or more dimensions.

[0016] Figure 5 A top view of a semiconductor device according to an embodiment of the present invention is shown, wherein the semiconductor device includes a metal structure in the top side and a metal structure in the bottom side, wherein the metal structures in the top side and the bottom side provide dual connections but are not mirror images of each other, and include through-hole contacts through the semiconductor substrate.

[0017] Figure 6 An embodiment of the invention is shown in Figure 5The three schematic cross-sectional views of the semiconductor device are taken at section lines C, D and F, wherein the semiconductor device includes a metal structure in the top side and a metal structure in the bottom side, wherein the metal structures in the top side and the bottom side provide dual connections but are not mirror images of each other, and include through contacts that penetrate the semiconductor substrate.

[0018] Figure 7 A schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention is shown. The semiconductor device has a central portion with a substrate and a nanosheet stacked gate structure having dual connections, which are also connected by through contacts extending through the substrate to reduce gate resistance.

[0019] Figure 8 A schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention is shown. The semiconductor device has a central portion with a substrate and a nanosheet stacked gate structure, as well as an active region with dual connections connected across different circuits.

[0020] Figure 9 A schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention is shown. The semiconductor device has a central portion with a substrate and a nanosheet stacked gate structure, and active regions with dual connections connected across different circuits via bridging elements, the dual connections also being connected via through-contact elements; and

[0021] Figure 10 A schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention is shown. The semiconductor device has a central portion with a substrate and a nanosheet stacked gate structure, as well as stacked field-effect transistors with dual connections that are connected across different circuits by bridging elements and are also connected by through contacts. Detailed Implementation

[0022] According to embodiments of the present invention, apparatus and methods are described including a semiconductor device having front and back wiring to allow dual connections to a single component. The dual connections may include a connection from a top wiring circuit and a connection from a bottom wiring circuit. The top and bottom wiring circuits are separated by a semiconductor substrate. Connections between the dual connections may be made, for example, using through contacts. The dual connections may be controlled to simultaneously activate the component from both the top and bottom wiring circuits. In other embodiments, the top and bottom wiring circuits may be used independently to power the component or to derive signals from the component.

[0023] Dual connections are formed within a metal layer or structure of a semiconductor device, and also on opposite sides of the semiconductor device, providing access to components via those opposite sides. The metal layer or structure provides completely separate connections from the same components. In this way, current density can be reduced by employing a completely different circuit path from common components of the semiconductor device (e.g., gate, source region, drain region, etc.).

[0024] In one embodiment, an electrical connection can be made between two device elements having front and back sides connected to the same device element. In one example, the source / drain (S / D) region can be connected from both the front and back sides of the device. In another example, the gate region can be connected from both the front and back sides of the device.

[0025] In useful embodiments, a first wiring connection can be made to a component (e.g., to the top of the S / D converter), and a second wiring connection can be made to the same component (the bottom of the S / D converter), and a third wiring connection (e.g., a through contact formed through the semiconductor substrate) can be made between the first and second wiring connections. This can include many different configurations. For example, the wiring connection can be engaged on one side or the other, or the connection can pass through the substrate on which the component is formed.

[0026] In another embodiment, the component may include a gate, wherein a first wiring connection may be made, for example, to the top of the gate, and a second wiring connection may be made to the same component (e.g., to the bottom of the gate), and a third wiring connection may be made between the first wiring connection and the second wiring connection.

[0027] In other embodiments, a first wiring connection can be made to the top of the first S / D and the top of the second S / D, and a second wiring connection and a third wiring connection can be made to the bottom of the first S / D and the bottom of the second S / D, as well as to the first wiring. In one embodiment, a first top and bottom connection can be made to the first device S / D, and a second top and bottom connection can be made to the gate of the second device. One or more electrical connections can be made between the first device and the second device.

[0028] By utilizing top-side and bottom-side wiring circuitry, a more symmetrical power or signal structure is achieved. The top-side and bottom-side circuitry can be mirror images of each other, or they can have different layouts. Even with different layouts, similar metal density can be used to provide a more uniform voltage field across the device. In either case, the top-side and bottom-side circuitry provides greater electrical symmetry and parallelism to the device.

[0029] By making the back metal parallel to the front metal, circuit performance can be improved by reducing wiring resistance and parasitic resistance. Furthermore, the additional back metal also improves electromigration resistance by reducing the current density through the electrical connections. For example, two connections instead of one reduce the current density by approximately half. This is particularly evident in small-node devices, where feature sizes are on the nanometer scale.

[0030] When used in conjunction with a gate structure, top-side and bottom-side wiring improves the electrostatic performance of devices with thicker nanosheet (NS) stacks (especially stacks with, for example, three or more sheets) by contacting the gate from both sides. In this way, the voltage drop across the gate structure due to gate resistance is minimized.

[0031] Embodiments of the present invention can be applied to any type of semiconductor device or chip. In particularly useful embodiments, a chip with logic circuitry may include dual connections according to embodiments of the present invention. For example, this embodiment may include input / output (I / O) circuitry, high-performance computing (HPC) circuitry, clock buffers, processors, memory devices, or any other integrated circuit chip or combination thereof. By utilizing top-side and bottom-side metals to clamp the central portion of the device in parallel, the circuit performance of any of these devices can be improved by reducing wiring and parasitic resistance. Furthermore, adding additional metals to opposite sides of the device can be integrated into any manufacturing process with little or no impact on cost or processing time.

[0032] In useful embodiments, the top and bottom metals are uniformly distributed to disperse current density. In particularly useful embodiments, the front metal structure is a mirror image of the back metal structure. Mirroring can include one-dimensional, two-dimensional, or three-dimensional symmetry between the top and bottom metal structures relative to the central plane (or central region) of the device. In this way, an intentional effort is made to form corresponding contacts and metal lines on opposite sides of the device. This can include identical width, length, footprint, connection points, spacing, etc., of the metal structures on opposite sides of the device.

[0033] Referring now to the accompanying drawings, where the same reference numerals denote the same or similar elements, and first referring to... Figure 1 The diagram illustrates a schematic cross-sectional view of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a central region 102. The central region 102 may include a front-end line (FEOL) structure and may also include a middle line (MOL) structure. The central region 102 may include a substrate 101 having semiconductor components 104 formed therein and / or on it.

[0034] Substrate 101 may include any suitable substrate structure, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and preferably includes a single-crystal semiconductor. In one example, substrate 101 may include a silicon-containing material. Illustrative examples of silicon-containing materials suitable for a substrate may include, but are not limited to, Si, SiGe, SiGeC, SiC, and multiple layers thereof. Although silicon is the primary semiconductor material used in wafer fabrication, alternative semiconductor materials may be used as additional layers, such as, but not limited to, germanium, gallium arsenide, gallium nitride, silicon germanium, cadmium telluride, zinc selenide, etc.

[0035] Semiconductor component 104 may include, for example, active regions (such as source / drain regions (S / D regions)), gate structures, capacitor plates, memory elements, etc. Other components may include other electronic and electrical components. Contacts connected to the component as described herein provide physical and electrical connections. Dual connections provide at least two contacts for the component, wherein each of the dual connections is associated with wiring on opposite sides of the device. Semiconductor component 104 with dual connections is formed on or in substrate 101 in central region 102.

[0036] In one embodiment, the central region 102 is sandwiched between the top side 106 and the bottom side 108 of the semiconductor device 100. In this embodiment, the metal structures of the top side 106 and the bottom side 108 are mirror images of each other. For example, the metal lines 114 and contacts 118, 120 of the top side 106 provide symmetry or mirror imagery with the metal lines 116 and contacts 122, 124 of the bottom side 108. The metal structures of the top side 106 will be collectively referred to as top-side wiring 110, and the metal structures of the bottom side 108 will be collectively referred to as bottom-side wiring 112. The symmetry or mirror imagery provided between the top-side wiring 110 and the bottom-side wiring 112 can extend to one or more dimensions. For example, the top-side wiring 110 can be symmetrical to the bottom-side wiring 112 in any one or all of the x, y, and / or z directions, where two of these directions define the plane of the substrate 101.

[0037] The symmetry between the top-side wiring 110 and the bottom-side wiring 112 is provided to reduce the asymmetry of the overall electrical characteristics of the semiconductor device 100. For example, the symmetry provides two paths for the flow of circuit current. Half of the current flows through the top-side wiring 110, while the other half flows through the bottom-side wiring 112. By reducing the amount of current flowing through each wiring, this implementation avoids high currents that could lead to electromigration faults.

[0038] Additionally, parasitic resistance and wiring resistance can be reduced or better controlled based on the characteristics of the top-side wiring 110 and the bottom-side wiring 112. It should be understood that perfect symmetry is not required, and the degree of symmetry can vary based on the performance objectives of a specific design.

[0039] Central region 102 includes double-sided circuit connections (double connections) from both top-side wiring 110 and bottom-side wiring 112. Contact 118 connects to component 104 from top side 106, and contact 122 connects to component 104 from bottom-side wiring 112. Contacts 118 and 122 can be positioned relative to each other in the same vertical column and contact the component from opposite sides. Top-side wiring 110 and bottom-side wiring 112 can provide power or signal connections to component 104.

[0040] It should be understood that top-side wiring 110 and bottom-side wiring 112 can be constructed outward from the central region 102 by constructing one side and then flipping the semiconductor device to construct the other side. In other embodiments, the construction may be unidirectional from the bottom side 108 to the top side 106 and vice versa. Top-side wiring 110 and bottom-side wiring 112 are in electrical communication with each other. The dual connections can work together to provide concurrent power or signals to a single component from opposite sides of the device. The dual connections can also work independently of each other, for example, powering a component from one side under a first condition (e.g., activating a first circuit) and powering a component from both sides under a second condition (e.g., activating a second circuit, where the component is shared by both circuits).

[0041] In some embodiments, it may be useful to have a connection 126 between the top-side wiring 110 and the bottom-side wiring 112. The connection 126 may include a through contact that extends through the central region 102, for example, connected to or through the substrate of the semiconductor device 100. The connection 126 may be formed from one side, or it may be formed from the top side 106 and the bottom side 108 to meet within the central region 102.

[0042] In one embodiment, an etching mask is formed on the top or bottom side, and etching is performed through the substrate 101 (and any other intermediate structures) to open trenches. The holes or trenches can then be filled using optional barrier layers and conductors to form connectors 126. In some embodiments, connectors 126 may comprise a sequence of connectors or a stack of connectors. It should be understood that... Figure 1 The electrical connections shown in the other accompanying drawings are illustrative, and other connections, wiring configurations, and connection points are considered in accordance with embodiments of the invention.

[0043] refer to Figure 2 The diagram illustrates a schematic cross-sectional view of a semiconductor device 130 according to an embodiment of the present invention. The semiconductor device 130 includes a central region 102. The central region 102 may include a front-end line (FEOL) structure and may also include a middle line (MOL) structure. The central region 102 may include a substrate 101 having semiconductor components 104 formed therein and / or on it.

[0044] Semiconductor component 104 may include, for example, active regions (such as source / drain regions (S / D regions)), gate structures, capacitor plates, memory elements, etc. Other components may include other electronic and electrical components.

[0045] In one embodiment, the central region 102 is sandwiched between the top side 106 and the bottom side 128 of the semiconductor device 130. In this embodiment, the top side 106 and the bottom side 128 do not include a symmetrical structure, but a similar metallic structure is provided based on the metal or conductor density (e.g., the mass of conductor per unit volume) to uniformly distribute the conductive material between the top side 106 and the bottom side 128. In one example, the conductor density between the metallic structures of the top side 106 and the bottom side 128 is kept within approximately 10%.

[0046] In one example, the metal lines 114 and contacts 118, 120 of the top side 106 and the metal lines 136 and contacts 122, 134 of the bottom side 138 provide similar amounts of metal. The metal structure of the top side 106 will be collectively referred to as top-side wiring 110, and the metal structure of the bottom side 128 will be collectively referred to as bottom-side wiring 132. Greater uniformity of current density across the semiconductor device 100 can still be achieved to help control the effects of electromigration, parasitic resistance, and wiring resistance based on the characteristics of the top-side wiring 110 and the bottom-side wiring 132.

[0047] Central region 102 includes double-sided circuit connections from both top-side wiring 110 and bottom-side wiring 132. Contact 118 connects to component 104 from top side 106, and contact 122 connects to component 104 from bottom side 138. Contacts 118 and 122 can be positioned relative to each other in the same vertical column and contact the component from opposite sides. Top-side wiring 110 and bottom-side wiring 132 can provide power or signal connections to component 104.

[0048] It should be understood that the top-side wiring 110 and the bottom-side wiring 132 can be constructed outward from the central region 102 by constructing one side and then flipping the semiconductor device to construct the other side. In other embodiments, the construction can be unidirectional from the bottom side 128 to the top side 106, or vice versa.

[0049] In some embodiments, a connection 126 may be useful between the top-side wiring 110 and the bottom-side wiring 132. The connection 126 may include a through-contact extending through the central region 102, for example, connected to or passing through the substrate of the semiconductor device 130. The connection 126 may be formed from one side, or may be formed from the top side 106 and the bottom side 128 to converge within the central region 102. It should be understood that... Figure 2 The electrical connections shown in the other accompanying drawings are illustrative, and other connections, wiring configurations, and connection points are considered in accordance with embodiments of the invention.

[0050] refer to Figure 3 and Figure 4 The diagram illustrates a top layout view 202 and three schematic cross-sectional views 230, 232, and 234 of a semiconductor device 200 with dual connections according to an embodiment of the invention. Dielectric materials and layers are omitted to allow viewing of the underlying metal structure. Top view 202 shows active regions 204 and 206. In one embodiment, active region 204 includes a p-doped region, and active region 206 includes an n-doped region. This can be reversed, or all regions can be n-doped or p-doped. Active regions 204 and 206 provide S / D regions and channels between S / D regions for transistor devices such as field-effect transistors (FETs). The channel of the device lies beneath a gate conductor 210. The gate conductor 210 is connected to a metal line 214 via a contact 212. Active regions 204 and 206 are connected via a metal line 208 where appropriate. The contact 212 connects the metal line 208 to the metal line 214.

[0051] Shallow Trench Isolation (STI) region 220 is depicted in partial cross-sectional views 230, 232, and 234. View 230 is taken through section line A, view 232 through section line E, and view 234 through section line B, as shown in top view 202. Region 240 shows a mirrored metal structure formed to provide a dual-contact connection. In view 230, the active regions 204 and 206 are dual-connected, both above and below, by contact 212 above and contact 242 below. Metal lines 244 and 248 in region 240 correspond mirror images of their respective metal lines 214 and 208. Similarly, contacts 212 and 242 are dual-connected from their relative positions to the active regions 204 and 206.

[0052] In view 232, the gate conductor 210 and the gate conductor 210 are doubly connected via a contact 212 above the gate conductor 210 and a contact 242 below the gate conductor 210. Metal lines 244 and 248 in region 240 correspond in a mirror image to their respective metal lines 214 and 208. Similarly, contacts 212 and 242 are doubly connected from their relative positions to the gate conductor 210.

[0053] In view 234, the gate conductor 210 and the gate conductor 210 are doubly connected via a contact 212 above the gate conductor 210 and a contact 242 below the gate conductor 210. The metal line 244 in region 240 corresponds to the corresponding metal line 214 in a mirror relationship. Similarly, contacts 212 and 242 are doubly connected from their relative positions to the gate conductor 210.

[0054] Dual connections on opposite sides of a device 200 with a mirror image between the top and bottom metal structures are particularly useful in I / O circuits, clock distribution circuits, high-performance circuits (HPC), and other circuits sensitive to parasitic losses and wiring resistance issues. In this way, the mirroring of the relative wiring scheme reduces current density by halving the current passing through each of the dual connections.

[0055] The dual connections on opposite sides of device 200 also address problems caused by large gate structures. For example, the gate conductor 210 can be activated simultaneously from both the top and bottom to turn the transistor on and off. With large gates, the resistance on the gate structure is high, especially at the furthest points on the gate structure. By providing two connection points on opposite sides of the gate conductor 210, the gate resistance is significantly reduced, and better device performance can be achieved.

[0056] refer to Figure 5 and Figure 6 The diagram illustrates a top layout view 302 and three schematic cross-sectional views 330, 332, and 334 of a semiconductor device 300 with dual connections according to an embodiment of the invention. Dielectric materials and layers are omitted to allow viewing of the underlying metal structure. Top view 302 shows active regions 304 and 306. In one embodiment, active region 304 includes a p-doped region, and active region 306 includes an n-doped region. This can be reversed, or all regions can be n-doped or p-doped. Active regions 304 and 306 provide the S / D regions for forming transistor devices such as field-effect transistors (FETs) and the channel between the S / D regions. The channel of the device lies beneath the gate conductor 310. The gate conductor 310 is connected to a metal line 314 via a contact 312. Active regions 304 and 306 are connected via a metal line 308 where appropriate. The contact 312 connects the metal line 308 to the metal line 314.

[0057] STI region 320 is shown in partial cross-sectional views 330, 332, and 334. View 330 is taken through section line C, view 332 through section line F, and view 334 through section line D, as shown in top view 302. In view 330, active regions 304 and 306, and between active regions 304 and 306, are doubly connected via contact 312 above active regions 304 and 306 and contact 342 below active regions 304 and 306. In view 330, metal lines 344 and 348 correspond in a mirror image to the corresponding metal lines 314 and 308. Similarly, contacts 312 and 342 are doubly connected from their relative positions to active regions 304 and 306.

[0058] In view 334, a double connection is made between the gate conductor 310 and the gate conductor 310 via a contact 312 above the gate conductor 310 and a contact 342 below the gate conductor 310. Metal lines 344 in region 340 correspond to their respective metal lines 314 in a mirror image. Similarly, contacts 312 and 342 are double-connected from their relative positions to the gate conductor 310.

[0059] In view 332, a double connection is made between the gate conductor 310 and the gate conductor 310 via a contact 312 above the gate conductor 310 and a contact 342 below the gate conductor 310. Metal lines 344 and 348 do not correspond in a mirror image to metal lines 314 and 308. Here, a modification has been made so that the back metal structure 354 complements the front metal structure of view 302. In region 352, the front and back metal structures are not symmetrical, but metal balance and double connection are still provided on opposite sides of the central region between the front and back metal structures.

[0060] Through contacts 350 and 351 are provided across the central region (which includes the substrate of device 300) to provide a connection between the front and back metal structures. In view 332, through contact 350 connects metal line 314 to metal line 344. Through contact 350 passes through the substrate and other structures in the central region of the device. In addition to the dual connection provided by contacts 312 and 342, through contact 350 provides an additional conductive path across the central region and reduces the resistance of the connection path between active regions 304 and 306 connected as shown in view 330. The additional connection of through contact 350 can reduce signal delay and allow for an overall lower resistance electrical path between electrical nodes.

[0061] A through-contact 351 is also provided across the central region (which includes the substrate of device 300) to provide a connection between the front and back metal structures. In view 332, the through-contact 351 connects metal line 314 to metal line 344. The through-contact 351 passes through the substrate and other structures in the central region of the device. In addition to the dual connection provided by contacts 312 and 342, the through-contact 351 provides an additional conductive path across the central region, connecting the two ends of the gate conductor 310. This further reduces the gate resistance. The additional connection of the through-contact 351 can reduce signal delay and allow for an overall lower resistivity electrical path. This improves transistor switching performance and reduces signal delay in the gate.

[0062] The dual connections on opposite sides of device 300 are substantially mirror images between the top and bottom metal structures. Although not perfectly symmetrical, the substantial symmetry can still provide improvements for I / O circuits, clock distribution circuits, high-performance circuits (HPC), and other circuits sensitive to parasitic losses and wiring resistance issues, and can still provide improvements in electromigration performance by providing multiple conductive paths.

[0063] The dual connections on opposite sides of device 300 also address problems caused by large gate structures. For example, the gate conductor 310 can be activated simultaneously from both the top and bottom to turn the transistor on and off. The additional connection provided by the through contact 351 further ensures that resistance is reduced, especially at the furthest relative locations on the gate structure (e.g., gate conductor 310). By providing two connection points on opposite sides of the gate conductor 310, plus the redundant through contact 351 between them, gate resistance is reduced, and better device performance can be achieved.

[0064] refer to Figure 7 This image shows a partial schematic cross-sectional view of a semiconductor device 400 with dual connections according to an embodiment of the present invention. Dielectric materials and layers are omitted to allow viewing of the underlying metal structure. The gate structure 410 comprises a nanosheet (NS) structure. The nanosheet comprises multiple layers prefabricated and used to reduce manufacturing costs. The nanosheet typically comprises a large number of alternating layers that are processed to form a metal gate, such as a high-dielectric-constant metal gate (HKMG) structure. Due to area constraints on the semiconductor chip, the gate structure is grown vertically. As the vertical dimension increases, the gate resistance also increases.

[0065] In one embodiment, the gate structure 410 is dually connected via a contact 418 associated with a top-side metal structure 402, including metal lines 414 and 416 and contact 408, and via a contact 420 associated with a bottom-side metal structure 404, including metal line 422. A through-contact 424 spans a central region 406, including a substrate and other components. The through-contact 424 connects the top and bottom of the gate structure 410 via alternative paths. Metal lines 416 and 422 correspond in a mirror relationship; however, in this embodiment, mirroring is not maintained in the higher metal layers (e.g., metal line 414). Instead, metal lines 414 and contact 408 are aligned with the through-contact 424 to provide a more direct connection (e.g., metal line 414, contact 408, metal line 416, through-contact 424, metal line 422) between circuitry on the top side 402, through the central region 406, and to circuitry on the bottom side 404.

[0066] Through-contact 424 extends through the substrate and other structures in the central region 406 of device 400. In addition to the dual connections provided by contacts 418 and 420, through-contact 424 provides an additional conductive path across the central region 406, connecting the two ends of gate structure 410. This further reduces gate resistance, especially for high-nanofamber gate structures comprising multiple layers. The additional connection of through-contact 424, with its direct connection to contact 408 on the top side 402, can further reduce signal / power delay and allow for a lower-resistance electrical path.

[0067] refer to Figure 8 A partial schematic cross-sectional view of a semiconductor device 500 with dual connections according to an embodiment of the present invention is shown. Dielectric materials and layers are omitted to allow viewing of the underlying metal structure. The gate structure 510 may include a nanosheet structure, such as, for example, a high-dielectric-constant metal gate (HKMG) structure. The gate structure 510 is included as part of an electrical circuit 532. The electrical circuit 530 may include any useful circuitry, such as memory circuitry, I / O circuitry, etc. In one embodiment, the gate structure 510 is dually connected via contacts 508 associated with a top-side 502 metal structure including metal lines 516 and contacts 508, and via contacts 520 associated with a bottom-side 504 metal structure including metal lines 522 and contacts 520.

[0068] A dual connection is also provided across the central region 506. Source / drain regions 512 are connected via opposing contacts 508 and 520, which are included as part of electrical circuitry 530. Electrical circuitry 530 may include any useful circuitry, such as memory circuitry, I / O circuitry, etc. Circuitry 530 and circuitry 532 can be connected or wired together using the dual connection between components of each circuit. In this way, the two sub-circuits 530, 532 can form a single circuit distributed across any of the top-side wiring, bottom-side wiring, and central portion of device 500. In one embodiment, circuitry 530 and 532 are connected using dual connections (e.g., metal wires 516 and 522) to form a single input / output circuit. Figure 8 As shown, dual connection paths connect different devices within different circuits 530 and 532, but each component (e.g., S / D region 512 and gate structure 510) includes a top connection (contact 508) and a bottom connection (contact 520).

[0069] Metal lines 516 and 522 correspond in a mirror relationship; however, components and circuit elements can be connected using both the top-side metal structure 502 and the bottom-side metal structure 504 to connect to components within the same component, the same circuit, or different circuits on the chip. The dual-connection structure of the embodiments described herein provides additional connection opportunities and allows for additional flexibility in implementing circuit configurations for performance or functionality. These performance enhancement features can be achieved without increasing chip area or additional processing steps, as the additional metal lines can be integrated into existing process of record (POR) sequences.

[0070] refer to Figure 9 A partial schematic cross-sectional view of a semiconductor device 600 having dual connections with additional through-contact connections according to an embodiment of the present invention is shown. Dielectric materials and layers are omitted to allow viewing of the underlying metal structure. Figure 9 In the configuration shown, local dual connections 634 and 635 are provided via through contacts 628 and 629, respectively, together with contacts 608 and 620. These dual connections are provided across a central region 606 that includes the semiconductor substrate and other chip components. These local connections are then linked to each other or to other structures using higher-level metal structures such as bridging elements 624 and 626.

[0071] Source / drain regions 612 are connected via opposing contacts 608 and 620, which are included as part of electrical circuitry 630. Gate structure 610 is connected via opposing contacts 608 and 620, which are included as part of electrical circuitry 632. Electrical circuitry 630, 632 may include any useful circuitry, such as memory circuitry, I / O circuitry, etc. Circuitry 630 and circuitry 632 may be connected or wired together using a bridging member 624, which may be positioned on one side of the central region 606, in this case on the top side 602. In other embodiments, bridging member 624 may be formed on the bottom side 604, and in other embodiments, bridging member 624 may be formed on both the top side 602 and the bottom side 604, mirrored or non-mirrored relative to the other side.

[0072] In one embodiment, circuits 630 and 632 are connected via a bridging element 624, which includes a metal wire and a contact 626. Contact 626 connects to metal wire 616, which in turn connects to contact 608. Contact 626 can achieve performance advantages by being close to the connection point of contacts 628 and 629. In this way, line resistance can be reduced. Connecting circuits 630 and 632 provides a single input / output circuit distributed across device 600 and located on opposite sides of the central region 606. The dual-connection structure provides additional connectivity opportunities and allows for additional flexibility in implementing circuit configurations for performance or function.

[0073] refer to Figure 10 A partial cross-sectional view of a semiconductor device 700 with dual connections and additional through-contact connections according to an embodiment of the present invention is shown. Dielectric material and layers are omitted to allow viewing of the underlying metal structure. Figure 10 In the configuration shown, local dual connections 734 and 735 are provided via through contacts 728 and 729, respectively, together with contacts 708 and 720. The dual connections are provided across a central region 706 that includes the semiconductor substrate and other chip components. These local connections are then linked to each other or to other structures using higher-level metal structures, such as bridging elements 724 and 726.

[0074] In one embodiment, semiconductor device 700 includes a stacked field-effect transistor (FET) device. The stacked FET device includes an active region 711 (e.g., an S / D region) on a top side 702 and an active region 713 (e.g., an S / D region) on a bottom side 704. The top-side and bottom-side active regions 711, 713 provide S / D regions for operational FETs, which are stacked and separated by a distance 712 including a dielectric. The corresponding active regions 711 and 713 can be connected across the central region using a through contact 728. Active regions 711 and 713 can be connected via contacts 708 and 720, respectively, with contacts 708 and 720 included as part of electrical circuitry 730. A gate structure 710 is connected via opposing contacts 708 and 720, with opposing contacts 708 and 720 included as part of electrical circuitry 732. Here, the gate structure 710 includes a portion 703 on the top side 702 and a portion 705 on the bottom side 704, which are separated by an intermediate dielectric region 709. Portions 703 and 705 can be connected via through-contacts 729. In other embodiments, portions 703 and 705 of the gate structure 710 can be wired independently and function separately from each other.

[0075] Electrical circuits 730 and 732 may include any useful circuitry, such as memory circuits, I / O circuits, etc. Circuits 730 and 732 may be connected or wired together using a bridging member 724, which may be positioned on one side of the central region 706, in this case, on the top side 702. In other embodiments, the bridging member 724 may be formed on the bottom side 704, and in other embodiments, the bridging member 724 may be formed on both the top side 702 and the bottom side 704, in a mirror or non-mirror relationship relative to the other side.

[0076] In one embodiment, circuits 730 and 732 are connected via a bridging element 724, which includes a metal wire and a contact 726. Contact 726 connects to metal wire 716, which in turn connects to contact 708. Contact 726 can achieve performance advantages by being close to the connection point of contacts 728 and 729. In this way, line resistance can be reduced. Connecting circuits 730 and 732 provides a single input / output circuit distributed across device 700 and located on opposite sides of the central region 706. The dual-connection structure provides additional connectivity opportunities and allows for additional flexibility in implementing circuit configurations for performance or function.

[0077] Exemplary applications / uses to which this invention can be applied include, but are not limited to, semiconductor devices. Semiconductor devices may include processors, memory devices, application-specific integrated circuits (ASICs), logic circuits or devices, combinations thereof, and any other circuit devices. In such devices, one or more semiconductor devices may be included in a central processing unit, a graphics processing unit, and / or a separate processor- or computing element-based controller (e.g., logic gates, etc.). Semiconductor devices may include one or more on-board memories (e.g., caches, dedicated memory arrays, read-only memory, etc.). In some embodiments, a semiconductor device may include one or more memories that may be on-board or off-board, or may be dedicated to use by a hardware processor subsystem (e.g., ROM, RAM, basic input / output system (BIOS), etc.).

[0078] In some embodiments, the semiconductor device may include and execute one or more software elements. The one or more software elements may include an operating system and / or one or more applications and / or specific code that implements a specified result. In other embodiments, the semiconductor device may include dedicated, specialized circuitry that performs one or more electronic processing functions to achieve the specified result. Such circuitry may include one or more field-programmable gate arrays (FPGAs) and / or programmable application-programmable logic arrays (PLAs).

[0079] It should be understood that aspects of the invention will be described based on the given illustrative framework; however, other frameworks, structures, substrate materials, and process features and steps may vary within the scope of aspects of the invention.

[0080] It will also be understood that when a component, such as a layer, region, or substrate, is referred to as being "on" or "above" another component, it can be directly on the other component, or there may be intermediate components present. In contrast, when a component is referred to as being "directly on" or "directly above" another component, there are no intermediate components. It will also be understood that when a component is referred to as being "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, or there may be intermediate components present. In contrast, when a component is referred to as being "directly connected" or "directly coupled" to another component, there are no intermediate components.

[0081] Embodiments of the present invention may include designs for integrated circuit chips, which can be created using a graphical computer programming language and stored in a computer storage medium, such as a disk, magnetic tape, physical hard disk drive, or virtual hard disk drive (such as in a memory access network). If the designer does not manufacture the chip or the photomask used to manufacture the chip, the designer can transfer the resulting design directly or indirectly to such an entity by physical means (e.g., by providing a copy of the storage medium storing the design) or electronic means (e.g., via the Internet). The stored design is then converted into a suitable format (e.g., GDSII) for manufacturing the photomask, which typically includes multiple copies of the chip design in question to be formed on a wafer. The photomask is used to define areas of the wafer (and / or layers on it) to be etched or otherwise processed.

[0082] The methods described herein can be used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other higher-level carrier) or a multi-chip package (such as a ceramic carrier with either surface-mount or buried interconnects, or both). In either case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0083] It should also be understood that material compounds will be described according to the listed elements, such as SiGe. These compounds include different proportions of elements within the compound; for example, SiGe includes Si. x Ge 1-x Where x is less than or equal to 1, etc. Additionally, other elements can be included in the compound and still function according to this principle. Compounds with additional elements will be referred to herein as alloys.

[0084] References to "one embodiment" or "embodiment" and other variations thereof in the specification mean that a particular feature, structure, characteristic, etc., described in conjunction with that embodiment is included in at least one embodiment. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout the specification, as well as any other variations, do not necessarily refer to the same embodiment.

[0085] It should be understood that the following use of “ / ”, “and / or”, and “at least one” (e.g., in the cases of “A / B”, “A and / or B”, and “at least one of A and B”) is intended to cover selecting only the first listed option (A), or only the second listed option (B), or both options (A and B). As a further example, in the cases of “A, B, and / or C” and “at least one of A, B, and C”, such wording is intended to cover selecting only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). This can be extended to as many listed items as possible, as is readily understood by those skilled in the art and related fields.

[0086] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that, when used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0087] Spatial relative terms (such as “below,” “under,” “lower,” “above,” “upper,” “top,” “bottom,” etc.) are used herein to facilitate description of the relationship between one element or feature and another, as shown in the figures. It will be understood that, in addition to the orientation depicted in the figures, spatial relative terms are intended to also cover different orientations of the device during use or operation. For example, if the device in the figure is flipped, an element described as “below” or “under” other elements or features will be oriented as “above” other elements or features. Thus, the term “below” can encompass both above and below orientations. The device may also be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more intermediate layers.

[0088] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the scope of this concept, the first element discussed below may be referred to as the second element.

[0089] Preferred embodiments of the apparatus and method have been described (these are intended to be illustrative, not restrictive), and it should be noted that modifications and variations can be made by those skilled in the art based on the above teachings. Therefore, it is to be understood that changes can be made to the specific embodiments disclosed, and these changes are within the scope of the invention as outlined in the appended claims. Thus, aspects of the invention have been described with the detail and exhaustion required by patent law, and the contents claimed and desired for protection under patent certificates are set forth in the appended claims.

Claims

1. A semiconductor device, comprising: Top side and bottom side opposite to the top side; The central portion includes a semiconductor substrate disposed between the top and bottom sides; as well as A component disposed in the central portion on a semiconductor substrate, the component including a first electrical connection from the top side and a second electrical connection from the bottom side.

2. The semiconductor device according to claim 1, wherein, The component includes a gate structure, a first electrical connection to a top portion of the gate structure, and a second electrical connection to a bottom portion of the gate structure opposite to the top portion.

3. The semiconductor device according to claim 1, wherein, The top side includes a metal structure that is symmetrical with respect to the bottom side.

4. The semiconductor device according to claim 1, wherein, The first electrical connection is connected to the second electrical connection via a through contact across the central portion.

5. The semiconductor device according to claim 1, wherein, The component includes an active region, a first electrical connection portion connected to the top portion of the active region, and a second electrical connection portion connected to the bottom portion of the active region opposite to the top portion.

6. The semiconductor device according to claim 5, wherein, The active region includes the source / drain regions of a transistor device.

7. The semiconductor device according to claim 5, wherein, The active region includes the source / drain regions of a stacked field-effect transistor device.

8. A semiconductor device, comprising: Top-side wiring, including metal wires and contacts; Bottom side wiring, including metal wires and contacts, is arranged opposite to the top side wiring; The central portion includes a semiconductor substrate disposed between the top-side wiring and the bottom-side wiring; as well as A component formed on a semiconductor substrate and arranged in the central portion; The component includes a first electrical connection from the top side wiring and a second electrical connection from the bottom side wiring.

9. The semiconductor device according to claim 8, wherein, The component includes a gate structure, a first electrical connection to a top portion of the gate structure, and a second electrical connection to a bottom portion of the gate structure opposite to the top portion.

10. The semiconductor device according to claim 9, wherein, The top and bottom wiring consist of metal structures that are symmetrical about each other.

11. The semiconductor device according to claim 8, wherein, The first electrical connection is connected to the second electrical connection across the central portion via a through contact that penetrates the semiconductor substrate.

12. The semiconductor device according to claim 8, wherein, The component includes an active region, a first electrical connection portion connected to the top portion of the active region, and a second electrical connection portion connected to the bottom portion of the active region opposite to the top portion.

13. The semiconductor device according to claim 12, wherein, The active region includes the source / drain regions of a transistor device.

14. The semiconductor device according to claim 12, wherein, The active region includes the source / drain regions of a stacked field-effect transistor device.

15. The semiconductor device according to claim 8, wherein, The top wiring is a mirror image of the bottom wiring relative to the central part.

16. The semiconductor device according to claim 8, wherein, The top wiring is a mirror image of the bottom wiring in three dimensions.

17. A semiconductor device, comprising: Top-side wiring, including metal wires and contacts; Bottom side wiring, including metal wires and contacts, is arranged opposite to the top side wiring; The central portion includes a semiconductor substrate disposed between the top-side wiring and the bottom-side wiring; A first component formed on a semiconductor substrate and arranged in a central portion, the first component including a first electrical connection portion from a top-side wiring and a second electrical connection portion from a bottom-side wiring; A second component formed on a semiconductor substrate and arranged in the central portion, the second component including a first electrical connection portion from a top side wiring and a second electrical connection portion from a bottom side wiring; as well as A bridging component connects the first electrical connection portion of the first component to the first electrical connection portion of the second component.

18. The semiconductor device according to claim 17, wherein, The first component includes a gate structure, a first electrical connection portion connected to a top portion of the gate structure, and a second electrical connection portion connected to a bottom portion of the gate structure opposite to the top portion.

19. The semiconductor device according to claim 17, wherein, The first electrical connection is connected to the second electrical connection across the central portion via a corresponding through contact that penetrates the semiconductor substrate.

20. The semiconductor device according to claim 17, wherein, The second component includes an active region, a first electrical connection portion connected to the top portion of the active region, and a second electrical connection portion connected to the bottom portion of the active region opposite to the top portion.

21. The semiconductor device according to claim 17, wherein, The top wiring is a mirror image of the bottom wiring relative to the central part.

22. A semiconductor device, comprising: Top-side wiring, including metal wires and contacts; Bottom side wiring, including metal wires and contacts, is arranged opposite to the top side wiring; The central portion includes a semiconductor substrate disposed between the top-side wiring and the bottom-side wiring; A first circuit is arranged in a top-side wiring and a bottom-side wiring. The first circuit includes a first component, which includes a first electrical connection portion from the top-side wiring and a second electrical connection portion from the bottom-side wiring. A second circuit is provided in the top side wiring and the bottom side wiring. The second circuit includes a second component, which includes a first electrical connection portion from the top side wiring and a second electrical connection portion from the bottom side wiring. as well as A bridging element connects a first circuit to a second circuit to form a single circuit spanning a top-side wiring, a bottom-side wiring, and a central portion, wherein the top-side wiring is a mirror image of the bottom-side wiring relative to the central portion.

23. The semiconductor device according to claim 22, wherein, The first component includes a gate structure, a first electrical connection portion of the first component connected to a top portion of the gate structure, and a second electrical connection portion of the first component connected to a bottom portion of the gate structure opposite to the top portion.

24. The semiconductor device according to claim 22, wherein, The first electrical connection is connected to the second electrical connection across the central portion via a corresponding through contact that penetrates the semiconductor substrate.

25. The semiconductor device according to claim 22, wherein, The second component includes an active region, a first electrical connection portion of the second component connected to the top portion of the active region, and a second electrical connection portion of the second component connected to the bottom portion of the active region opposite to the top portion.

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