Semiconductor device and preparation method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body which comprises a first surface and a second surface which are oppositely arranged, and further comprises a first region, a well region and a second region; the gate insulating layer is located on the first surface; the gate layer is located on the side, away from the first surface, of the gate insulating layer; the first dielectric layer is located on the side, away from the first surface, of the gate layer; the semiconductor device further comprises a plurality of first contact holes and a second dielectric layer, and the first contact holes penetrate through the gate insulating layer, the gate layer and the first dielectric layer and expose the side wall of the gate insulating layer, the side wall of the gate layer and the side wall of the first dielectric layer. The second dielectric layer is located on the side wall of the first contact hole, the second dielectric layer located in the same first contact hole forms a second contact hole, and the second contact hole exposes at least part of the surface, located on the first surface, of the first area. The problem that the position deviation of the contact hole is large can be solved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle. Background Technology

[0002] Wide bandgap semiconductor materials such as silicon carbide are widely used in power electronics, automotive, aerospace and other fields due to their excellent high-temperature performance, chemical stability and electronic properties.

[0003] Silicon-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) in related technologies have advantages such as high current density and small cell spacing. Transistors require contact (CT) holes to be fabricated on the interlayer dielectric layer to connect the source and epitaxial layer. Related technologies use an overlay method to fabricate these contact holes. However, when the transistor cell size is small, making the contact hole size approach the capability limit of the photolithography machine, overlay deviations may occur. This means a large positional deviation of the contact hole, which may cause the contact hole to be positioned above the gate, leading to a short circuit between the source and gate; or, a large positional deviation may result in poor performance of the semiconductor device. Summary of the Invention

[0004] This invention provides a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle to solve the problem of large contact hole position deviation.

[0005] According to one aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising: A semiconductor body includes a first surface and a second surface disposed opposite to each other. The semiconductor body also includes a first region, a well region, and a second region. The first region is configured with a first conductivity type and is located on the first surface. The well region is configured with a second conductivity type and is located between the first region and the second region. The second region is configured with the first conductivity type. A gate insulating layer is located on the first surface; A gate layer is located on the side of the gate insulating layer away from the first surface; The first dielectric layer is located on the side of the gate layer away from the first surface; The semiconductor device further includes a plurality of first contact holes and second dielectric layers. The first contact holes penetrate the gate insulating layer, the gate layer and the first dielectric layer, and expose the sidewalls of the gate insulating layer, the gate layer and the first dielectric layer. The second dielectric layer is located on the sidewall of the first contact hole, and the second dielectric layer located on the same first contact hole forms a second contact hole. The second contact hole exposes at least a portion of the surface of the first region located on the first surface.

[0006] Optionally, the second dielectric layer includes a first sidewall and a second sidewall located on the side of the first sidewall away from the first contact hole; the first sidewall includes an undoped oxide layer, and the second sidewall includes a doped oxide layer.

[0007] Optionally, along the thickness direction of the semiconductor device, the height of the second dielectric layer is the same as the depth of the first contact hole.

[0008] According to another aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising: An epitaxial structure is provided, the epitaxial structure comprising a semiconductor body and a gate insulating material layer, a gate material layer and a first dielectric material layer sequentially stacked on the semiconductor body; the semiconductor body includes a first surface and a second surface disposed opposite to each other, the semiconductor body further including a first region, a well region and a second region, the gate insulating material layer being located on the first surface, the first region being configured with a first conductivity type and located on the first surface, the well region being configured with a second conductivity type and located between the first region and the second region, and the second region being configured with the first conductivity type; The first dielectric material layer, the gate material layer, and the gate insulating material layer are patterned to form a first dielectric layer, a gate layer, and a gate insulating layer, and a plurality of first contact holes are formed. A second dielectric material layer is formed, which fills the first contact hole and covers the first dielectric layer; the second dielectric material layer has a third contact hole corresponding to the first contact hole, and along the thickness direction of the semiconductor device, the orthographic projection of the third contact hole on the second surface is located within the orthographic projection of the first contact hole on the second surface, and the orthographic projection area of ​​the third contact hole on the second surface is smaller than the orthographic projection area of ​​the first contact hole on the second surface. The second dielectric material layer is thinned to form a second dielectric layer and a second contact hole; the second dielectric layer is located on the sidewall of the first contact hole, and the second dielectric layer located in the same first contact hole forms the second contact hole, the second contact hole exposing at least a portion of the surface of the first region located on the first surface.

[0009] Optionally, forming the second dielectric layer includes: A first sub-dielectric layer is formed, the first sub-dielectric layer comprising an undoped oxide layer; A second sub-dielectric layer is formed to cover the first sub-dielectric layer, the second sub-dielectric layer including a doped oxide layer; and the thickness of the second sub-dielectric layer is greater than the thickness of the first sub-dielectric layer.

[0010] Optionally, the thickness of the second sub-dielectric layer is greater than or equal to five times the thickness of the first sub-dielectric layer.

[0011] Optionally, the step of patterning the first dielectric material layer, the gate material layer, and the gate insulating material layer to form the first dielectric layer, the gate layer, and the gate insulating layer, and forming a plurality of first contact holes, includes: The first dielectric material layer is patterned with a first etching gas; the etching selectivity ratio of the first etching gas for the first dielectric material layer and the gate material layer is greater than 1. The gate material layer is patterned with a second etching gas; the etching selectivity ratio of the second etching gas for the gate material layer and the gate insulating material layer is greater than 1. The gate insulating material layer is patterned with a third etching gas; the etching selectivity ratio of the third etching gas for the gate insulating material layer and the semiconductor body is greater than 1.

[0012] Optionally, the process of thinning the second dielectric material layer to form the second dielectric layer and the second contact hole further includes: The surface of the first dielectric layer that is away from the second surface.

[0013] According to another aspect of the present invention, a power module is provided, comprising a substrate and at least one semiconductor device as described in any of the preceding claims, the substrate being used to support the semiconductor device.

[0014] According to another aspect of the present invention, a power conversion circuit is provided, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described above, the semiconductor device being electrically connected to the circuit board.

[0015] According to another aspect of the present invention, a vehicle is provided, including a load and a power conversion circuit as described above, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.

[0016] The technical solution of this invention uses a semiconductor device comprising: a semiconductor body including a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a first region, a well region, and a second region; the first region being configured with a first conductivity type and located on the first surface; the well region being configured with a second conductivity type and located between the first region and the second region; and the second region being configured with a first conductivity type; a gate insulating layer located on the first surface; a gate layer located on the side of the gate insulating layer away from the first surface; and a first dielectric layer located on the side of the gate layer away from the first surface; the semiconductor device further comprising a plurality of first contact holes and a second dielectric layer; the first contact holes penetrating the gate insulating layer, the gate layer, and the first dielectric layer, and exposing the sidewalls of the gate insulating layer, the gate layer, and the first dielectric layer; the second dielectric layer located on the sidewall of the first contact hole, and the second dielectric layer located on the same first contact hole forming a second contact hole; the second contact hole exposing at least a portion of the surface of the first region located on the first surface. The sidewalls of the first dielectric layer, the gate layer, and the gate insulating layer are roughly on the same plane, meaning the first contact hole is formed by continuously etching the above three film layers. The second dielectric layer is disposed on the sidewall of the first contact hole. The second dielectric layer can be fabricated by self-alignment without photolithography, which saves one photolithography process and avoids the problem of large positional deviation of the second contact hole due to overlay misalignment.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention; Figure 3 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention; Figures 4 to 10 This is a schematic diagram of the product structure corresponding to the main steps of a semiconductor device fabrication method provided in an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention, with reference to... Figure 1 The semiconductor device includes: a semiconductor body 100, including a first surface 101 and a second surface 102 disposed opposite to each other; the semiconductor body 100 further includes a first region 107, a well region 105, and a second region 104; the first region 107 is configured with a first conductivity type and is located on the first surface 101; the well region 105 is configured with a second conductivity type and is located between the first region 107 and the second region 104; the second region 104 is configured with a second conductivity type; the semiconductor device further includes a gate insulating layer 20 located on the first surface 101; and a gate layer 30 located on the gate insulating layer 20 away from the first surface 101. The semiconductor device further includes a plurality of first contact holes 70 and a second dielectric layer 50. The first contact holes 70 penetrate the first dielectric layer 40, the gate layer 30 and the gate insulating layer 20, and expose the sidewalls of the gate insulating layer 20, the sidewalls of the gate layer 30 and the first dielectric layer 40. The second dielectric layer 50 is located on the sidewall of the first contact hole 70, and the second dielectric layer 50 located in the same first contact hole 70 forms a second contact hole 701. The second contact hole exposes at least a portion of the surface of the first surface 101 of the first region 107.

[0023] Specifically, the semiconductor device can be a MOSFET made of third-generation wide-bandgap semiconductor materials such as silicon carbide. In other words, the semiconductor body material can be third-generation wide-bandgap semiconductor materials such as silicon carbide. The semiconductor device can be an N-type MOSFET or a P-type MOSFET. When the semiconductor device is an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type; when the semiconductor device is a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type. The N-type conductivity region can be formed by N-type doping, and the dopant ions for N-type doping can be phosphorus (P) ions or nitrogen (N) ions; for the P-type conductivity region, it can be formed by P-type doping, and the dopant ions for P-type doping can be aluminum (Al) ions or boron (B) ions.

[0024] The semiconductor device may include a substrate 10 and at least one epitaxial layer; in some embodiments, the semiconductor device may not include a substrate 10. A first region 107, a second region 104, and a well region 105 are all formed in the epitaxial layer. The semiconductor device may include multiple cells, each cell corresponding to a gate, with the gates of adjacent cells separated by second contact vias. All gates of the cells are located in the gate layer 30. The first region 107 and the second region 104 have the same conductivity type, and the ion doping concentration of the first region 107 is greater than that of the second region 104. The first region 107 is in contact with the source 60 to provide a stable channel for majority carrier injection. Well region 105 has a different conductivity type than the first region 107. When the voltage applied between the gate and source 60 is less than the threshold voltage of the semiconductor device, well region 105 still exhibits the second conductivity type. At this time, a depletion region is formed between well region 105 and the first region 107, and a depletion region is also formed between well region 105 and the second region 104. The depletion region blocks the movement of electrons, and electrons cannot move freely between the source 60 and the drain 70, so the semiconductor device is in the off state. When the voltage applied between the gate and the source is greater than the threshold voltage of the semiconductor device, a large number of minority carriers in well region 105 are attracted to the surface near the gate, causing a large number of minority carriers to accumulate on the surface of well region 105 near the gate, thus causing the part of well region 105 near the gate to invert to the first conductivity type. At this time, the conductivity types of the first region 107, the part of well region 105 near the gate, and the second region 104 are the same, the conductive channel is open, and electrons can move freely in the conductive channel. When a voltage is applied between the source 60 and the drain 80, a current can be generated between the source and the drain. In this embodiment, the specific locations and formation methods of the first region 107, the well region 105, and the second region 104 are not limited.

[0025] The gate insulating layer 20 is used to isolate the gate layer 30 from the semiconductor body 100. In this embodiment, the first dielectric layer 40 is used to isolate the surface of the gate layer 30 away from the first surface 101 from the source 60, while the second dielectric layer 50 is used to isolate the sidewall of the gate layer 30 from the source 60. That is, in this embodiment, the gate layer 30 and the source 60 are isolated by two different dielectric layers. Based on the above structure, the sidewall of the first dielectric layer 40, the sidewall of the gate layer 30, and the sidewall of the gate insulating layer 20 are approximately located on the same plane, that is, the first contact hole is formed by continuously etching the above three film layers; the second dielectric layer 50 is disposed on the sidewall of the first contact hole 50, so the second dielectric layer 50 can be fabricated by self-alignment without photolithography, which can save a photolithography process and avoid the problem of large positional deviation of the second contact hole 701 due to overlay misalignment.

[0026] The technical solution of this embodiment uses a semiconductor device including: a semiconductor body, including a first surface and a second surface disposed opposite to each other, the semiconductor body further including a first region, a well region and a second region, the first region being configured with a first conductivity type and located on the first surface, the well region being configured with a second conductivity type and located between the first region and the second region, and the second region being configured with a first conductivity type; a gate insulating layer located on the first surface; a gate layer located on the side of the gate insulating layer away from the first surface; a first dielectric layer located on the side of the gate layer away from the first surface; the semiconductor device further includes a plurality of first contact holes and a second dielectric layer, the first contact holes penetrating the gate insulating layer, the gate layer and the first dielectric layer, and exposing the sidewalls of the gate insulating layer, the sidewalls of the gate layer and the sidewalls of the first dielectric layer; the second dielectric layer located on the sidewall of the first contact hole, and the second dielectric layer located on the same first contact hole forming a second contact hole, the second contact hole exposing at least a portion of the surface of the first region located on the first surface. The sidewalls of the first dielectric layer, the gate layer, and the gate insulating layer are roughly on the same plane, meaning the first contact hole is formed by continuously etching the above three film layers. The second dielectric layer is disposed on the sidewall of the first contact hole. The second dielectric layer can be fabricated by self-alignment without photolithography, which saves one photolithography process and avoids the problem of large positional deviation of the second contact hole due to overlay misalignment.

[0027] Optionally, Figure 2 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention, with reference to... Figure 2 The second dielectric layer 50 includes a first sidewall 501 and a second sidewall 502 located on the side of the first sidewall 501 away from the sidewall of the first contact hole 70; the first sidewall 501 includes an undoped oxide layer, and the second sidewall 502 includes a doped oxide layer.

[0028] Specifically, the first sidewall 501 is a pure oxide layer, such as pure silicon dioxide. The use of undoped silicon dioxide in the first sidewall 501 results in higher interface quality, fewer interface defects, and fewer interface defects in contact with the epitaxial layer and gate layer 30, leading to better performance of the semiconductor device. Furthermore, undoped silicon dioxide can serve as an etch stop layer, providing a precise etch stop position for the second contact hole. The second sidewall 502 is a doped oxide layer, such as doped silicon dioxide, with boron and phosphorus as the doping elements. The second sidewall 502 has good flowability during fabrication, allowing for better filling of uneven areas, resulting in a smoother sidewall corresponding to the second contact hole 701, thus improving the quality of the source 60 within the second contact hole 701. The second dielectric layer 50 can be formed stepwise using CVD (Chemical Vapor Deposition) and self-aligned processes.

[0029] Optionally, in some embodiments, the thickness of the second sidewall 502 is greater than the thickness of the first sidewall 501. For example, the thickness of the second sidewall 502 is greater than or equal to five times the thickness of the first sidewall 501.

[0030] Optionally, continue to refer to Figure 1 Along the thickness direction of the semiconductor device, the height of the second dielectric layer 50 is the same as the depth of the first contact hole 70. Alternatively, the second dielectric layer 50 includes a third surface away from the first surface 101, and the first dielectric layer 40 includes a fourth surface away from the first surface 101; the third and fourth surfaces are flush. That is, the third and fourth surfaces are located on the same plane. Of course, the flushness of the third and fourth surfaces is within the allowable range of process condition errors, and their surfaces may have uneven structures. The second dielectric layer is formed by first forming a second dielectric material layer on its entire surface and then thinning the second dielectric material layer. The arrangement in this embodiment ensures that the epitaxial layer can be exposed when the second dielectric material layer is thinned, thereby avoiding affecting the contact between the source 60 and the epitaxial layer.

[0031] Optionally, continue to refer to Figure 1 The semiconductor device also includes a third region 106, which is configured with a second conductivity type and located on the first surface 101. The ion doping concentration of the third region 106 is greater than that of the well region 105. The third region 106 contacts the first region 101 and the well region 105, and a second contact hole 701 exposes the surface of the third region 106 located on the first surface 101. The third region 106 contacts the source 60, thereby providing the first region 107 and the well region 105 with the same potential, avoiding latch-up problems.

[0032] Optionally, continue to refer to Figure 1The semiconductor device also includes a source 60, which fills the second contact hole 701 and covers the first dielectric layer 40 and the second dielectric layer 50.

[0033] Optionally, continue to refer to Figure 1 The semiconductor device also includes a drain 80, which is disposed on the second surface 102.

[0034] Based on the same inventive concept, this invention also provides a method for fabricating a semiconductor device, used to fabricate the semiconductor device provided in any embodiment of this invention. For example... Figure 3 As shown, Figure 3 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. The method includes: Step S110: Provide an epitaxial structure, the epitaxial structure including a semiconductor body and a gate insulating material layer, a gate material layer and a first dielectric material layer sequentially stacked on the semiconductor body; the semiconductor body includes a first surface and a second surface disposed opposite to each other, the semiconductor body also includes a first region, a well region and a second region, the gate insulating material layer is located on the first surface, the first region is configured as a first conductivity type and is located on the first surface, the well region is configured as a second conductivity type and is located between the first region and the second region, and the second region is configured as a first conductivity type; Specifically, Figures 4 to 10 This is a schematic diagram of the product structure corresponding to the main steps of a semiconductor device fabrication method provided in an embodiment of the present invention, with reference to... Figure 4 A semiconductor body 100 can be provided first, which includes a substrate 10 and at least one epitaxial layer. A first region 107, a well region 105, and a third region 106 are formed in the epitaxial layer by means of ion implantation or the like. A second region 104 can be formed by epitaxy, that is, the second region 104 is formed after the epitaxial layer is completed.

[0035] Then, as Figure 5 As shown, an epitaxial structure can be formed by methods such as CVD to form a gate insulating material layer 201, a gate material layer 301, and a first dielectric material layer 401. The gate insulating material layer 201 can be made of oxide and is used to form the gate insulating layer after patterning. The gate material layer 301 can be made of polysilicon and is used to form the gate layer after patterning. The first dielectric material layer 401 is used to form the first dielectric layer after patterning.

[0036] Step S120: Pattern the first dielectric material layer, the gate material layer, and the gate insulating material layer to form the first dielectric layer, the gate layer, and the gate insulating layer, and form a plurality of first contact holes; Specifically, such as Figure 6As shown, a mask 80 can be fabricated on the first dielectric material layer 401, and then the same mask 80 can be used to etch the first dielectric material layer 401, the gate material layer 301, and the gate insulating material layer 201. The etched structure is as follows. Figure 7 As shown, the first dielectric material layer 401 is patterned as the first dielectric layer 40, the gate material layer 301 is patterned as the gate layer 30, and the gate insulating material layer 201 is patterned as the gate insulating layer 20. The etched via is the first contact hole. The first contact hole 70 exposes at least a portion of the surface of the first surface 101 in the first region 107.

[0037] Step S130: A second dielectric material layer is formed, which fills the first contact hole and covers the first dielectric layer. The second dielectric material layer has a third contact hole corresponding to the first contact hole. Along the thickness direction of the semiconductor device, the orthographic projection of the third contact hole on the second surface is located within the orthographic projection of the first contact hole on the second surface, and the orthographic projection area of ​​the third contact hole on the second surface is smaller than the orthographic projection area of ​​the first contact hole on the second surface. Specifically, such as Figure 8 As shown, after forming the first contact hole 70, the mask 80 is removed first, and then... Figure 9 As shown, a second dielectric material layer 503 is deposited across the entire surface. Since the surface on which the second dielectric material layer 503 is deposited is non-uniform, the second dielectric material layer 503 will also form a non-uniform surface. The deposition time is controlled to ensure that the second dielectric material layer 503 completely fills the first contact hole. Furthermore, the size of the third contact hole 504 can be controlled by controlling the deposition time. In this embodiment, the size of the third contact hole 504 is set smaller than the size of the first contact hole 70, at which point the thickness of the second dielectric material layer 503 corresponding to the sidewall of the first contact hole 70 is at its maximum.

[0038] Step S140: Thin the second dielectric material layer to form a second dielectric layer and a second contact hole; the second dielectric layer is located on the sidewall of the first contact hole, and the second dielectric layer located in the same contact hole forms the second contact hole, and the second contact hole exposes at least a portion of the surface of the first region located on the first surface.

[0039] Specifically, such as Figure 10As shown, the second dielectric material layer 503 is thinned through a thinning process to expose the first surface. Since the thickness of the portion of the second dielectric material layer 503 corresponding to the sidewall of the first contact hole is greater than the thickness of other portions, i.e., greater than the depth of the first contact hole, after thinning the second dielectric material layer 503, the portion of the second dielectric material layer 503 corresponding to the sidewall of the first contact hole is not completely removed; instead, the second dielectric layer 50 is retained, while the portions of the second dielectric material layer 503 located at other positions are completely removed, forming the second contact hole 701. In summary, the sidewalls of the first dielectric layer 40, the gate layer 30, and the gate insulating layer 20 are approximately located on the same plane, meaning the first contact hole is formed by continuously etching these three layers. The second dielectric layer 50 is fabricated using a self-aligned method, eliminating the need for photolithography. This saves one photolithography step and avoids the problem of large positional deviations in the second contact hole 701 due to overlay errors.

[0040] The technical solution of this embodiment employs a semiconductor device fabrication method comprising: providing an epitaxial structure, the epitaxial structure including a semiconductor body and a gate insulating material layer, a gate material layer, and a first dielectric material layer sequentially stacked on the semiconductor body; the semiconductor body includes a first surface and a second surface disposed opposite to each other, the semiconductor body further including a first region, a well region, and a second region, the gate insulating material layer being located on the first surface, the first region being configured as a first conductivity type and located on the first surface, the well region being configured as a second conductivity type and located between the first region and the second region, and the second region being configured as a first conductivity type; patterning the first dielectric material layer, the gate material layer, and the gate insulating material layer to form the first dielectric layer, the gate layer, and the gate insulating layer, and forming a plurality of first contact holes; forming a second dielectric material layer, the second dielectric material layer filling the first contact holes and covering the first dielectric layer; the second dielectric material layer forming corresponding first contact holes. The third contact hole of the first contact hole is located along the thickness direction of the semiconductor device. The orthographic projection of the third contact hole on the second surface is located within the orthographic projection of the first contact hole on the second surface, and the orthographic projection area of ​​the third contact hole on the second surface is smaller than the orthographic projection area of ​​the first contact hole on the second surface. The second dielectric material layer is thinned to form the second dielectric layer and the second contact hole. The second dielectric layer is located on the sidewall of the first contact hole, and the second dielectric layer located on the same contact hole forms the second contact hole. The second contact hole exposes at least a portion of the surface of the first surface in the first region. The sidewalls of the first dielectric layer, the sidewalls of the gate layer, and the sidewalls of the gate insulating layer are approximately located on the same plane, that is, the first contact hole is formed by continuously etching the above three film layers. The second dielectric layer is fabricated by self-alignment, without the need for photolithography, which can save a photolithography process and avoid the problem of large positional deviation of the second contact hole due to overlay misalignment.

[0041] Optionally, when thinning the second dielectric material layer to form the second dielectric layer and the second contact hole, the method further includes: The surface that exposes the first dielectric layer away from the second surface.

[0042] Specifically, the settings in this embodiment, by controlling the thinning time, can ensure that the first surface can be exposed after the thinning process is completed, thereby avoiding the situation where the source cannot contact the epitaxial layer.

[0043] Optionally, forming the second dielectric layer includes: forming a first sub-dielectric layer, the first sub-dielectric layer including an undoped oxide layer; forming a second sub-dielectric layer covering the first sub-dielectric layer, the second sub-dielectric layer including a doped oxide layer; and the thickness of the second sub-dielectric layer is greater than the thickness of the first sub-dielectric layer.

[0044] Specifically, in this embodiment, the second dielectric layer consists of two layers of material, which can be referred to as follows: Figure 2 The second dielectric layer 50 includes a first sidewall 501 and a second sidewall 502 located on the side of the first sidewall 501 away from the sidewall of the first contact hole 70. The first sidewall 501 is formed by thinning the first sub-dielectric layer, and the second sidewall 502 is formed by thinning the second sub-dielectric layer. The first sub-dielectric layer is made of undoped silicon dioxide. Undoped silicon dioxide has higher interface quality and fewer interface defects, resulting in fewer interface defects in contact with the epitaxial layer and the gate layer 30, thus improving the performance of the semiconductor device. Furthermore, undoped silicon dioxide can also serve as an etch stop layer, providing a precise etch stop position for the second contact hole. The second sub-dielectric layer is a doped oxide layer, such as doped silicon dioxide, with boron and phosphorus as the doping elements. The second sub-dielectric layer has good fluidity during fabrication, allowing it to better fill uneven areas, making the sidewall of the second sidewall 502 corresponding to the second contact hole 701 smoother, thereby improving the quality of the source 60 within the second contact hole 701.

[0045] Further optionally, the thickness of the second sub-dielectric layer is greater than or equal to five times the thickness of the first sub-dielectric layer.

[0046] For example, the thickness of the first sub-dielectric layer can be 200 nanometers, and the thickness of the second sub-dielectric layer can be 1 micrometer. The greater thickness of the second sub-dielectric layer ensures that the second dielectric layer has a larger thickness, thereby meeting the corresponding design requirements.

[0047] Optionally, patterning a first dielectric material layer, a gate material layer, and a gate insulating material layer to form a first dielectric layer, a gate layer, and a gate insulating layer, and forming a plurality of first contact holes includes: The first dielectric material layer is patterned with a first etching gas; the etching selectivity ratio of the first etching gas for the first dielectric material layer and the gate material layer is greater than 1. The gate material layer is patterned with a second etching gas; the etching selectivity ratio of the second etching gas for the gate material layer and the gate insulating material layer is greater than 1. The gate insulating material layer is patterned with a third etching gas; the etching selectivity ratio of the third etching gas for the gate insulating material layer and the semiconductor body is greater than 1.

[0048] Specifically, this embodiment utilizes three different etching gases to sequentially etch the first dielectric material layer, the gate material layer, and the gate insulating material layer. This allows for more precise etching of different film layers, ensuring that each film layer meets the expected etching requirements. The first etching gas is, for example, a gas containing elements such as fluorine and carbon; the second etching gas is, for example, a mixture of HBr and chlorine; and the third etching gas can be, for example, a fluorine-based gas. Furthermore, in this embodiment, the size of the first contact hole is set close to the limit of the lithography machine's capabilities, resulting in superior performance for the semiconductor device.

[0049] Of course, it is understandable that after forming the second contact hole, a source electrode and a drain electrode are fabricated to form a... Figure 1 The semiconductor device shown.

[0050] Based on the same inventive concept, the present invention also provides a power module. The power module includes a substrate and at least one semiconductor device as described in any embodiment of the present invention, with the substrate serving to support the semiconductor device. Therefore, the beneficial effects of this power module including any semiconductor device as described in any embodiment of the present invention will not be elaborated further here.

[0051] Based on the same inventive concept, this invention also provides a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this invention, with the semiconductor device electrically connected to the circuit board. Therefore, the beneficial effects of this power conversion circuit including any semiconductor device as described in any embodiment of this invention will not be elaborated further here.

[0052] Based on the same inventive concept, the present invention also provides a vehicle, which includes a load and the aforementioned power conversion circuit. The power conversion circuit is used to convert alternating current to direct current, alternating current to alternating current, direct current to direct current, or direct current to alternating current, and then input the converted direct current to the load. Therefore, the beneficial effects of the vehicle including the semiconductor device described in any embodiment of the present invention will not be elaborated further here.

[0053] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0054] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: A semiconductor body includes a first surface and a second surface disposed opposite to each other. The semiconductor body also includes a first region, a well region, and a second region. The first region is configured with a first conductivity type and is located on the first surface. The well region is configured with a second conductivity type and is located between the first region and the second region. The second region is configured with the first conductivity type. A gate insulating layer is located on the first surface; A gate layer is located on the side of the gate insulating layer away from the first surface; The first dielectric layer is located on the side of the gate layer away from the first surface; The semiconductor device further includes a plurality of first contact holes and second dielectric layers. The first contact holes penetrate the gate insulating layer, the gate layer and the first dielectric layer, and expose the sidewalls of the gate insulating layer, the gate layer and the first dielectric layer. The second dielectric layer is located on the sidewall of the first contact hole, and the second dielectric layer located on the same first contact hole forms a second contact hole. The second contact hole exposes at least a portion of the surface of the first region located on the first surface.

2. The semiconductor device according to claim 1, characterized in that, The second dielectric layer includes a first sidewall and a second sidewall located on the side of the first sidewall away from the first contact hole; the first sidewall includes an undoped oxide layer and the second sidewall includes a doped oxide layer.

3. The semiconductor device according to claim 1, characterized in that, Along the thickness direction of the semiconductor device, the height of the second dielectric layer is the same as the depth of the first contact hole.

4. A method for fabricating a semiconductor device, characterized in that, include: An epitaxial structure is provided, the epitaxial structure comprising a semiconductor body and a gate insulating material layer, a gate material layer and a first dielectric material layer sequentially stacked on the semiconductor body; The semiconductor body includes a first surface and a second surface disposed opposite to each other. The semiconductor body also includes a first region, a well region, and a second region. The gate insulating material layer is located on the first surface. The first region is configured with a first conductivity type and is located on the first surface. The well region is configured with a second conductivity type and is located between the first region and the second region. The second region is configured with a first conductivity type. The first dielectric material layer, the gate material layer, and the gate insulating material layer are patterned to form a first dielectric layer, a gate layer, and a gate insulating layer, and a plurality of first contact holes are formed. A second dielectric material layer is formed, which fills the first contact hole and covers the first dielectric layer; The second dielectric material layer has a third contact hole corresponding to the first contact hole. Along the thickness direction of the semiconductor device, the orthographic projection of the third contact hole on the second surface is located within the orthographic projection of the first contact hole on the second surface, and the orthographic projection area of ​​the third contact hole on the second surface is smaller than the orthographic projection area of ​​the first contact hole on the second surface. Thin the second dielectric material layer to form a second dielectric layer and a second contact hole; The second dielectric layer is located on the sidewall of the first contact hole, and the second dielectric layer located in the same first contact hole forms the second contact hole, the second contact hole exposing at least a portion of the surface of the first region located on the first surface.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The formation of the second dielectric layer includes: A first sub-dielectric layer is formed, the first sub-dielectric layer comprising an undoped oxide layer; A second sub-dielectric layer is formed to cover the first sub-dielectric layer, the second sub-dielectric layer including a doped oxide layer; and the thickness of the second sub-dielectric layer is greater than the thickness of the first sub-dielectric layer.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The thickness of the second sub-dielectric layer is greater than or equal to five times the thickness of the first sub-dielectric layer.

7. The method for fabricating a semiconductor device according to claim 4, characterized in that, The process of patterning the first dielectric material layer, the gate material layer, and the gate insulating material layer to form the first dielectric layer, the gate layer, and the gate insulating layer, and forming a plurality of first contact holes, includes: The first dielectric material layer is patterned with a first etching gas; the etching selectivity ratio of the first etching gas for the first dielectric material layer and the gate material layer is greater than 1. The gate material layer is patterned with a second etching gas; the etching selectivity ratio of the second etching gas for the gate material layer and the gate insulating material layer is greater than 1. The gate insulating material layer is patterned with a third etching gas; the etching selectivity ratio of the third etching gas for the gate insulating material layer and the semiconductor body is greater than 1.

8. The method for fabricating a semiconductor device according to claim 4, characterized in that, The process of thinning the second dielectric material layer to form the second dielectric layer and the second contact hole further includes: The surface of the first dielectric layer that is away from the second surface.

9. A power module, characterized in that, It includes a substrate and at least one semiconductor device as described in any one of claims 1-3, wherein the substrate is used to support the semiconductor device.

10. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1-3, wherein the semiconductor device is electrically connected to the circuit board.

11. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 10, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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