Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes: a substrate having a chip region and a scribe region, the scribe region having a first edge extending in a first direction and a second edge extending in a second direction; a first insulating interlayer structure located on the scribe region and including a low-k dielectric material; a first conductive structure located on a portion of the scribe region adjacent to one of the first edges and extending vertically through the first insulating interlayer structure and in the first direction; a second insulating interlayer located on the first insulating interlayer structure and including a material having a dielectric constant greater than that of the first insulating interlayer structure; first vias each extending in the first direction through the second insulating interlayer to contact one of the first conductive structures; and a first wiring commonly contacting upper surfaces of the first vias.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2019-0113332, filed with the Korean Intellectual Property Office on September 16, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments of the present disclosure relate to semiconductor devices, and more particularly, to DRAM devices. Background Art

[0003] A wafer may include a plurality of chip regions and a dicing street region surrounding them, and test element groups (TEGs), alignment keys, etc. for testing the electrical characteristics of elements on the chip regions may be formed on the dicing street region. After a semiconductor chip is formed on the wafer, a dicing process for cutting the wafer and the structures thereon may be performed through the dicing street region, whereby the semiconductor chips may be divided. Due to structures such as TEGs on the dicing street, it may not be easy to perform the dicing process. Summary of the Invention

[0004] According to an example embodiment of the inventive concept, a semiconductor device may include a substrate, a first interlayer dielectric structure, a first conductive structure, a second interlayer dielectric, a first via, and a first wiring. The substrate may include a chip region and a dicing street region surrounding the chip region. The dicing street region may have a first edge opposite to each other and a second edge opposite to each other. Each first edge may extend in a first direction, and each second edge may extend in a second direction intersecting the first direction. The first interlayer dielectric structure may be formed on the dicing street region of the substrate and may include a low-k dielectric material. The first conductive structure may be formed on a portion of the dicing street region of the substrate adjacent to one first edge. Each first conductive structure may extend through the first interlayer dielectric structure in a vertical direction substantially perpendicular to the upper surface of the substrate and may extend in the first direction. The second interlayer dielectric may be formed on the first interlayer dielectric structure and may include a material having a dielectric constant greater than that of the first interlayer dielectric structure. Each first via may extend in the first direction and pass through the second interlayer dielectric to contact one first conductive structure. The first wiring may commonly contact the upper surfaces of the first vias.

[0005] According to an exemplary embodiment of the inventive concept, a semiconductor device may include a substrate, a contact plug, a conductive structure, and a second wiring. The substrate may include a chip region and a scribe region surrounding the chip region. The scribe region may have a first edge opposite to each other and a second edge opposite to each other. Each first edge may extend in a first direction, and each second edge may extend in a second direction intersecting the first direction. The contact plug may be formed on the scribe region of the substrate. The conductive structure may be formed on the contact plug on a portion of the scribe region of the substrate adjacent to one of the first edges. The conductive structure may include a first wiring and a first via alternately and repeatedly stacked in a vertical direction substantially perpendicular to the upper surface of the substrate. The second wiring may commonly contact the upper surface of the conductive structure. Each first wiring and each first via may extend in the first direction.

[0006] According to an exemplary embodiment of the inventive concept, a semiconductor device may include a substrate, a gate structure, a bit line structure, a first contact plug, a capacitor, a second contact plug, a third contact plug, a first interlayer dielectric, a second interlayer dielectric structure, a conductive structure, a third interlayer dielectric, a first via, and a first wiring. The substrate may include a chip region and a scribe region surrounding the chip region. The scribe region may have a first edge opposite to each other and a second edge opposite to each other. Each first edge may extend in a first direction, and each second edge may extend in a second direction intersecting the first direction. The substrate may have a first active pattern and a second active pattern on the chip region and the scribe region, and the first active pattern and the second active pattern may be defined by an isolation pattern on the substrate. The gate structure may be disposed on an upper portion of the first active pattern. The bit line structure may be formed on the chip region of the substrate. The first contact plug may be formed on the first active pattern. The capacitor may be formed on the first contact plug. The second contact plug may be formed on the capacitor. The third contact plug may be formed on the second active pattern. The second contact plug and the third contact plug may be formed in the first interlayer dielectric. The second interlayer dielectric structure may be formed on the first interlayer dielectric. The conductive structure may be formed on a portion of the scribe region of the substrate adjacent to one of the first edges. Each first conductive structure may extend through the second interlayer dielectric structure in a vertical direction substantially perpendicular to the upper surface of the substrate and may extend in the first direction. The third interlayer dielectric may be formed on the second interlayer dielectric structure. The third interlayer dielectric may include a material having a dielectric constant greater than that of the second interlayer dielectric structure. Each first via may extend in the first direction and pass through the third interlayer dielectric to contact a conductive structure on the scribe region of the substrate. The first wiring may commonly contact the upper surface of the first via.

[0007] In a method of manufacturing a semiconductor device according to an exemplary embodiment, a semiconductor chip and a TEG may be respectively formed on a chip region and a scribe region of a wafer, and when the wafer is cut through the scribe region to separate the semiconductor chip, a cutting process may be guided by a conductive structure included in the TEG, and an impact generated by the cutting process may be prevented from spreading to the semiconductor chip. Accordingly, the semiconductor chip may have improved electrical characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1 to 25 are a plan view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.

[0009] Figure 26 is a plan view of a semiconductor device according to an exemplary embodiment, Figure 27 including cross-sections taken along lines A-A', C-C', and D-D' of regions Y and Z of the corresponding plan view. DETAILED DESCRIPTION

[0010] The above and other aspects and features of a semiconductor device and a method of manufacturing the same according to an exemplary embodiment will become readily apparent from the following detailed description with reference to the accompanying drawings. It will be understood that although terms such as "first", "second", and / or "third" may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first element, first component, first region, first layer, or first portion discussed below may be referred to as a second element, second component, second region, second layer, or second portion or a third element, third component, third region, third layer, or third portion without departing from the teachings of the inventive concept.

[0011] Figures 1 to 25 are a plan view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Specifically, Figures 1 to 3 , Figure 5 , Figure 8 , Figure 12 , Figure 17 and Figures 20 to 22 are plan views, Figure 4 , Figure 6 and Figure 7 , Figures 9 to 11 , Figures 13 to 16 , Figures 18 to 19 and Figures 23 to 25 are cross-sectional views.

[0012] Figure 2 is Figure 1 an enlarged plan view of region X ofFigure 4 , Figure 6 and Figure 7 , Figures 9 to 11 , Figures 13 to 16 and Figure 18 including cross-sections taken along lines A-A', B-B' and C-C' of regions Y and Z of the corresponding plan view, Figure 19 and Figures 23 to 25 including cross-sections taken along lines A-A', C-C' and D-D' of regions Y and Z of the corresponding plan view.

[0013] Hereinafter, in the specification (not necessarily in the claims), two directions that are substantially parallel to the upper surface of the substrate 100 and substantially perpendicular to each other may be defined as the first direction and the second direction, respectively, and a direction that is substantially parallel to the upper surface of the substrate 100 and is acute with respect to each of the second direction and the first direction may be defined as the third direction.

[0014] Referring to Figure 1 and Figure 2 , the substrate 100 may include a first region I and a fourth region IV, and the first region I may include a second region II and a third region III.

[0015] The substrate 100 may be a wafer including silicon, germanium, silicon-germanium, or a III-V compound semiconductor (such as GaP, GaAs, or GaSb). In an exemplary embodiment, the substrate 100 may be a silicon-on-insulator (SOI) wafer or a germanium-on-insulator (GOI) wafer.

[0016] The first region I of the substrate 100 may be a chip region in which a pattern for a semiconductor chip may be formed. In an exemplary embodiment, a plurality of first regions I may be spaced apart from each other in each of the first direction and the second direction. Each first region I may include a second region II and a third region III surrounding the second region II. Memory cells may be formed in the second region II, and thus the second region II may be referred to as a cell region. Peripheral circuit patterns for driving the memory cells may be formed in the third region III, and thus the third region III may be referred to as a peripheral circuit region.

[0017] The fourth region IV of the substrate 100 may be formed between the first regions I and may be a scribe (or saw line) region for cutting the pattern on the substrate 100 into semiconductor chips. In an exemplary embodiment, a test element group (TEG) for testing the electrical characteristics or faults of elements included in the semiconductor chip, an alignment key for alignment in a photo process, etc. may be formed on the fourth region IV of the substrate 100.

[0018] Hereinafter, reference will be made toFigures 3 to 18 A method of forming an element on a Y region included in a first region I of a substrate 100 will then be described with reference to Figures 19 to 25 A method of forming an element on a Y region and a Z region included in a first region I and a fourth region IV of a substrate 100, respectively, will be described with reference to

[0019] In an exemplary embodiment, a TEG on the fourth region IV of the substrate 100 may be formed to have a structure substantially the same as that of some elements on the second region II or the third region III of the substrate 100. Therefore, when referring to Figures 3 to 18 the element, the structure on the fourth region IV of the substrate 100 will not be shown. When referring to Figures 19 to 25 the element, it may be assumed that the structure on the third region III of the substrate 100 is also formed on the fourth region IV of the substrate 100.

[0020] Referring to Figure 3 and Figure 4 , a first active pattern 105 and a second active pattern 108 may be formed on the second region II and the third region III of the substrate 100, respectively, and an isolation pattern 110 may be formed on the substrate 100 to cover sidewalls of the first active pattern 105 and the second active pattern 108.

[0021] The first active pattern 105 and the second active pattern 108 may be formed by removing an upper portion of the substrate 100 to form a first recess. A plurality of the first active patterns 105 may be spaced apart from each other in a first direction and a second direction. Each of the first active patterns 105 may extend longitudinally in a third direction.

[0022] The isolation pattern 110 may be formed by forming an isolation layer on the substrate 100 to fill the first recess and planarizing the isolation layer until upper surfaces of the first active pattern 105 and the second active pattern 108 are exposed. In an exemplary embodiment, the planarization process may include a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0023] After forming an impurity region in the substrate 100 by performing, for example, an ion implantation process, the first active pattern 105 and the isolation pattern 110 on the second region II of the substrate 100 may be partially etched to form a second recess extending longitudinally in a first direction.

[0024] The first gate structure 160 may be formed in the second recess. The first gate structure 160 may include: a first gate insulating layer 130 located on the surface of the first active pattern 105 exposed by the second recess; a first gate electrode 140 located on the first gate insulating layer 130 to fill the lower portion of the second recess; and a first gate mask 150 located on the first gate electrode 140 to fill the upper portion of the second recess. The first gate structure 160 may extend longitudinally in a first direction, and a plurality of first gate structures 160 may be spaced apart from each other in a second direction.

[0025] The first gate insulating layer 130 may be formed by performing a thermal oxidation process on the surface of the first active pattern 105 exposed by the second recess. Thus, the first gate insulating layer 130 may include, for example, silicon oxide.

[0026] Referring Figure 5 and Figure 6 and, a thermal oxidation process may be performed on the upper surface of the second active pattern 108 on the third region III of the substrate 100 to form a second gate insulating layer 600, and an insulating layer structure 200 may be formed on the first active pattern 105 and the isolation pattern 110 on the second region II of the substrate 100.

[0027] In an exemplary embodiment, the insulating layer structure 200 may include a first insulating layer 170, a second insulating layer 180, and a third insulating layer 190 stacked in sequence. The first insulating layer 170 and the third insulating layer 190 may include an oxide such as silicon oxide, and the second insulating layer 180 may include a nitride such as silicon nitride.

[0028] A first conductive layer 210 and a first mask 220 may be sequentially formed on the insulating layer structure 200, the second gate insulating layer 600, and the isolation pattern 110, and the first conductive layer 210 and the insulating layer structure 200 may be etched using the first mask 220 as an etch mask to form a first opening 230 exposing the first active pattern 105.

[0029] The first conductive layer 210 may include, for example, polysilicon doped with impurities, and the first mask 220 may include a nitride such as silicon nitride.

[0030] During the etching process, the upper portions of the first active pattern 105, the isolation pattern 110, and the first gate mask 150 exposed by the first opening 230 may also be etched to form a third recess. For example, the bottom of the first opening 230 may be referred to as the third recess. The bottom of the first opening 230 may be located at a vertical level lower than the top surfaces of the first active pattern 105, the isolation pattern 110, and the first gate mask 150.

[0031] In an exemplary embodiment, the first openings 230 may expose the upper surfaces of the central portions of each of the first active patterns 105 extending in the third direction, and thus a plurality of first openings 230 may be formed in the first direction and the second direction.

[0032] A second conductive layer 240 may be formed to fill the first openings 230.

[0033] In an exemplary embodiment, the second conductive layer 240 may be formed by: forming a preliminary second conductive layer on the first active patterns 105, the isolation patterns 110, the first gate mask 150, and the first mask 220 to fill the first openings 230, and removing an upper portion of the preliminary second conductive layer by a CMP process and / or an etch-back process. The second conductive layer 240 may have an upper surface that is substantially coplanar with the upper surface of the first conductive layer 210. When referring to orientation, layout, position, shape, size, quantity, or other metrics, terms such as "same", "equal", "planar", or "coplanar" as used herein do not necessarily mean exactly the same orientation, layout, position, shape, size, quantity, or other metrics, but are intended to include nearly the same orientation, layout, position, shape, size, quantity, or other metrics within acceptable variations that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning.

[0034] In an exemplary embodiment, a plurality of second conductive layers 240 may be spaced apart from each other in the first direction and the second direction on a second region II of the substrate 100. The second conductive layer 240 may include, for example, doped polysilicon and may be incorporated into the first conductive layer 210. For example, side surfaces of the second conductive layer 240 may contact side surfaces of the first conductive layer 210.

[0035] Referring to Figure 7 , after removing the first mask 220, a third conductive layer 250, a barrier layer 270, and a first metal layer 280 may be sequentially formed on the first conductive layer 210 and the second conductive layer 240.

[0036] In an exemplary embodiment, the third conductive layer 250 may include a material that is substantially the same as the materials of the first conductive layer 210 and the second conductive layer 240. For example, the third conductive layer 250 may include doped polysilicon, and thus in some embodiments, the third conductive layer 250 may be merged with the first conductive layer 210 and the second conductive layer 240.

[0037] A second mask (not shown) may be formed to cover a portion of the first metal layer 280 located on the second region II of the substrate 100, a second gate mask 618 may be formed to partially cover a portion of the first metal layer 280 located on the third region III of the substrate 100, and the first metal layer 280, the barrier layer 270, the third conductive layer 250, the first conductive layer 210, and the second gate insulating layer 600 may be etched sequentially using the second mask and the second gate mask 618 as etching masks.

[0038] Accordingly, a second gate structure 628 may be formed on the third region III of the substrate 100. The second gate structure 628 may include a second gate insulating pattern 608, a second conductive pattern 218, a fifth conductive pattern 258, a second barrier pattern 278, a second metal pattern 288, and a second gate mask 618 sequentially stacked on the second active pattern 108. The second conductive pattern 218 and the fifth conductive pattern 258 may include the same material and thus may be merged with each other to form a second gate electrode 268.

[0039] A gate spacer 630 may be formed to cover sidewalls of the second gate structure 628, and impurities may be implanted into an upper portion of the second active pattern 108 adjacent to the second gate structure 628 to form source / drain layers 109.

[0040] After removing the second mask, a first insulating interlayer may be formed on the second region II and the third region III of the substrate 100, and the first insulating interlayer may be planarized until the first metal layer 280 and the second gate mask 618 are exposed, to form a first insulating interlayer pattern 640 around the second gate structure 628 and the gate spacer 630 on the third region III of the substrate 100. The first insulating interlayer pattern 640 may include an oxide such as silicon oxide.

[0041] A capping layer 290 may be formed on the first metal layer 280, the first insulating interlayer pattern 640, and the second gate mask 618. The capping layer 290 may include a nitride such as silicon nitride.

[0042] Referring to Figure 8 and Figure 9 , a portion of the capping layer 290 located on the second region II of the substrate 100 may be etched to form a first capping pattern 295, and the first capping pattern 295 may be used as an etching mask to sequentially etch the first metal layer 280, the barrier layer 270, the third conductive layer 250, the first conductive layer 210, and the second conductive layer 240, and the third insulating layer 190.

[0043] In an exemplary embodiment, the first cover pattern 295 may extend longitudinally in a second direction, and a plurality of the first cover patterns 295 may be spaced apart from each other in a first direction on a second region II of the substrate 100. A portion of the cover layer 290 located on a third region III of the substrate 100 may remain as a second cover pattern 298.

[0044] Through an etching process, on the second region II of the substrate 100, the third conductive pattern 245, the fourth conductive pattern 255, the first barrier pattern 275, the first metal pattern 285, and the first cover pattern 295 may be sequentially stacked on the first active pattern 105, the isolation pattern 110, and the first gate mask 150 in the first opening 230, and the third insulating pattern 195, the first conductive pattern 215, the fourth conductive pattern 255, the first barrier pattern 275, the first metal pattern 285, and the first cover pattern 295 may be sequentially stacked on the second insulating layer 180 of the insulating layer structure 200 outside the first opening 230.

[0045] As shown above, the first conductive layer 210, the second conductive layer 240, and the third conductive layer 250 may be merged with each other, so that both the sequentially stacked third conductive pattern 245 and fourth conductive pattern 255 and the sequentially stacked first conductive pattern 215 and fourth conductive pattern 255 may form a first conductive structure 265. Hereinafter, the sequentially stacked first conductive structure 265, the first barrier pattern 275, the first metal pattern 285, and the first cover pattern 295 may be referred to as a bit line structure 305.

[0046] In an exemplary embodiment, the bit line structure 305 may extend longitudinally in a second direction on the second region II of the substrate 100, and a plurality of the bit line structures 305 may be spaced apart from each other in the first direction.

[0047] Referring to Figure 10 , a first spacer layer may be formed to cover the bit line structure 305 on the upper surfaces of the first active pattern 105, the isolation pattern 110, and the first gate mask 150 exposed by the first opening 230, the sidewalls of the first opening 230, the second insulating layer 180, the first cover pattern 295, and the second cover pattern 298, and a fourth insulating layer and a fifth insulating layer may be sequentially formed on the first spacer layer.

[0048] The first spacer layer may also cover the sidewalls of the third insulating pattern 195 located between the second insulating layer 180 and the bit line structure 305, and the fifth insulating layer may fill the first opening 230.

[0049] The fourth insulating layer and the fifth insulating layer can be etched through an etching process. In an exemplary embodiment, the etching process can be performed through a wet etching process, and other parts of the fourth insulating layer and the fifth insulating layer except for the parts in the first opening 230 can be removed. Therefore, most of the entire surface of the first spacer layer (e.g., the entire surface except for the part thereof in the first opening 230) can be exposed, and the parts of the fourth insulating layer and the fifth insulating layer remaining in the first opening 230 can respectively form a fourth insulating pattern 320 and a fifth insulating pattern 330.

[0050] A second spacer layer can be formed on the exposed surface of the first spacer layer and the fourth insulating pattern 320 and the fifth insulating pattern 330 in the first opening 230, and the second spacer layer can be anisotropically etched to form a second spacer 340 on the surface of the first spacer layer and the fourth insulating pattern 320 and the fifth insulating pattern 330 to cover the sidewalls of the bit line structure 305.

[0051] A dry etching process can be performed using the first cover pattern 295, the second cover pattern 298, and the second spacer 340 as an etching mask to form a second opening 350 that exposes the upper surface of the first active pattern 105. The upper surfaces of the isolation pattern 110 and the first gate mask 150 can be exposed by the second opening 350.

[0052] Through the dry etching process, the parts of the first spacer layer located on the upper surfaces of the first cover pattern 295 and the second cover pattern 298 and the upper surface of the second insulating layer 180 can be removed, so that a first spacer 315 covering the sidewalls of the bit line structure 305 can be formed. During the dry etching process, the first insulating layer 170 and the second insulating layer 180 can be partially removed, so that the first insulating pattern 175 and the second insulating pattern 185 can be retained under the bit line structure 305. The first insulating pattern 175, the second insulating pattern 185, and the third insulating pattern 195 sequentially stacked under the bit line structure 305 can form an insulating pattern structure.

[0053] Refer to Figure 11 As shown in, a third spacer layer can be formed on the upper surfaces of the first cover pattern 295 and the second cover pattern 298, the outer sidewalls of the second spacer 340, the parts of the upper surfaces of the fourth insulating pattern 320 and the fifth insulating pattern 330, and the upper surfaces of the first active pattern 105, the isolation pattern 110, and the first gate mask 150 exposed by the second opening 350. A third mask (not shown) covering the third region III of the substrate 100 can be formed on the third spacer layer, and the third spacer layer can be anisotropically etched to form a third spacer 375 covering the sidewalls of the bit line structure 305.

[0054] The third spacer layer may include a nitride such as silicon nitride and may be merged with the second cap pattern 298. In addition, the third mask may include a material having an etching selectivity with respect to the third spacer layer, e.g., a photoresist pattern.

[0055] The first spacer 315, the second spacer 340, and the third spacer 375 sequentially stacked on the sidewalls of the bit line structure 305 in a horizontal direction substantially parallel to the upper surface of the substrate 100 on the second region II of the substrate 100 may be referred to as a preliminary spacer structure.

[0056] The third mask may be removed by, for example, an ashing process and / or a lift-off process, and the upper portion of the first active pattern 105 may be removed by an etching process to form a fourth recess 390 connected to the second opening 350.

[0057] A lower contact plug layer 400 may be formed to fill the second opening 350 and the fourth recess 390 on the second region II of the substrate 100, and the lower contact plug layer 400 may be planarized until the upper surfaces of the first cap pattern 295 and the second cap pattern 298 can be exposed.

[0058] In an exemplary embodiment, the lower contact plug layer 400 may extend longitudinally in the second direction, and a plurality of lower contact plug layers 400 may be formed to be spaced apart from each other by the bit line structure 305 in the first direction.

[0059] Refer to Figure 12 and Figure 13 , a fourth mask (not shown) including a third opening may be formed on the first cap pattern 295 and the lower contact plug layer 400. Each third opening may extend in the first direction and be spaced apart from each other in the second direction on the second region II of the substrate 100, and the lower contact plug layer 400 may be etched using the fourth mask as an etching mask.

[0060] In an exemplary embodiment, each third opening may be stacked with the first gate structure 160 in a vertical direction substantially perpendicular to the upper surface of the substrate 100. Through an etching process, a fourth opening may be formed to expose the upper surface of the first gate mask 150 of the first gate structure 160 located between the bit line structures 305 on the second region II of the substrate 100.

[0061] After removing the fourth mask, a third cap pattern 410 may be formed on the second region II of the substrate 100 to fill the fourth opening. The third cap pattern 410 may include a nitride such as silicon nitride. In an exemplary embodiment, the third cap pattern 410 may extend in the first direction between the bit line structures 305, and a plurality of third cap patterns 410 may be formed in the second direction.

[0062] Accordingly, the lower contact plug layer 400 extending in the second direction between the bit line structures 305 can be divided by the third capping pattern 410 into a plurality of lower contact plugs 405 spaced apart from each other in the second direction on the second region II of the substrate 100.

[0063] Referring Figure 14 thereto, the upper portions of the lower contact plugs 405 can be removed to expose the upper portions of the preliminary spacer structures on the sidewalls of the bit line structures 305, and the upper portions of the second spacer 340 and the third spacer 375 of the exposed preliminary spacer structures can be removed.

[0064] The upper portions of the lower contact plugs 405 can be further removed. Accordingly, the upper surfaces of the lower contact plugs 405 can be located at a vertical level lower than the uppermost surfaces of the second spacer 340 and the third spacer 375.

[0065] A fourth spacer layer can be formed on the bit line structures 305, the preliminary spacer structures, the second capping pattern 298 and the third capping pattern 410, and the lower contact plugs 405, and the fourth spacer layer can be anisotropically etched, whereby fourth spacers 425 can be formed to cover the first spacer 315, the second spacer 340, and the third spacer 375 on each of the opposite sidewalls of the bit line structures 305 in the first direction, and the upper surfaces of the lower contact plugs 405 can be exposed.

[0066] A metal silicide pattern 435 can be formed on the exposed upper surfaces of the lower contact plugs 405. The upper surface of the metal silicide pattern 435 can be located at a vertical level lower than the uppermost surfaces of the second spacer 340 and the third spacer 375. In an exemplary embodiment, the metal silicide pattern 435 can be formed by forming a second metal layer on the first capping pattern 295, the second capping pattern 298 and the third capping pattern 410, the fourth spacers 425, and the lower contact plugs 405, performing a heat treatment on the second metal layer, and removing the unreacted portions of the second metal layer. The metal silicide pattern 435 can include, for example, cobalt silicide, nickel silicide, titanium silicide, etc.

[0067] Referring Figure 15 thereto, a first sacrificial layer can be formed on the first capping pattern 295, the second capping pattern 298 and the third capping pattern 410, the metal silicide pattern 435, and the lower contact plugs 405, the first sacrificial layer can be planarized until the upper surfaces of the first capping pattern 295, the second capping pattern 298, and the third capping pattern 410 are exposed, and a first hole can be formed in the third region III of the substrate 100.

[0068] The first sacrificial layer can include, for example, silicon-on-hard-mask (SOH), amorphous carbon layer (ACL), etc.

[0069] The first hole may extend vertically through the second cap pattern 298 and the first insulating interlayer pattern 640 to expose the upper surface of the source / drain layer 109 located on the third region III of the substrate 100.

[0070] After removing the first sacrificial layer, an upper contact plug layer 450 may be formed on the first cap pattern 295, the second cap pattern 298, and the third cap pattern 410, the first spacer 315, the second spacer 340, the third spacer 375, and the fourth spacer 425, the metal silicide pattern 435, the lower contact plug 405, and the source / drain layer 109, and the upper contact plug layer 450 may be planarized.

[0071] In an exemplary embodiment, the upper surface of the upper contact plug layer 450 may be at a vertical level higher than the upper surfaces of the first cap pattern 295, the second cap pattern 298, and the third cap pattern 410.

[0072] Referring Figure 16 , a second hole 470 may be formed in the second region II of the substrate 100, and the upper contact plug layer 450 may be patterned in the third region III of the substrate 100.

[0073] The second hole 470 may be formed by removing the upper portion of the upper contact plug layer 450, the upper portion of the first cap pattern 295, and the upper portions of the first spacer 315, the third spacer 375, and the fourth spacer 425. The second hole 470 may expose the upper surface of the second spacer 340.

[0074] When forming the second hole 470, on the second region II of the substrate 100, the upper contact plug layer 450 may be divided into a plurality of upper contact plugs 455. In an exemplary embodiment, the plurality of upper contact plugs 455 may be formed along a first direction and a second direction and may be arranged in a honeycomb pattern in a plan view. Each upper contact plug 455 may have a circular, oval, or polygonal shape in a plan view.

[0075] The lower contact plug 405, the metal silicide pattern 435, and the upper contact plug 455 sequentially stacked on the second region II of the substrate 100 may form a contact plug structure.

[0076] The upper contact plug layer 450 may be patterned in the third region III of the substrate 100 to form a first contact plug 458, and the first contact plug 458 may be electrically connected to the source / drain layer 109.

[0077] The exposed second spacer 340 may be removed to form an air gap 345 connected to the second hole 470. The second spacer 340 may be removed by, for example, a wet etching process.

[0078] In an exemplary embodiment, not only the portion of the second spacer 340 directly exposed by the second hole 470 can be removed, but also other portions of the second spacer 340 parallel to its directly exposed portion in the horizontal direction can be removed. For example, in addition to the portion of the second spacer 340 exposed by the second hole 470 and not covered by the upper contact plug 455, the portion of the second spacer 340 adjacent to the exposed portion in the second direction and covered by the third capping pattern 410 and the portion of the second spacer 340 adjacent to the exposed portion in the second direction and covered by the upper contact plug 455 can also be removed.

[0079] The second insulating interlayer 480 and the third insulating interlayer 490 can be sequentially stacked to fill the space between the second hole 470 in the second region II of the substrate 100 and the first contact plug 458 in the third region III of the substrate 100. The second insulating interlayer 480 and the third insulating interlayer 490 can also be sequentially stacked on the third capping pattern 410.

[0080] The second insulating interlayer 480 can include a material having low gap filling characteristics, so the air gap 345 below the second hole 470 can be not filled. The air gap 345 can also be referred to as an air spacer 345, and can form a spacer structure together with the first spacer 315, the third spacer 375, and the fourth spacer 425. For example, the air gap 345 can be a spacer including air. The term "air" as discussed herein can refer to atmospheric air or other gases that may be present during the manufacturing process.

[0081] Referring to Figure 17 and Figure 18 , a capacitor 540 can be formed such that the capacitor 540 contacts the upper surface of the upper contact plug 455.

[0082] Specifically, a first etch stop layer 500 and a molding layer (not shown) can be sequentially formed on the upper contact plug 455, the second insulating interlayer 480, the third insulating interlayer 490, and the first contact plug 458, and the first etch stop layer 500 and the molding layer can be partially etched to form a fifth opening that partially exposes the upper surface of the upper contact plug 455.

[0083] A lower electrode layer (not shown) can be formed on the sidewall of the fifth opening, the exposed upper surface of the upper contact plug 455, and the molding layer, and a second sacrificial layer (not shown) can be formed on the lower electrode layer to fill the fifth opening. The lower electrode layer and the second sacrificial layer can be planarized until the upper surface of the molding layer is exposed to divide the lower electrode layer. The second sacrificial layer and the molding layer can be removed by, for example, a wet etching process, so that a lower electrode 510 having a cylindrical shape (in a plan view) can be formed on the exposed upper surface of the upper contact plug 455. Optionally, the lower electrode 510 can have a column shape that fills the fifth opening.

[0084] A dielectric layer 520 can be formed on the surfaces of the lower electrode 510 and the first etch stop layer 500, and an upper electrode 530 can be formed on the dielectric layer 520, so that a capacitor 540 including the lower electrode 510, the dielectric layer 520, and the upper electrode 530 can be formed.

[0085] A fourth insulating interlayer 550 can be formed to cover the capacitor 540. The fourth insulating interlayer 550 can be formed on the second region II and the third region III of the substrate 100. The fourth insulating interlayer 550 can include an oxide such as silicon oxide.

[0086] As mentioned above, hereinafter, it is assumed that the elements on the third region III of the substrate 100 have also been formed on the fourth region IV of the substrate 100, and the structures that can be formed on the second region II, the third region III, and the fourth region IV of the substrate 100 will be shown.

[0087] Referring to Figure 19 , a fifth insulating interlayer 700 can be formed on the fourth insulating interlayer 550. A second contact plug 712 can be formed to vertically extend through the fourth insulating interlayer 550 and the fifth insulating interlayer 700 to contact the capacitor 540 on the second region II of the substrate 100, a third contact plug 714 can be formed to vertically extend through the fourth insulating interlayer 550 and the fifth insulating interlayer 700 to contact the first contact plug 458 on the third region III of the substrate 100, and a fourth contact plug 716 can be formed to vertically extend through the fourth insulating interlayer 550 and the fifth insulating interlayer 700 to contact the first contact plug 458 on the fourth region IV of the substrate 100. The fifth insulating interlayer 700 can include silicon oxide such as tetraethyl orthosilicate (TEOS).

[0088] A sixth insulating interlayer 720 may be formed over the fifth insulating interlayer 700 and the second contact plug 712, the third contact plug 714, and the fourth contact plug 716, and first wiring 722, second wiring 724, and third wiring 726 may be formed to vertically extend through the sixth insulating interlayer 720 to contact the second contact plug 712, the third contact plug 714, and the fourth contact plug 716, respectively.

[0089] A second etch stop layer 730 and a seventh insulating interlayer 740 may be sequentially formed over the sixth insulating interlayer 720 and the first wiring 722, the second wiring 724, and the third wiring 726. First vias 751, second vias 753, and third vias 755 may be formed to vertically extend through a lower portion of the seventh insulating interlayer 740 and the second etch stop layer 730 to contact the first wiring 722, the second wiring 724, and the third wiring 726, respectively, and fourth wiring 752, fifth wiring 754, and sixth wiring 756 may be formed to extend through an upper portion of the seventh insulating interlayer 740 to contact the first vias 751, the second vias 753, and the third vias 755, respectively. In an exemplary embodiment, the first vias 751, the second vias 753, and the third vias 755 and the fourth wiring 752, the fifth wiring 754, and the sixth wiring 756 may be formed simultaneously by a dual damascene process. However, the inventive concept is not limited thereto, and they may all be independently formed by a single damascene process.

[0090] A third etch stop layer 760 and an eighth insulating interlayer 770 may be sequentially formed over the seventh insulating interlayer 740 and the fourth wiring 752, the fifth wiring 754, and the sixth wiring 756. Fourth vias 781, fifth vias 783, and sixth vias 785 may be formed to vertically extend through a lower portion of the eighth insulating interlayer 770 and the third etch stop layer 760 to contact the fourth wiring 752, the fifth wiring 754, and the sixth wiring 756, respectively, and seventh wiring 782, eighth wiring 784, and ninth wiring 786 may be formed to extend through an upper portion of the eighth insulating interlayer 770 to contact the fourth vias 781, the fifth vias 783, and the sixth vias 785, respectively.

[0091] A fourth etch stop layer 790 and a ninth insulating interlayer 800 may be sequentially formed over the eighth insulating interlayer 770 and the seventh wiring 782, the eighth wiring 784, and the ninth wiring 786. Seventh vias 811, eighth vias 813, and ninth vias 815 may be formed to vertically extend through the fourth etch stop layer 790 and the ninth insulating interlayer 800 to contact the seventh wiring 782, the eighth wiring 784, and the ninth wiring 786, respectively, and tenth wiring 822, eleventh wiring 824, and twelfth wiring 826 may be formed over the ninth insulating interlayer 800 to contact the seventh vias 811, the eighth vias 813, and the ninth vias 815, respectively.

[0092] In an exemplary embodiment, each of the sixth insulating interlayer 720, the seventh insulating interlayer 740, and the eighth insulating interlayer 770 may include a low-k dielectric material, such as silicon oxide doped with fluorine or carbon, porous silicon oxide (SiOCH), spin-on organic polymers, inorganic polymers such as HSSQ, MSSQ, etc. Each of the second etch stop layer 730, the third etch stop layer 760, and the fourth etch stop layer 790 may include, for example, silicon carbonitride (SiCN), and the ninth insulating interlayer 800 may include an oxide such as TEOS. In some embodiments, the second etch stop layer 730, the third etch stop layer 760, the fourth etch stop layer 790, and the sixth insulating interlayer 720, the seventh insulating interlayer 740, and the eighth insulating interlayer 770 may be referred to as an insulating interlayer structure, and the ninth insulating interlayer 800 may include a material having a dielectric constant greater than that of the insulating interlayer structure.

[0093] Figure 20 is a plan view showing the layout of wirings and vias in region Z according to an exemplary embodiment.

[0094] Further referring to Figure 19 and Figure 20 When viewed in the plan view, each of the third wiring 726, the sixth wiring 756, and the ninth wiring 786, and each of the third via 755, the sixth via 785, and the ninth via 815 may have a bar shape extending longitudinally in the second direction, and the twelfth wiring 826 thereon may have a shape such as a polygon, a circle, or an ellipse like a rectangle. Figure 20 The twelfth wiring 826 having a rectangular shape is shown.

[0095] As shown above, a TEG, alignment keys, etc. may be formed on the fourth region IV of the substrate 100, and pads of the TEG may be formed on region Z of the fourth region IV of the substrate 100. The twelfth wiring 826 that can be formed at the highest level on region Z may have a polygonal shape or a circular shape so that a probe for applying a voltage to the TEG can easily contact the TEG. The third wiring 726, the sixth wiring 756, and the ninth wiring 786 below the twelfth wiring 826 may not directly contact the probe, so the third wiring 726, the sixth wiring 756, and the ninth wiring 786 may not have a polygonal shape or a circular shape, but may have a bar shape extending in the second direction.

[0096] Each of the third via 755, the sixth via 785, and the ninth via 815 that can be formed between the third wiring 726, the sixth wiring 756, the ninth wiring 786, and the twelfth wiring 826 may also have a bar shape extending in the second direction.

[0097] In an exemplary embodiment, the third wiring 726, the sixth wiring 756, and the ninth wiring 786, and the third via 755, the sixth via 785, and the ninth via 815 may be stacked in the vertical direction, so that the third wiring 726, the sixth wiring 756, and the ninth wiring 786, and the third via 755, the sixth via 785, and the ninth via 815 may form a second conductive structure extending in the second direction and in the vertical direction. Each second conductive structure may be substantially perpendicular to the upper surface of the substrate 100. For example, when viewed in cross-section, the vertical central axis of each of the third wiring 726, the sixth wiring 756, and the ninth wiring 786, and the third via 755 and the sixth via 785 may extend in a direction substantially perpendicular to the top surface of the substrate 100. In some embodiments, when viewed in cross-section, the vertical central axes of each of the third wiring 726, the sixth wiring 756, and the ninth wiring 786, and the third via 755 and the sixth via 785 may be substantially aligned with each other.

[0098] In some embodiments, the third wiring 726, the sixth wiring 756, and the ninth wiring 786, and the third via 755 and the sixth via 785 may be referred to as conductive structures. For example, each conductive structure formed on a portion of the scribing area adjacent to the first edge E1 of the substrate 100 (see Figure 26 ) may include the third wiring 726, the sixth wiring 756, and the ninth wiring 786, and the third via 755 and the sixth via 785. Each ninth via 815 may be formed to extend through the ninth insulating interlayer 800 to contact a corresponding conductive structure in the conductive structure including the third wiring 726, the sixth wiring 756, and the ninth wiring 786, and the third via 755 and the sixth via 785, and the twelfth wiring 826 may be formed on the upper surface of the ninth insulating interlayer 800 and the upper surface of the ninth via 815 by commonly contacting the upper surface of the ninth via 815.

[0099] When viewed in a plan view, each of the third wiring 726, the sixth wiring 756, the ninth wiring 786, and the twelfth wiring 826 may have an area larger than the area of each of the third via 755, the sixth via 785, and the ninth via 815; however, the inventive concept is not limited thereto.

[0100] Figure 21 and Figure 22 is a plan view showing the layout of wirings and vias according to an exemplary embodiment.

[0101] Referring to Figure 21 , each of the third wiring 726, the sixth wiring 756, and the ninth wiring 786, and the third via 755, the sixth via 785, and the ninth via 815 may have a mesh structure extending in the second direction.

[0102] The mesh structure may include first extension portions connected to each other through second extension portions. Each first extension portion may longitudinally extend in a second direction, and each second extension portion may longitudinally extend in a first direction. In the first direction, the material does not move through the mesh structure from one side of the mesh structure to the other side thereof.

[0103] Refer to Figure 22 , some of the third wiring 726, the sixth wiring 756, and the ninth wiring 786, and the third via 755, the sixth via 785, and the ninth via 815 may have a strip shape extending in the second direction, while the others of the third wiring 726, the sixth wiring 756, and the ninth wiring 786, and the third via 755, the sixth via 785, and the ninth via 815 may have a mesh structure extending in the second direction. Figure 22 It is shown that each of the wirings and vias located at both ends in the first direction has a strip shape, while each of the wirings and vias located in the middle has a mesh structure.

[0104] Refer to Figure 23 , a first protective layer structure may be formed on the tenth wiring 822, the eleventh wiring 824, and the twelfth wiring 826, and the ninth insulating interlayer 800, and a tenth via 860 may be formed to vertically extend through the first protective layer structure to contact the tenth wiring 822, the eleventh wiring 824, and the twelfth wiring 826. A redistribution layer 870 may be formed on the first protective layer, and the redistribution layer 870 may contact the upper surface of the tenth via 860.

[0105] In an exemplary embodiment, the first protective layer structure may include a first oxide layer 830, a nitride layer 840, and a second oxide layer 850 stacked in sequence. The redistribution layer 870 may contact the top surface of the second oxide layer 850.

[0106] The redistribution layer 870 may be formed on the second region II and the third region III of the substrate 100, and the redistribution layer 870 may be formed only on the edge portion of the fourth region IV of the substrate 100. The redistribution layer 870 may include, for example, a seed layer and a third metal layer stacked in sequence. The seed layer may include metals such as copper, ruthenium, nickel, gold, tungsten, etc., and the seed layer may be formed by, for example, physical vapor deposition (PVD). The third metal layer may be formed by a plating process using a plating solution including an electrolyte solution containing metal ions (for example, copper ions, ruthenium ions, nickel ions, gold ions, tungsten ions, etc.).

[0107] Refer to Figure 24, a second protective layer 880 may be formed on the redistribution layer 870 and the second oxide layer 850, and a portion of the second protective layer 880 located on the fourth region IV of the substrate 100 and a portion of the first protective layer structure located below the second protective layer 880 may be removed to form a sixth opening 890 exposing the upper surface of the twelfth wiring 826.

[0108] The second protective layer 880 may include a photosensitive organic material such as polyimide, and thus may include a thermosetting organic polymer and a photosensitive material. In an exemplary embodiment, the second protective layer 880 may be formed by a spin coating process, and the second protective layer 880 may be cured by heat treatment.

[0109] Semiconductor chips may be respectively formed on the first region I of the substrate 100 through the above process.

[0110] Referring to Figure 25 , a dicing process or a sawing process may be performed such that the semiconductor chips respectively on the first region I of the substrate 100 may be spaced apart from each other, and thus a seventh opening 900 may be formed on the fourth region IV of the substrate 100.

[0111] The dicing process may include, for example, a laser dicing process, a blade dicing process, etc., and a grinding process for removing the backside portion of the substrate 100 may also be performed before or after the dicing process.

[0112] In an exemplary embodiment, on the fourth region IV of the substrate 100, the seventh opening 900 formed by the dicing process may be formed between second conductive structures adjacent in a first direction, and each second conductive structure may extend in a second direction. Therefore, the impact generated by the dicing process may be absorbed by the second conductive structures without spreading outward.

[0113] Specifically, when the dicing process is performed, the dicing force does not spread in the vertical direction but spreads in the horizontal direction in the sixth insulating interlayer 720, the seventh insulating interlayer 740, and the eighth insulating interlayer 770. The sixth insulating interlayer 720, the seventh insulating interlayer 740, and the eighth insulating interlayer 770 include a low-k dielectric material that may be relatively soft between the fifth insulating interlayer 700 and the ninth insulating interlayer 800 including a relatively hard material. However, in an exemplary embodiment, the second conductive structures in the sixth insulating interlayer 720, the seventh insulating interlayer 740, and the eighth insulating interlayer 770 may extend in the vertical direction and the second direction, and thus the seventh opening 900 may be guided by the second conductive structures to be formed between the second conductive structures in the vertical direction.

[0114] In addition, unlike on the first region I of the substrate 100, the first protective layer structure may not be retained on the portion of the twelfth wiring 826 where the seventh opening 900 is formed, so that the impact of the cutting force may not spread toward the first region I of the substrate 100 through the first protective layer structure.

[0115] Therefore, during the cutting process on the fourth region IV of the substrate 100, the spread of the impact toward the first region I of the substrate 100 can be minimized, so that the semiconductor chip on the first region I of the substrate 100 can have improved characteristics, as shown in Figure 26 and Figure 27 shown.

[0116] Figure 26 is a plan view showing a semiconductor device according to an exemplary embodiment, Figure 27 including cross-sections taken along lines A-A', C-C', and D-D' of regions Y and Z of the corresponding plan view.

[0117] Referring to Figure 26 、 Figure 27 and Figure 20 , the fourth region IV surrounding the first region I of the substrate 100 may include a first edge E1 opposite to each other in a first direction and a second edge E2 opposite to each other in a second direction. Each first edge E1 may extend in the second direction, and each second edge E2 may extend in the first direction. If the first direction and the second direction are substantially perpendicular to each other, the outer contour of the fourth region IV of the substrate 100 may have a rectangular shape. Optionally, if the first direction and the second direction are not perpendicular to each other, the outer contour of the fourth region IV of the substrate 100 may have a parallelogram shape.

[0118] A part of the TEG may be retained on the fourth region IV of the substrate 100. Specifically, at least a part of the pads of the TEG may be retained on a part of region Z adjacent to the first edge E1.

[0119] The pads of the TEG may include a second conductive structure having a third wiring 726, a third via 755, a sixth wiring 756, a sixth via 785, a ninth wiring 786, and a ninth via 815 sequentially stacked in a vertical direction, and a twelfth wiring 826 commonly contacting the upper surfaces of the plurality of second conductive structures.

[0120] In an exemplary embodiment, the second conductive structure may extend in a direction (i.e., the second direction) that is substantially parallel to the extending direction of the first edge E1, and a plurality of second conductive structures may be formed to be spaced apart from each other in the first direction. The third wiring 726, the third via 755, the sixth wiring 756, the sixth via 785, and the ninth wiring 786 included in the second conductive structure may be formed in the sixth insulating interlayer 720, the seventh insulating interlayer 740, and the eighth insulating interlayer 770 including a low-k dielectric material, while the ninth via 815 included in the second conductive structure may be formed in the ninth insulating interlayer 800 including silicon oxide such as TEOS.

[0121] So far, the structure on the region Z adjacent to the first edge E1 in the fourth region IV around the first region I of the substrate 100 has been mainly shown. However, a similar structure may also be formed on the region (e.g., region W) adjacent to the second edge E2 in the fourth region IV of the substrate 100.

[0122] For example, in the region W formed adjacent to the second edge E2, the third wiring 726, the sixth wiring 756, and the ninth wiring 786, and the third via 755 and the sixth via 785 may be formed, and they may be referred to as conductive structures. For example, each conductive structure formed on the portion of the scribe region of the substrate 100 adjacent to the second edge E2 may include the third wiring 726, the sixth wiring 756, and the ninth wiring 786, and the third via 755 and the sixth via 785. Each conductive structure may be substantially perpendicular to the upper surface of the substrate 100. For example, when viewed in cross-section, the vertical central axis of each of the third wiring 726, the sixth wiring 756, and the ninth wiring 786, and the third via 755 and the sixth via 785 may extend in a direction substantially perpendicular to the top surface of the substrate 100. In some embodiments, when viewed in cross-section, the vertical central axes of each of the third wiring 726, the sixth wiring 756, and the ninth wiring 786, and the third via 755 and the sixth via 785 may be substantially aligned with each other. Each ninth via 815 may be formed to extend through the ninth insulating interlayer 800 to contact a corresponding conductive structure in the conductive structure including the third wiring 726, the sixth wiring 756, and the ninth wiring 786, and the third via 755 and the sixth via 785, while the twelfth wiring 826 may be formed on the upper surface of the ninth insulating interlayer 800 and the upper surface of the ninth via 815 to commonly contact the upper surface of the ninth via 815.

[0123] Specifically, in the example of the region W, the seventh opening 900 may be formed to extend in a direction substantially parallel to the extending direction of the second edge E2. For example, by a cutting process or a slicing process, the seventh opening 900 may be formed to extend between the second conductive structures in a first direction, and each of the second conductive structures may extend in the first direction. Thus, the cutting process may be guided by the second conductive structures extending in the first direction, and thus the seventh opening 900 may be formed not in the horizontal direction but in the vertical direction. Accordingly, the impact generated by the cutting process may be blocked by the second conductive structures so as not to spread to the inside of the semiconductor chip.

[0124] Although the inventive concept has been shown and described with reference to exemplary embodiments of the inventive concept, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as set forth by the claims.

Claims

1. A semiconductor device, the semiconductor device comprising: A substrate including a chip region and a scribe region surrounding the chip region, the scribe region having a first edge opposite to each other and a second edge opposite to each other, each first edge extending in a first direction, and each second edge extending in a second direction intersecting the first direction; A first insulating interlayer structure located on the scribe region of the substrate, the first insulating interlayer structure including a low-k dielectric material; A first conductive structure located on a portion of the scribe region of the substrate adjacent to one first edge, each first conductive structure extending in a vertical direction substantially perpendicular to the upper surface of the substrate through the first insulating interlayer structure and extending in the first direction; A second insulating interlayer located on the first insulating interlayer structure, the second insulating interlayer including a material having a dielectric constant greater than that of the first insulating interlayer structure; A first via hole on the scribe region and all extending in the first direction and passing through the second insulating interlayer to contact one first conductive structure; And A first wiring on the scribe region, having a plate shape and commonly contacting the upper surface of the first via hole, Wherein each first conductive structure includes second wirings and second via holes alternately and repeatedly stacked in the vertical direction, and each second wiring and each second via hole extend in the first direction.

2. The semiconductor device according to claim 1, wherein The topmost second wiring contacts the first via hole.

3. The semiconductor device according to claim 2, wherein, In a plan view, the area of each second wiring is larger than the area of each second via hole.

4. The semiconductor device according to claim 2, wherein Each second wiring and each of the first via hole and the second via hole have a strip shape extending in the first direction.

5. The semiconductor device according to claim 2, wherein, Each second wiring and each of the first via hole and the second via hole have a mesh structure extending in the first direction.

6. The semiconductor device according to claim 2, wherein, Some of the second wirings and the second via holes have a strip shape extending in the first direction, and some of the second wirings and the second via holes have a mesh structure extending in the first direction.

7. The semiconductor device according to claim 1, wherein, The first direction and the second direction are substantially perpendicular to each other, and the scribe region has a rectangular shape in a plan view.

8. The semiconductor device according to claim 1, Among them, The first insulating interlayer structure includes low-k dielectric layers and etch stop layers alternately and repeatedly stacked in the vertical direction, and Wherein the low-k dielectric layer includes porous silicon oxide, the etch stop layer includes silicon carbonitride, and the second insulating interlayer includes tetraethyl orthosilicate.

9. The semiconductor device according to claim 1, wherein, The first conductive structure, the first via hole, and the first wiring are part of a test element group.

10. The semiconductor device according to claim 1, the semiconductor device further comprising: A second conductive structure located on a portion of the scribe region of the substrate adjacent to one second edge, each second conductive structure extending in the vertical direction through the first insulating interlayer structure and extending in the second direction; A third via hole all extending in the second direction and passing through the second insulating interlayer to contact one second conductive structure; And A third wiring commonly contacting the upper surface of the third via hole.

11. The semiconductor device according to claim 1, Among them, The first insulating interlayer structure and the second insulating interlayer are also formed on the chip region of the substrate, and Wherein the semiconductor device further comprises: A second conductive structure extending through a first insulating interlayer structure over a chip region of the substrate; A third via extending through a second insulating interlayer over a chip region of the substrate; and A third wiring located on the third via over a chip region of the substrate.

12. The semiconductor device according to claim 11, wherein the semiconductor device further comprises: A first protective layer structure located on the second insulating interlayer, the first protective layer structure covering the third wiring; A redistribution layer located on the first protective layer structure, the redistribution layer being electrically connected to the third wiring; And A second protective layer located on the redistribution layer, wherein at least a portion of the first wiring is not covered by the first protective layer structure.

13. The semiconductor device according to claim 12, wherein The first protective layer structure includes a first oxide layer, a nitride layer, and a second oxide layer sequentially stacked in a vertical direction.

14. The semiconductor device according to claim 11, wherein the semiconductor device further comprises: A bit line structure located on a chip region of the substrate; A contact plug adjacent to the bit line structure, the contact plug extending in a vertical direction; And A capacitor located on the contact plug, wherein the capacitor is electrically connected to the second conductive structure.

15. A semiconductor device, the semiconductor device comprising: A substrate including a chip region and a scribe region surrounding the chip region, the scribe region having a first edge opposite to each other and a second edge opposite to each other, each first edge extending in a first direction, and each second edge extending in a second direction intersecting the first direction; A contact plug located on the scribe region of the substrate; A conductive structure located on the contact plug and extending in the first direction on a portion of the scribe region of the substrate adjacent to one of the first edges, the conductive structure including first wirings and first vias alternately and repeatedly stacked in a vertical direction substantially perpendicular to the upper surface of the substrate; And A second wiring on the scribe region, having a plate shape and commonly contacting the upper surface of the conductive structure, wherein each first wiring and each first via extend in the first direction.

16. The semiconductor device according to claim 15, wherein, The uppermost first via of each conductive structure is formed in the second insulating interlayer, and the other first vias and first wirings of each conductive structure are formed in the first insulating interlayer structure, and wherein the material of the first insulating interlayer structure is softer than the material of the second insulating interlayer.

17. The semiconductor device according to claim 16, Among them, The first insulating interlayer structure includes a low-k dielectric layer and an etch stop layer alternately and repeatedly stacked in a vertical direction, and wherein the low-k dielectric layer includes porous silicon oxide, the etch stop layer includes silicon carbonitride, and the second insulating interlayer includes tetraethyl orthosilicate.

18. A semiconductor device, the semiconductor device comprising: A substrate including a chip region and a scribe region surrounding the chip region, the scribe region having a first edge opposite to each other and a second edge opposite to each other, each first edge extending in a first direction, and each second edge extending in a second direction intersecting the first direction, the substrate having a first active pattern and a second active pattern located on the chip region and the scribe region, the first active pattern and the second active pattern being defined by an isolation pattern on the substrate; A gate structure, disposed on an upper portion of a first active pattern; A bit line structure, located on a chip region of a substrate; A first contact plug, located on the first active pattern; A capacitor, located on the first contact plug; A second contact plug, located on the capacitor; A third contact plug, located on a second active pattern; A first interlayer dielectric, in which the second contact plug and the third contact plug are formed; A second interlayer dielectric structure, located on the first interlayer dielectric; A conductive structure, located on a portion of a dicing region of the substrate adjacent to a first edge, each conductive structure extending through the second interlayer dielectric structure in a vertical direction substantially perpendicular to an upper surface of the substrate and extending in a first direction; A third interlayer dielectric, located on the second interlayer dielectric structure, the third interlayer dielectric including a material having a dielectric constant greater than that of the second interlayer dielectric structure; A first via, each first via extending in the first direction and passing through the third interlayer dielectric to contact a conductive structure on the dicing region of the substrate; And A first wiring, commonly contacting an upper surface of the first via.

19. The semiconductor device according to claim 18, wherein, Each conductive structure includes second wirings and second vias alternately and repeatedly stacked in the vertical direction, and the uppermost second wiring contacts the first via.

20. The semiconductor device according to claim 19, wherein, Each of the second wirings, and each of the first via and the second vias has a bar shape extending in the first direction.

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