Integrated circuit device and method for forming the same

Abstract

The present disclosure relates to integrated circuit devices and methods for forming the same. A method includes: depositing a first work function layer and a second work function layer in a first device region and a second device region, respectively, and depositing a first fluorine barrier layer and a second fluorine barrier layer in the first device region and the second device region, respectively. The first fluorine barrier layer is located above the first work function layer, and the second fluorine barrier layer is located above the second work function layer. The method also includes: removing the second fluorine barrier layer, and forming a first metal filling layer above the first fluorine barrier layer, and forming a second metal filling layer above the second work function layer.

Description

Technical Field

[0001] The present disclosure relates generally to integrated circuit devices and methods of forming the same. Background Art

[0002] Metal oxide semiconductor (MOS) devices typically include a metal gate that is formed to address the polysilicon depletion effect in traditional polysilicon gates. The polysilicon depletion effect occurs when an applied electric field removes carriers from the gate region near the gate dielectric, forming a depletion layer. In an n-doped polysilicon layer, the depletion layer includes ionized non-mobile donor sites, wherein in a p-doped polysilicon layer, the depletion layer includes ionized non-mobile acceptor sites. The depletion effect causes the effective gate dielectric thickness to increase, making it more difficult to form an inversion layer on the surface of the semiconductor.

[0003] The metal gate may include multiple layers to meet the requirements of NMOS devices and PMOS devices. The formation of the metal gate generally involves depositing multiple metal layers, forming a fill metal region with tungsten, and then performing chemical mechanical polishing (CMP) to remove excess portions of the metal layer. The remaining portions of the metal layer form the metal gate. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for forming an integrated circuit device is provided, comprising: removing a dummy gate stack to form a first groove between a first gate spacer and a second groove between a second gate spacer, wherein the first gate spacer and the second gate spacer are respectively located in a short channel device region and a long channel device region; forming a first work function layer extending into the first groove and a second work function layer extending into the second groove; forming a first fluorine barrier layer above the first work function layer, wherein the first fluorine barrier layer is formed of a fluorine barrier material; forming a first fluorine-containing metal layer above the first work function layer, wherein the first fluorine-containing metal layer is formed of a fluorine-containing material; and forming a second fluorine-containing metal layer above the second work function layer, wherein there is no fluorine barrier material between the second fluorine-containing metal layer and the second work function layer, or there is a second fluorine barrier layer, wherein the thickness of the second fluorine barrier layer is less than the thickness of the first fluorine barrier layer.

[0005] According to another embodiment of the present disclosure, a method for forming an integrated circuit device is provided, comprising: depositing a first work function layer and a second work function layer in a first device region and a second device region, respectively; depositing a first fluorine barrier layer and a second fluorine barrier layer in the first device region and the second device region, respectively, wherein the first fluorine barrier layer is located above the first work function layer, and the second fluorine barrier layer is located above the second work function layer; removing the second fluorine barrier layer; and forming a first metal filling layer above the first fluorine barrier layer, and forming a second metal filling layer above the second work function layer.

[0006] According to another embodiment of the present disclosure, an integrated circuit device is provided, comprising: a first transistor, comprising: a first work function layer; a first cap layer, located above the first work function layer; a first fluorine barrier layer, located above the cap layer; and a first metal filling region, located above the first fluorine barrier layer, wherein the first metal filling region comprises fluorine; and a second transistor, comprising: a second work function layer; a second cap layer, located above the second work function layer; and a second metal filling region, located above the second cap layer and in contact with the second cap layer, wherein the second metal filling region comprises fluorine. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1-Figure 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Figure 9-Figure 15 , Fig.16A and Fig. 16B Perspective and cross-sectional views illustrate intermediate stages in the formation of a fin field effect transistor (FinFET) in accordance with some embodiments.

[0009] Figures 17 to 23 Perspective and cross-sectional views illustrate intermediate stages in the formation of a fin field effect transistor (FinFET) in accordance with some embodiments.

[0010] Fig.24 and Fig.25 A cross-sectional view of a FinFET is shown in accordance with some embodiments.

[0011] Fig.26 A graph of threshold voltage versus channel length is shown in accordance with some embodiments.

[0012] Fig. 27 A process flow for forming a FinFET according to some embodiments is shown. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0015] According to some embodiments, a transistor with a replacement gate and a method for forming the same are provided. According to some embodiments, an intermediate stage of forming a transistor is shown. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, the same reference numerals are used to indicate the same elements. In the illustrated embodiment, the formation of a fin field effect transistor (FinFET) is used as an example to explain the concept of the present disclosure. Planar transistors may also adopt the concept of the present disclosure. According to some embodiments of the present disclosure, a fluorine barrier layer is used to block fluorine from diffusing from a fluorine-containing metal region into the work function layer below a shorter channel transistor. When diffused into the work function layer, fluorine has the effect of causing the threshold voltage of the corresponding transistor to increase. Due to geometric effects, the threshold voltage of a long channel transistor is lower than that of a short channel transistor, so blocking fluorine from diffusing into its work function layer may cause its threshold voltage to be lower than the value for maintaining its normal operation. Therefore, in a long channel transistor, a fluorine barrier layer is not formed, or a fluorine barrier layer having a thickness thinner than that of a short channel transistor is formed, thereby increasing the threshold voltage of the long channel transistor by the merged fluorine.

[0016] Figure 1-Figure 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Figure 9-Figure 15 , Fig.16A and Fig. 16B The cross-sectional and perspective views show intermediate stages in the formation of a fin field effect transistor (FinFET) according to some embodiments of the present disclosure. The processes shown in these figures are also schematically reflected in Fig. 27 In the process flow 400 shown.

[0017] exist Figure 1 , a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, for example, a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, etc., which may be doped (for example, with a p-type or n-type dopant) or undoped. The semiconductor substrate 20 may be a portion of the wafer 10, for example, a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates may also be used, for example, a multilayer or gradient substrate. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

[0018] Further references Figure 1 , a well region 22 is formed in the substrate 20. The corresponding process is Fig. 27 The process flow 400 is shown as process 402. According to some embodiments of the present disclosure, the well region 22 is a p-type well region formed by injecting p-type impurities (which may be boron, indium, etc.) into the substrate 20. According to other embodiments of the present disclosure, the well region 22 is an n-type well region formed by injecting n-type impurities (which may be phosphorus, arsenic, antimony, etc.) into the substrate 20. The formed well region 22 may extend to the top surface of the substrate 20. The n-type or p-type impurity concentration may be equal to or less than 10 18 cm -3 , for example, at about 10 17 cm -3 and about 10 18 cm -3 in the range between.

[0019] refer to Figure 2 , the isolation region 24 is formed to extend from the top surface of the substrate 20 into the substrate 20. Hereinafter, the isolation region 24 is alternatively referred to as a shallow trench isolation (STI) region. Fig. 27 The process flow 400 shown in FIG. 4 is shown as process 404. The portion of the substrate 20 between adjacent STI regions 24 is referred to as a semiconductor strip 26. In order to form the STI region 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate and then patterned. The pad oxide layer 28 may be a thin film formed of silicon oxide. According to some embodiments of the present disclosure, the pad oxide layer 28 is formed in a thermal oxidation process, wherein the top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 is used as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 may also be used as an etch stop layer for etching the hard mask layer 30. According to some embodiments of the present disclosure, the hard mask layer 30 is formed of silicon nitride, for example, using low pressure chemical vapor deposition (LPCVD). According to other embodiments of the present disclosure, the hard mask layer 30 is formed by thermal nitridation of silicon or plasma enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 30 and then patterned. Then, the hard mask layer 30 is patterned using the patterned photoresist as an etching mask to form a Figure 2 A hard mask 30 is shown.

[0020] Next, the patterned hard mask layer 30 is used as an etching mask to etch the pad oxide layer 28 and the substrate 20, and then the resulting trenches in the substrate 20 are filled with (one or more) dielectric materials. A planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process is performed to remove excess portions of the dielectric material, and the remaining portions of the (one or more) dielectric materials are the STI regions 24. The STI regions 24 may include a liner dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The liner dielectric may also be a deposited silicon oxide layer, a silicon nitride layer, etc. formed using, for example, atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI regions 24 may also include a dielectric material above the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, etc. According to some embodiments, the dielectric material above the liner dielectric may include silicon oxide.

[0021] The top surface of hard mask 30 and the top surface of STI region 24 may be substantially flush with each other. Semiconductor strips 26 are between adjacent STI regions 24. According to some embodiments of the present disclosure, semiconductor strips 26 are portions of original substrate 20, and thus the material of semiconductor strips 26 is the same as the material of substrate 20. According to alternative embodiments of the present disclosure, semiconductor strips 26 are replacement strips formed by etching portions of substrate 20 between STI regions 24 to form grooves, and performing epitaxy to re-grow another semiconductor material in the grooves. Therefore, semiconductor strips 26 are formed of a semiconductor material different from that of substrate 20. According to some embodiments, semiconductor strips 26 are formed of silicon germanium, silicon carbon, or III-V compound semiconductor materials.

[0022] refer to Figure 3 , the STI region 24 is recessed so that the top of the semiconductor strip 26 protrudes above the top surface 24A of the rest of the STI region 24 to form a protruding fin 36. The corresponding process is Fig. 27 4 is shown as process 406 in the process flow 400 shown in . The etching can be performed using a dry etching process, wherein, for example, HF3 and NH3 are used as etching gases. During the etching process, plasma may be generated. Argon may also be included. According to an alternative embodiment of the present disclosure, the recessing of the STI region 24 is performed using a wet etching process. The etching chemical may include, for example, HF.

[0023] In the above embodiments, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, the double patterning or multi-patterning process combines photolithography and self-alignment processes, allowing for the creation of patterns with, for example, smaller pitches than can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0024] refer to Figure 4 , a dummy gate stack 38 is formed to extend over the top surface and sidewalls of the (protruding) fin 36. The corresponding process is Fig. 27408 in the process flow 400 shown in FIG. 408. The dummy gate stack 38 may include a dummy gate dielectric 40, and a dummy gate electrode 42 above the dummy gate dielectric 40. The dummy gate electrode 42 may be formed, for example, using polysilicon, and other materials may also be used. Each dummy gate stack 38 may also include one (or more) hard mask layers 44 above the dummy gate electrode 42. The hard mask layer 44 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. The dummy gate stack 38 may span a single or multiple protruding fins 36 and / or STI regions 24. The dummy gate stack 38 also has a length direction perpendicular to the length direction of the protruding fins 36.

[0025] Next, a gate spacer 46 is formed on the sidewall of the dummy gate stack 38. The corresponding process is Fig. 27 The process flow 400 shown in FIG. 4 is also shown as process 408. According to some embodiments of the present disclosure, the gate spacer 46 is formed of dielectric material(s) such as silicon nitride, silicon carbonitride, etc., and may have a single layer structure or a multi-layer structure including multiple dielectric layers.

[0026] Then, an etching process is performed to etch the portion of the protruding fin 36 that is not covered by the dummy gate stack 38 and the gate spacer 46, resulting in Figure 5 The corresponding process is Fig. 27 4 is shown as process 410 in the process flow 400 shown in FIG. The recess may be anisotropic, so that the portion of the fin 36 directly below the dummy gate stack 38 and the gate spacer 46 is protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 26 may be lower than the top surface 24A of the STI region 24. Recess 50 is formed accordingly. Recess 50 includes portions on opposite sides of the dummy gate stack 38 and portions between the remaining portions of the protruding fin 36.

[0027] Next, epitaxial regions (source / drain regions) 54 are formed by selectively growing (by epitaxy) semiconductor material in the recesses 50, resulting in Figure 6 The corresponding process is Fig. 27The process flow 400 shown in is shown as process 412. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities may be in-situ doped as the epitaxy proceeds. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB) or silicon boron (SiB) may be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP) or silicon carbon phosphorus (SiCP) may be grown. According to an alternative embodiment of the present disclosure, the epitaxial region 54 includes a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, multiple layers thereof, and the like. After the groove 50 is filled with the epitaxial region 54, further epitaxial growth of the epitaxial region 54 causes the epitaxial region 54 to expand horizontally, and facets may be formed. Further growth of the epitaxial region 54 may also cause adjacent epitaxial regions 54 to merge with each other. A void (air gap) 56 may be generated. According to some embodiments of the present disclosure, when the top surface of the epitaxial region 54 is still wavy, or when the top surface of the merged epitaxial region 54 has become flat (this is achieved by further growth on the epitaxial region 54, such as Figure 6 As shown), the formation of the epitaxial region 54 can be completed.

[0028] After the epitaxial process, the epitaxial region 54 may be further implanted with p-type or n-type impurities to form source and drain regions, which are also indicated by reference numeral 54. According to an alternative embodiment of the present disclosure, when the epitaxial region 54 is in-situ doped with p-type or n-type impurities during epitaxy, the implantation step is skipped.

[0029] Fig. 7A FIG. 4 shows a perspective view of the structure after forming a contact etch stop layer (CESL) 58 and an interlayer dielectric (ILD) 60. The corresponding process is shown in FIG. Fig. 27 4. The CESL 58 may be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and may be formed using CVD, ALD, etc. The ILD 60 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition method. The ILD 60 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material, such as tetraethylorthosilicate (TEOS) oxide, phospho-silicate glass (PSG), borosilicate glass (BSG), boron-doped phospho-silicate glass (BPSG), etc. A planarization process such as a CMP process or a mechanical grinding process may be performed to make the top surfaces of the ILD 60, the dummy gate stack 38, and the gate spacers 46 flush with each other.

[0030] Figure 7BA cross-sectional view of an intermediate structure in which a short channel FinFET and a long channel FinFET are formed on the same substrate 20 is shown. A short channel device (which may be a FinFET) is formed in a device region 100, and a long channel device (which may be a FinFET) is formed in a device region 200. The channel length Lg1 of the short channel device is less than the channel length Lg2 of the long channel device, as shown. According to some embodiments, the ratio Lg2 / Lg1 may be greater than about 1.5 or 2.0, and may be in a range between about 1.5 and about 10. According to some embodiments, the short channel device is a core transistor or a transistor in other circuits such as a static random access memory (SRAM), and the long channel device is a transistor in a driver circuit, a peripheral circuit, etc. A cross-sectional view of either the short channel device and the long channel device may correspond to a cross-sectional view from a device including Figure 6 A cross-sectional view obtained in a plane perpendicular to line AA.

[0031] According to some embodiments, each of the short channel device and the long channel device may be a short channel device, a medium channel device, and a long channel device. It should be understood that whether the device is a short channel device, a medium channel device, or a long channel device is relative and may be related to the formation technology of the device (transistor). According to some embodiments of the present disclosure, the channel length of the short channel device may be less than about 30nm, and the channel length of the long channel device may be greater than about 100nm. The channel length of the medium channel device may be in the range between about 30nm and about 100nm. When the transistor is a short channel transistor, a medium channel transistor, or a long channel transistor, the corresponding device region is referred to as a short channel device region, a medium channel device region, or a long channel device region, respectively. It should be understood that the channel length ranges of short channel devices, medium channel devices, and long channel devices are examples and may be redefined. For example, when the size of the transistor is reduced, the channel length ranges of the short channel transistor, the medium channel transistor, and the long channel transistor may be reduced. Each of the device regions 100 and 200 may be any one of a short channel device region, a medium channel device region, and a long channel device region, as long as the channel of the transistor in the device region 200 is longer than the channel of the transistor in the device region 100. For example, the device region 100 may be a short channel device region or a medium channel device region, and the device region 200 may be a medium channel device region or a long channel device region, respectively. The device regions 100 and 200 may both be short channel device regions, both be medium channel device regions, or may also both be long channel device regions.

[0032] To distinguish features in short-channel devices from those in long-channel devices, use Fig. 7A The reference numerals of the corresponding features in the short channel device are increased by 100, and the ... Fig. 7AThe reference numerals of the corresponding features in FIG. 7 are added with the number 200 to indicate features in the long channel device. For example, the source / drain regions 154 and 254 in FIG. 7 correspond to Fig. 7A 146 and 246. The gate spacers in the short channel device region and the long channel device region are respectively indicated as 146 and 246. The corresponding features in the short channel device and the long channel device can be formed in the same process, some example processes of which are discussed in the following paragraphs.

[0033] In the formation Fig. 7A and Figure 7B After the structure shown, the dummy gate stacks 138 and 238 are replaced with metal gates and replacement gate dielectrics, as shown in FIG. Fig. 8A , Figure 8B as well as Figures 9 to 14 As shown. Fig. 8A , Figure 8B as well as Figures 9 to 14 , top surfaces 124A and 224A of STI regions 24 are shown, and semiconductor fins 124 ′ and 224 ′ protrude above top surfaces 124A and 224A, respectively.

[0034] To form a replacement gate, first remove Fig. 7A and Figure 7B The hard mask layers 144 and 244, the dummy gate electrodes 142 and 242, and the dummy gate dielectrics 140 and 240 are formed as shown. Fig. 8A The opening 59 shown. The corresponding process is Fig. 27 This is shown as process 416 in the illustrated process flow 400 . Fig. 8A The opening 59 in corresponds to Figure 8B The device region 100 and the device region 200 are formed by an opening 159 in the device region 100 and an opening 259 in the device region 200. Top surfaces and sidewalls of the protruding fins 124' and 224' are exposed to the openings 159 and 259, respectively.

[0035] Next, refer to Fig. 9 , forming gate dielectrics 161 / 162 and 261 / 262, which extend into openings 159 and 259, respectively. The corresponding process is Fig. 27The process flow 400 shown is shown as process 418. According to some embodiments of the present disclosure, the gate dielectric includes an interfacial layer (IL) 161 and 261, which is formed on the exposed surface of the protruding fins 124' and 224'. The ILs 161 and 261 may include an oxide layer such as a silicon oxide layer, which is formed by thermal oxidation, chemical oxidation process, or deposition process of the protruding fins 124' and 224'. The gate dielectric may also include a high-k dielectric layer 162 and 262 above the corresponding ILs 161 and 261. The high-k dielectric layers 162 and 262 may be formed of a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, etc. The dielectric constant (k value) of the high-k dielectric material is higher than 3.9, and may be higher than about 7.0, and sometimes as high as 21.0 or higher. The high-k dielectric layers 162 and 262 cover the corresponding underlying ILs 161 and 261 and may be in contact with them. The high-k dielectric layers 162 and 262 are formed as conformal layers and extend over the sidewalls of the protruding fins 124' and 224', and the top surfaces and sidewalls of the gate spacers 146 and 246. According to some embodiments of the present disclosure, the high-k dielectric layers 162 and 262 are formed using ALD or CVD. The high-k dielectric layers 162 and 262 may be part of the same dielectric layer and formed simultaneously with the same material and the same thickness, or may be formed separately with different materials and / or different thicknesses.

[0036] Further references Fig. 9 , by depositing work function layers 163 and 263. The corresponding process is Fig. 27 The process flow 400 shown is shown as process 420. Each of the work function layers 163 and 263 includes at least one homogeneous layer formed entirely of the same material, or may include multiple sublayers composed of different materials. The corresponding layers in the work function layers 163 and 263 are formed in the same deposition process. The specific materials of the layers in the work function layers 163 and 263 may include work function metals selected according to whether the corresponding FinFETs formed in the device regions 100 and 200 are n-type FinFETs or p-type FinFETs. For example, when the FinFET is an n-type FinFET, the work function layers 163 and 263 may include a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, and an Al-based layer (e.g., formed of TiAl, TiAlN, TiAlC, TaAlN, or TaAlC). When the FinFET is a p-type FinFET, the work function layers 163 and 263 may include a TiN layer, a TaN layer, and another TiN layer.

[0037] According to some embodiments of the present disclosure, capping layers 164 and 264 (also adhesion layers) are formed on work function layers 163 and 263, respectively. Fig. 27The process flow 400 is shown as process 422. Capping layers 164 and 264 may be metal-containing layers, which may be formed of TiN according to some embodiments. Other materials such as TaN may be used. According to some embodiments, ALD is used to form capping layers 164 and 264. The thickness of capping layers 164 and 264 is small enough that they do not significantly block the diffusion of fluorine in the layers above into the underlying work function layers 163 and 263. Instead, the function of blocking fluorine is achieved by a subsequently formed fluorine barrier layer. According to some embodiments of the present disclosure, capping layers 164 and 264 have a thickness of less than about The thickness of the capping layers 164 and 264 may be in a range of about 10 nm to about 40 nm. The capping layers 164 and 264 may be part of the same metal-containing layer, formed simultaneously with the same material and the same thickness, or formed separately with different materials and / or different thicknesses.

[0038] Fig.10 The formation of fluorine barrier layers 166 and 266 in device regions 100 and 200, respectively, is shown. The corresponding process is shown in FIG. Fig. 27 The process flow 400 is shown as process 424. The fluorine barrier layers 166 and 266 are formed of a material (e.g., metal) having good fluorine diffusion barrier capability and / or having the ability to capture fluorine. In addition, the fluorine barrier layers 166 and 266 have a low resistivity value. The fluorine barrier layers 166 and 266 can be formed of a material having a high density, for example, having a resistivity greater than about 8 g / cm 3 density. The resistivity can be less than about 600 μm*cm. The fluorine barrier layers 166 and 266 can be formed of metals such as tungsten, cobalt, molybdenum, or alloys thereof. The thickness of the fluorine barrier layers 166 and 266 can be large enough to block at least a majority (e.g., greater than 75% or greater than 90%) of the fluorine diffused from the layers above from reaching the work function layers 163 and 263 (if the fluorine barrier layer 266 is not removed in a subsequent process). The desired thickness is also material-dependent, and a fluorine barrier layer formed of a denser material can be formed thinner without sacrificing its ability to inhibit diffusion. The fluorine barrier layers 166 and 266 can also include other high-density materials, such as silicon nitride, silicon oxide, aluminum-based oxide, and the like. The dielectric fluorine barrier layer can be above or below the metal fluorine barrier layer. Despite being dielectric materials, the thickness of these materials can be large enough to at least partially block fluorine diffusion, but small enough for electrical tunneling. For example, the thickness of the dielectric material can be less than about And can be about About in the range between.

[0039] According to some embodiments of the present disclosure in which a metal such as tungsten, cobalt, or molybdenum is used, the thickness of the fluorine barrier layers 166 and 266 is greater than about In order to fully inhibit diffusion. The thickness can be about Peace in the range between.

[0040] The formation method of the fluorine barrier layers 166 and 266 may include ALD. The deposition process is performed using a process gas that does not contain fluorine, and the process gas may include hydrogen (H2) and a metal-containing process gas. For example, when the fluorine barrier layers 166 and 266 are formed of tungsten, the corresponding metal-containing process gas may include WCl x , WBr x , WCN or a combination thereof. The process gas may or may not include NH3. The deposition may be performed at a temperature between about 200°C and about 450°C. The resulting fluorine barrier layers 166 and 266 may have a crystalline structure. The corresponding fluorine barrier layers 166 and 266 do not contain fluorine when deposited. The fluorine barrier layers 166 and 266 may be parts of the same metal-containing layer, which are formed simultaneously with the same material and the same thickness, or may be formed separately with different materials and / or different thicknesses.

[0041] refer to Fig.11 , forming an etching mask 165, and patterning it to protect the fluorine barrier layer 166, while exposing the fluorine barrier layer 266 ( Fig.10 ). The etching mask 165 may be formed of a photoresist. Next, the fluorine barrier layer 266 is removed in an etching process, thereby exposing the cap layer 264 below. Fig.11 The corresponding process is Fig. 27 This is shown as process 426 in the illustrated process flow 400. The etch mask 165 is then removed, for example, in an ashing process.

[0042] Fig.12 The formation of nucleation layers 168 and 268 is shown, which are used for nucleation to help form subsequently deposited fluorine-containing layers 170 and 270. The corresponding process is Fig. 27 The process flow 400 is shown as process 428. According to some embodiments, the nucleation layers 168 and 268 are formed using ALD by pulsing a first gas (e.g., H2, B2H6, NH3, etc.) and a second gas (which may be a metal halide, such as WF6). Other methods such as CVD may be used, and the process gas may include WF6 and H2 and some carrier gas, such as argon. Thus, the nucleation layers 168 and 268 may include fluorine therein. The deposition may be performed at a temperature in a range between about 250° C. and about 450° C. The thickness of the nucleation layers 168 and 268 may be about 1000 mm / s. Peace In the device region 100, the nucleation layer 168 is above the fluorine barrier layer 166 and may be in contact with it. In the device region 200, the nucleation layer 268 is above the cap layer 264 and may be in contact with it. In some impurities in the nucleation layers 168 and 268, the nucleation layers 168 and 268 may be amorphous.

[0043] Fig.13 2 shows a gap filling process, wherein fluorine-containing metal layers 170 and 270 are formed to fill the remaining openings 159 and 259 ( Fig.12 ). The corresponding process is Fig. 27 The process flow 400 shown is shown as process 430. According to some embodiments, CVD is used to form the fluorine-containing metal layers 170 and 270. Alternatively, ALD can be used, but the deposition rate of ALD is lower than that of CVD. The process gas may include WF6, H2, and some carrier gases, such as argon. Therefore, the fluorine-containing metal layers 170 and 270 also contain fluorine therein. The deposition can be performed at a temperature in the range of about 250°C to about 450°C. According to some embodiments of the present disclosure, the fluorine barrier layer 166, the nucleation layer 168, and the fluorine-containing metal layer 170 can be distinguished from each other, for example, using a transmission electron microscope (TEM), regardless of whether they include the same metal. The nucleation layer 268 and the fluorine-containing metal layer 270 can also be distinguished from each other using TEM.

[0044] After forming the fluorine-containing metal layers 170 and 270, as Fig.13 As shown, a planarization process such as a chemical mechanical polishing (CMP) process or a mechanical polishing process may be performed to remove excess portions of the deposited layer, producing a planarization process such as Fig.14 The gate stacks 174 and 274 are shown. The corresponding process is Fig. 27 This is shown as process 432 in the illustrated process flow 400. The gate stacks 174 and 274 include gate dielectrics 161 / 162 and 261 / 262, and gate electrodes 172 and 272, respectively.

[0045] Fig.15The formation of source / drain contact plugs 84 and source / drain silicide regions 86 is shown. Forming the source / drain contact plugs 84 includes forming contact openings by etching the ILD 60 to expose the underlying portion of the CESL 58, and then etching the exposed portion of the CESL 58 to expose the source / drain regions 154 and 254. In a subsequent process, a metal layer (e.g., a Ti layer) is deposited and extends into the contact openings. A metal nitride capping layer may be performed. An annealing process is then performed to react the metal layer with the top of the source / drain regions 154 / 254 to form the silicide regions 86. Next, the previously formed metal nitride layer is retained without being removed, or the previously formed metal nitride layer is removed, and then a new metal nitride layer (e.g., a titanium nitride layer) is deposited. A fill metal material such as tungsten, cobalt, etc. is then filled into the contact openings, and then planarization is performed to remove excess material, thereby producing the source / drain contact plugs 84.

[0046] Fig.16A The formation of a hard mask 80 according to some embodiments is shown. The formation of the hard mask 80 may include performing an etching process to recess the gate stacks 174 and 274 so that a groove is formed between the opposing portions of the gate spacers 146 and 246, filling the groove with a dielectric material, and then performing a planarization process such as a CMP process or a mechanical grinding process to remove excess portions of the dielectric material. The hard mask 80 may be formed of silicon nitride, silicon oxynitride, silicon oxycarbonitride, etc. An etch stop layer 88 and a dielectric layer 90 are then formed. A gate contact plug 82 is formed to penetrate a portion of each hard mask 80 to contact the gate electrodes 172 and 272. Thus, a short channel FinFET 184 and a long channel FinFET 284 are formed.

[0047] Fig. 16B A perspective view of a FinFET is shown, which may represent a Fig.16A Any of the short channel FinFET 184 and the long channel FinFET 284 are shown. The gate contact plug 82, the source / drain silicide regions 86, and the source / drain contact plugs 84 are also shown.

[0048] like Fig.16A As shown, the short channel FinFET 184 includes a fluorine barrier layer 166, which prevents and / or reduces the diffusion of fluorine in the upper layers 168 and 170 into the work function layer 163. Therefore, the increase in the threshold voltage in the short channel FinFET 184 is suppressed. On the other hand, in the long channel FinFET 284, there is no fluorine barrier layer, so fluorine may diffuse into the underlying work function layer 263 and cause the threshold voltage of the long channel FinFET 284 to increase. Due to geometric effects, such as Fig.26As shown, as the channel length increases, the threshold voltage of the FinFET decreases, as shown by line 94. If a fluorine barrier layer is also formed in the long channel FinFET, the threshold voltage of the long channel FinFET may be too low to enable the long channel FinFET to operate normally. Therefore, by forming a fluorine barrier layer in the short channel FinFET but not in the long channel FinFET, the high threshold voltage of the short channel FinFET is suppressed, while the low threshold voltage of the long channel FinFET is not suppressed. Line 96 represents the increase in threshold voltage due to the diffusion of fluorine into the long channel FinFET.

[0049] Figures 17 to 23 1 shows a cross-sectional view of an intermediate stage in the formation of a FinFET according to some embodiments of the present disclosure. Unless otherwise specified, the materials and formation processes of the components in these embodiments are the same as those in Figure 1-6 , 7A, 7B, 8A, 8B, 9-15, 16A and 16B, the same components represented by the same reference numerals in the above-mentioned embodiments are substantially the same. Therefore, the discussion of the above-mentioned embodiments can be found in detail. Figures 17 to 23 Details of the formation process and materials of the components shown.

[0050] The initial steps of these embodiments are Figures 1 to 9 Next, refer to Fig.17 , the fluorine barrier layers 166A and 266A are formed by deposition. The materials and forming methods of the fluorine barrier layers 166A and 266A can be selected from the candidate materials and candidate forming methods discussed in the previous embodiments, and thus will not be repeated here. The thickness of the fluorine barrier layers 166A and 266A is less than Fig.10 In addition, the thickness of the fluorine barrier layers 166A and 266A is small enough so that some fluorine (eg, between about 40% and 70%) can penetrate and cause a significant increase in the threshold voltage of the corresponding FinFET. The thickness will be discussed in detail in the subsequent paragraphs.

[0051] Then, an etching mask 165 is formed and patterned so that the remaining portion protects the fluorine barrier layer 166A in the device region 100 and exposes the fluorine barrier layer 266A. Next, the fluorine barrier layer 266A is removed in an etching process to expose the cap layer 264 below. The etching mask 165 is then removed, and Fig.18 The resulting structure is shown in .

[0052] Fig.19The formation of fluorine barrier layers 166B and 266B is shown, which are formed simultaneously with the same material. The materials and formation methods of fluorine barrier layers 166B and 266B can be selected from the candidate materials and candidate formation methods in the embodiments discussed previously, so they are not repeated here. The materials of fluorine barrier layers 166B and 266B can be the same as or different from the materials of fluorine barrier layers 166A and 266A. Fluorine barrier layers 166A and 166B are collectively referred to as fluorine barrier layers 166. Fluorine barrier layers 166A and 166B can be distinguished from each other, for example using TEM, regardless of whether they are formed of the same material or different materials.

[0053] According to some embodiments of the present disclosure, the thickness of the fluorine barrier layer 166 is about Fig.10 In addition, the thickness of the fluorine barrier layer 166 is large enough so that most (e.g., more than about 75% or 90%) of the fluorine is blocked from reaching the underlying work function layer 163. For example, the increase in threshold voltage (if any) due to diffused fluorine incorporated into the underlying work function layer 163 can be less than about 0.05V. On the other hand, the thickness of the fluorine barrier layer 266B is small enough so that the fluorine will pass through it to reach the underlying work function layer 263 and cause a significant increase in the threshold voltage of the resulting FinFET. For example, the increase in threshold voltage due to diffused fluorine incorporated into the underlying work function layer 263 is greater than about 0.07V.

[0054] According to some embodiments of the present disclosure, the thickness T2 of the fluorine barrier layer 166B is less than about And can be about Peace The thickness T1 of the fluorine barrier layer 166 is greater than about And can be about Peace . The thickness ratio T2 / T1 is maintained within the selected range. When the thickness ratio T2 / T1 is too large, this means that the thickness T2 is too large (which means that the threshold voltage of the resulting long channel FinFET is not increased enough) or the thickness T1 is too small (which means that the threshold voltage of the resulting short channel FinFET is not sufficiently suppressed). When the thickness ratio T2 / T1 is too small, the fluorine barrier layer 266B does not have sufficient ability to block the diffusion of fluorine, so that the fluorine barrier layer 266B cannot be formed. According to some embodiments, the thickness ratio T2 / T1 can be in the range between about 0.2 and about 0.8.

[0055] exist Fig. 20 In the embodiment, nucleation layers 168 and 268 and fluorine-containing metal layers 170 and 270 are formed, and then a planarization process is performed to form gate electrodes 172 and 272 and corresponding gate stacks 174 and 274, as shown in FIG. Fig.21Next, source / drain contact plugs 84 and source / drain silicide regions 86 are formed, as shown in FIG. Fig. 22 Then, a gate contact plug 82 is formed, as shown in FIG. Fig.23 As shown. The materials and the formation process have been discussed in the previous embodiment and will not be repeated here. Thus, FinFETs 184 and 284 are formed.

[0056] Fig.24 FinFETs 184, 284, and 384 are shown formed in three device regions 100, 200, and 300, respectively. Some details such as source / drain regions of FinFETs 184, 284, and 384 are not shown. Each of FinFETs 184, 284, and 384 may be a short channel FinFET, a mid-channel FinFET, or a long channel FinFET, wherein the channel of FinFET 184 is shorter than the channel of FinFET 284, and the channel of FinFET 284 is shorter than the channel of FinFET 384. For example, FinFETs 184, 284, and 384 may be short channel FinFETs, mid-channel FinFETs, and long channel FinFETs, respectively. According to some embodiments of the present disclosure, the thickness TA of the fluorine barrier layer 166 is greater than the thickness TB of the fluorine barrier layer 266, and the thickness TB of the fluorine barrier layer 266 is greater than the thickness TC of the fluorine barrier layer. For example, the ratio TB / TA may be in the range of about 0.5 to about 0.8, and the ratio TC / TA may be in the range of about 0.2 to about 0.6.

[0057] Fig.25 FinFETs 184, 284, and 384' are shown according to some embodiments. These embodiments are similar to Fig.24 The embodiment shown, except that there is no fluorine barrier layer in FinFET 384'.

[0058] Embodiments of the present disclosure have some advantageous features. By forming a fluorine barrier layer in a short channel transistor, the increase in the corresponding threshold voltage due to the fluorine diffused in the work function layer is substantially eliminated, and the threshold voltage of the short channel transistor can be maintained low. The threshold voltage of the long channel transistor is lower than that of the short channel transistor. Therefore, blocking the diffusion of fluorine into its work function layer may cause its threshold voltage to be too low. Therefore, the fluorine barrier layer in the long channel transistor is thinner than the fluorine barrier layer in the short channel transistor, or is completely removed, so that the threshold voltage of the long channel FinFET is not undesirably reduced too much.

[0059] According to some embodiments of the present disclosure, a method includes: removing a dummy gate stack to form a first groove between a first gate spacer and a second groove between a second gate spacer, wherein the first gate spacer and the second gate spacer are respectively located in a short channel device region and a long channel device region; forming a first work function layer extending into the first groove and a second work function layer extending into the second groove; forming a first fluorine barrier layer above the first work function layer, wherein the first fluorine barrier layer is formed of a fluorine barrier material; forming a first fluorine-containing metal layer above the first work function layer, wherein the first fluorine-containing metal layer is formed of a fluorine-containing material; and forming a second fluorine-containing metal layer above the second work function layer, wherein there is no fluorine barrier material between the second fluorine-containing metal layer and the second work function layer, or there is a second fluorine barrier layer, wherein the thickness of the second fluorine barrier layer is less than the thickness of the first fluorine barrier layer. In an embodiment, the method further includes: forming a fluorine barrier material above the second work function layer in the same process used to form the first fluorine barrier layer; and removing the fluorine barrier material from the long channel device region before forming the second fluorine-containing metal layer. In an embodiment, the method further includes: forming a first sub-fluorine barrier layer, the first sub-fluorine barrier layer including a first portion overlapping the first work function layer and a second portion overlapping the second work function layer; removing the second portion of the first sub-fluorine barrier layer, and not removing the first portion of the first sub-fluorine barrier layer; and forming a second sub-fluorine barrier layer, the second sub-fluorine barrier layer including a first portion overlapping the first portion of the first work function layer and a second portion overlapping the second work function layer, wherein the first portion of the first sub-fluorine barrier layer and the first portion of the second sub-fluorine barrier layer are combined to form a first fluorine barrier layer, and the second portion of the second sub-fluorine barrier layer forms a second fluorine barrier layer. In an embodiment, forming the first fluorine-containing metal layer includes: depositing a fluorine-free metal layer. In an embodiment, the fluorine-free metal layer includes tungsten, cobalt, or molybdenum. In an embodiment, forming the first fluorine barrier layer includes depositing a silicon nitride layer, a silicon oxide layer, or an aluminum-based oxide layer. In an embodiment, forming the second fluorine-containing metal layer includes: depositing a nucleation layer; and depositing a metal filling region, wherein the nucleation layer and the metal filling region include fluorine.

[0060] According to some embodiments of the present disclosure, a method includes: depositing a first work function layer and a second work function layer in a first device region and a second device region, respectively; depositing a first fluorine barrier layer and a second fluorine barrier layer in the first device region and the second device region, respectively, wherein the first fluorine barrier layer is located above the first work function layer and the second fluorine barrier layer is located above the second work function layer; removing the second fluorine barrier layer; and forming a first metal filling layer above the first fluorine barrier layer and forming a second metal filling layer above the second work function layer. In an embodiment, the first work function layer is included in a first transistor including a first channel, and the second work function layer is included in a second transistor including a second channel, and the first channel is shorter than the second channel. In an embodiment, the first work function layer and the second work function layer are formed in the same deposition process. In an embodiment, the first fluorine barrier layer and the second fluorine barrier layer are formed in the same deposition process. In an embodiment, the method further includes: depositing a third fluorine barrier layer and a fourth fluorine barrier layer in the first device region and the second device region, respectively, wherein the third fluorine barrier layer is located above the first fluorine barrier layer. In an embodiment, the first metal filling layer and the second metal filling layer include fluorine. In an embodiment, depositing the first fluorine barrier layer and the second fluorine barrier layer includes depositing a fluorine-free metal layer.

[0061] According to some embodiments of the present disclosure, an integrated circuit device includes a first transistor and a second transistor. The first transistor includes: a first work function layer; a first cap layer located above the first work function layer; a first fluorine barrier layer located above the first cap layer; and a first metal-filled region located above the first fluorine barrier layer, wherein the first metal-filled region includes fluorine. The second transistor includes: a second work function layer; a second cap layer located above the second work function layer; and a second metal-filled region located above the second cap layer and in contact with the second cap layer, wherein the second metal-filled region includes fluorine. In an embodiment, the first cap layer and the second cap layer are formed of the same material, and the first metal-filled region and the second metal-filled region are formed of the same material. In an embodiment, the first fluorine barrier layer does not contain fluorine, and the first fluorine barrier layer includes tungsten, cobalt, or molybdenum. In an embodiment, the thickness of the first fluorine barrier layer is greater than about In an embodiment, the first metal-filled region and the second metal-filled region include fluorine. In an embodiment, the second capping layer includes TiN.

[0062] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments or examples introduced herein and / or achieve the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0063] Example 1 is a method for forming an integrated circuit device, comprising: removing a dummy gate stack to form a first groove between a first gate spacer and a second groove between a second gate spacer, wherein the first gate spacer and the second gate spacer are respectively located in a short channel device region and a long channel device region; forming a first work function layer extending into the first groove and a second work function layer extending into the second groove; forming a first fluorine barrier layer above the first work function layer, wherein the first fluorine barrier layer is formed of a fluorine barrier material; forming a first fluorine-containing metal layer above the first work function layer, wherein the first fluorine-containing metal layer is formed of a fluorine-containing material; and forming a second fluorine-containing metal layer above the second work function layer, wherein there is no fluorine barrier material between the second fluorine-containing metal layer and the second work function layer, or there is a second fluorine barrier layer, wherein the thickness of the second fluorine barrier layer is less than the thickness of the first fluorine barrier layer.

[0064] Example 2 is the method described in Example 1, further comprising: forming the fluorine barrier material above the second work function layer in the same process used to form the first fluorine barrier layer; and removing the fluorine barrier material from the long channel device region before forming the second fluorine-containing metal layer.

[0065] Example 3 is the method described in Example 1, further comprising: forming a first sub-fluorine barrier layer, the first sub-fluorine barrier layer comprising a first portion overlapping the first work function layer and a second portion overlapping the second work function layer; removing the second portion of the first sub-fluorine barrier layer without removing the first portion of the first sub-fluorine barrier layer; and forming a second sub-fluorine barrier layer, the second sub-fluorine barrier layer comprising a first portion overlapping the first work function layer and a second portion overlapping the second work function layer, wherein the first portion of the first sub-fluorine barrier layer and the first portion of the second sub-fluorine barrier layer are combined to form the first fluorine barrier layer, and the second portion of the second sub-fluorine barrier layer forms the second fluorine barrier layer.

[0066] Example 4 is the method described in Example 1, wherein forming the first fluorine-containing metal layer includes depositing a fluorine-free metal layer.

[0067] Example 5 is the method of Example 4, wherein the fluorine-free metal layer includes tungsten, cobalt, or molybdenum.

[0068] Example 6 is the method described in Example 1, wherein forming the first fluorine barrier layer includes depositing a silicon nitride layer, a silicon oxide layer, or an aluminum-based oxide layer.

[0069] Example 7 is the method described in Example 1, wherein forming the second fluorine-containing metal layer includes: depositing a nucleation layer; and depositing a metal-filled region, wherein the nucleation layer and the metal-filled region include fluorine.

[0070] Example 8 is a method for forming an integrated circuit device, comprising: depositing a first work function layer and a second work function layer in a first device region and a second device region, respectively; depositing a first fluorine barrier layer and a second fluorine barrier layer in the first device region and the second device region, respectively, wherein the first fluorine barrier layer is located above the first work function layer, and the second fluorine barrier layer is located above the second work function layer; removing the second fluorine barrier layer; and forming a first metal filling layer above the first fluorine barrier layer, and forming a second metal filling layer above the second work function layer.

[0071] Example 9 is the method described in Example 8, wherein the first work function layer is part of a first gate in a first transistor having a first channel length, and the second work function layer is part of a second gate in a second transistor having a second channel length, and the first channel length is shorter than the second channel length.

[0072] Example 10 is the method of Example 8, wherein the first work function layer and the second work function layer are formed in the same deposition process.

[0073] Example 11 is the method of Example 8, wherein the first fluorine barrier layer and the second fluorine barrier layer are formed in the same deposition process.

[0074] Example 12 is the method described in Example 8, further comprising: depositing a third fluorine barrier layer and a fourth fluorine barrier layer in the first device region and the second device region, respectively, wherein the third fluorine barrier layer is located above the first fluorine barrier layer.

[0075] Example 13 is the method of Example 8, wherein the first metal fill layer and the second metal fill layer include fluorine.

[0076] Example 14 is the method of Example 8, wherein depositing the first fluorine barrier layer and the second fluorine barrier layer includes depositing a fluorine-free metal layer.

[0077] Example 15 is an integrated circuit device, comprising: a first transistor, comprising: a first work function layer; a first cap layer, located above the first work function layer; a first fluorine barrier layer, located above the cap layer; and a first metal filling region, located above the first fluorine barrier layer, wherein the first metal filling region includes fluorine; and a second transistor, comprising: a second work function layer; a second cap layer, located above the second work function layer; and a second metal filling region, located above the second cap layer and in contact with the second cap layer, wherein the second metal filling region includes fluorine.

[0078] Example 16 is the integrated circuit device of Example 15, wherein the first capping layer and the second capping layer are formed of the same material, and the first metal-filled region and the second metal-filled region are formed of the same material.

[0079] Example 17 is the integrated circuit device of Example 15, wherein the first fluorine barrier layer does not contain fluorine, and the first fluorine barrier layer includes tungsten, cobalt, or molybdenum.

[0080] Example 18 is the integrated circuit device of Example 15, wherein the thickness of the first fluorine barrier layer is greater than about

[0081] Example 19 is the integrated circuit device of Example 15, wherein the first metal-filled region and the second metal-filled region include fluorine.

[0082] Example 20 is the integrated circuit device of Example 15, wherein the second capping layer comprises TiN.

Claims

1. A method for forming an integrated circuit device, comprising: removing the dummy gate stack to form a first groove between the first gate spacers and a second groove between the second gate spacers, wherein the first gate spacers and the second gate spacers are located in the short channel device region and the long channel device region, respectively; forming a first work function layer extending into the first groove and a second work function layer extending into the second groove; forming a first fluorine barrier layer over the first work function layer, wherein the first fluorine barrier layer is formed of a fluorine barrier material; forming a first fluorine-containing metal layer over the first fluorine barrier layer, wherein the first fluorine-containing metal layer is formed of a fluorine-containing material; and A second fluorine-containing metal layer is formed above the second work function layer, wherein there is no fluorine barrier material or there is a second fluorine barrier layer between the second fluorine-containing metal layer and the second work function layer, wherein the thickness of the second fluorine barrier layer is less than that of the first fluorine barrier layer.

2. The method according to claim 1, further comprising: forming the fluorine barrier material over the second work function layer in the same process used to form the first fluorine barrier layer; as well as Prior to forming the second fluorine-containing metal layer, the fluorine blocking material is removed from the long channel device region.

3. The method according to claim 1, further comprising: forming a first sub-fluorine barrier layer, the first sub-fluorine barrier layer comprising a first portion overlapping the first work function layer and a second portion overlapping the second work function layer; removing a second portion of the first sub-fluorine barrier layer without removing a first portion of the first sub-fluorine barrier layer; as well as A second sub-fluorine barrier layer is formed, the second sub-fluorine barrier layer comprising a first portion overlapping the first work function layer and a second portion overlapping the second work function layer, wherein the first portion of the first sub-fluorine barrier layer and the first portion of the second sub-fluorine barrier layer are combined to form the first fluorine barrier layer, and the second portion of the second sub-fluorine barrier layer forms the second fluorine barrier layer.

4. The method according to claim 1, wherein: Forming the first fluorine-containing metal layer includes: depositing a fluorine-free metal layer.

5. The method according to claim 4, wherein: The fluorine-free metal layer includes tungsten, cobalt or molybdenum.

6. The method according to claim 1, wherein: Forming the first fluorine barrier layer includes depositing a silicon nitride layer, a silicon oxide layer, or an aluminum-based oxide layer.

7. The method according to claim 1, wherein: Forming the second fluorine-containing metal layer comprises: depositing a nucleation layer; and A metal fill region is deposited, wherein the nucleation layer and the metal fill region include fluorine.

8. A method of forming an integrated circuit device, comprising: Depositing a first work function layer and a second work function layer in the first device region and the second device region, respectively; Depositing a first fluorine barrier layer and a second fluorine barrier layer in the first device region and the second device region, respectively, wherein the first fluorine barrier layer is located above the first work function layer, and the second fluorine barrier layer is located above the second work function layer; removing the second fluorine barrier layer; and forming a first metal filling layer on the first fluorine barrier layer, and forming a second metal filling layer on the second work function layer, The first work function layer is part of a first gate in a first transistor having a first channel length, and the second work function layer is part of a second gate in a second transistor having a second channel length, and the first channel length is shorter than the second channel length.

9. The method according to claim 8, wherein: The first work function layer and the second work function layer are formed in the same deposition process.

10. The method according to claim 8, wherein: The first fluorine barrier layer and the second fluorine barrier layer are formed in a same deposition process.

11. The method according to claim 8, further comprising: A third fluorine barrier layer and a fourth fluorine barrier layer are deposited in the first device region and the second device region, respectively, wherein the third fluorine barrier layer is located above the first fluorine barrier layer.

12. The method according to claim 8, wherein: The first metal filling layer and the second metal filling layer include fluorine.

13. The method according to claim 8, wherein: Depositing the first fluorine barrier layer and the second fluorine barrier layer includes depositing a fluorine-free metal layer.

14. An integrated circuit device comprising: A first transistor comprising: a first work function layer; A first capping layer, located above the first work function layer; A first fluorine barrier layer is located above the cap layer; and a first metal-filled region located above the first fluorine barrier layer, wherein the first metal-filled region includes fluorine; and A second transistor comprising: a second work function layer; A second capping layer, located above the second work function layer; and a second metal filling region located above the second capping layer and in contact with the second capping layer, wherein the second metal filling region comprises fluorine, There is no fluorine barrier material between the second metal filling region and the second cap layer, or there is a second fluorine barrier layer, wherein the thickness of the second fluorine barrier layer is less than the thickness of the first fluorine barrier layer.

15. The integrated circuit device according to claim 14, wherein: The first capping layer and the second capping layer are formed of a same material, and the first metal-filled region and the second metal-filled region are formed of a same material.

16. The integrated circuit device according to claim 14, wherein: The first fluorine barrier layer does not contain fluorine, and the first fluorine barrier layer includes tungsten, cobalt, or molybdenum.

17. The integrated circuit device according to claim 14, wherein: The thickness of the first fluorine barrier layer is greater than 18. The integrated circuit device according to claim 14, wherein: The first metal-filled region and the second metal-filled region include fluorine.

19. The integrated circuit device according to claim 14, wherein: The second capping layer includes TiN.

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