Method, apparatus and system for providing a hardware implementation of a quasi-cyclic syndrome decoder

Abstract

The present invention discloses an apparatus, system and method for providing a hardware implementation of a quasi-cyclic syndrome decoder. An exemplary method for reducing the complexity of the decoder includes: receiving a noise codeword based on a transmitted codeword generated from a quasi-cyclic linear code; calculating a plurality of syndromes based on the noise codeword; selecting a first syndrome from the plurality of syndromes; generating a memory cell address according to the first syndrome; reading a coset leader corresponding to the first syndrome based on the memory cell address; and determining a candidate version of the transmitted codeword based on the noise codeword and the coset leader.

Description

Technical Field

[0001] The patent document relates generally to a non-volatile memory device, and more particularly to error correction in a non-volatile memory device. Background Art

[0002] The integrity of data is an important characteristic of any data storage device and data transfer.The use of strong error correction codes (ECC) is recommended for various types of data storage devices including NAND flash memory devices.

[0003] Solid-state drives (SSDs) use multi-layer NAND flash memory devices for persistent storage. However, multi-layer NAND flash memory devices are inherently unreliable and typically require ECC to significantly improve data reliability at the expense of additional storage space for ECC parity bits. Therefore, there is a need for ECC to provide robust and reliable data protection with a low-complexity hardware implementation. Summary of the invention

[0004] Embodiments of the disclosed technology are directed to a method, apparatus, and system for providing a low-complexity hardware implementation of a quasi-cyclic syndrome decoder.

[0005] In an example aspect, a method of reducing complexity of a decoder includes: receiving a noise codeword based on a transmitted codeword generated from a quasi-cyclic linear code; calculating a plurality of syndromes based on the noise codeword; selecting a first syndrome from the plurality of syndromes; generating a memory cell address according to the first syndrome; based on the memory cell address, reading a coset leader corresponding to the first syndrome; and determining a candidate version of the transmitted codeword based on the noise codeword and the coset leader.

[0006] In another example aspect, the above method may be implemented by a video encoder device or a video decoder device including a processor.

[0007] In yet another example aspect, the methods may be implemented in the form of processor executable instructions and stored on a computer readable program medium.

[0008] The subject matter described in this patent document may be implemented in a specific manner by providing one or more of the following features. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a memory system is shown.

[0010] Figure 2 is a diagram of an exemplary nonvolatile memory device.

[0011] Figure 3 is a diagram showing the cell voltage level distribution (V th )

[0012] Figure 4 is a diagram showing the cell voltage level distribution (V th ) is another example diagram.

[0013] Figure 5 2 is a graph showing the cell voltage level distribution (V th )

[0014] Figure 6 2 is a diagram showing the cell voltage level distribution (V th )

[0015] Figure 7 is a block diagram of an exemplary quasi-cyclic code syndrome based decoder.

[0016] Figure 8 A flow chart illustrating another example method for reducing delay of a quasi-cyclic linear code decoder. DETAILED DESCRIPTION

[0017] Flash memory is very common in portable electronic devices such as computers, digital cameras, digital music players, cellular phones, personal data assistants (PDAs), etc. These host devices communicate with the flash memory using a flash translation layer (FTL), which is a table used to divert the address of any host request (called a logical block address (LBA)) to the actual location (called a physical block address (PBA)) where the corresponding data is stored in the flash memory. The size of this table is usually large and is usually stored in dynamic random access memory (DRAM).

[0018] Typically, FTL performs at least the following functions:

[0019] ○ Write the updated information to a new empty page and convert all subsequent requests to its new address;

[0020] ○Use available pages uniformly to maintain wear leveling;

[0021] ○ Efficiently perform garbage collection operations on all used blocks.

[0022] Figures 1 to 6 A non-volatile memory system is outlined in which embodiments of the disclosed technology may be implemented.

[0023] Figure 11 is a block diagram of an example of a memory system 100 implemented based on some embodiments of the disclosed technology. The memory system 100 includes a memory module 110, which can be used to store information used by other electronic devices or systems. The memory system 100 can be integrated into (e.g., located on a circuit board) other electronic devices and systems. Alternatively, the memory system 100 can be implemented as an external storage device such as a USB flash drive and a solid-state drive (SSD).

[0024] The memory module 110 included in the memory system 100 may include memory areas (e.g., memory arrays) 102, 104, 106, and 108. Each of the memory areas 102, 104, 106, and 108 may be included in a single memory die or multiple memory dies. The memory die may be included in an integrated circuit (IC) chip.

[0025] Each of the memory regions 102, 104, 106, and 108 includes a plurality of memory cells. Read, program, or erase operations may be performed based on memory units. Thus, each memory unit may include a predetermined number of memory cells. The memory cells in the memory regions 102, 104, 106, or 108 may be included in a single memory die or in multiple memory dies.

[0026] The memory cells in each of the memory regions 102, 104, 106, and 108 may be arranged in rows and columns in memory units. Each of the memory units may be a physical unit. For example, a group of multiple memory cells may form a memory unit. Each of the memory units may also be a logical unit. For example, a memory unit may be a bank, block, or page that may be identified by a unique address such as a bank address, a block address, and a page-based address. During a read or write operation, a unique address associated with a particular memory unit may be used to access the particular memory unit. Based on the unique address, information may be written to or retrieved from one or more memory cells in the particular memory unit.

[0027] The memory cells in memory regions 102, 104, 106, and 108 may include nonvolatile memory cells. Examples of nonvolatile memory cells include flash memory cells, phase change memory (PRAM) cells, magnetoresistive random access memory (MRAM) cells, or other types of nonvolatile memory cells. In example embodiments where the memory cells are configured as NAND flash memory cells, read or write operations may be performed on a page basis. However, erase operations in NAND flash memory are performed on a block basis.

[0028] Each of the non-volatile memory cells may be configured as a single-level cell (SLC) or a multi-level memory cell. A single-level cell may store one bit of information per cell. A multi-level memory cell may store more than one bit of information per cell. For example, each of the memory cells in the memory regions 102, 104, 106, and 108 may be configured as a multi-level cell (MLC) storing two bits of information per cell, a triple-level cell (TLC) storing three bits of information per cell, and a quad-level cell (QLC) storing four bits of information per cell. In another example, each of the memory cells in the memory region may be configured to store at least one bit of information (e.g., one bit of information or multiple bits of information), and each of the memory cells in the memory region may be configured to store more than one bit of information.

[0029] like Figure 1 As shown, the memory system 100 includes a controller module 120. The controller module 120 includes: a memory interface 121, which communicates with the memory module 110; a host interface 126, which communicates with the host (not shown); a processor 124, which runs the firmware layer code; and a system memory 122 and a buffer / cache 123, which temporarily or permanently stores executable firmware / instructions and related information. In some embodiments, the controller module 120 may include an error correction engine 125 to perform error correction operations on the information stored in the memory module 110. The error correction engine 125 can be configured to detect / correct single bit errors or multiple bit errors. In another embodiment, the error correction engine 125 can be located in the memory module 110.

[0030] The host may be a device or system including one or more processors for retrieving data from the memory system 100 or storing or writing data to the memory system 100. In some embodiments, examples of the host may include a personal computer (PC), a portable digital device, a digital camera, a digital multimedia player, a television, and a wireless communication device.

[0031] In some embodiments, the controller module 120 may further include a host interface 126 for communicating with a host. The host interface 126 may include a component that complies with at least one of the host interface specifications, including but not limited to Serial Advanced Technology Attachment (SATA), Serial Small Computer System Interface (SAS), and Peripheral Component Interconnect Express (PCIe).

[0032] Figure 2 An example of a memory cell array implemented based on some embodiments of the disclosed technology is shown.

[0033] In some embodiments, the memory cell array may include a NAND flash memory array divided into a number of blocks, and each block contains a certain number of pages. Each block includes a plurality of memory cell strings, and each memory cell string includes a plurality of memory cells.

[0034] In some embodiments where the memory cell array is a NAND flash memory array, read and write (programming) operations are performed on a page basis, and erase operations are performed on a block basis. Before performing a programming operation on any page included in a block, all memory cells in the same block must be erased simultaneously. In an embodiment, the NAND flash memory may use an even / odd bit line structure. In another embodiment, the NAND flash memory may use an all-bit line structure. In the even / odd bit line structure, even and odd bit lines are interlaced along each word line and are accessed alternately, so that each pair of even and odd bit lines can share peripheral circuits such as page buffers. In the all-bit line structure, all bit lines can be accessed simultaneously.

[0035] Figure 3 An example of a threshold voltage distribution curve in a multi-level cell device is shown, where the number of cells for each program / erase state is plotted as a function of threshold voltage. As shown therein, the threshold voltage distribution curve includes an erased state (denoted as "ER" and corresponding to "11") having the lowest threshold voltage and three program states (denoted as "P1," "P2," and "P3," and corresponding to "01," "00," and "10," respectively) having read voltages (denoted by dashed lines) between the states. In some embodiments, each of the threshold voltage distributions for the program / erase states has a finite width due to differences in the material properties of the memory array.

[0036] When writing more than one data bit into a memory cell, the threshold voltage levels of the memory cells need to be carefully arranged because the distance between adjacent distributions decreases. This is achieved by using incremental step pulse programming (ISPP), that is, using a program verification method, a ladder programming voltage is applied to the word line, and the memory cells on the same word line are repeatedly programmed. Each programming state is associated with a verification voltage used in the verification operation and sets the target position of each threshold voltage distribution window.

[0037] Distorted or overlapping threshold voltage distributions may cause read errors. The ideal memory cell threshold voltage distribution may be severely distorted or overlapped due to, for example, program and erase (P / E) cycles, cell-to-cell interference, and data retention errors discussed below, and such read errors can be managed in most cases by using error correction codes (ECC).

[0038] Figure 4An example of an ideal threshold voltage distribution curve 410 and an example of a distorted threshold voltage distribution curve 420 are shown. The vertical axis represents the number of memory cells having a particular threshold voltage on the horizontal axis.

[0039] For n-bit multi-level cell NAND flash memory, the threshold voltage of each cell can be programmed to 2 n In an ideal multi-level cell NAND flash memory, each value corresponds to a non-overlapping threshold voltage window.

[0040] Flash memory P / E cycles damage the tunnel oxide of the floating gate of the charge trapping layer of the cell transistor, causing the threshold voltage to shift, which gradually reduces the noise margin of the memory device. As the number of P / E cycles increases, the margin between adjacent distributions of different programming states decreases, and eventually the distributions begin to overlap. The data bits stored in the memory cells with threshold voltages programmed within the overlapping range of adjacent distributions may be misinterpreted as values ​​other than the original target value.

[0041] Figure 5 An example of inter-cell interference in a NAND flash memory is shown. Inter-cell interference may also cause distortion of the threshold voltage of a flash memory cell. The threshold voltage shift of one memory cell transistor can affect the threshold voltage of its adjacent memory cell transistor through the parasitic capacitance coupling effect between the interfering cell and the victim cell. The amount of inter-cell interference may be affected by the bit line structure of the NAND flash memory. In an even / odd bit line structure, memory cells on one word line are alternately connected to even and odd bit lines, and even cells are programmed before odd cells in the same word line. Therefore, even cells and odd cells are subject to different amounts of inter-cell interference. Cells in a full bit line structure are subject to less inter-cell interference than even cells in an even / odd bit line structure, and the full bit line structure can effectively support high-speed current sensing to increase memory read and verification speeds.

[0042] Figure 5 The dashed line in represents the nominal distribution of the P / E state of the cell under consideration (before program disturb), and the “neighboring state value” represents the value to which the neighboring state has been programmed. Figure 5 As shown, if the adjacent state is programmed to P1, the threshold voltage distribution of the considered cell shifts by a certain amount. However, if the adjacent state is programmed to P2, which has a higher threshold voltage than P1, a larger shift will result compared to the adjacent state being P1. Similarly, when the adjacent state is programmed to P3, the shift in the threshold voltage distribution is the largest.

[0043] Figure 6An example of retention errors in NAND flash memory is shown by comparing a normal threshold voltage distribution and an offset threshold voltage distribution. Over time, data stored in NAND flash memory is susceptible to corruption, which is called a data retention error. Retention errors are caused by the loss of charge stored in the floating gate or charge trap layer of the cell transistor. Memory cells with more program-erase cycles are more likely to experience retention errors due to the loss of the floating gate or charge trap layer. Figure 6 In the example of , comparing the voltage distribution of the upper row (before damage) and the distribution of the lower row (damaged by retention errors) shows a leftward shift.

[0044] Figures 4 to 6 The distortion and interference effects described in can occur in the DRAM that stores the FTL, and in most cases, the majority of the ECC workload is used to correct arbitrary errors when reading data from the DRAM (e.g., FTL mapping from LBA to PBA).

[0045] Examples of ECC used in DRAM include binary linear codes, which are often denoted as (n,k) linear codes, where n is the codeword length and k is the row rank or number of rows in the generator matrix of the binary linear code. Some binary codes are quasi-cyclic codes, but there are no known efficient decoders for these quasi-cyclic linear codes.

[0046] In some embodiments, the standard decoding method used is syndrome decoding, which requires the storage of a larger table (standard array table) to store syndromes, error patterns, etc. The decoding via the standard array is a form of nearest neighbor decoding (also known as minimum distance decoding). Embodiments of the disclosed technology include efficient techniques for reducing the size of the standard array table, which advantageously reduces the implementation complexity of the quasi-cyclic linear code decoder in hardware, but does not significantly affect the latency of the decoding operation.

[0047] Quasi-cyclic codes are defined by the following property: for an integer n0, every codeword cyclically shifted by n0 positions is also a codeword. For a system of (n=mn0; k=mk0) quasi-cyclic linear codes, the corresponding parity check matrix H is expressed as:

[0048]

[0049] In this article, I n-k represents the (nk)×(nk) identity matrix, each C′ i，j are all m×m circulant matrices of the form:

[0050]

[0051] In some embodiments, the syndrome decoder for quasi-cyclic linear codes uses a standard array table, an example of which is shown in Table 1. The coset leader (e.g., i ) represents the correction factor (for example, s in Table 1 i ) is the most likely error mode corresponding to the received sequence, which is calculated based on the parity check matrix.

[0052] Table 1: Example of a standard array table

[0053]

[0054] An example decoding operation in a syndrome decoder includes first finding the received sequence r in the standard array table, and then assigning the top element in the column corresponding to r as the correct codeword. As previously mentioned, storing the entire standard array table typically results in large memory requirements.

[0055] In some embodiments, only the first two columns (syndrome and coset leader) of Table 1 are stored instead of storing the entire standard array table. Instead of finding r in the standard array table and selecting the top element in the column corresponding to r, the following decoding operation can be used to determine the correct codeword:

[0056] 1. Calculate the syndrome s' = H·r,

[0057] 2. Find the corresponding coset leader e', then

[0058] 3. Generate the most likely transmitted codeword in Represents a bitwise addition operation.

[0059] As mentioned above, for quasi-cyclic codes, there is a cyclic shift property between the syndrome and the corresponding coset leader. Therefore, for each syndrome and its corresponding coset leader, we use (s i ,e i ) indicates that there are m-1 other pairs of syndromes and coset leaders, represented by (s j ,e j ) means that they are (s i ,e i ). In some embodiments, this property is exploited to store only one of the shifted pairs, thereby reducing the size of the standard array table to 1 / m of the original. Since the cyclic shifts are shifted by a predetermined integer (e.g., n0 in the example discussed previously), storing only a single pair does not result in any ambiguity or lack of information, and the correct syndrome and coset leader can be determined.

[0060] An example of a syndrome-coset leader pair table that may be stored in memory to implement a lower complexity implementation of a syndrome decoder is shown in Table 2.

[0061] Table 2: Example of a syndrome-coset first pair table

[0062]

[0063]

[0064] Based on the error mode i The following properties store only the syndrome-coset leading pairs instead of the entire standard array table:

[0065]

[0066] In this paper, h j is the jth column of the parity check matrix H, and the syndrome s i is the sum of those columns of the parity check matrix corresponding to the "1" in the error pattern. The validity of the above property depends on the columns of the parity check matrix, which also have the cyclic shift property. Therefore, by storing only unique syndrome-coset leader (equivalently, syndrome-error) pairs instead of all syndrome-error pairs, the size of the standard array table can be reduced to 1 / m of the original size.

[0067] In some embodiments, by storing only the coset header in the memory cell i Instead of (s i ,e i ) can further reduce the size of the standard array table. The reduction of the table is based on the use of the syndrome s i To calculate the corresponding coset first e i In the example, the address of the memory cell (denoted as A) can be calculated based on the syndrome i ), for example, A i =f(s i ). Storing only the coset leaders instead of the pairs can reduce the size of the standard array table to 1 / 2 of its original size.

[0068] In some embodiments, the two techniques described can be used to advantageously reduce the size of the original standard array table to 1 / 2m of the original size. However, in this case, when only unique syndrome-error pairs are stored, the syndromes are no longer continuous and cannot be used directly as addresses, and as described above, a function of the syndrome is used as an address. In an example, the function is a hash function, and an open addressing technique can be implemented to handle any conflicts that may occur.

[0069] Figure 7 is a block diagram of an exemplary decoder based on quasi-cyclic code syndrome. Figure 7 As shown, the syndrome generator 710 uses the received n-bit noise codeword (in Figure 7 In [0, n-1]) to calculate the syndrome (S). For example, if the parity check matrix is ​​represented as H, the syndrome is calculated as:

[0070] S=H·(In[0,n-1]) T .

[0071] In some embodiments, and because the table has been compressed by exploiting the cyclic shift property of quasi-cyclic linear codes, the syndrome (S) is one of a plurality of calculated syndromes. Each of the plurality of calculated syndromes is a cyclic shift of one another. For example, the plurality of syndromes may be calculated in parallel. The calculation of the plurality of syndromes may be based on a decimal representation of the syndromes, and the selected syndrome (in Figure 7 denoted as Syn[0,nk]) is the syndrome with the smallest magnitude in decimal representation.

[0072] The (n-k+1)-bit syndrome (Syn[0,nk]) is input to an address generator 720, which generates an address and a shift amount. In some embodiments, the output address is generated based on a hash function, and the calculated shift amount is the maximum possible shift. In other embodiments, the hash function performs a modulus operation (with the memory size as the modulus) to generate the address. In an example, the hash function can be an MD-5 or SHA-3 hash function. In another example, a linear feedback shift register (LFSR) can be used to implement the hash function.

[0073] In this example, the compression table 730 implements the above two table reduction methods, resulting in a table size of 1 / (2m) of the original standard array table. Since not all coset leaders (and, accordingly, their syndromes) are stored in the compression table, circular shifts are used in both the address generator 720 and the error location calculation unit 740 to find the correct address and the correct error pattern, respectively.

[0074] The correct error pattern coset leader, the shift amount (generated by address generator 720 and based on the cyclic shift), and the received noise codeword (In[0,n-1]) are input to an error location calculator 740, which calculates the correct error pattern. In an example, the correct error pattern is determined based on the correct error pattern coset leader and the shift amount. The correct error pattern and the received noise codeword are used to output a candidate (or most likely) transmitted codeword (in Figure 7 In the example, it is represented as Out[0,k-1]).

[0075] Figure 8 A method for reducing the decoder (eg, Figure 78. The method 800 includes, in operation 810, receiving a noise codeword based on a transmitted codeword generated from a quasi-cyclic linear code.

[0076] The method 800 includes, at operation 820 , calculating a plurality of syndromes based on the noise codeword.

[0077] The method 800 includes, in operation 830 , selecting a first syndrome from a plurality of syndromes.

[0078] The method 800 includes, at operation 840 , generating a memory cell address according to a first syndrome.

[0079] The method 800 includes, at operation 850 , reading a coset leader corresponding to a first syndrome based on a memory cell address.

[0080] The method 800 includes, at operation 860, determining a candidate version of the transmitted codeword based on the noise codeword and the coset leader.

[0081] In some embodiments, multiple syndromes are calculated in parallel.

[0082] In some embodiments, the first syndrome is selected based on decimal representations of the plurality of syndromes, and the first syndrome has a smallest decimal representation associated with the shift.

[0083] In some embodiments, method 800 further includes the operations of: determining an error pattern based on the coset leader; and applying a shift to the error pattern to generate a shifted error pattern for determining a candidate version of the transmitted codeword.

[0084] In some embodiments, memory cell addresses are generated based on a hash function, and conflicts of the hash function are reduced based on an open addressing technique.

[0085] In some embodiments, the quasi-cyclic linear code is a quasi-cyclic linear code used in a flash translation layer (FTL), and the codeword is a mapping from a logical block address (LBA) to a physical block address (PBA).

[0086] In some embodiments, the memory cell address corresponds to a memory storing one or more coset leaders and excluding syndromes.

[0087] In some embodiments, each of the one or more coset leaders corresponds to a plurality of syndromes that are cyclic shifts of the syndrome paired with each of the one or more coset leaders.

[0088] The embodiments of the subject matter and functional operations described in this patent document can be implemented in various systems, digital electronic circuits or in computer software, firmware or hardware, including the structures disclosed in this specification and their structural equivalents or in a combination of one or more of them. The embodiments of the subject matter described in this specification can be implemented as one or more computer program products, that is, one or more modules of computer program instructions encoded on a tangible and non-transitory computer-readable medium to be executed by a data processing device or control the operation of the data processing device. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a material composition that affects a machine-readable propagation signal, or a combination of one or more of them. The term "data processing unit" or "data processing device" covers all devices, devices and machines for processing data, including, for example, a programmable processor, a computer or multiple processors or computers. In addition to hardware, the device may also include code that creates an execution environment for the computer program in question, for example, code that constitutes a processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0089] A computer program (also referred to as a program, software, software application, script, or code) may be written in any form of programming language (including compiled or interpreted languages) and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for a computing environment. A computer program does not necessarily correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or portions of code). A computer program may be deployed on one computer or executed on multiple computers located on one site or distributed on multiple sites and interconnected by a communications network.

[0090] The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by special purpose logic circuits, and the apparatus can also be implemented as special purpose logic circuits, such as an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0091] As an example, processors suitable for executing computer programs include general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Typically, the processor will receive instructions and data from a read-only memory or a random access memory or both. The basic elements of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include or be operably connected to one or more large-capacity storage devices for storing data, such as magnetic optical disks, magneto-optical disks, or optical disks, to receive data from or transmit data to or both. However, a computer does not have to have such devices. Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices. The processor and memory can be supplemented by or integrated into a dedicated logic circuit.

[0092] Although this patent document contains many details, these details should not be interpreted as limitations on any invention or the scope of what may be claimed, but rather as descriptions of features specific to particular embodiments of particular inventions. Certain features described in this patent document in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable subcombination. Furthermore, although features are described above as functioning in certain combinations, or even initially stated as such, in some cases one or more features may be deleted from the combination of claims, and the combination of claims may be directed to subcombinations or variations of subcombinations.

[0093] Similarly, although operations are described in a particular order in the drawings, this should not be understood as requiring that such operations be performed in the particular order shown or in a sequential order, or that all of the illustrated operations be performed to achieve the desired results. Furthermore, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.

[0094] Only a few embodiments and examples are described, and other implementations, enhancements, and variations may be made based on what is described and illustrated in this patent document.

Claims

1. A method for reducing the complexity of a decoder, comprising: receiving a noise codeword based on the transmitted codeword generated from a quasi-cyclic linear code; Calculating a plurality of syndromes based on the noise codeword; selecting a first syndrome from the plurality of syndromes; generating a memory cell address based on the first syndrome, wherein the memory cell address corresponds to a memory cell storing one or more coset leaders and excluding the syndrome; Based on the memory cell address, reading a coset leader stored in the memory cell accessed using the memory cell address, the coset leader corresponding to the first syndrome; and A candidate version of the transmitted codeword is determined based on the noise codeword and the coset leader. The method according to claim 1 , wherein the plurality of syndromes are calculated in parallel.

3. The method of claim 1, wherein the first syndrome is selected based on decimal representations of the plurality of syndromes, and wherein the first syndrome has a smallest decimal representation associated with a shift.

4. The method according to claim 3, further comprising: determining an error mode based on the coset leader; and The shift is applied to the error pattern to generate a shifted error pattern, the shifted error pattern is used to determine the candidate version of the transmitted codeword. 5 . The method of claim 1 , wherein the memory cell address is generated based on a hash function, and wherein collisions of the hash function are reduced based on an open addressing technique.

6. The method of claim 1 , wherein the quasi-cyclic linear code is a quasi-cyclic linear code used in a flash translation layer, i.e., FTL, and wherein the transmitted codeword is a mapping from a logical block address, i.e., LBA, to a physical block address, i.e., PBA.

7. The method of claim 1, wherein each of the one or more coset leaders corresponds to a plurality of syndromes, the plurality of syndromes being cyclic shifts of a syndrome paired with each of the one or more coset leaders.

8. A device for reducing the complexity of a decoder, the device comprising: at least one processor; as well as a non-transitory memory storing thereon instructions that, when executed by the at least one processor, cause the at least one processor to: receiving a noise codeword based on the transmitted codeword generated from a quasi-cyclic linear code; Calculating a plurality of syndromes based on the noise codeword; selecting a first syndrome from the plurality of syndromes; generating a memory cell address based on the first syndrome, wherein the memory cell address corresponds to a memory cell storing one or more coset leaders and excluding the syndrome; Based on the memory cell address, reading a coset leader stored in the memory cell accessed using the memory cell address, the coset leader corresponding to the first syndrome; and Based on the noise codeword and the coset leader, a candidate version of the transmitted codeword is determined.

9. The apparatus of claim 8, wherein the plurality of syndromes are calculated in parallel.

10. The apparatus of claim 8, wherein the first syndrome is selected based on decimal representations of the plurality of syndromes, and wherein the first syndrome has a smallest decimal representation associated with a shift.

11. The apparatus of claim 10, wherein when executed by the at least one processor, the instructions further cause the at least one processor to: Based on the coset leader, determining an error mode; and The shift is applied to the error pattern to generate a shifted error pattern, the shifted error pattern is used to determine the candidate version of the transmitted codeword.

12. The apparatus of claim 8, wherein the memory unit address is generated based on a hash function, and wherein collisions of the hash function are reduced based on an open addressing technique.

13. The apparatus of claim 12, wherein the hash function is implemented based on a Linear Feedback Shift Register (LFSR).

14. The apparatus of claim 8, wherein each of the one or more coset leaders corresponds to a plurality of syndromes, the plurality of syndromes being cyclic shifts of a syndrome paired with each of the one or more coset leaders.

15. A non-transitory computer-readable storage medium storing thereon instructions which, when executed by a processor, cause the processor to implement a method for reducing the complexity of a decoder, the instructions comprising: instructions for receiving a noise codeword based on the transmitted codeword generated from a quasi-cyclic linear code; instructions for calculating a plurality of syndromes based on the noise codeword; instructions for selecting a first syndrome from the plurality of syndromes; instructions for generating a memory cell address based on the first syndrome, wherein the memory cell address corresponds to a memory cell storing one or more coset leaders and excluding syndromes; for reading, based on the memory cell address, a coset head stored in the memory cell accessed using the memory cell address, the coset head corresponding to the first syndrome; as well as Instructions for determining a candidate version of the transmitted codeword based on the noisy codeword and the coset leader.

16. The non-transitory computer-readable storage medium of claim 15, wherein the memory unit address is generated based on a hash function, and wherein collisions of the hash function are reduced based on an open addressing technique.

17. The non-transitory computer-readable storage medium of claim 15, wherein each of the one or more coset leaders corresponds to a plurality of syndromes that are cyclic shifts of a syndrome paired with each of the one or more coset leaders.

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