Methods for manufacturing semiconductor devices and semiconductor devices

Abstract

The semiconductor device includes a gate structure disposed above a channel region, a source / drain epitaxial layer disposed in a source / drain region, a nitrogen-containing layer disposed on the source / drain epitaxial layer, a silicide layer disposed on the nitrogen-containing layer, and a conductive contact disposed on the silicide layer. Embodiments of the present invention also relate to a method of manufacturing a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention relate to methods for manufacturing semiconductor devices and semiconductor devices. Background Technology

[0002] This invention relates to semiconductor integrated circuits, and more particularly to semiconductor devices having epitaxial source / drain (S / D) structures. As the semiconductor industry moves toward nanotechnology process nodes in pursuit of higher performance and lower costs, challenges from manufacturing and design issues have led to the development of three-dimensional designs such as FinFETs and the use of metal gate structures with high-k (dielectric constant) materials. Summary of the Invention

[0003] Some embodiments of the present invention provide a method for manufacturing a semiconductor device, the method comprising: forming an epitaxial source / drain structure at a source / drain region disposed above a substrate; forming a nitrogen-containing layer on or in the surface of the epitaxial source / drain structure; forming a metal layer above the nitrogen-containing layer; and an alloy layer above the source / drain region and forming the elements of the epitaxial source / drain structure based on the elements of the metal layer.

[0004] Other embodiments of the present invention provide a method for manufacturing a semiconductor device, the method comprising: forming an epitaxial source / drain structure at a source / drain region disposed above a substrate; performing a first implantation operation to introduce a first ion into the epitaxial source / drain structure; performing a second implantation operation to introduce a second ion different from the first ion into the epitaxial source / drain structure; performing a first annealing operation; forming a nitrogen-containing layer on or in the surface of the epitaxial source / drain structure; forming a metal layer above the nitrogen-containing layer; and an alloy layer above the source / drain region and based on the elements of the metal layer forming the elements of the epitaxial source / drain structure.

[0005] Some embodiments of the present invention provide a semiconductor device, including: a gate structure disposed above a channel region; a source / drain epitaxial layer located in the source / drain region; a nitrogen-containing layer disposed on the source / drain epitaxial layer; a silicide layer disposed on the nitrogen-containing layer; and a conductive contact disposed on the silicide layer. Attached Figure Description

[0006] The invention is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A cross-sectional view of one of the various stages of a semiconductor device manufacturing operation according to an embodiment of the present invention is shown.

[0008] Figure 2 A cross-sectional view of one of the various stages of a semiconductor device manufacturing operation according to an embodiment of the present invention is shown.

[0009] Figure 3 A cross-sectional view of one of the various stages of a semiconductor device manufacturing operation according to an embodiment of the present invention is shown.

[0010] Figure 4 A cross-sectional view of one of the various stages of a semiconductor device manufacturing operation according to an embodiment of the present invention is shown.

[0011] Figure 5A , Figure 5B and Figure 5C A view is shown of one of the various stages of a semiconductor device manufacturing operation according to an embodiment of the present invention.

[0012] Figure 6 A cross-sectional view of one of the various stages of a semiconductor device manufacturing operation according to an embodiment of the present invention is shown.

[0013] Figure 7 A cross-sectional view of one of the various stages of a semiconductor device manufacturing operation according to an embodiment of the present invention is shown.

[0014] Figure 8 A cross-sectional view of one of the various stages of a semiconductor device manufacturing operation according to an embodiment of the present invention is shown.

[0015] Figure 9 A cross-sectional view of one of the various stages of a semiconductor device manufacturing operation according to an embodiment of the present invention is shown.

[0016] Figure 10 A cross-sectional view of one of the various stages of a semiconductor device manufacturing operation according to an embodiment of the present invention is shown.

[0017] Figure 11 A cross-sectional view of one of the various stages of a semiconductor device manufacturing operation according to an embodiment of the present invention is shown.

[0018] Figure 12 A cross-sectional view of one of the various stages of a semiconductor device manufacturing operation according to an embodiment of the present invention is shown.

[0019] Figure 13 A cross-sectional view of one of the various stages of a semiconductor device manufacturing operation according to an embodiment of the present invention is shown.

[0020] Figure 14 A cross-sectional view of one of the various stages of a semiconductor device manufacturing operation according to an embodiment of the present invention is shown.

[0021] Figure 15 A cross-sectional view of one of the various stages of a semiconductor device manufacturing operation according to an embodiment of the present invention is shown.

[0022] Figure 16 A cross-sectional view of one of the various stages of a semiconductor device manufacturing operation according to an embodiment of the present invention is shown.

[0023] Figure 17 A cross-sectional view of one of the various stages of a semiconductor device manufacturing operation according to an embodiment of the present invention is shown.

[0024] Figure 18 and Figure 19 Cross-sectional views of various stages of a semiconductor device manufacturing operation according to an embodiment of the present invention are shown.

[0025] Figure 20 and Figure 21 Cross-sectional views of various stages of a semiconductor device manufacturing operation according to an embodiment of the present invention are shown.

[0026] Figure 22 and Figure 23 Cross-sectional views of various stages of a semiconductor device manufacturing operation according to an embodiment of the present invention are shown.

[0027] Figure 24A , Figure 24B , Figure 24C , Figure 24D , Figure 24E , Figure 24F , Figure 24G and Figure 24H A cross-sectional view of a semiconductor device according to an embodiment of the present invention is shown.

[0028] Figure 25 The results of measurements of various samples using a Fourier transform infrared spectrometer (FTIR) according to an embodiment of the present invention are shown.

[0029] Figure 26 The results of depth-direction elemental analysis according to an embodiment of the present invention are shown.

[0030] Figure 27 A comparison of elemental analysis results according to an embodiment of the present invention is shown.

[0031] Figure 28 and Figure 29A cross-sectional view of a semiconductor device according to an embodiment of the present invention is shown.

[0032] Figure 30 and Figure 31 A cross-sectional view of a semiconductor device according to an embodiment of the present invention is shown. Detailed Implementation

[0033] It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or desired characteristics of the device. Furthermore, in the following description, forming a first component on or above a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. For simplicity and clarity, the various components may be drawn at any scale. In the drawings, some layers / components may be omitted for simplicity.

[0034] Furthermore, for ease of description, spaced relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another (or other) element or component as shown in the figures. In addition to the orientations shown in the figures, spaced relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spaced relative descriptors used herein can be interpreted accordingly. Additionally, the term “made of” may mean “comprising” or “consisting of.” Furthermore, one or more additional operations may occur during / between the described operations in subsequent manufacturing processes, and the order of operations may change. In this invention, the phrase “one of A, B, and C” means “A, B, and / or C” (A, B, C, A and B, A and C, B and C, or A, B, and C), and does not mean an element from A, an element from B, and an element from C, unless otherwise stated. The same or similar materials, configurations, dimensions, processes and / or operations as described in one embodiment may be used in other embodiments, and detailed descriptions may be omitted.

[0035] The disclosed embodiments relate to semiconductor devices and methods of fabrication thereof, specifically to source / drain contact region structures for field-effect transistors (FETs) with reduced vertical contact resistance. Embodiments such as those disclosed herein are generally applicable not only to FinFETs but also to other FETs. Reducing contact resistance in a small contact area is a significant challenge for smaller three-dimensional structures. Inserting an ultrathin interlayer between the metal and semiconductor is a promising method for reducing contact resistance in order to lower the Schottky barrier height (SBH).

[0036] Figures 1 to 17 Cross-sectional views of various stages in the fabrication of a FinFET device according to an embodiment of the present invention are shown. It should be understood that... Figures 1 to 17 Additional operations are provided before, during, and after the process shown, and some of the operations described below may be replaced or eliminated in other embodiments of the method. The order of operations / processes may be interchanged.

[0037] FinFET fin structures can be patterned using any suitable method. For example, fin structures can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, spacing smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern fin structures. Multi-patterning processes, combining photolithography and self-alignment processes, typically form pairs of fin structures.

[0038] In some embodiments, a mask layer 15 is formed over a substrate 10 to fabricate the fin structure. The mask layer 15 is formed, for example, by a thermal oxidation process and / or a chemical vapor deposition (CVD) process. The substrate 10 is, for example, characterized by an impurity concentration ranging from about 1 × 10⁻⁶. 15 cm -3 To approximately 1×10 16 cm -3 The substrate is a p-type silicon or germanium substrate within the specified range. In other embodiments, the substrate has an impurity concentration ranging from about 1 × 10⁻⁶. 15 cm -3 To approximately 1×10 16 cm -3 n-type silicon or germanium substrates within the range.

[0039] Optionally, substrate 10 may include another elemental semiconductor, such as germanium; compound semiconductors, including group IV-IV compound semiconductors (such as SiC and SiGe), group III-V compound semiconductors (such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP); or combinations thereof. In one embodiment, substrate 10 is a silicon layer of an SOI (silicon-on-insulator) substrate. When using an SOI substrate, the fin structure may protrude from the silicon layer of the SOI substrate or from the insulating layer of the SOI substrate. In the latter case, the silicon layer of the SOI substrate is used to form the fin structure. Amorphous substrates such as amorphous Si or amorphous SiC, or insulating materials such as silicon oxide, may also be used as substrate 10. Substrate 10 may include various regions that have been suitably doped with impurities (e.g., p-type or n-type conductivity).

[0040] In some embodiments, the mask layer 15 includes, for example, a pad oxide (e.g., silicon oxide) layer 15A and a silicon nitride mask layer 15B. The pad oxide layer 15A can be formed using thermal oxidation or CVD processes. The silicon nitride mask layer 15B can be formed using physical vapor deposition (PVD) (such as sputtering methods), CVD, plasma-enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low-pressure CVD (LPCVD), high-density plasma CVD (HDPCVD), atomic layer deposition (ALD), and / or other processes.

[0041] In some embodiments, the thickness of the pad oxide layer 15A is in the range of about 2 nm to about 15 nm, and the thickness of the silicon nitride mask layer 15B is in the range of about 2 nm to about 50 nm. A mask pattern is further formed over the mask layer. The mask pattern is, for example, a resist pattern formed by a photolithography operation.

[0042] A hard mask pattern 15 is formed by using a mask pattern as an etching mask to create a pad oxide layer and a silicon nitride mask layer, as shown below. Figure 1 As shown.

[0043] Then, as Figure 2 As shown, the substrate 10 is patterned into fin structure 20 by using a hard mask pattern 15 as an etching mask and by trench etching using a dry etching method and / or a wet etching method.

[0044] exist Figure 2In this embodiment, three fin structures 20 are disposed above the substrate 10. However, the number of fin structures is not limited to three. The number can be as small as one or more than three. In some embodiments, the number of fin structures ranges from 5 to 1000, and they are connected via source / drain epitaxial layers formed in subsequent operations. In other embodiments, the number of fin structures ranges from 5 to 100, and they are connected via source / drain epitaxial layers formed in subsequent operations. In some embodiments, the number of fin structures ranges from 5 to 20, and they are connected via source / drain epitaxial layers formed in subsequent operations. Additionally, one or more pseudo-fin structures may be disposed near both sides of the fin structure 20 to improve pattern fidelity during the patterning process.

[0045] The fin structure 20 can be made of the same material as the substrate 10 and can extend continuously from the substrate 10. In this embodiment, the fin structure is made of Si. The silicon layer of the fin structure 20 can be intrinsic or can be suitably doped with n-type or p-type impurities.

[0046] The width W1 of the fin structure 20 is in the range of about 5 nm to about 40 nm in some embodiments, and in the range of about 7 nm to about 12 nm in other embodiments. In some embodiments, the spacing S1 between the two fin structures is in the range of about 10 nm to about 50 nm. The height of the fin structure 20 (along the Z direction) is in the range of about 100 nm to about 300 nm in some embodiments, and in the range of about 50 nm to 100 nm in other embodiments.

[0047] Gate structure 40 (see) Figure 5A The lower portion of the fin structure 20 below the gate structure 40 can be referred to as the well region, and the upper portion of the fin structure 20 can be referred to as the channel region. Below the gate structure 40, the well region is embedded in the isolation insulating layer 30 (see...). Figure 5A The channel region protrudes from the insulating layer 30. The lower portion of the channel region may also be embedded in the insulating layer 30 to a depth of about 1 nm to about 5 nm.

[0048] In some embodiments, the height of the well region is in the range of about 60 nm to 100 nm, and the height of the channel region is in the range of about 40 nm to 60 nm, and in other embodiments it is in the range of about 38 nm to about 55 nm.

[0049] After forming the fin structure 20, in some embodiments, the substrate 10 may be further etched to form a mesa shape 10M, such as... Figure 3 As shown. In other embodiments, the mesa shape 10M is first formed, and then the fin structure 20 is formed. In some embodiments, the mesa shape is not formed. In the following embodiments, the accompanying drawings illustrate an example in which the mesa structure is not formed.

[0050] After forming the fin structure 20 (and optionally the mesa shape 10M), an insulating layer 30 is formed in the gaps between the fin structures and / or in the gaps between one fin structure and another element formed above the substrate 10. The insulating layer 30 may also be referred to as a “shallow trench isolation (STI)” layer. The insulating material used for the insulating layer 30 may include one or more layers of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, fluorine-doped silicate glass (FSG), or a low-k dielectric material. The insulating layer is formed by LPCVD (low-pressure chemical vapor deposition), plasma CVD, or flowable CVD. In flowable CVD, a flowable dielectric material can be deposited instead of silicon oxide. As the name suggests, the flowable dielectric material can “flow” during deposition to fill gaps or spaces with a high aspect ratio. Typically, various chemicals are added to the silicon-containing precursor to allow the deposited film to flow. In some embodiments, nitrogen-hydrogen bonds are added. Examples of flowable dielectric precursors (particularly, flowable silicon oxide precursors) include silicates, siloxanes, methylsilsesquioxanes (MSQ), hydrosilsesquioxanes (HSQ), MSQ / HSQ, perhydrosilazanes (TCPS), perhydropolysilazanes (PSZ), tetraethyl orthosilicate (TEOS), or silylamines (such as trimethylsilylamine (TSA)). These flowable silicon oxide materials are formed in multiple processing steps. After depositing the flowable film, the flowable film is cured and then annealed to remove unwanted elements to form silicon oxide. When unwanted elements are removed, the flowable film densifies and shrinks. In some embodiments, multiple annealing processes are performed. The flowable film is cured and annealed more than once. The flowable film may be doped with boron and / or phosphorus.

[0051] First, the insulating layer 30 is formed as a thick layer, such that the fin structure is embedded in the thick layer, and the thick layer is recessed to expose the upper part of the fin structure 20, as shown below. Figure 4 As shown. The height H1 of the fin structure from the upper surface of the insulating layer 30 is in some embodiments ranging from about 20 nm to about 100 nm, and in other embodiments ranging from about 30 nm to about 50 nm. A thermal process, such as an annealing process, can be performed before or after recessing the insulating layer 30 to improve the quality of the insulating layer 30. In some embodiments, the thermal process is performed for about 1.5 seconds to about 10 seconds in an inert gas environment (such as N2, Ar, or He) at a temperature ranging from about 900°C to about 1050°C using rapid thermal annealing (RTA).

[0052] After forming the insulating layer 30, a gate structure 40 is formed above the fin structure 20, such as... Figures 5A to 5C As shown. Figure 5A This is an exemplary 3D diagram. Figure 5B It is along Figure 5A An exemplary cross-sectional view of line aa, and Figure 5C It is along Figure 5A An exemplary cross-sectional view of line bb. Figures 6 to 11 and Figures 13 to 17 Also along Figure 5A A cross-sectional view of line bb.

[0053] like Figure 5A As shown, the gate structure 40 extends in the X direction, while the fin structure 20 extends in the Y direction. To fabricate the gate structure 40, a dielectric layer and a polysilicon layer are formed over the insulating layer 30 and the exposed fin structure 20, and then a patterning operation is performed to obtain a gate structure comprising a gate pattern 44 made of polysilicon and a dielectric layer 42. In some embodiments, the polysilicon layer is patterned using a hard mask, and the hard mask remains on the gate pattern 44 as a cover insulating layer 46. The hard mask (cover insulating layer 46) comprises one or more layers of insulating material. In some embodiments, the cover insulating layer 46 comprises a silicon nitride layer formed over a silicon oxide layer. In other embodiments, the cover insulating layer 46 comprises a silicon oxide layer formed over a silicon nitride layer. The insulating material for the cover insulating layer 46 can be formed by CVD, PVD, ALD, electron beam evaporation, or other suitable processes. In some embodiments, the dielectric layer 42 comprises one or more layers of silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the thickness of the dielectric layer 42 is in the range of about 2 nm to about 20 nm, and in other embodiments it is in the range of about 2 nm to about 10 nm. The height H2 of the gate structure is in the range of about 50 nm to about 400 nm in some embodiments, and in other embodiments it is in the range of about 100 nm to 200 nm.

[0054] In some embodiments, a gate replacement technique is employed. In this case, the gate pattern 44 and the dielectric layer 42 are subsequently removed as a dummy gate electrode and a dummy gate dielectric layer, respectively. If a gate-first technique is employed, the gate pattern 44 and the dielectric layer 42 serve as the gate electrode and the gate dielectric layer, respectively.

[0055] Furthermore, gate sidewall spacers 48 are formed on the two sidewalls of the gate pattern. The sidewall spacers 48 comprise one or more layers of insulating material, such as SiO2, SiN, SiON, SiOCN, or SiCN, formed by CVD, PVD, ALD, electron beam evaporation, or other suitable processes. Low-k dielectric materials can be used as sidewall spacers. The sidewall spacers 48 are formed by forming a blanket layer of insulating material and performing anisotropic etching. In one embodiment, the sidewall spacer layer is made of a silicon nitride-based material, such as SiN, SiON, SiOCN, or SiCN.

[0056] Then, as Figure 6 As shown, a fin liner layer 50 is formed above the fin structure 20. The fin liner layer 50 is made of a dielectric material including silicon nitride-based materials, such as SiN, SiON, SiOCN, or SiCN. In one embodiment, SiN is used as the fin liner layer 50. The fin liner layer 50 is formed by CVD, PVD, ALD, electron beam evaporation, or other suitable processes. In some embodiments, the thickness of the fin liner layer 50 is in the range of about 30 nm to about 70 nm.

[0057] In some embodiments, the fin pad layer 50 and sidewall spacers 48 for the gate structure are formed separately. In other embodiments, the same blanket layer is used for the fin pad layer 50 and the sidewall spacers 48.

[0058] After the fin pad layer 50 is formed, the upper part of the fin structure 20 is recessed. A portion of the fin pad layer 50, which is disposed on the side and top surfaces of the fin structure protruding from the insulating layer, is removed by dry etching and / or wet etching operations. The upper part of the fin structure 20 is recessed (etched) downward to a level equal to or lower than the level of the upper surface of the fin pad layer 50 on the upper surface of the insulating layer 30, such as... Figure 7 As shown.

[0059] In some embodiments, a portion of the fin liner layer 50 disposed on the sidewall of the fin structure is retained after fin recess etching, such as Figure 7 As shown. In other embodiments, the fin pad layer 50 disposed on the sidewall of the fin structure is completely removed, and after fin recess etching, the fin pad layer 50 is left only on the upper surface of the insulating layer 30.

[0060] In some embodiments, the top of the recessed fin structure 20 (the bottom of the groove 25) has a U-shape, a semi-circular shape, or a bullet shape (collectively referred to as a rounded shape), such as Figure 7 As shown, it is a cross-sectional view along the gate extension direction (X).

[0061] The fin structure 20 is recessed to form a rounded corner shape using a pulsed bias etching operation of a plasma etching apparatus. In some embodiments, a substrate 10 is placed on a wafer stage of the etching chamber, and the substrate 10 and / or the wafer stage is biased with, for example, a DC voltage. In some embodiments, RF power is applied to a counter electrode disposed on the substrate. In other embodiments, RF power is applied via a coil surrounding the etching chamber. In some embodiments, the etching gas comprises a halogen-containing gas, such as HBr. In some embodiments, the HBr is diluted with an inert gas such as He and / or Ar. In some embodiments, the ratio of HBr to the diluent gas is in the range of about 0.3 to about 0.7, and in other embodiments, the ratio is in the range of about 0.4 to about 0.6.

[0062] In some embodiments, during the etching operation, the pressure in the plasma chamber is maintained in the range of about 1 mTorr to about 100 mTorr by a pumping system. In other embodiments, the pressure during the etching operation is in the range of about 3 mTorr to about 15 mTorr. The bias voltage is in the range of about 300 V to about 800 V in some embodiments, and in the range of about 500 V to 600 V in others. In some embodiments, the input RF power is in the range of about 300 W to about 800 W. The RF frequency is 13.56 MHz, 2.56 GHz, or any other suitable frequency used in the semiconductor industry.

[0063] In some embodiments, the bias voltage is a pulsed voltage having a duty cycle (switching ratio) ranging from about 10% to about 90%. In other embodiments, the duty cycle ranges from about 30% to about 70%. In some embodiments, the unit cycle (one “on” cycle and one “off” cycle) ranges from about 0.5 sec to 10 sec, and from about 1 sec to 5 sec. In some embodiments, pulsed bias etch is a repetition of etch and deposition operations. During the “on” period, the fin structure is etched, while during the “off” period, the deposition rate of byproducts is greater than the etch rate. Therefore, by adjusting the duty cycle, RF power, and / or bias voltage, a structure such as Figure 7 The rounded corner shape shown.

[0064] In some embodiments, by adjusting etching conditions, such as over-etching time, a portion of the fin liner layer 50 disposed on the sidewall of the fin structure is retained, such as... Figure 7 As shown, the fin pad layer 50 disposed on the sidewall of the fin structure may be completely removed, and after fin recess etching, the fin pad layer 50 is left only on the upper surface of the insulating layer 30.

[0065] Then, as Figure 8 As shown, an epitaxial source / drain structure 60 is formed above the recessed fin structure 20. The epitaxial source / drain structure 60 is made of one or more layers of semiconductor material having a different lattice constant than the fin structure 20 (channel region). When the fin structure is made of Si, the epitaxial source / drain structure 60 includes SiP, SiC, or SiCP for n-channel Fin FETs and SiGe or Ge for p-channel Fin FETs. In some embodiments, the source / drain epitaxial layer 60 is SiGe with a Ge content ranging from about 20% atoms to about 50% atoms. The epitaxial source / drain structure 60 is epitaxially formed above the upper portion of the recessed fin structure. Due to the crystal orientation (e.g., (100) plane) of the substrate formed as the fin structure 20, the epitaxial source / drain structure 60 grows laterally and has a rhomboid shape.

[0066] The source / drain epitaxial layer 60 can be grown at a temperature of approximately 600 to 800 °C and a pressure of approximately 80 to 150 Torr using silicon-containing gases such as SiH4, Si2H6, or SiCl2H2; germanium-containing gases such as GeH4, Ge2H6, or GeCl2H2; carbon-containing gases such as CH4 or C2H6; and / or doping gases such as PH3. The source / drain structures for n-channel FETs and p-channel FETs can be formed using separate epitaxial processes.

[0067] Due to the relatively small spacing between the fin structure and the fin liner 50, maintained on the upper surface of the insulating layer between the fin structures, and the rounded corner shape of the recessed fin structure 20, adjacent epitaxial source / drain structures formed above each first fin structure 20 merge, thereby creating a gap or void (air gap) 65 on the upper surface of the insulating layer 30 by the merged second epitaxial source / drain structure 60 and the fin liner 50. Figure 8 As shown.

[0068] After forming the epitaxial source / drain structure 60, in some embodiments, a first ion implantation operation 65 as pre-amorphization implantation (PAI) is performed, such as... Figure 9 As shown. PAI is used to narrow the channel for subsequently implanted boron. PAI can improve the junction characteristics of the source / drain junction. In some embodiments, Ge is implanted into the PMOS device. In some embodiments, a Ge-containing layer is formed on the surface of the epitaxial source / drain structure 60 by a deposition method.

[0069] In addition, such as Figure 10 As shown, a second ion implantation operation 67 is performed after the first PAI. In some embodiments, during the second ion implantation, for PMOS, an energy of approximately 250 eV to 5 keV and approximately 5 × 10⁻⁶ ions are implanted. 14 cm -2 Approximately 5×10 15 cm -2 The dose of B is injected. In some embodiments, for NMOS, PAI is not performed, and in the second ion implantation, an energy of about 250 eV to 5 keV and about 5 × 10⁻⁶ ions are injected. 14 cm -2 Approximately 5×10 15 cm -2 The dose of P and / or As is injected.

[0070] Following the second ion implantation, an annealing operation is performed. In some embodiments, the annealing temperature is in the range of about 500°C to about 750°C.

[0071] In some embodiments, such as Figure 11As shown, an insulating layer 70, serving as a contact etch stop layer, is formed over the source / drain epitaxial layer 60, followed by the formation of one or more interlayer dielectric (ILD) layers 80. The insulating layer 70 is one or more layers of insulating material. In one embodiment, the insulating layer 70 is made of silicon nitride formed by CVD. Materials used for the ILD layer 80 include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers may be used for the interlayer dielectric layer 80.

[0072] After forming the ILD layer 80, a planarization operation such as CMP is performed to expose the gate pattern 44 (dummy gate electrode). The dummy gate electrode 44 and the dummy gate dielectric layer 42 are then removed using an appropriate etching process to form the gate opening. Figure 12 As shown, a metal gate structure including a gate dielectric layer 102 and a metal gate electrode 104 is formed in the gate opening. This metal gate structure is... Figure 5A The cross-sectional view corresponding to line aa.

[0073] In some embodiments, the gate dielectric layer 102 is formed over an interface layer (not shown) disposed above the channel layer of the fin structure 20. In some embodiments, the interface layer may comprise silicon oxide or germanium oxide having a thickness of 0.2 nm to 1.5 nm. In other embodiments, the thickness of the interface layer is in the range of about 0.5 nm to about 1.0 nm.

[0074] The gate dielectric layer 102 comprises one or more layers of dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer is formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), or other suitable methods and / or combinations thereof. In some embodiments, the thickness of the gate dielectric layer is in the range of about 1 nm to about 10 nm, and in other embodiments, it may be in the range of about 2 nm to about 7 nm.

[0075] A metal gate electrode 104 is formed above the gate dielectric layer. The metal gate electrode 104 comprises one or more layers of any suitable metallic material, such as aluminum, copper, titanium, tantalum, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials and / or combinations thereof.

[0076] In some embodiments of the invention, one or more power function adjustment layers (not shown) are inserted between the gate dielectric layer and the metal gate electrode. The power function adjustment layer is made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. For n-channel FinFETs, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the power function adjustment layer, and for p-channel FinFETs, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the power function adjustment layer.

[0077] After depositing the appropriate material for the metal gate structure, a planarization operation such as CMP is performed.

[0078] After the metal gate electrode is formed, one or more additional ILD layers are formed above ILD layer 80. Figures 13 to 17 In this context, ILD layer 80 and the additional ILD layer are collectively referred to as ILD layer 81.

[0079] like Figure 13 As shown, a contact opening 85 is formed above the source / drain epitaxial layer 60 by using one or more photolithography and etching operations to expose at least a portion of the upper surface of the source / drain epitaxial layer 60.

[0080] In some embodiments, the process of forming the contact opening 85 is implemented afterward. Figure 9 and Figure 10 The first and second ion implantation operations and the subsequent annealing operation are described.

[0081] After forming the contact opening 85, as Figure 14 As shown, a nitrogen-containing layer 90 is formed on the surface of the exposed source / drain epitaxial layer 60 by nitrogen treatment.

[0082] In some embodiments, the nitrogen-containing layer 90 is formed by exposing the surface of the epitaxial source / drain layer 60 to a plasma formed from a nitrogen-containing gas. In some embodiments, the nitrogen-containing gas is N2 and / or NH3. In some embodiments, an inert gas such as Ar, He, and / or Ne is also added to the nitrogen-containing gas. In some embodiments, a mixture of N2 and Ar is used to generate the plasma. In some embodiments, the substrate 10 is heated to 450°C or higher during and / or after plasma processing. In some embodiments, the substrate 10 is heated to a temperature ranging from about 450°C to about 600°C. In other embodiments, the temperature ranges from about 475°C to about 550°C.

[0083] In other embodiments, the nitrogen-containing layer 90 is formed by exposing the surface of the epitaxial source / drain layer 60 to NH3 gas while heating the substrate 10 to 450°C or higher. In some embodiments, the substrate 10 is heated to a temperature ranging from about 450°C to about 600°C. In other embodiments, this temperature ranges from about 475°C to about 550°C.

[0084] In some embodiments, the nitrogen-containing layer 90 is formed at a temperature below, for example, 450°C, and an annealing operation is performed at a temperature ranging from about 450°C to about 600°C. In other embodiments, the temperature ranges from about 475°C to about 550°C.

[0085] Figure 25 The Fourier Transform Infrared (FTIR) measurements of the various samples after nitrogen treatment are shown. At temperatures below 450°C, virtually no peaks corresponding to Si-N bonds were observed. Conversely, at temperatures above 450°C, more specifically, 475°C, peaks corresponding to Si-N bonds were observed, indicating high film quality of the nitrogen-containing layer 90 and / or the source / drain epitaxial layer 60. The formation of Si-N bonds also helps to reduce the Schottky barrier height between the source / drain epitaxial layer 60 and the subsequently formed metal contact 100.

[0086] After the formation of the nitrogen-containing layer 90, such as Figure 15 As shown, a metal layer 94 is formed. The metal layer 94 can be formed by CVD, ALD, PVD, or any other suitable film formation method. In some embodiments, the metal layer 94 is a layer of Ni, Ti, Ta, and / or W. In some embodiments, Ti is used as the metal layer 94. After forming the metal layer 94, an annealing operation is performed to form an alloy layer 95 of the metal elements of the metal layer 94 and the elements of the source / drain epitaxial layer 60 (e.g., Si or Si and Ge), as shown. Figure 16 As shown.

[0087] In some embodiments, the annealing operation is performed at a temperature of about 250°C to about 850°C. In some embodiments, the thickness of the alloy layer 95 is in the range of about 4 nm to about 10 nm. Before or after the annealing operation, the metallic material 94 formed on the insulating layer 30 is selectively removed.

[0088] In some embodiments, alloy layer 95 is a silicide layer. In some embodiments, alloy layer 95 is a TiSi layer. In some embodiments, the alloy layer is a nitrogen-containing TiSi layer. In other embodiments, alloy layer 95 is a Ge-containing TiSi layer. In some embodiments, the alloy layer is a Ge and N-containing TiSi layer. In some embodiments, the semiconductor device is a p-type MOSFET. In other embodiments, the semiconductor device is an n-type MOSFET. An appropriate material is selected depending on the type of MOSFET.

[0089] In some embodiments, a portion of the nitrogen-containing layer 90 is retained after the alloy layer 95 is formed. In other embodiments, all of the nitrogen-containing layer 90 (nitrogen-containing semiconductor (Si, SiGe layer)) is consumed to form the alloy layer 95.

[0090] In some embodiments, all metal (e.g., Ti) layers formed on the nitrogen-containing layer 90 are consumed to form the alloy layer 95, and a portion of the metal layer on the ILD layer 81 is retained. In other embodiments, a portion of the metal layer 94 formed on the nitrogen-containing layer 90 is retained after the alloy layer 95 is formed. In some embodiments, the remaining metal layer 94 is removed, while in other embodiments it is not removed.

[0091] Then, the contact opening 85 is filled with a conductive material to form a metal contact 100 (contact plug), such as... Figure 17 As shown. After forming a conductive material on the remaining metal layer 94, a CMP operation is performed to remove the conductive material and the metal layer formed above the upper surface of the ILD layer 81. The metal contact 100 may comprise a single or multiple layers of any suitable metal, such as Co, W, Ti, Ta, Cu, Al and / or Ni and / or their nitrides.

[0092] After the metal contacts are formed, further CMOS processes are performed to form individual components, such as additional interlayer dielectric layers, contacts / vias, interconnect metal layers, and passivation layers.

[0093] In some embodiments, a nitrogen-containing layer 90 is formed before the formation of the ILD layer 80, and an alloy layer 95 is formed after the formation of contact openings 85 in the ILD layer 81. In this case, the nitrogen-containing layer 90 is formed over the entire outer surface of the source / drain epitaxial layer 60. In other embodiments, the nitrogen-containing layer 90 and the alloy layer 95 are formed before the formation of the ILD layer 80. In this case, in some embodiments, a wrap-around contact covering the entire outer surface of the source / drain epitaxial layer 60 may be formed.

[0094] In some embodiments, the metal gate structure is formed after the source / drain epitaxial layer 60 is formed and before the silicide layer 95 is formed. In other embodiments, the metal gate structure is formed before the source / drain epitaxial layer is formed.

[0095] Figure 18 and Figure 19 Exemplary cross-sectional views of various stages for manufacturing a FinFET device according to another embodiment of the present invention are shown. The same or similar materials, configurations, dimensions, processes, and / or operations as those described in the above embodiments may be used in the following embodiments, and detailed descriptions may be omitted.

[0096] In such Figure 13 After the contact opening 85 is formed as shown, a metal nitride layer 92 is formed in the contact opening 85, and a metal layer 94 is formed above the metal nitride layer 92, as shown. Figure 18 As shown. The metal nitride layer 92 and the metal layer 94 can be formed by CVD, ALD, PVD or any other suitable film formation method.

[0097] In some embodiments, the metal nitride layer 92 is a nitride layer of Ni, Ti, Ta, and / or W. In some embodiments, TiN is used as the metal nitride layer 92. In some embodiments, the metal layer 94 is a nitride layer of Ni, Ti, Ta, and / or W. In some embodiments, Ti is used as the metal layer 94. In some embodiments, the metal element of the metal nitride layer 92 is the same as that of the metal layer 94, while in other embodiments it is different. In some embodiments, the thickness of the metal nitride layer 94 is in the range of about 0.5 nm to about 50 nm, and in other embodiments it is in the range of about 1 nm to about 10 nm. When the thickness of the metal nitride layer (e.g., the TiN layer) 92 is greater than about 50 nm, the junction resistance Rscd increases, and when the thickness of the metal nitride layer 92 is less than 0.5 nm, the effect of nitrogen cannot be fully obtained.

[0098] After forming the metal layer 94, an annealing operation is performed to form an alloy layer 95 of the metal elements of the metal nitride layer 92 and / or the metal elements of the source / drain epitaxial layer 60 (e.g., Si or Si and Ge), and then the metal contact 100 is formed, such as Figure 19 As shown.

[0099] In some embodiments, all metal nitride (e.g., TiN) layers 92 formed on the source / drain epitaxial layer 60 are consumed to form an alloy layer 95, and a portion of the metal nitride layer 92 on the ILD layer 81 is retained. In other embodiments, after forming the alloy layer 95, a portion of the metal nitride layer 92 formed on the source / drain epitaxial layer 60 is retained. In some embodiments, the remaining metal nitride layer 92 and / or the remaining metal layer 94 are removed, while in other embodiments, they are not removed.

[0100] In some embodiments, by controlling the annealing conditions, an alloy layer (e.g., titanium silicide) is formed on the source / drain epitaxial layer 60, and a nitrogen-containing layer is formed on the alloy layer, wherein the metal layer on the nitrogen-containing layer is retained.

[0101] Figure 20 and Figure 21 Exemplary cross-sectional views of various stages for manufacturing a FinFET device according to another embodiment of the present invention are shown. The same or similar materials, configurations, dimensions, processes, and / or operations as those described in the above embodiments may be used in the following embodiments, and detailed descriptions may be omitted.

[0102] In such Figure 13 After the contact opening 85 is formed as shown, a metal layer 94 is formed in the contact opening 85, and a metal nitride layer 92 is formed on top of the metal layer 94, as shown. Figure 20 As shown. The metal nitride layer 92 and the metal layer 94 can be formed by CVD, ALD, PVD or any other suitable film formation method.

[0103] In some embodiments, the metal nitride layer 92 is a nitride layer of Ni, Ti, Ta, and / or W. In some embodiments, TiN is used as the metal nitride layer 92. In some embodiments, the metal layer 94 is a nitride layer of Ni, Ti, Ta, and / or W. In some embodiments, Ti is used as the metal layer 94. In some embodiments, the metal element of the metal nitride layer 92 is the same as that of the metal layer 94, while in other embodiments it is different. In some embodiments, the thickness of the metal nitride layer 94 is in the range of about 0.5 nm to about 50 nm, and in other embodiments it is in the range of about 1 nm to about 10 nm. When the thickness of the metal nitride layer (e.g., the TiN layer) 92 is greater than about 50 nm, the junction resistance Rscd increases, and when the thickness of the metal nitride layer 92 is less than 0.5 nm, the effect of nitrogen cannot be fully obtained.

[0104] After forming the metal nitride layer 94, an annealing operation is performed to form an alloy layer 95 of the metal elements of the metal layer 94 and / or the metal nitride layer 92 and the elements of the source / drain epitaxial layer 60 (e.g., Si or Si and Ge), and then the metal contact 100 is formed, such as Figure 21 As shown.

[0105] In some embodiments, all metal (e.g., Ti) layers 94 formed on the source / drain epitaxial layer 60 are consumed to form an alloy layer 95, and a portion of the metal layer 94 on the ILD layer 81 is retained. In other embodiments, a portion of the metal layer 94 formed on the source / drain epitaxial layer 60 is retained after the alloy layer 95 is formed. In some embodiments, the remaining metal layer 94 and / or metal nitride layer 92 are removed, while in other embodiments, they are not removed.

[0106] In some embodiments, by controlling the annealing conditions, nitrogen in the metal nitride layer 92 diffuses to the source / drain epitaxial layer 60 and forms a nitrogen-containing layer on the alloy layer, on which the metal layer is formed.

[0107] In some embodiments, a metal nitride layer 92 (e.g., TiN) is formed on the source / drain epitaxial layer 60, and an annealing operation to form an alloy layer 95 is performed without forming a metal layer. By controlling the annealing conditions, nitrogen in the metal nitride layer 92 diffuses into the source / drain epitaxial layer 60, and a nitrogen-containing layer is formed on the alloy layer, on which the metal layer is formed.

[0108] Figure 22 and Figure 23Exemplary cross-sectional views of various stages for manufacturing a FinFET device according to another embodiment of the present invention are shown. The same or similar materials, configurations, dimensions, processes, and / or operations as those described in the above embodiments may be used in the following embodiments, and detailed descriptions may be omitted.

[0109] In such Figure 13 After the contact opening 85 is formed as shown, and regarding Figure 14 The procedure is similar, forming a nitrogen-containing layer 90. Then, a metal nitride layer 92 is formed in the contact opening 85, and a metal layer 94 is formed above the metal nitride layer 92, as described above. Figure 22 As shown. In some embodiments, the metal nitride layer 92 is a nitride layer of Ni, Ti, Ta, and / or W. In some embodiments, TiN is used as the metal nitride layer 92. In some embodiments, the metal layer 94 is a nitride layer of Ni, Ti, Ta, and / or W. In some embodiments, Ti is used as the metal layer 94. In some embodiments, the metal element of the metal nitride layer 92 is the same as that of the metal layer 94, while in other embodiments it is different from that of the metal layer 94. In some embodiments, the thickness of the metal nitride layer 94 is in the range of about 0.5 nm to about 50 nm, and in other embodiments it is in the range of about 1 nm to about 10 nm. When the thickness of the metal nitride layer (e.g., the TiN layer) 92 is greater than about 50 nm, the junction resistance Rscd increases, and when the thickness of the metal nitride layer 92 is less than 0.5 nm, the effect of nitrogen cannot be fully obtained.

[0110] After forming the metal layer 94, an annealing operation is performed to form a metal nitride layer 92 and / or an alloy layer 95 of the metal elements of the metal layer 94 and the elements of the nitrogen-containing layer 90 (e.g., Si or Si and Ge), and then the metal contact 100 is formed, such as Figure 23 As shown.

[0111] In some embodiments, all metal nitride (e.g., TiN) layers 92 formed on the nitrogen-containing layer 90 are consumed to form an alloy layer 95. A portion of the metal nitride layer 92 on the ILD layer 81 is retained. In other embodiments, a portion of the metal nitride layer 92 formed on the nitrogen-containing layer 90 is retained after the alloy layer 95 is formed. In some embodiments, the remaining metal nitride layer 92 and / or the remaining metal layer 94 are removed, while in other embodiments, they are not removed.

[0112] In some embodiments, by controlling the annealing conditions, an alloy layer (e.g., titanium silicide) is formed on the source / drain epitaxial layer 60, and a nitrogen-containing layer is formed on the alloy layer, while retaining the metal layer on the nitrogen-containing layer.

[0113] Figures 24A to 24HA cross-sectional view of the contact structure between the conductive contact 100 and the source / drain epitaxial layer 60 according to various embodiments of the present invention is shown.

[0114] exist Figure 24A In the middle, the alloy layer 95 (a nitrogen-containing silicide layer) is disposed between the source / drain epitaxial layer 60 and the conductive contact 100.

[0115] exist Figure 24B In this process, an alloy layer 95 (a nitrogen-containing silicide layer) is disposed on the source / drain epitaxial layer 60, and a metal layer 94 is retained between the alloy layer 95 and the conductive contact 100.

[0116] exist Figure 24C In the middle, the remaining nitrogen-containing layer 90 is disposed between the alloy layer 95 (which is a nitrogen-containing silicide layer) and the source / drain epitaxial layer 60, and the conductive contact 100 is disposed on the alloy layer 95.

[0117] exist Figure 24D In the middle, the remaining nitrogen-containing layer 90 is disposed between the alloy layer 95 (which is a nitrogen-containing silicide layer) and the source / drain epitaxial layer 60, and the remaining metal layer 94 is disposed between the conductive contact 100 and the alloy layer 95.

[0118] exist Figure 24E In this configuration, an alloy layer 95 (a nitrogen-containing silicide layer) is disposed on the source / drain epitaxial layer 60, and a remaining metal nitride layer 92 is disposed on the alloy layer 95. Furthermore, a remaining metal layer 94 is disposed between the conductive contact 100 and the metal nitride layer 92.

[0119] exist Figure 24F In this configuration, the remaining nitrogen-containing layer 90 is disposed between the alloy layer 95 (which is a nitrogen-containing silicide layer) and the source / drain epitaxial layer 60. The remaining metal nitride layer 92 is disposed on the alloy layer 95, and the remaining metal layer 94 is disposed between the conductive contact 100 and the metal nitride layer 92.

[0120] exist Figure 24G In the process, an alloy layer 95 (a nitrogen-containing silicide layer) is disposed on the source / drain epitaxial layer 60, and a nitrogen-containing layer 90' is formed between the alloy layer 95 and the conductive contact 100.

[0121] exist Figure 24H In the process, an alloy layer 95 (a nitrogen-containing silicide layer) is disposed on the source / drain epitaxial layer 60, and a nitrogen-containing layer 90' is formed between the alloy layer 95 and the remaining metal layer 94, and a conductive contact 100 is disposed on the remaining metal layer 94.

[0122] exist Figures 24A to 24HIn some embodiments, the nitrogen-containing layer comprises at least 5% atomic nitrogen. In other embodiments, the nitrogen-containing layer comprises at least 20% atomic nitrogen. In some embodiments, Figures 24A to 24H One or more of the alloy layers 95 contain less than about 5% nitrogen atoms.

[0123] Figure 26 The results of depth-direction elemental analysis according to an embodiment of the present invention are shown. Figure 18 and Figure 19 The illustrated example shows the preparation of the measurement sample. Figure 26 As shown, a nitrogen-containing layer is formed between the Si layer (e.g., source / drain epitaxial layer 60) and the Ti layer (e.g., metal layer 94). Figure 26 In this process, the thickness of the nitrogen-containing layer, which contains at least 20% nitrogen atoms, is approximately 7 nm, and can range from approximately 5 nm to approximately 10 nm. Figure 26 In the nitrogen-containing layer, the peak nitrogen content is about 80% atoms, and it can range from 50% to 95% atoms.

[0124] Figure 27 A comparison of elemental analysis results according to embodiments of the present invention is shown. The samples include a structure without a nitrogen-containing layer, a structure containing a nitrogen-containing layer through TiN layer deposition, and a structure containing a nitrogen-containing layer through nitrogen treatment. The amount of elements is measured at the center of the silicide layer. By forming a nitrogen-containing layer, the oxygen content is reduced to less than about 13.5% atoms. A lower oxygen content can also improve contact resistance.

[0125] Figure 28 and Figure 29 A cross-sectional view of a semiconductor device according to an embodiment of the present invention is shown. In some embodiments, the nitrogen-containing layer 90 has a convex, curved shape toward the substrate. Figure 30 A cross-sectional view of a ring oscillator of a semiconductor device according to an embodiment of the present invention is shown, while Figure 31 A cross-sectional view of a static random access memory (SRAM) of a semiconductor device is shown. In some embodiments, the nitrogen-containing layer has a convex, curved shape toward the substrate.

[0126] It should be understood that not all advantages have been discussed here, no particular advantage is needed for all embodiments or instances, and other embodiments or instances may provide different advantages.

[0127] According to embodiments of the present invention, one or more nitrogen-containing layers containing at least, for example, 5% nitrogen atoms are disposed between the source / drain epitaxial layer and the conductive metal contact. The nitrogen-containing layer can reduce the Schottky barrier height between the source / drain epitaxial layer and the conductive metal contact, thereby reducing the contact resistance Rscd in the source / drain region.

[0128] According to one aspect of the present invention, in a method of manufacturing a semiconductor device, an epitaxial source / drain structure is formed at a source / drain region disposed above a substrate, a nitrogen-containing layer is formed on or in the surface of the epitaxial source / drain structure, a metal layer is formed above the nitrogen-containing layer, and an alloy layer of the elements of the epitaxial source / drain structure is formed above the source / drain region and based on the elements of the metal layer. In one or more embodiments above and below, the nitrogen-containing layer is formed by exposing the surface of the epitaxial source / drain structure to a plasma formed by a nitrogen-containing gas. In one or more embodiments above and below, the nitrogen-containing layer is formed by exposing the surface of the epitaxial source / drain structure to NH3 gas while heating the substrate. In one or more embodiments above and below, the substrate is heated to a temperature of 475°C or higher. In one or more embodiments above and below, the nitrogen-containing layer is a TiN layer. In one or more embodiments above and below, the metal layer comprises a Ti layer. In one or more embodiments above and below, the nitrogen-containing layer contains at least 20% atomic nitrogen. In one or more of the above and below embodiments, the thickness of the nitrogen-containing layer, containing at least 20% nitrogen atoms, is in the range of 5 nm to 10 nm. In one or more of the above and below embodiments, the peak nitrogen content in the nitrogen-containing layer is in the range of 50% to 95% atoms. In one or more of the above and below embodiments, after the nitrogen-containing layer is formed, an annealing operation is performed at a temperature of 475°C or higher.

[0129] According to another aspect of the present invention, in a method of manufacturing a semiconductor device, an epitaxial source / drain structure is formed at a source / drain region disposed above a substrate; a first implantation operation is performed to introduce a first ion into the epitaxial source / drain structure; a second implantation operation is performed to introduce a second ion different from the first ion into the epitaxial source / drain structure; a first annealing operation is performed; a nitrogen-containing layer is formed on or in the surface of the epitaxial source / drain structure; a metal layer is formed above the nitrogen-containing layer; and an alloy layer of the elements of the epitaxial source / drain structure is formed above the source / drain region and based on the elements of the metal layer. In one or more of the above and below embodiments, the epitaxial source / drain structure comprises SiGe. In one or more of the above and below embodiments, the first ion is a Ge ion. In one or more of the above and below embodiments, the second ion comprises boron. In one or more of the above and below embodiments, the first annealing operation comprises laser annealing. In one or more of the above and below embodiments, after the formation of the nitrogen-containing layer, a second annealing operation is performed at a temperature of 475°C or higher.

[0130] According to another aspect of the present invention, in a method of manufacturing a semiconductor device, an epitaxial source / drain structure is formed at a source / drain region located above a substrate; an interlayer dielectric (ILD) layer is formed above the epitaxial source / drain structure; a contact opening is formed in the ILD layer to expose a portion of the upper surface of the epitaxial source / drain structure; a nitrogen-containing layer is formed on or in the upper surface of the epitaxial source / drain structure; a metal layer is formed above the nitrogen-containing layer; an alloy layer of elements of the epitaxial source / drain structure is formed above the source / drain region and based on the elements of the metal layer; and a conductive layer is formed above the alloy layer of the contact opening. In one or more embodiments above and below, the nitrogen-containing layer is formed by exposing the surface of the epitaxial source / drain structure to a plasma formed by a nitrogen-containing gas. In one or more embodiments above and below, the nitrogen-containing layer is formed by exposing the surface of the epitaxial source / drain structure to NH3 gas while heating the substrate. In one or more embodiments above and below, after forming the nitrogen-containing layer, an annealing operation is performed at a temperature of 475°C or higher.

[0131] According to one aspect of the present invention, a semiconductor device includes a gate structure disposed above a channel region, a source / drain epitaxial layer disposed at a source / drain region, a nitrogen-containing layer disposed on the source / drain epitaxial layer, a silicide layer disposed on the nitrogen-containing layer, and a conductive contact disposed on the silicide layer. In one or more embodiments above and below, the nitrogen-containing layer comprises at least 20% atomic nitrogen. In one or more embodiments above and below, the thickness of the nitrogen-containing layer with at least 20% atomic nitrogen content is in the range of 5 nm to 10 nm. In one or more embodiments above and below, the peak nitrogen content in the nitrogen-containing layer is in the range of 50% atomic to 95% atomic. In one or more embodiments above and below, the silicide layer comprises TiSi. In one or more embodiments above and below, the source / drain epitaxial layer comprises SiGe, and the silicide layer comprises Ge-containing TiSi. In one or more embodiments above and below, the nitrogen-containing layer comprises Si-N bonds. In one or more embodiments above and below, the nitrogen-containing layer is a TiN layer. In one or more embodiments above and below, the nitrogen-containing layer is not a TiN layer. In one or more of the embodiments above and below, the semiconductor device further includes a TiN layer between the nitrogen-containing layer and the silicide layer.

[0132] According to another aspect of the present invention, a semiconductor device includes a gate structure disposed above a channel region, a source / drain epitaxial layer disposed at a source / drain region, a silicide layer disposed on the source / drain epitaxial layer, a nitrogen-containing layer disposed on the silicide layer, and a conductive contact disposed on the nitrogen-containing layer. In one or more embodiments above and below, the nitrogen-containing layer contains at least 20% atomic amounts of nitrogen. In one or more embodiments above and below, the thickness of the nitrogen-containing layer containing at least 20% atomic amounts of nitrogen is in the range of 5 nm to 10 nm. In one or more embodiments above and below, the peak nitrogen content in the nitrogen-containing layer is in the range of 50% atomic to 95% atomic. In one or more embodiments above and below, the silicide layer comprises TiSi. In one or more embodiments above and below, the source / drain epitaxial layer comprises SiGe, and the silicide layer comprises Ge-containing TiSi.

[0133] According to another aspect of the present invention, a semiconductor device includes an insulating layer disposed above a substrate, a plurality of fin structures disposed above the substrate and extending along a first direction in a plan view, a gate structure disposed above a portion of the plurality of fin structures and extending in a second direction intersecting the first direction, a source / drain epitaxial layer, a dielectric layer disposed on an upper surface of the insulating layer, a silicide layer disposed on the source / drain epitaxial layer, and conductive contacts disposed on the silicide layer. The silicide layer comprises a metal element, silicon, and nitrogen. In one or more embodiments above and below, the metal element is Ti. In one or more embodiments above and below, the silicide layer contains at least 20% atomic amounts of nitrogen. In one or more embodiments above and below, the peak nitrogen content in the silicide layer ranges from 50% to 95% atomically.

[0134] The foregoing outlines features of several embodiments or examples to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. A method of fabricating a semiconductor device, the method comprising: forming a source / drain epitaxial layer at a source / drain region disposed above a substrate; forming a nitrogen-containing layer on a surface of the source / drain epitaxial layer by exposing the surface of the source / drain epitaxial layer to a plasma formed from a nitrogen-containing gas while heating the substrate to a temperature of 475 °C or greater, wherein the nitrogen-containing layer is non-planar and has a convexly curved shape toward the substrate; forming a metal layer over the nitrogen-containing layer; and forming an alloy layer of elements of the source / drain epitaxial layer over the source / drain region and based on elements of the metal layer, wherein a portion of the nitrogen-containing layer is retained after forming the alloy layer, and the nitrogen-containing layer is between the source / drain epitaxial layer and the metal layer, and the nitrogen-containing layer includes at least 5% atomic nitrogen.

2. The method of claim 1, wherein, The source / drain epitaxial layer includes SiGe.

3. The method of claim 1, wherein, The nitrogen-containing gas is a mixed gas of N2 and Ar.

4. The method of claim 1, wherein, The alloy layer has a thickness in a range from 4 nm to 10 nm.

5. The method of claim 1, wherein, The metal layer is a Ni layer, a W layer, or a Ta layer.

6. The method of claim 1, wherein, The metal layer includes a Ti layer.

7. The method of claim 1, wherein, The nitrogen-containing layer includes at least 20% atomic nitrogen.

8. The method of claim 7, wherein, The nitrogen-containing layer having at least 20% atomic nitrogen has a thickness in a range from 5 nm to 10 nm.

9. The method of claim 1, wherein, The nitrogen-containing layer has a peak nitrogen amount in a range from 50% atomic to 95% atomic.

10. The method of claim 1, further comprising, after forming the nitrogen-containing layer, performing an anneal operation at a temperature of 475 °C or greater.

11. A method of fabricating a semiconductor device, the method comprising: forming a source / drain epitaxial layer at a source / drain region disposed above a substrate; performing a first implant operation to introduce first ions into the source / drain epitaxial layer; performing a second implant operation to introduce second ions different from the first ions into the source / drain epitaxial layer; performing a first anneal operation; forming a nitrogen-containing layer on a surface of the source / drain epitaxial layer by exposing the surface of the source / drain epitaxial layer to a plasma formed from a nitrogen-containing gas while heating the substrate to a temperature of 475 °C or greater, wherein the nitrogen-containing layer is non-planar and has a convexly curved shape toward the substrate; forming a metal layer over the nitrogen-containing layer; and forming an alloy layer of elements of the source / drain epitaxial layer over the source / drain region and based on elements of the metal layer, wherein a portion of the nitrogen-containing layer is retained after forming the alloy layer, and the nitrogen-containing layer is between the source / drain epitaxial layer and the metal layer, and the nitrogen-containing layer includes at least 5% atomic nitrogen.

12. The method of claim 11, wherein, The source / drain epitaxial layer includes SiGe.

13. The method of claim 12, wherein, The first ions are Ge ions.

14. The method of claim 12, wherein, The second ions include boron.

15. The method of claim 11, wherein, The first anneal operation includes a laser anneal.

16. The method of claim 11, further comprising, after forming the nitrogen-containing layer, performing a second anneal operation at a temperature of 475 °C or greater.

17. A semiconductor device, comprising: a gate structure disposed over a channel region located over a substrate; a source / drain epitaxial layer located at a source / drain region disposed over the substrate; a nitrogen-containing layer disposed on the source / drain epitaxial layer; a silicide layer disposed on the nitrogen-containing layer; a metal nitride layer disposed on the silicide layer; and a conductive contact disposed on the metal nitride layer, wherein the nitrogen-containing layer has a convex curvature shape toward the substrate, and wherein the nitrogen-containing layer includes at least 5% atomic nitrogen. The nitrogen-containing layer includes nitrogen in an amount of at least 20% of atoms.

18. The semiconductor device of claim 17, wherein, The nitrogen-containing layer has a thickness in a range from 5 nm to 10 nm.

19. The semiconductor device of claim 18, wherein, A peak nitrogen amount in the nitrogen-containing layer is in a range from 50% atomic to 95% atomic.

20. The semiconductor device of claim 17, wherein, ​

Images