Semiconductor device and method for manufacturing the same

Abstract

An embodiment of the present invention provides a semiconductor device and a manufacturing method, wherein a metallization layer is located above a substrate, and a power grid line is located in the metallization layer. A signal pad is located in the metallization layer, and the signal pad is surrounded by the power grid line. A signal external connector is electrically connected to the signal pad. Another embodiment of the present invention provides a method for manufacturing a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to the semiconductor field, and in particular, to semiconductor devices and methods for manufacturing the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density comes from the continuous reduction of the minimum feature size (e.g., shrinking semiconductor process nodes to nodes below 20nm), which allows more components to be integrated into a given area. With the recent growth in demand for miniaturization, higher speed and greater bandwidth, as well as lower power consumption and latency, there is an increasing demand for smaller and more creative packaging technologies for semiconductor dies.

[0003] With the further development of semiconductor technology, stacked semiconductor devices such as 3D integrated circuits (3DIC) have emerged, which are effective for further reducing the physical size of semiconductor devices. In stacked semiconductor devices, active circuits such as logic circuits, storage circuits, processor circuits, etc. are manufactured on different semiconductor wafers. Two or more semiconductor wafers can be mounted on top of each other to further reduce the form factor of the semiconductor device. However, in order to further reduce the size and improve the operating characteristics of the device, further improvements are needed. Summary of the invention

[0004] An embodiment of the present application provides a semiconductor device, comprising: a metallization layer located above a substrate; a power grid line located within the metallization layer; a first signal pad located within the metallization layer and surrounded by the power grid line; and a signal external connector electrically connected to the first signal pad.

[0005] An embodiment of the present application provides a semiconductor device, comprising: a signal connector of a first semiconductor device; a through hole of the first semiconductor device, physically contacting the signal connector and a first conductive portion of a metallization layer; and a power grid located within the metallization layer, wherein a first single line of the power grid surrounds the first conductive portion.

[0006] An embodiment of the present application provides a method for manufacturing a semiconductor device, the method comprising: forming a first metallization layer above a first semiconductor substrate, the first metallization layer comprising a power grid having a first line and a signal connector, the first line having a first width along a first direction, the signal connector being adjacent to at least two sides of the first line, the signal connector having a second width along the first direction that is smaller than the first width; and forming a bonding pad metal trace electrically connected to the signal connector. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 A first semiconductor device according to some embodiments is shown;

[0009] Figure 2 is a top view of a power grid according to some embodiments;

[0010] Figure 3 illustrates bonding of a first semiconductor device to a second semiconductor device according to some embodiments;

[0011] Figure 4 shows improvements that can be achieved according to some embodiments;

[0012] Figure 5 shows offset power grid metal traces according to some embodiments;

[0013] Figure 6A-6B A flow chart according to some embodiments is shown. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or structures discussed.

[0015] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0016] Embodiments will now be described with respect to specific embodiments incorporating the concepts into a three-dimensional integrated circuit (3DIC) structure. However, the embodiments are not limited to the precise embodiments described herein and may be incorporated into a wide variety of applications.

[0017] Reference now Figure 1 , a first semiconductor device 100 is shown, which includes a substrate 101, a through substrate via (TSV) 102 extending through the substrate 101, an active device 103 on the substrate 101, an interlayer dielectric (ILD) layer 105 above the active device 103, and a metallization layer 107 above the ILD layer 105. In one embodiment, the first semiconductor device 100 may be a portion of a semiconductor wafer (not shown in full because the rest of the semiconductor wafer is far away). Figure 1 The structure shown in FIG. 1 is extended), for example, for a chip-on-wafer-on-substrate (CoWoS) embodiment. In other embodiments, the first semiconductor device 100 may be separated from a semiconductor wafer, for example, already formed and singulated. Any suitable embodiment may be utilized.

[0018] The substrate 101 may include bulk silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. Typically, an SOI substrate includes a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates. Additionally, the substrate 101 at this point in the process may be a portion of a semiconductor wafer that will be singulated in a subsequent step ( Figure 1 The complete wafer is not shown).

[0019] Within the substrate 101, the TSV 102 may be formed to extend through the substrate 101 to provide a fast path for data signals from a first side of the substrate 101 to a second side of the substrate 101. In one embodiment, the TSV 102 may be formed by first forming a through silicon via (TSV) opening in the substrate 101. The TSV opening may be formed by applying and developing a suitable photoresist and removing a portion of the substrate 101 exposed to a desired depth. The TSV opening may be formed to extend into the substrate 101 so that the depth is greater than the final desired height of the substrate 101. Therefore, although the depth depends on the overall design, the depth may be between about 20 μm and about 200 μm, for example, a depth of about 50 μm.

[0020] Once the TSV openings are formed in the substrate 101, the TSV openings may be lined with a liner. The liner may be an oxide formed, for example, from tetraethyl orthosilicate (TEOS) or silicon nitride, although any suitable dielectric material may be used. The liner may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, although other suitable processes such as physical vapor deposition or thermal treatment processes may be used. Additionally, the liner may be formed to a thickness between about 0.1 μm and about 5 μm, for example about 1 μm.

[0021] Once the liner is formed along the sidewalls and bottom of the TSV opening, a barrier layer can be formed and the remainder of the TSV opening can be filled with a first conductive material. The first conductive material can include copper, although other suitable materials such as aluminum, alloys, doped polysilicon, combinations thereof, etc. can be utilized. The first conductive material can be formed by electroplating copper onto a seed layer, filling, and overfilling the TSV opening. Once the TSV opening is filled, the excess liner, barrier layer, seed layer, and first conductive material outside of the TSV opening can be removed by a planarization process such as chemical mechanical polishing (CMP), although any suitable removal process can be used.

[0022] Once the TSV openings are filled, the second side of the substrate 101 is thinned to expose the openings for the TSVs 102 and form the TSVs 102 by the conductive material extending through the substrate 101. In one embodiment, the thinning of the second side of the substrate 101 may expose the TSVs 102. The thinning of the second side of the substrate 101 may be performed by a planarization process such as CMP or etching.

[0023] Active device 103 Figure 1 100. However, as will be appreciated by those skilled in the art, a wide variety of active devices such as capacitors, resistors, inductors, etc. may be used to generate the desired structural and functional requirements for the design of the first semiconductor device 100. The active device 103 may be formed in or on the surface of the substrate 101 using any suitable method.

[0024] The ILD layer 105 may include a material such as borophosphosilicate glass (BPSG), although any suitable dielectric may be used. The ILD layer 105 may be formed using a process such as PECVD, although other processes such as LPCVD may be used. The ILD layer 105 may be formed to a thickness between about 100 angstroms and about 3000 angstroms.

[0025] Metallization layer 107 is formed over substrate 101, active devices 103, and ILD layer 105 and is designed to connect various active devices 103 to form functional circuits. Figure 1Although shown as two layers in FIG. 1 , the metallization layer 107 is formed by alternating layers of dielectric and conductive materials and may be formed by any suitable process, such as deposition, damascene, dual damascene, etc. In one embodiment, thirteen metallization layers may be separated from the substrate 101 by the ILD layer 105, but the exact number of metallization layers 107 depends on the design of the first semiconductor device 100.

[0026] As part of the metallization layer 107, the top metal layer 111 is formed as the topmost layer within the metallization layer 107. In one embodiment, the top metal layer 111 is the thirteenth metallization layer and includes a dielectric layer 109 and a conductive component 112 formed within the dielectric layer 109. The top metal layer 111 can be formed by first depositing the dielectric layer 109 over the top surface of the layer below the metallization layer 107 (e.g., over the twelfth metallization layer of the metallization layer 107). The dielectric layer 109 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. The dielectric layer can include a dielectric material such as silicon oxide, SiCOH, etc., and can be formed to a first thickness T1 between about 2 μm and about 4 μm, for example, about 3 μm. However, any suitable material, thickness, and deposition method can be utilized.

[0027] Once the dielectric layer 109 has been formed, the dielectric layer 109 may then be etched to form an opening that exposes the top surface of the underlying layer of the metallization layer 107. In one embodiment, the dielectric layer 109 may be etched using, for example, a via-first dual damascene process, whereby a via pattern is patterned and etched at least partially into the dielectric layer 109 using a first mask and etching process. Once the via pattern is etched, a trench pattern is patterned and etched into the dielectric layer 109 using a second mask and etching process, wherein the etching of the trench pattern further extends the via pattern through the dielectric layer 109 to expose the underlying layer (e.g., the twelfth metallization layer of the metallization layer 107).

[0028] However, although a via-first dual damascene structure is described, this is intended to be exemplary only and is not intended to limit the embodiments. Instead, any suitable process or processes may be utilized to form the via openings and trench openings of the top metal layer 111. For example, a trench-first dual damascene process may be utilized, or even multiple single damascene processes. All such processes are fully intended to be included within the scope of the embodiments.

[0029] Once the via openings and the trench openings are formed, the conductive features 112 may be formed by depositing conductive materials in the via openings and the trench openings using, for example, a plating process. In one embodiment, the conductive features 112 may include conductive trenches, and conductive vias that connect the conductive trenches to underlying structures (e.g., the twelfth metallization layer of the metallization layer 107). In one embodiment, the conductive material may be copper, copper alloys, aluminum, aluminum alloys, combinations of these, and the like. However, any suitable material and any suitable formation process may be utilized.

[0030] Once the via openings and trench openings are filled and / or overfilled with conductive material, conductive features 112 may be formed by removing excess material from the exterior of the via openings and trench openings. In one embodiment, the removal may be performed using a planarization process such as a chemical mechanical polishing (CMP) process. However, any suitable removal process may be utilized.

[0031] In one embodiment, the conductive features 112 formed in the dielectric layer 109 are formed to create a plurality of conductive structures in the top metal layer 111, which are conductive structures between the first semiconductor device 100 and the second semiconductor device 300 ( Figure 1 Not shown, but the following Figure 3 In one embodiment, the conductive features 112 will form power grid metal traces 119 and metallized bonding pads 121 within the top metal layer 111. In one embodiment, the metallized bonding pads 121 are used to help route electrical signals (other than power and ground) from the underlying metallization layer 107 to the upper bonding pad metal traces 117 (described further below), so that the electrical signals can be routed to the second semiconductor device 300, or the electrical signals can be received from the second semiconductor device 300.

[0032] In addition, the power grid metal traces 119 form part of a power grid that will be used to provide power and ground connections between the first semiconductor device 100 and the second semiconductor device 300. By providing power between the first semiconductor device 100 and the second semiconductor device 300, other connections that are not routed through the 3DIC stack (e.g., the stack of the first semiconductor device 100, the second semiconductor device, and any other semiconductor devices within the stack) become unnecessary and can be omitted. This omission can further reduce the surface area required for the stack, thereby achieving a smaller overall device.

[0033] Although power grid metal traces 119 and metallized bond pads 121 are shown, this is intended to be illustrative and not limiting. Instead, any suitable number of other structures may also be located within the top metal layer 111 of the metallization layer 107. All such structures and combinations of structures may be utilized, and all such combinations are fully intended to be included within the scope of the embodiments.

[0034] However, by stacking the first semiconductor device 100 and the second semiconductor device 300 (or even stacking more semiconductor devices not shown separately), the total power consumption is at least twice that of a more traditional two-dimensional design (e.g., n times the number of semiconductor devices located within the stack) or more, thereby eliminating a traditional two-dimensional power grid design.

[0035] In view of the increased power consumption, in some embodiments, the power grid may arrange the individual power grid metal traces 119 into a series of strips located within the top metal layer 111. From the perspective of the power grid, ideally, the individual strips extend continuously across the entire bonding surface of the first semiconductor device 100. However, the presence of the metallized bonding pads 121 and the need to connect the metallized bonding pads 121 to the bonding pad metal traces 117 (e.g., for transmitting signals to and from the second semiconductor device 300) prevents the ideal situation from being fully realized because the introduction of the metallized bonding pads 121 for the signals interrupts and destroys the power grid metal traces 119 into individual segments of reduced length. If this is not handled properly (as described below with respect to Figure 2 ), will increase the overall resistance of the power grid metal trace 119 and result in a higher IR drop in the entire power grid.

[0036] Figure 1 Also shown is a dielectric bonding layer 113 formed over the metallization layer 107. The dielectric bonding layer 113 may be used as a hybrid bonding (hereinafter referred to as Figure 3 A portion of the dielectric bonding layer 113 is used for fusion bonding (also referred to as inter-oxide bonding) according to some embodiments. The dielectric bonding layer 113 is formed by a silicon-containing dielectric material such as silicon oxide, silicon nitride, etc. The dielectric bonding layer 113 may be deposited using any suitable method such as CVD, high-density plasma chemical vapor deposition (HDPCVD), PVD, atomic layer deposition (ALD), etc., and has a thickness between about 0.65 μm and about 6 μm, for example, about 5.5 μm. However, any suitable material, deposition process, and thickness may be utilized.

[0037] Once formed, the dielectric bonding layer 113 may be planarized to provide a planar surface for further processing. In one embodiment, a planarization process such as CMP may be used to planarize the dielectric bonding layer 113. However, any other suitable planarization process may also be used.

[0038] Once the dielectric bonding layer 113 is formed, an opening is formed in the dielectric bonding layer 113 to expose the metallized bonding pad 121 (eg, Figure 1 ) and power grid metal trace 119 (in Figure 1 The conductive portions of the metallization layer 107 (not separately shown) are removed in preparation for forming the bonding pad through hole trace (BPVT) 115. In one embodiment, a photoresist is applied over the top surface of the dielectric bonding layer 113, and then the photoresist is used together with one or more etches to etch the dielectric bonding layer 113 to form an opening. The etching used to form the opening may include dry etching (e.g., RIE or NBE), wet etching, etc. According to some embodiments of the present invention, the etching stops on the metallization layer 107, thereby exposing the conductive portions of the metallization bonding pad 121 and the power grid metal trace 119 through the opening in the dielectric bonding layer 113. However, any suitable process may be utilized.

[0039] The second opening in the dielectric bonding layer 113 is also utilized to widen a portion of the opening in preparation for forming a bonding pad metal trace (BPMT) 117. In one embodiment, another photoresist is applied over the top surface of the dielectric bonding layer 113. The patterned photoresist is then used to etch the dielectric bonding layer 113 to form the second opening. The dielectric bonding layer 113 may be etched by dry etching (e.g., RLE or NBE), wet etching, etc.

[0040] Once the opening and the second opening are formed in the dielectric bonding layer 113, the opening and the second opening may be filled with a seed layer and plated metal to form a bonding pad via trace 115 and a bonding pad metal trace 117 (in Figure 11, but may or may not be physically separated in the final structure). The seed layer may cover the top surface of the dielectric bonding layer 113, the exposed conductive portions of the metallized bonding pads 121 and the power grid metal traces 119, and the sidewalls of the opening and the second opening. The seed layer may include a copper layer. Depending on the desired material, the seed layer may be deposited using processes such as sputtering, evaporation, or plasma enhanced chemical vapor deposition (PECVD). The plated metal may be deposited over the seed layer by a plating process such as electroplating or chemical plating. The plated metal may include copper, copper alloys, etc. The plated metal may be a filling material. In front of the seed layer, a barrier layer (not shown separately) may cover the top surface of the dielectric bonding layer 113, the exposed conductive portions of the power grid metal traces 119 and the metallized bonding pads 121, and the sidewalls of the opening and the second opening. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0041] After filling the opening and the second opening, a planarization process such as CMP is performed to remove the excess portion of the seed layer and the plated metal, thereby forming a bonding pad via trace 115 and a bonding pad metal trace 117. In some embodiments, the bonding pad via trace 115 is used to connect the bonding pad metal trace 117 with the underlying metallization bonding pad 121, and through the underlying metallization bonding pad 121, the bonding pad metal trace 117 is connected to the underlying metallization layer 107 and the active device 103.

[0042] In addition, the bonding pad metal trace 117 is used to physically bond and electrically connect the first semiconductor device 100 to the second semiconductor device 300 above (in Figure 1 Not shown, but the following Figure 3 Utilizing the electrical connection between the bonding pad metal trace 117 and the second semiconductor device 300 , the bonding pad metal trace 117 may be used to send and / or receive electrical signals between the first semiconductor device 100 and the second semiconductor device 300 .

[0043] In one embodiment, the bond pad via trace 115 may be sized as a via to transmit electrical signals between the metallized bond pad 121 and the bond pad metal trace 117 to facilitate transmitting signals between the first semiconductor device 100 and the second semiconductor device 300. In some embodiments, the bond pad via trace 115 may be shaped as a circle (in a top view) with a diameter of a first distance D1 between about 1.25 μm and about 2.5 μm, such as about 1.8 μm. However, any suitable size may be utilized.

[0044] Similarly, the size setting of the bonding pad metal trace 117 can not only facilitate signal transmission between the first semiconductor device 100 and the second semiconductor device 300, but also facilitate the bonding of the first semiconductor device 100 and the second semiconductor device 300. In a specific embodiment, the bonding pad metal trace 117 can be shaped as a circle (in a top view) with a diameter of the second distance D2 between about 1.5 μm and about 2.5 μm, such as about 2.5 μm. However, any suitable size can be utilized.

[0045] Figure 2 A top view of a first semiconductor device 100 is shown, wherein Figure 1 is along Figure 2 The line 1-1' in Figure 2 A cross-sectional view of Figure 2 Shown along line 2-2' (for clarity, from Figure 2 The dielectric bonding layer 113 is removed Figure 1 Top view of the . Figure 2 Two power grid metal traces 119 are shown, which are formed into power grid strips, which reduce IR drop by incorporating holes 201 in each power grid metal trace 119. Through the incorporated holes 201, the bond pad metal traces 117 for the signal can be positioned through the holes 201 in the power grid metal traces 119 without causing the power grid metal traces 119 to be segmented into different parts that are separated from each other. In this way, the power grid metal traces 119 are not separated and segmented, so that the overall resistance of the power grid can be reduced, and the IR drop through the power grid will be less.

[0046] In one embodiment, the power grid metal trace 119 may include a plurality of parallel strips (e.g., a plurality of power grid metal traces 119 parallel to each other). In a particular embodiment, the power grid metal trace 119 is sized to be large enough to accommodate the hole 201 for the bond pad metal trace 117, the bond pad via trace 115 thereon, and the metallized bond pad 121 thereon. In one embodiment, the power grid metal trace 119 is sized to have a first width W1 that is as large as possible given the overall design of the first semiconductor device 100 and the minimum and maximum pitch provided by the particular technology node used to manufacture the first semiconductor device 100. Thus, while the first width W1 depends at least in part on the technology node of the semiconductor manufacturing process, in one embodiment, the first width W1 may be between about 0.36 μm and about 10.8 μm, for example, about 10.8 μm. However, any suitable width may be utilized.

[0047] In addition, each power grid metal trace 119 has a first overlap length L1 (the distance where one power grid metal trace 119 is directly adjacent to a second power grid metal trace 119), which is equal to the length of the power grid metal trace 119 and is sufficient to provide a desired path for power and ground. Figure 2 In the illustrated embodiment, adjacent power grid metal traces 119 are formed to have the same length and are positioned so that the first overlap length L1 may be greater than about 4.05 μm, for example, about 50 μm, although the minimum value will at least partially vary with different process nodes, and the maximum length depends at least in part on the overall design and the area on the chip. In addition, adjacent power grid metal traces 119 have ends that abut each other, so that the entire length of one power grid metal trace 119 overlaps with an adjacent one of the power grid metal traces 119. However, any suitable length may be utilized.

[0048] To ensure proper separation between the metallized bonding pad 121 and the power grid metal trace 119, the metallized bonding pad 121 may be spaced a third distance D3 away from the power grid metal trace 119 (e.g., through the dielectric layer 109). In some embodiments, the third distance D3 depends at least in part on the first width W1 and the first overlap length L1 of the power grid metal trace 119. In one embodiment, as long as the first threshold has been reached, the third distance D3 may be a fraction of the smaller of the first width W1 or the first overlap length L1, or may be a fraction of the first threshold itself. For example, the first fraction may be about one-third, and the first threshold may be between about 1.35 μm and about 4.05 μm, for example about 1.35 μm.

[0049] In addition, in some embodiments, multiple thresholds may be used. For example, if both the first width W1 and the first overlap length L1 satisfy the first threshold, a second threshold higher than the first threshold may also be used. In such an embodiment, if both the first width W1 and the first overlap length L1 satisfy both the first threshold and the second threshold, the third distance D3 may be set to a first fraction of any one of the first width W1, the first overlap length L1, or the second threshold.

[0050] To illustrate these issues, in a specific embodiment where the first threshold is the only threshold and is 1.35 μm, the third distance D3 can be determined by first determining whether the first overlap length L1 and the first width W1 are both greater than the first threshold of 1.35 μm. If both are greater than the first threshold, the third distance D3 can be determined by multiplying the first threshold by the first fraction. In an embodiment where the first fraction is one-third and the first threshold is 1.35 μm, the third distance D3 can be 0.45 μm.

[0051] In another embodiment using multiple thresholds, the first fraction can remain one-third, and the first threshold can be set to 1.35 μm and the second threshold can be set to 4.05 μm. In this embodiment, if the first width W1 and the first overlap length L1 are both greater than the first threshold (e.g., greater than 1.35 μm) and are also greater than the second threshold (e.g., greater than 4.05 μm), the third distance D3 is set to one-third of the second threshold of 4.05 μm. In this way, the third distance D3 is at least 1.35 μm.

[0052] In another embodiment using multiple thresholds, the first width W1 and the first overlap length L1 may both be greater than the first threshold, but one of them may be less than the second threshold. In such an embodiment, since the condition of the second threshold is not met, the third distance D3 may be set to the first threshold instead of the first fraction of the second threshold.

[0053] In addition, a first spacing S1 separates the first power grid metal trace 119 from the second power grid metal trace 119. In one embodiment, the first spacing S1 can be determined according to the above pattern and can be the same as the third distance D3. For example, the first spacing S1 can be determined by comparing the first width W1 and the first overlap length L1 to a first threshold (a second threshold in some embodiments), and then using the first threshold, the second threshold, the first width W1, or a fraction of the first overlap length L1 to determine the desired spacing. However, any suitable spacing can be used.

[0054] In one embodiment, the metallized bonding pad 121 may also have a second width W2 between about 0.36 μm and about 10.8 μm, for example about 1.96 μm. Similarly, the power grid metal trace 119 may have a third width W3 extending from the hole 201 to the sidewall of the power grid metal trace 119. In one embodiment, the third width W3 may be about 3.97 μm. However, any suitable width may be utilized.

[0055] Figure 3The bonding of the first semiconductor device 100 to the second semiconductor device 300 is shown. In one embodiment, the second semiconductor device 300 is designed to be bonded to the first semiconductor device 100 and functionally work together with it to provide the desired functionality. In embodiments where the first semiconductor device 100 is, for example, a logic die, a central processing unit (CPU) die, a memory die (e.g., a DRAM die), a combination thereof, etc., the second semiconductor device 300 can be designed to be a device that works with and / or supports the logic die, for example, by being a memory device, a power die, a sensor die, a combination thereof, etc. However, any suitable combination of functionality between the first semiconductor device 100 and the second semiconductor device 300 can be utilized.

[0056] In one embodiment, the second semiconductor device 300 may have a similar structure to the first semiconductor device 100. For example, the second semiconductor device 300 may include a second substrate 302 (similar to substrate 101), a second active device 303 (similar to active device 103), a second ILD layer 305 (similar to ILD layer 105), a second metallization layer 307 (similar to metallization layer 107), a second top metal layer 311 (similar to top metal layer 111), a second power grid metal trace 319 (similar to power grid metal trace 119), a second bonding pad via trace 315 (similar to bonding pad via trace 115), a second metallization bonding pad 321 (similar to metallization bonding pad 121), a second bonding pad metal trace 317 (similar to bonding pad metal trace 117), and a second dielectric bonding layer 313 (similar to dielectric bonding layer 113). However, any suitable structure may be utilized.

[0057] In some embodiments, the first semiconductor device 100 is bonded to the second semiconductor device 300 by, for example, hybrid bonding. After planarizing the top surfaces of the first semiconductor device 100 and the second semiconductor device 300, the top surfaces of the first semiconductor device 100 and the second semiconductor device 300 may be activated. As an example, activating the top surfaces of the first semiconductor device 100 and the second semiconductor device 300 may include dry processing, wet processing, plasma processing, exposure to an inert gas plasma, exposure to H2, exposure to N2, exposure to O2, or a combination thereof. In an embodiment using wet processing, for example, RCA cleaning may be used. In another embodiment, the activation process may include other types of processing. The activation process facilitates hybrid bonding of the first semiconductor device 100 and the second semiconductor device 300; advantageously allowing lower pressures and temperatures to be used in subsequent hybrid bonding processes.

[0058] After the activation process, the first semiconductor device 100 and the second semiconductor device 300 may be placed in contact. In a specific embodiment utilizing hybrid bonding, the bond pad metal trace 117 is placed in physical contact with the second bond pad metal trace 317, and the dielectric bonding layer 113 is placed in physical contact with the second dielectric bonding layer 313. The bonding process between materials begins with physical contact by chemically modifying the surface through the activation process.

[0059] Once the physical contact begins the bonding process, the bond can be strengthened by subjecting the components to heat treatment and contact pressure. In one embodiment, the first semiconductor device 100 and the second semiconductor device 300 can be subjected to a pressure of about 200 kPa or less and a temperature between about 200° C. and about 400° C. to enhance the bond between the dielectric bonding layer 113 and the second dielectric bonding layer 313. The first semiconductor device 100 and the second semiconductor device 300 can then be subjected to a temperature equal to or higher than the eutectic point of the material of the bonding pad metal trace 117, for example, between about 150° C. and about 650° C., to fuse the bonding pad metal trace 117 to the second bonding pad metal trace 317. In this way, the fusion of the first semiconductor device 100 and the second semiconductor device 300 forms a hybrid bonded device.

[0060] In addition, although specific processes for initiating and strengthening the hybrid bonding between the first semiconductor device 100 and the second semiconductor device 300 have been described, these descriptions are intended to be illustrative and not intended to limit the embodiments. Instead, any suitable combination of baking, annealing, pressing, or other bonding processes or process combinations may be used. All such processes are fully intended to be included within the scope of the embodiments.

[0061] In addition, although hybrid bonding is described as a method of bonding the first semiconductor device 100 to the second semiconductor device 300, this is only intended to be illustrative and not intended to limit the embodiments. Instead, any suitable bonding method may be utilized, such as fusion bonding, copper-copper bonding, etc., or even solder bonding using, for example, a ball grid array. Any suitable method of bonding the first semiconductor device 100 to the second semiconductor device 300 may be utilized.

[0062] Finally, other features and processes may also be included. For example, a test structure may be included to assist in verification testing of 3D packages or 3DIC devices. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows the 3D package or 3DIC to be tested using a probe and / or a probe card, etc. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method for intermediate verification of a known good die to increase yield and reduce costs.

[0063] During operation, each power grid metal trace 119 within the power grid can be connected to power or ground. In this way, the power grid can be used to provide power between the first semiconductor device 100 and the second semiconductor device 300. Similarly, the metallized bonding pad 121 can be connected to an active device or other structure so that an electrical signal (not simply power or ground) can be transmitted between the first semiconductor device 100 and the second semiconductor device 300.

[0064] Figure 4 1 shows a comparison of the IR drop that can be achieved by positioning the bond pad metal trace 117 for electrical signals through the power grid metal trace 119. In particular, the graph shows that the Y-axis represents the percentage of static IR drop, while the X-axis represents the percentage of IO connections that are signals (as opposed to power / ground IO connections). It can be seen that when using a heavily segmented power grid metal trace 119 (in Figure 4 In a semiconductor device (represented by the line labeled 401 in FIG. 1 ), the worst-case IR drop increases significantly with the addition of more IO connections for signals (eg, the line moves to the right along the x-axis) and the segmentation of the power grid metal trace 119.

[0065] However, when the IO connection is located within the hole 201 of the power grid metal trace 119 (in Figure 4 As shown in FIG. 1 , the static IR drop is significantly reduced as additional IO connections are added for the signals, and may be improved for up to 80% of the IO signal net connections. In addition, the IR drop of this embodiment with vias 201 approaches the fully realized, unsegmented ideal case scenario of IR drop, as represented by the line labeled 405. Thus, by avoiding segmenting the power grid metal trace 119 by utilizing vias 201, the total IR drop caused by the positioning of the IO connections can be minimized or even eliminated, resulting in an overall more efficient operation.

[0066] Figure 5Another embodiment that can be used to help reduce the spacing between the first power grid metal trace 119 and the second power grid metal trace 119 to a second spacing S2 is shown. In this embodiment, one power grid metal trace 119 is offset from an adjacent one power grid metal trace 119. By offsetting the first power grid metal trace 119 and the second power grid metal trace 119, a second overlap length L2 between the first power grid metal trace 119 and the second power grid metal trace 119 (e.g., the distance where one power grid metal trace 119 and the second power grid metal trace are directly adjacent to each other) is reduced. By reducing this distance, interference between the first power grid metal trace 119 and the second power grid metal trace 119 can be reduced.

[0067] In addition, the first width W depends on l and overlap distance (as mentioned above Figure 2 By reducing the second overlap length L2 without reducing the total length of the first power grid metal trace 119 or the second power grid metal trace 119, the second overlap length L2 can be reduced by offsetting the power grid metal trace 119 without reducing the total length of the first power grid metal trace 119 or the second power grid metal trace 119. By reducing the second overlap length L2 without reducing the actual length, in embodiments utilizing multiple thresholds (e.g., the first threshold and the second threshold), the second overlap length L2 can drop below one threshold (e.g., the second threshold), which allows the second spacing S2 to be set to a first fraction of the first threshold (rather than being set to a first fraction of the second threshold). In this way, the second spacing S2 can be reduced, thereby allowing the first power grid metal trace 119 to be placed closer to the second power grid metal trace 119. By placing the power grid metal traces 119 closer to each other, additional via path options are available, and more via paths can be implemented in the same area.

[0068] In a specific embodiment, the second overlap length L2 can be reduced to a length that allows a reduction in the second spacing S2 (e.g., between the first power grid metal trace 119 and the second power grid metal trace 119). In some embodiments, the second overlap length L2 can be reduced to between about 1.35 μm and about 4.05 μm, such as about 3 μm. However, any suitable overlap spacing can be utilized.

[0069] By reducing the second overlap length L2, the second spacing S2 can also be reduced because there is less interference between the first power grid metal trace 119 and the second power grid metal trace 119. In some embodiments, the second spacing S2 can be reduced (based on the first threshold and the second threshold in some embodiments) to between about 0.45 μm and about 1.35 μm, for example, about 0.45 μm. However, any suitable spacing can be utilized.

[0070] exist Figure 5 In yet another embodiment shown, in addition to reducing the second overlap length L2 by offsetting the first power grid metal trace 119 from the second power grid metal trace 119, the holes 201 in each power grid metal trace 119 are offset or misaligned with the holes 201 in an adjacent one of the power grid metal traces 119 while being aligned with each other along the first direction in their respective power grid metal traces 119. By offsetting the holes 201 in adjacent power grid metal traces 119, the distance between the bond pad via traces 115 in adjacent power grid metal traces 119 is increased to a fourth distance D4. In one embodiment, the fourth distance D4 may be between about 6 μm and about 50 μm, such as about 9 μm. However, any suitable distance may be utilized and may depend at least in part on the precise processing node utilized.

[0071] By placing the metallized bond pads 121 within the holes 201 of the lines of the power grid metal traces 119 so that the metallized bond pads 121 are adjacent to at least two sides of the power grid metal traces 119, the metallized bond pads 121 for sending and receiving signals between semiconductor devices can be placed without having to separate and segment the lines of the power grid metal traces 119. By keeping the power grid metal traces 119 continuous and unsegmented, the IR drop through the power grid metal traces 119 can be reduced. In addition, by offsetting the power grid metal traces 119 and the holes 201 from each other, adjacent power grid metal traces 119 can be placed closer together, allowing additional space savings to be achieved. All of these advantages allow for smaller and more efficient devices.

[0072] Fig. 6A A flow chart for determining the third distance D3 in an embodiment where the first threshold is the only threshold utilized is shown. In a first step 601, a first width W1, a first overlap length L1, and a first threshold T1 are received. In step 603, a determination is made to see if both the first width W1 and the first overlap length L1 are greater than the first threshold T1. If both the first width W1 and the first overlap length L1 are greater than the first threshold T1, then in step 605 the third distance D3 is set to a first fraction of the smallest of the first width W1, the first overlap length L1, or the first threshold T1. However, any suitable steps in any order may be utilized.

[0073] Figure 6BAnother flow chart for determining the third distance D3 in an embodiment where the first threshold is used together with the second threshold is shown. In a first step 607, a first width W1, a first overlap length L1, a first threshold T1, and a second threshold T2 are received. A determination is made in a second step 609 to determine whether the first width W1 and the first overlap length L1 are both greater than both the first threshold T1 and the second threshold T2. If the determination is yes, the third distance D3 is set to a first fraction of the minimum of the first width W1, the first overlap length L1, and the second threshold T2 in a third step 611. If the determination is no, a determination is made in a fourth step 613 to see whether the first width W1 and the first overlap length L1 are both greater than the first threshold T1. If yes, the third distance D3 is set to a first fraction of the first threshold T1. However, any suitable steps in any order may be utilized.

[0074] According to one embodiment, a semiconductor device includes: a metallization layer located above a substrate; a power grid line located within the metallization layer; a first signal pad located within the metallization layer and surrounded by the power grid line; and a signal external connector electrically connected to the first signal pad. In one embodiment, the semiconductor device also includes a bonding pad via trace that physically contacts the first signal pad and the signal external connector. In one embodiment, the semiconductor device also includes a semiconductor device that is bonded to the signal external connector. In one embodiment, the semiconductor device is bonded using hybrid bonding. In one embodiment, the semiconductor device also includes a second signal pad located within the metallization layer and surrounded by the power grid line. In one embodiment, the first signal pad is separated from the power grid line by a dielectric material. In one embodiment, the dielectric material has a width of approximately 0.45 μm.

[0075] According to another embodiment, a semiconductor device includes: a metallization layer located above a substrate; a power grid line located within the metallization layer; a first signal pad located within the metallization layer and surrounded by the power grid line; and a signal external connector electrically connected to the first signal pad. In one embodiment, the first signal pad is separated from the power grid line by a dielectric material. In one embodiment, the dielectric material has a width between about 0.45 μm and about 1.35 μm.

[0076] According to another embodiment, a semiconductor device includes: a signal connector of a first semiconductor device; a through hole of the first semiconductor device, the through hole physically contacting the signal connector and a first conductive portion of a metallization layer; and a power grid, the power grid being located within the metallization layer, wherein a first single line of the power grid surrounds the first conductive portion. In one embodiment, the semiconductor device further includes: a second conductive portion of the metallization layer; a second single line of the power grid, the second single line surrounding the second conductive portion, the second single line being different from the first single line; and a second through hole of the first semiconductor device, the second through hole physically contacting the second conductive portion of the metallization layer and a second external connector. In one embodiment, the first conductive portion and the second conductive portion are aligned with each other. In one embodiment, the first conductive portion and the second conductive portion are not aligned with each other. In one embodiment, the first single line is separated from the second single line by a distance of about 0.45 μm. In one embodiment, the first single line has a width of about 10.8 μm. In one embodiment, the first conductive portion has a width of about 1.96 μm.

[0077] According to another embodiment, a semiconductor device includes: a signal connector of a first semiconductor device; a through-hole of the first semiconductor device, physically contacting the signal connector and a first conductive portion of a metallization layer; and a power grid located within the metallization layer, wherein a first single line of the power grid surrounds the first conductive portion. In one embodiment, the first single line has a width between about 0.36 μm and about 10.8 μm. In one embodiment, the first conductive portion has a width between about 0.36 μm and about 10.8 μm.

[0078] According to yet another embodiment, a method for manufacturing a semiconductor device includes: forming a first metallization layer over a first semiconductor substrate, the first metallization layer including a power grid having a first line and a signal connector, the first line having a first width along a first direction, the signal connector being adjacent to at least two sides of the first line, the signal connector having a second width along the first direction that is less than the first width; and forming a bonding pad metal trace electrically connected to the signal connector. In one embodiment, the method also includes hybrid bonding the semiconductor die to the bonding pad metal trace. In one embodiment, the method also includes sending an electrical signal through the bonding pad metal trace. In one embodiment, the method also includes connecting the power grid to a power source. In one embodiment, the first line surrounds the signal connector in a top view. In one embodiment, the first line is continuous from a first point to a second point, the first point is adjacent to a first side of the signal connector, the second point is adjacent to a second side of the signal connector, and the second side of the signal connector is opposite to the first side of the signal connector.

[0079] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a metallization layer located above the substrate; A power grid line located in the metallization layer; a first signal pad located within the metallization layer and surrounded on each side by the power grid line; and a signal external connector electrically connected to the first signal pad through a through hole, the signal external connector being coplanar with a dielectric material covering a sidewall of the signal external connector; a second signal pad located within the metallization layer and surrounded on each side by a second power grid line different from the power grid line, the second signal pad being electrically connected to at least one second active device on the substrate; and a second through hole, physically contacting both the second signal pad and the second signal external connector, Wherein, the first signal pad surrounded by the power grid line and the second signal pad surrounded by the second power grid line are respectively located in different rows where the power grid line and the second power grid line are located, and wherein the second power grid line is offset from the power grid line, and the second signal pad is offset from the first signal pad. 2 . The semiconductor device of claim 1 , further comprising a bond pad via trace physically contacting the first signal pad and the signal external connector. 3 . The semiconductor device according to claim 1 , further comprising a semiconductor device bonded to the signal external connection.

4. The semiconductor device according to claim 3, wherein: The semiconductor device is bonded using hybrid bonding. 5 . The semiconductor device of claim 1 , further comprising a second signal pad located within the metallization layer and surrounded by the power grid line.

6. The semiconductor device according to claim 1, wherein The first signal pad is separated from the power grid line by a dielectric material.

7. The semiconductor device according to claim 6, wherein: The dielectric material has a width between 0.45 μm and 1.35 μm.

8. A semiconductor device comprising: a signal connection of a first semiconductor device; The through hole of the first semiconductor device physically contacts the signal connection and the first conductive portion of the metallization layer; a power grid located within the metallization layer, wherein a first single line of the power grid surrounds each side of the first conductive portion; a second conductive portion of the metallization layer; and a second single line of the power grid surrounding each side of the second conductive portion, the second single line being different from the first single line, wherein the first conductive portion surrounded by the first single wire and the second conductive portion surrounded by the second single wire are respectively located in different rows where the first single wire and the second single wire are located, and wherein the second single wire is offset from the first single wire, and the second conductive portion is offset from the first conductive portion.

9. The semiconductor device according to claim 8, further comprising: A second via of the first semiconductor device physically contacts the second conductive portion of the metallization layer and a second external connection.

10. The semiconductor device according to claim 9, wherein The first conductive portion and the second conductive portion are aligned with each other.

11. The semiconductor device according to claim 9, wherein: The first conductive portion and the second conductive portion are not aligned with each other.

12. The semiconductor device according to claim 9, wherein: The first single line is separated from the second single line by a distance between 0.45 μm and 1.35 μm.

13. The semiconductor device according to claim 8, wherein: The first single line has a width between 0.36 μm and 10.8 μm.

14. The semiconductor device according to claim 13, wherein: The first conductive portion has a width between 0.36 μm and 10.8 μm.

15. A method for manufacturing a semiconductor device, the method comprising: forming a first metallization layer over a first semiconductor substrate, the first metallization layer comprising a power grid having a first line and a second line different from the first line, and a signal connector and a second signal connector, the first line having a first width along a first direction, the signal connector being adjacent to at least two sides of the first line, the signal connector having a second width along the first direction that is smaller than the first width; and forming a bonding pad metal trace electrically connected to the signal connector, wherein the first line surrounds each side of the signal connector, the second line surrounds each side of the second signal connector, the signal connector and the second signal connector are located in different rows from the first line and the second line, respectively, and wherein the second line is offset from the first line and the second signal connector is offset from the signal connector.

16. The method of claim 15, further comprising hybrid bonding a semiconductor die to the bond pad metal trace.

17. The method of claim 15, further comprising routing an electrical signal through the bond pad metal trace.

18. The method of claim 17, further comprising connecting the power grid to a power source.

19. The method according to claim 15, wherein: The first line surrounds the signal connector in a top view.

20. The method according to claim 15, wherein: The first line is continuous from a first point adjacent to a first side of the signal connector to a second point adjacent to a second side of the signal connector, the second side of the signal connector being opposite to the first side of the signal connector.

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