A method for quantifying network load rate before architecture design, electronic device and storage medium

Abstract

The present invention discloses a method for quantifying the network load rate before architecture design, an electronic device and a storage medium. It determines the time difference and buffer size between two buffer reads by the ECU based on the way the ECU reads the buffer, calculates the theoretical load rate that the ECU can bear based on the time difference and buffer size, calculates the actual load rate that the ECU can bear based on the theoretical load rate that the ECU can bear and a set proportional coefficient, and determines the network load rate based on the actual load rates that all ECUs can bear. Before the network architecture is designed, the present invention determines the network load rate based on the characteristics and working parameters of all ECUs. The method is simple, and the network architect can know the load rate tolerance range, so that a more perfect arrangement and layout can be made when discussing specific function definitions and information interactions, thereby preventing the later adjustments from bringing about greater resource investment.

Description

Technical Field

[0001] The present invention belongs to the field of automobile technology, and in particular relates to a method for quantifying a network load rate before architecture design. Background Art

[0002] With the increasing number of automotive electronics, the number of nodes through communication methods such as CAN (FD), LIN, FlexRay, Ethernet, etc. has also increased, and the cost of wiring harnesses has been reduced while ensuring the quality and reliability of communication. At present, the functions of the entire vehicle are constantly increasing, and the network architecture is constantly updated, but the limited communication load capacity has greatly restricted the expansion of functional nodes. At present, there is no clear way to quantify the bus load rate before the architecture design. There is no unified conclusion on how much is appropriate. Generally, after the function is defined, the communication matrix is ​​output based on experience or the existing platform, and then the load rate is obtained through simulation analysis. This process needs to be repeated several times to achieve better requirements, which takes a long time and is inefficient. Summary of the invention

[0003] The purpose of the present invention is to solve the deficiencies of the above-mentioned background technology and provide a method for quantifying the network load rate before architecture design.

[0004] The technical solution adopted by the present invention is: a method for quantifying the network load rate before architecture design, determining the time difference and buffer size between two buffer readings by the ECU based on the way the ECU reads the buffer, calculating the theoretical tolerable load rate of the ECU based on the time difference and the buffer size, calculating the actual tolerable load rate of the ECU based on the theoretical tolerable load rate of the ECU and a set proportional coefficient, and determining the network load rate based on the actual tolerable load rates of all ECUs.

[0005] Furthermore, the ECU reads the buffer in an interrupt mode.

[0006] Furthermore, the ECU reads the buffer in a polling manner.

[0007] Furthermore, the size of the buffer is calculated by the following formula:

[0008] m=t*M / T

[0009] Where M is the number of bus messages, t is the time it takes for the ECU to process the number of bus messages M, and T is the time difference between two buffer reads.

[0010] Furthermore, the theoretical load rate that the ECU can bear is calculated by the following formula:

[0011]

[0012] Among them, f k is the theoretically tolerable load rate, m is the buffer size, L is the message length; R b Communication transmission rate, T is the time difference between two buffer reads.

[0013] Furthermore, the actual tolerable load rate of the ECU is calculated by the following formula:

[0014] f0=f k *N,

[0015] Among them, f0 is the actual load rate that can be tolerated, f k is the theoretically tolerable load rate, and N is the proportionality coefficient.

[0016] Furthermore, the proportional coefficient is a calibrated value, and the proportional coefficients of different ECUs are set separately.

[0017] Furthermore, the actual tolerable load rates of all ECUs are compared, and the minimum value of the actual tolerable load rates of all ECUs is taken as the network load rate.

[0018] An electronic device comprising

[0019] A memory for storing one or more programs;

[0020] processor;

[0021] When the one or more programs are executed by the processor, any of the above methods is implemented.

[0022] A computer-readable storage medium stores a computer program, which implements any of the above methods when executed by a processor.

[0023] The present invention determines the network load rate based on the characteristics and working parameters of all ECUs before the network architecture is designed. The method is simple and can let the network architect know the load rate tolerance range, so as to make a more perfect arrangement when discussing specific function definitions and information interaction, and prevent the subsequent adjustment from bringing about greater resource investment. DETAILED DESCRIPTION

[0024] The specific embodiments of the present invention are further described below. It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0025] The present invention provides a method for quantifying a network load rate before architecture design. The method determines the time difference between two buffer readings by the ECU and the buffer size based on the way the ECU reads the buffer, calculates the theoretical tolerable load rate of the ECU according to the time difference and the buffer size, calculates the actual tolerable load rate of the ECU based on the theoretical tolerable load rate of the ECU and a set proportional coefficient, and determines the network load rate according to the actual tolerable load rates of all ECUs, specifically comparing the actual tolerable load rates of all ECUs, and taking the minimum value of the actual tolerable load rates of all ECUs as the network load rate.

[0026] In the above scheme, the ECU reads the buffer in an interrupt mode or a polling mode, but is not limited to these two modes and may also be other modes.

[0027] In the above solution, the buffer size is calculated by the following formula

[0028] m=t*M / T

[0029] Where M is the number of bus messages, t is the time it takes for the ECU to process the number of bus messages M, and T is the time difference between two buffer reads.

[0030] In the above scheme, the theoretical load rate that the ECU can bear is calculated by the following formula:

[0031]

[0032] Among them, f k is the theoretically tolerable load rate, m is the buffer size, L is the message length; R b Communication transmission rate, T is the time difference between two buffer reads.

[0033] In the above scheme, the actual load rate that the ECU can bear is calculated by the following formula:

[0034] f0=f k *N,

[0035] Among them, f0 is the actual load rate that can be tolerated, f k is the theoretically tolerable load rate, N is the proportional coefficient, the proportional coefficient is the calibrated value, and the proportional coefficients of different ECUs are set separately.

[0036] In actual calculation, the theoretical load rate and proportional coefficient of all ECUs are expressed in the form of element matrix, such as F = [f1, f2, f3, f4, ... fn], where F is the element matrix, fn is the theoretical load rate of the nth ECU, Nn is the proportional coefficient of the nth ECU.

[0037] According to the empirical value, the recommended theoretical load rate is 100%, and the actual design is 80%. Therefore, after adopting the quantization method of the present invention, the bus load rate is accurately 80% under the premise of meeting the T and m value requirements.

[0038] The present invention also provides an electronic device, including a memory and a processor, wherein the memory is used to store one or more programs; when the one or more programs are executed by the processor, the above-mentioned network load rate quantification method is implemented. The electronic device can be, but is not limited to, a smart phone, a personal computer (PC), a tablet computer, a personal digital assistant (PDA), etc.

[0039] If the functions implemented by the above-mentioned network load rate quantification method are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in the embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0040] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. The contents not described in detail in this specification belong to the prior art known to professional and technical personnel in the field.

Claims

1. A method for quantifying network load rate before architecture design, characterized by: Determine the time difference and buffer size between two buffer readings by the ECU based on the buffer reading method of the ECU, calculate the theoretical load rate of the ECU based on the time difference and buffer size, calculate the actual load rate of the ECU based on the theoretical load rate of the ECU and a set proportionality coefficient, and determine the network load rate based on the actual load rates of all ECUs; The size of the buffer is calculated using the following formula: m=t*M / T Where M is the number of bus messages, t is the time it takes for the ECU to process the number of bus messages M, and T is the time difference between two buffer reads; The theoretical load rate that the ECU can bear is calculated by the following formula: in, fk is the theoretically tolerable load rate, m is the buffer size, L is the message length; R b Communication transfer rate.

2. The method for quantifying network load rate before architecture design according to claim 1, characterized in that: The ECU reads the buffer in an interrupt mode.

3. The method for quantifying network load rate before architecture design according to claim 1, characterized in that: The ECU reads the buffer in a polling manner.

4. The method for quantifying network load rate before architecture design according to claim 1, characterized in that: The actual load rate that the ECU can bear is calculated by the following formula f 0＝ f k *N ， in, f0 is the actual load rate that can be tolerated, fk is the theoretically tolerable load rate, and N is the proportionality coefficient.

5. The method for quantifying network load rate before architecture design according to claim 1, characterized in that: The proportional coefficient is a calibrated value, and the proportional coefficients of different ECUs are set separately.

6. The method for quantifying network load rate before architecture design according to claim 1, characterized in that: Compare the actual tolerable load rates of all ECUs, and take the minimum value of the actual tolerable load rates of all ECUs as the network load rate.

7. An electronic device, characterized in that: include A memory for storing one or more programs; processor; When the one or more programs are executed by the processor, the method according to any one of claims 1 to 6 is implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

Images