A cache, data access method and instruction processing device

Abstract

The present invention discloses a cache comprising a data array group and a tag array group. The data array group comprises a plurality of data arrays, each data array comprising a predetermined number of cache data rows, each cache data row having a corresponding data index. The tag array group comprises a plurality of tag arrays, each tag array corresponding to a data array, and each tag array comprising a plurality of sub-tag arrays, each sub-tag array comprising a predetermined number of tags, each tag having a corresponding tag index and containing a physical address corresponding to a cache data row in the data array. The present invention also discloses an instruction processing device, a system on chip, and an intelligent device comprising the cache, as well as a data access method for operating the cache.

Description

Technical Field

[0001] The present invention relates to the field of processors, and in particular to a processor core and a processor with a data cache. Background Art

[0002] Modern processors or processor cores process instructions in a pipelined manner. A typical pipeline usually includes various pipeline stages such as instruction fetch, instruction decode, instruction issue, instruction execution, and instruction retirement.

[0003] Because the access speed of the memory does not match the execution speed of the processor, the instruction or data reading and writing operations on the memory during the instruction fetch and instruction execution stages have become one of the main bottlenecks of current processor performance. Taking into account the cost and storage speed of different storage media, in current processor architectures, a hierarchical storage mechanism is usually adopted, that is, a low-capacity cache is used to cache data in slow but low-cost storage media. Using the cache mechanism, when accessing instructions or data from an external storage medium, the accessed data or instructions can be stored in the cache. In this way, when the same instruction or data is accessed subsequently, the accessed data or instructions can be obtained directly from the cache without having to obtain the data or instructions from the external storage medium. The cache mechanism can significantly improve the execution speed of data access operations.

[0004] Managing the cache so as to improve the access speed to the cache is a problem to be solved in this field. In particular, when the space of the cache gradually becomes larger, how to quickly access the cached data in the cache is one of the problems to be solved in this field.

[0005] Therefore, a new data access solution is needed that can efficiently manage the cache and quickly access the cached data. Summary of the Invention

[0006] To this end, the present invention provides a new cache, an instruction processing device, a processor, and a data access method, in an effort to solve or at least alleviate at least one of the above problems.

[0007] According to one aspect of the present invention, a cache is provided, comprising a data array group and a tag array group. The data array group comprises a plurality of data arrays, each data array comprising a predetermined number of cache data lines, each having a corresponding data index. The tag array group comprises a plurality of tag arrays, each corresponding to a data array, and each tag array comprising a plurality of sub-tag arrays, each sub-tag array comprising a predetermined number of tags, each tag having a corresponding tag index and containing a physical address corresponding to a cache data line in the data array. A tag index, a data index, and a sub-tag index are generated based on a virtual address included in a data access request. The data index is used to retrieve the corresponding cache data line in the data array group, and the tag index is used to retrieve the corresponding tag in the tag array group. When the physical address corresponding to the virtual address is the same as the physical address included in the retrieved tag, the retrieved tag is a hit tag. When the sub-tag array position of the hit tag in the tag array is consistent with the sub-tag index, the cache data line of the data array corresponding to the tag array where the hit tag is located is selected from the retrieved cache data lines as the data to be accessed.

[0008] According to another aspect of the present invention, an instruction processing device is provided, comprising the cache described above and a data access unit. The data access unit is adapted to receive data access requests and process them to return the requested data. The data access unit includes an address generation unit, a memory management unit, a physical tag comparator, and a data output unit.

[0009] The address generation unit is adapted to obtain, based on a data access request, a virtual address of data to be accessed by the request, and generate a tag index, a data index, and a subtag index based on the obtained virtual address. The tag index is generated based on a first portion of the virtual address. The data index is generated based on a second portion of the virtual address. The subtag index is generated based on a third portion of the virtual address, wherein the second portion of the virtual address includes at least the first and third portions of the virtual address.

[0010] The memory management unit is coupled to the address generation unit and is adapted to obtain a physical address corresponding to the virtual address.

[0011] The physical tag comparator is coupled to the memory management unit and the tag array group in the cache, and is suitable for comparing the physical address obtained by the memory management unit with the physical address included in the tag corresponding to the tag index retrieved in the tag array group to determine a hit tag with the same physical address.

[0012] The data output unit is adapted to select, from cache data rows retrieved from the cached data array group according to the data index, a cache data row from the data array corresponding to the tag array where the hit tag is located as data to be output when the subarray position of the subtag array where the hit tag is located in the tag array is consistent with the subtag index.

[0013] Optionally, the instruction processing device according to the present invention also includes a backfill buffer, which is suitable for calculating a new data index based on the tag index and the subarray position when the subarray position is inconsistent with the subtag index; retrieving a new cache data row corresponding to the new data index in the data array corresponding to the tag array where the hit tag is located; writing the hit tag to the tag array where the hit tag is located and at the position indicated by the tag index in the subtag array corresponding to the subtag index; and writing the new cache data row to the position indicated by the data index in the same data array.

[0014] Optionally, in the instruction processing device according to the present invention, after the backfill buffer retrieves the new cache data line, it selects the new cache data line and sends it to the data output unit, so that the data output unit selects the new cache data line as data to be output.

[0015] Optionally, in the instruction processing device according to the present invention, after the backfill buffer writes the new cache data line to the position indicated by the data index, the data output unit reads the new cache data line from the position indicated by the data index as data to be output.

[0016] Optionally, in the instruction processing device according to the present invention, the backfill buffer is also suitable for obtaining a data row at a physical address from a memory coupled to the instruction processing device when the physical tag comparator determines that there is no hit tag, so as to send the obtained data row to the data output unit as data to be output; creating a tag based on the physical address, and writing the created tag into the tag array at a position indicated by the tag index in the sub-tag array corresponding to the sub-tag index; and writing the obtained data row into the data array corresponding to the tag array at a position indicated by the data index.

[0017] Optionally, in the instruction processing device according to the present invention, the address generation unit is further adapted to generate a data offset based on the obtained virtual address, wherein the data offset is generated based on the fourth part of the virtual address; and the data output unit is further adapted to select the data at the position indicated by the data offset in the cache data row as the data to be output.

[0018] Optionally, in an instruction processing device according to the present invention, the fourth part of the virtual address includes multiple bits starting from the lowest bit of the virtual address, and the number of bits contained in the fourth part corresponds to the length of the data row; the first part of the virtual address includes multiple bits adjacent to the fourth part in order from low to high address bits; the third part of the virtual address includes one or more bits adjacent to the first part in order from low to high address bits, and the number of bits contained in the third part corresponds to the number of sub-tag arrays; and the second part of the virtual address includes the first part and the third part.

[0019] Optionally, in the instruction processing device according to the present invention, the tag further includes status information of the cache data line.

[0020] According to another aspect of the present invention, a data access method is provided, which is suitable for execution in an instruction processing device including the above-mentioned cache, the method comprising the steps of: obtaining a virtual address of data to be accessed by the request based on a data access request; generating a tag index, a data index and a subtag index based on the obtained virtual address, the tag index being generated based on a first part of the virtual address, the data index being generated based on a second part of the virtual address, and the subtag index being generated based on a third part of the virtual address, and the second part of the virtual address at least including the first part and the third part of the virtual address; retrieving a cache data line corresponding to the data index in a cached data array group; retrieving a tag corresponding to the tag index in a cached tag array group; obtaining a physical address corresponding to the virtual address, and comparing the obtained physical address with the physical address contained in the tag retrieved from each subtag array to determine a hit tag with the same physical address; and when the subarray position of the subtag array where the hit tag is located in the tag array is consistent with the subtag index, selecting a cache data line from the data array corresponding to the tag array where the hit tag is located from the retrieved cache data lines as the data to be accessed.

[0021] According to another aspect of the present invention, a system on chip is provided, comprising an instruction processing device or a processor according to the present invention.

[0022] According to yet another aspect of the present invention, there is provided an intelligent device comprising the system on chip according to the present invention.

[0023] According to the solution of the present invention, a data cache is managed using a tag array and a data array in a VIPT (Virtual Index Physical Tag) manner. By setting the grouping granularity of the tag array to be smaller than the grouping granularity of the data array, when different virtual addresses are mapped to the same physical address, the physical address can also be found in the tag array, and the cached data at the physical address can be transferred to the location indexed by the latest virtual address, thereby solving the data aliasing problem that may be caused by different virtual addresses being mapped to the same physical address. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To achieve the above and related purposes, certain illustrative aspects are described herein in conjunction with the following description and accompanying drawings, which indicate various ways in which the principles disclosed herein may be practiced, and all aspects and their equivalents are intended to fall within the scope of the claimed subject matter. The above and other objects, features, and advantages of the present disclosure will become more apparent by reading the following detailed description in conjunction with the accompanying drawings. Throughout this disclosure, the same reference numerals generally refer to the same parts or elements.

[0025] Figure 1 A schematic diagram of an instruction processing device according to an embodiment of the present invention is shown;

[0026] Figure 2 A schematic diagram of a data access unit and a cache according to an embodiment of the present invention is shown;

[0027] Figure 3 A schematic flow chart of a data access method according to an embodiment of the present invention is shown;

[0028] Figure 4 A schematic diagram of implementing tag array access according to an embodiment of the present invention is shown;

[0029] Figure 5 A schematic diagram illustrating a logic implementation of data array access according to another embodiment of the present invention is shown; and

[0030] Figure 6A A schematic diagram of an instruction processing pipeline according to an embodiment of the present invention is shown;

[0031] Figure 6B A schematic diagram of a processor core architecture according to an embodiment of the present invention is shown;

[0032] Figure 7 A schematic diagram of a processor according to an embodiment of the present invention is shown;

[0033] Figure 8 A schematic diagram illustrating a computer system according to an embodiment of the present invention; and

[0034] Figure 9 A schematic diagram of a system on chip (SoC) according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0035] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0036] Figure 1 FIG2 is a schematic diagram of an instruction processing apparatus 100 according to an embodiment of the present invention. In some embodiments, the instruction processing apparatus 100 may be a processor, a processor core of a multi-core processor, or a processing element in an electronic system.

[0037] like Figure 1 As shown, instruction processing apparatus 100 includes an instruction fetch unit 130. Instruction fetch unit 130 can retrieve instructions to be processed from cache 110, memory 120, or other sources and send them to decode unit 140. The instructions fetched by instruction fetch unit 130 include, but are not limited to, high-level machine instructions or macroinstructions. Instruction processing apparatus 100 executes these instructions to perform specific functions.

[0038] The decoding unit 140 receives instructions passed into the instruction fetch unit 130 and decodes these instructions to generate low-level micro-operations, microcode entry points, microinstructions or other low-level instructions or control signals. They reflect the instructions received or are derived from the instructions received. The low-level instructions or control signals can implement the operation of high-level instructions through low-level (e.g., circuit level or hardware level) operations. Various different mechanisms can be used to implement the decoding unit 140. Examples of suitable mechanisms include, but are not limited to, microcode, lookup tables, hardware implementations, programmable logic arrays (PLA). The present invention is not limited to the various mechanisms that implement the decoding unit 140, and any mechanism that can implement the decoding unit 140 is within the scope of protection of the present invention.

[0039] These decoded instructions are then sent to and executed by execution unit 150. Execution unit 150 includes circuitry operable to execute instructions. When executing these instructions, execution unit 150 receives data inputs from register file 170, cache 110, and / or memory 120 and generates data outputs thereto.

[0040] In one embodiment, register file 170 includes architectural registers, also referred to as registers. Unless otherwise specified or clearly apparent, the phrases architectural registers, register file, and register are used herein to refer to registers that are visible to software and / or programmers (e.g., software-visible) and / or specified by macroinstructions to identify operands. These registers are distinct from other non-architectural registers in a given microarchitecture (e.g., temporary registers, reorder buffers, retirement registers, etc.). According to one embodiment, register file 170 may include a set of vector registers 175, each of which may be 512 bits, 256 bits, or 128 bits wide, or may use different vector widths. Optionally, register file 170 may also include a set of general registers 176. General registers 176 may be used by the execution unit when executing instructions, for example, to store jump conditions, store instruction operation results, store addresses of data to be accessed, store data read from cache 110 and / or memory 120, etc.

[0041] The execution unit 150 may include multiple specific instruction execution units 150a, 150b, ..., 150c, etc. These instruction execution units may include, for example, an arithmetic unit, an arithmetic logic unit (ALU), an integer unit, a floating point unit, a data access unit, etc., and may each execute different types of instructions. For example, the instruction execution unit 150a is a data access unit that may execute instructions related to data operations. Instructions related to data operations include data storage instructions and data loading instructions. Data storage instructions are used to write data to the cache 110 or the memory 120. Data loading instructions are used to read data from the cache 110 or the memory 120.

[0042] The instruction fetch unit 130 and the instruction execution unit 150a access the cache 110 and / or the memory 120 via the data access unit 180. The data access unit 180 manages data access to the cache 110 and the memory 120, and manages the data cached in the cache 110. For example, when the instruction fetch unit 130 and the instruction execution unit 150a access data in the memory 120 for the first time, the data access unit 180 retrieves the data from the memory 120 and caches the retrieved data in the cache 110 while providing the data. When the instruction fetch unit 130 and the instruction execution unit 150a subsequently access the data again, the data is directly provided from the cache 110, thereby significantly improving the execution speed of data access.

[0043] To avoid obscuring the description, a relatively simple instruction processing apparatus 100 has been shown and described. It will be appreciated that instruction processing apparatus 100 may have different forms, for example, other embodiments of instruction processing apparatus or processors may have multiple cores, logical processors, or execution engines.

[0044] When the data access unit 180 receives a data access request, it needs to efficiently and accurately determine whether the data to be accessed is cached in the cache 110. Therefore, the data access unit 180 provides a data access mechanism to efficiently and accurately manage the data cached in the cache 110.

[0045] Figure 2 FIG. 1 shows a schematic diagram of a data access unit 180 according to an embodiment of the present invention. Figure 2 In the embodiment of the present invention, the various components of data access unit 180 are logically divided according to the data access mode to be implemented in data access unit 180. These logical divisions are for illustration only and may be further divided according to actual physical layout and business needs. Even data access unit 180 itself may be further divided into multiple components, such as a data access unit for processing instruction access requests from instruction fetch unit 130 and a data access unit for processing data access requests from instruction execution unit 150a. Therefore, all of these do not depart from the scope of protection of the present invention. Figure 3 is a description of the data access method executed in the data access unit 180. Figure 3 The method shown can be used by Figure 2 The components shown are completed. Figure 2 When the components shown are recombined and divided, corresponding method steps can be completed according to the logic carried by the new components without departing from the scope of protection of the present invention.

[0046] like Figure 2As shown, the data access unit 180 includes an address generation unit 210. The address generation unit 210 receives a data access request and obtains the virtual address of the data to be accessed by the data access request. For the instruction processing device 100, when processing a program task, it constructs an instruction space and a data space around the task to be executed, and uses virtual addresses to reference the contents of these spaces. To this end, the data access unit 180 must determine the virtual address to be accessed by the data access request. There are multiple ways to determine the virtual address. According to one embodiment, for an instruction fetch request from the fetch unit 130, since the instruction fetch request includes the distance of the instruction to be fetched relative to the program counter (PC), the relative offset of the instruction to be fetched relative to the PC can be calculated based on the distance, and the virtual address of the PC is added to calculate the virtual address. According to another embodiment, for a data access request from instruction execution unit 150a, since the data access request originates from a data load instruction or a data store instruction, an offset can be obtained from the instruction (e.g., a specified register or immediate value) according to the instruction specification. The virtual address is then calculated based on the instruction base address (e.g., stored in another dedicated register) and the obtained offset. The present invention is not limited to the method for obtaining the virtual address; all methods for obtaining the virtual address from a data access request fall within the scope of protection of the present invention.

[0047] After obtaining the virtual address, the address generation unit 210 generates a virtual index based on the virtual address, using the virtual index to retrieve cached data from the cache 110. To this end, the cache 110 maintains a tag array group 112 and a data array group 114. The data array group 114 includes multiple data arrays (also known as multiplexed data arrays) 118. Each data array 118 contains a predetermined amount of cached data. According to one embodiment, cached data in the data arrays 118 is managed in units of data rows containing multi-bit data. Specifically, the cached data in the data arrays 118 can be divided into multiple data rows. Each data row is indexed by a data index, and each data row contains a fixed number of bits of data. Thus, the amount of cached data contained in each data array depends on the length of the data index and the length of the data row. For example, if each data row contains 512 bits (64 bytes) of data and the data index is 8 bits (allowing retrieval of up to 256 data rows), each data array 118 can manage 16K bytes of cached data.

[0048] Tag array group 112 also includes multiple tag arrays (also called multi-way tag arrays). The tag arrays correspond one-to-one to the data arrays, and each tag array further includes multiple sub-tag arrays. Each sub-tag array includes a predetermined number of tags. The number of tags depends on the length of the tag index used to index the sub-tag array. For example, when the tag index is 6 bits, the sub-tag array can include 64 tags. Each tag is retrieved by the corresponding tag index and contains at least the physical address corresponding to the cache data line in data array group 114. In addition, the tag may also contain other characteristics of the cache data line, such as the status information of the cache data line (including status information such as the valid bit, dirty bit, or shared bit of the cache line).

[0049] The address generation unit 210 generates a data index based on the virtual address, so that the generated data index can be used to retrieve a cached data line in the data array. The address generation unit 210 also generates a tag index and a subtag index based on the virtual address. The tag index is used to search the subtag arrays in each tag array, while the subtag index is used to determine which subtag array in the tag array the hit is.

[0050] According to one embodiment, a portion of the virtual address may be selected to generate these indexes. The portions of the virtual address used to generate the data index, tag index, and subtag index may be determined based on the size of the data to be cached by cache 110, the number n of tag arrays and data arrays, and the size of a cache data line.

[0051] For example, if cache 110 is to cache 64KB (i.e., 64K bytes) of data, and the entire data array group 114 is divided into four ways (n=4), i.e., four data arrays 118, and each data row consists of 64 bytes, the lowest six bits of the virtual address (represented as [5:0], with the first bit starting at position 0) are used to subsequently index data in the cache data row. The eight bits of the virtual address, from the 7th to the 14th bits (represented as [13:6]), starting from the lowest bit, are used as data indexes. This allows for indexing of 256 cache data rows, or 16KB of data. This satisfies the need to index each data array way after data array group 114 is divided into four ways.

[0052] Similarly, in the above example, if each subtag array provides tags for 4KB of cache data, each subtag index can use 6 bits, starting with the 7th to 12th bits of the virtual address (represented as [11:6]), so that 64 tags (corresponding to 64 cache data lines, that is, 4KB of data) can be indexed. In this case, the number of tag arrays is the same as the number of data arrays (n=4), and the number of subtag arrays contained in each tag array is m = (the size of the data to be cached by the cache, 64KB) / (n*4KB) = 4. Therefore, the subtag index also requires 2 bits, namely, bits 13 to 14 starting with the least significant bit of the virtual address (represented as [13:12]) as the subtag index.

[0053] According to one embodiment, considering that the tag array is further divided into multiple sub-tag arrays, and each tag performs state management for a cache data line, the number of virtual address bits used by the data index corresponds to the sum of the number of virtual address bits occupied by the tag index and the sub-tag index.

[0054] The memory management unit 220 is coupled to the address generation unit 210, receives the virtual address obtained by the address generation unit 210, and determines the physical address corresponding to the virtual address based on the obtained virtual address. The memory management unit 220 can use various methods to determine the physical address corresponding to the virtual address. According to one embodiment, the memory management unit 220 maintains a memory query page table, so that the physical address corresponding to the virtual address can be determined based on the page table. According to another embodiment, the memory management unit 220 can also maintain a TLB (Translation Lookaside Buffer), and the correspondence between the virtual address and the physical address is maintained in the TLB. In this way, when the memory management unit 220 receives a virtual address, it can retrieve the corresponding physical address from the TLB and output the retrieved physical address.

[0055] According to one embodiment, the virtual address received by the memory management unit 220 is a tag based on a portion of the virtual address. As described above, when the virtual address is 32 bits, the tag index uses bits 7 to 12 of the virtual address. The remaining 20 bits of the virtual address, namely bits 13 to 32 (which can be represented as [31:12]), can be used as the tag. The TLB establishes a correspondence between tags and physical addresses, allowing the corresponding physical address to be retrieved based on the tag.

[0056] After address generation unit 210 generates a tag index, it uses the tag index to search tag array group 112. As described above, tag array group 112 includes n tag arrays, and each tag array includes m sub-tag arrays. Therefore, using the tag index, n*m tags can be obtained as search results in tag array group 112.

[0057] The physical tag comparator 230 is coupled to the memory management unit 220 and the tag array group 112, and receives the physical address obtained by the memory management unit 220 and the n*m ​​tags retrieved from the tag array group 112, respectively. The tag includes a physical address, and the physical tag comparator 230 compares the physical address obtained from the memory management unit 220 with the physical addresses included in the n*m ​​tags to determine whether any tags include the same physical address (hereinafter, tags with the same physical address are referred to as hit tags).

[0058] In addition, the physical tag comparator 230 also receives the subtag index from the address generation unit 210. When a hit tag exists, the physical tag comparator 230 determines whether the position of the subtag array where the hit tag is located in the tag array is consistent with the subtag index. If the two are consistent, that is, the tag index is the original index, the physical tag comparator 230 outputs the hit result to the data output unit 240.

[0059] The data output unit 240 is coupled to the physical tag comparator 230. When the physical tag comparator 230 determines that the tag index is the original index, the data output unit 240 receives a hit result from the physical tag comparator 230. According to one embodiment, the hit result indicates which tag array (or, which data array) is hit.

[0060] After the address generation unit 210 generates the data index, the data index is used to search the data array group 114. As described above, the data array group 114 includes n data arrays. Therefore, n cache data lines can be obtained from the data array group 114 as search results using the data index.

[0061] The data output unit 240 is also coupled to the data array group 114 and obtains the n data cache lines as the search result. Then, based on the received hit result, the data output unit 240 selects one of the n data cache lines, i.e., the data cache line from the hit data array, as the data cache line to be output.

[0062] According to one embodiment, the data output unit 240 can output specific cache data in the hit data cache line. To this end, the address generation unit 210 can also generate a data offset based on the virtual address. As described above, the data offset can be generated using the lowest few bits of the virtual address (the number of bits is related to the line length of the data cache line. When each data cache line contains 64B of data, the number of bits used is, for example, the lowest 6 bits). The data output unit 240 is coupled to the address generation unit 210 and receives the generated data offset. It searches the hit data cache line based on the received data offset to select the data at the data offset as the cache data to be ultimately output.

[0063] In addition, when it is determined in the physical tag comparator 230 that there is no hit tag, that is, no retrieved tag has a physical address corresponding to the physical address from the memory management unit 220, the backfill buffer 250 can be instructed to obtain the corresponding tag from the memory 120 and cache it in the cache.

[0064] Backfill buffer 250 reads data from the location indicated by the physical address in memory 120 and sends the read data to data output unit 240 for return. For example, as described above, when the data array and tag array manage cache data in units of data rows, backfill buffer 250 can read an entire data row at the location indicated by the physical address, send the read data row to data output unit 240, and select the cached data to be ultimately output based on the data offset.

[0065] In addition, backfill buffer 250 caches the read data row in tag array group 112 and data array group 114. Specifically, backfill buffer 250 creates a tag based on the physical address and writes the created tag into the sub-tag array corresponding to the sub-tag index in the selected tag array. The location where the tag is written corresponds to the tag index, that is, the tag index is written at the location indicated by the tag index. Simultaneously, backfill buffer 250 writes the retrieved data row into the data array corresponding to the selected tag array. The location where the data row is written corresponds to the data index, that is, the data row is written at the location specified by the data index as the cached data row.

[0066] In this way, when a subsequent access request for data with the same virtual address is received, the physical tag comparator 230 can determine that there is a hit tag, and the data output unit 240 can obtain the data from the cache 110 .

[0067] In addition, if it is determined in the physical tag comparator 230 that there is a hit tag, but the position of the subtag array where the hit tag is located in the tag array is inconsistent with the subtag index, the physical tag comparator 230 may also instruct the backfill buffer 250 to perform backfill processing. In this case, the tag index is an alias index that is not the original index. As described above, when the number of subtag arrays included in each tag array is 4, there may be one tag index and three alias indexes. Since the instruction processing device 100 needs to process different programs and perform context switching, it is possible that different virtual addresses are mapped to the same physical address, which may result in the alias index being hit.

[0068] When a tag hit occurs but the tag index is an alias index, backfill buffer 250 determines that the data to be read is already cached in the data array but is not indicated by the appropriate tag. Therefore, backfill buffer 250 needs to update the tag and move the cached data within the data cache so that the cached data is subsequently indicated by the appropriate tag. Specifically, backfill buffer 250 determines a new data index corresponding to the hit tag, namely, calculating the new data index based on the tag index and the subarray position where the hit tag is located. As described above, in a virtual address, the portion used by the data index includes the portion used by the tag index and the subtag index. To this end, the subarray position where the hit tag is located can be used to replace the subtag index to generate a new data index. Backfill buffer 250 then uses the new data index to retrieve the corresponding new cached data line from the same way data array (i.e., the tag array corresponding to the hit way) and writes the retrieved new cached data line to the location indicated by the previous data index in the same way data array. In addition, the backfill buffer 250 writes the contents of the hit tag to the corresponding position in the subtag array indicated by the original index in the same tag array, that is, the position indicated by the same tag index. In other words, the contents of the hit tag are moved from the subtag array indicated by the alias index to the same position in the subtag array indicated by the original index. According to one embodiment, when the tag is moved, the corresponding state information can also be modified according to the state change of the cached data.

[0069] According to one embodiment, after acquiring appropriate cache data, the backfill buffer 250 may directly send the acquired data line to the data output unit 240 so as to output the cache data while moving the cache data line and the tag.

[0070] According to another embodiment, the backfill buffer 250 may instruct the data access unit 180 to reprocess the data access request after moving the cache data line and tag, so that the data output unit 240 can obtain and output the cache data from the appropriate data array.

[0071] use Figure 2 The data access unit 180 shown can further refine the tag array into multiple sub-tag arrays when managing cache data in the form of a tag array and a data array. In this way, even if there is a data aliasing problem because different virtual addresses can be mapped to the same physical address, the problem can be solved by backfilling the cache data to the correct index position.

[0072] Figure 4 and Figure 5 Schematic diagrams of the implementation logic of the access tag array group and the data array group according to an embodiment of the present invention are respectively given. Figure 4 As shown, it is assumed that the virtual address obtained by the address generation unit 210 is 32 bits, of which the 20 bits from the least significant bit, i.e., va[31:12], are used as a tag; bits 7 to 12, i.e., va[11:6], are used as a tag index; and bits 13 to 14, i.e., va[13:12], are used as a subtag index. The tag va[31:12] is used to search the TLB of the memory management unit 220 to obtain the corresponding physical address. Simultaneously, in the tag array group 112, the tag index va[11:6] can be used to frequently search the four subtag arrays (corresponding to va[13:12] = 00, va[13:12] = 01, va[13:12] = 10, and va[13:12] = 11, respectively) in the 4-way tag array (the 0th to 3rd way tag arrays), resulting in 4*4 = 16 search results. Subsequently, in the physical tag comparator 230, the comparator is used to compare the physical address from the memory management unit 220 with the contents of the 16 tags obtained from the tag array group 112 (i.e., the physical addresses contained in the tags), and the comparison result is output as input to the selector controlled by the subtag index va[13:12], so as to output the hit result, i.e., the true hit indication, based on whether the hit tag is on the subtag array indicated by the subtag index va[13:12]. The true hit has a length of 4 bits, and each bit value corresponds to one tag array. For example, when the hit tag is in the 1st way and the subtag index indicates the original index, the value of the true hit [1] bit is set to 1, and the other bits are set to 0.

[0073] like Figure 5As shown, in the address generation unit 210, bits 7 to 14 of the virtual address, i.e., va[13:6], are used as the data index, and bits 1 to 6 of the virtual address, i.e., va[5:0], are used as the data offset. Thus, in the data array group 114, four data arrays are simultaneously searched using the data index to obtain four search results. In the data output unit 240, the search result of one data array is selected for output based on the comparison result from the physical tag comparator 230, i.e., true hit [3:0]. As described above, a true hit has a length of 4 bits. When a certain output is selected, the corresponding bit is set to 1, so that the search result of the corresponding data array can be selected using a selector. Subsequently, the data offset from the address generation unit is used as the gate control of the selector to further select the cache data to be output from the selected cache data row.

[0074] It should be noted that the above describes how to use virtual addresses to access tag array groups and data array groups using a 32-bit virtual address as an example, but the present invention is not limited to this. The present invention can be applied to virtual addresses of other lengths, such as systems with addresses of 64 bits, 128 bits, or 256 bits.

[0075] Figure 3 FIG. 3 is a flow chart of a data access method 300 according to an embodiment of the present invention. Figure 1 The instruction processing device 100 shown in FIG. Figure 2 The method 300 is executed in the data access unit 180. The method 300 starts at step S310.

[0076] In step S310, a virtual address of the data to be accessed is obtained based on the data access request. As described above, a data access request generally originates from an instruction fetch request from the fetch unit 130 and an instruction related to data access from the instruction execution unit 150a. There are various methods for determining a virtual address. According to one embodiment, for an instruction fetch request from the fetch unit 130, the virtual address is calculated based on the distance of the instruction to be fetched relative to the program counter (PC) included in the instruction fetch request. According to another embodiment, for a data access request from the instruction execution unit 150a, an offset can be obtained from the instruction (e.g., a specified register or immediate value) according to the instruction specification. The virtual address is then calculated based on the instruction base address (e.g., stored in another dedicated register) and the obtained offset. The present invention is not limited to the method for obtaining a virtual address; all methods for obtaining a virtual address from a data access request fall within the scope of protection of the present invention.

[0077] Subsequently, in step S320, a tag index, a data index, and a subtag index are generated based on the virtual address obtained in step S310. The specific process of generating the tag index, data index, and subtag index has been described in detail above when describing the address generation unit 210, and will not be repeated here. In short, the tag index, data index, and subtag index are all generated based on a portion of the virtual address, and even a portion of the virtual address can be directly used as these indexes. Furthermore, considering that the tag array is further divided into subtag arrays, the portion of the virtual address used as the data index will include portions used as the tag index and the subtag index.

[0078] In step S330, the data index obtained in step S320 is used to retrieve the cache data row corresponding to the data index from the data array group 114 of the cache 110. Data array group 114 includes multiple data arrays (numbered n). Each data array contains a predetermined amount of cache data. According to one embodiment, in the data array, cache data is managed in units of data rows. Each data row is indexed by a data index, and each data row contains a fixed number of bits of data. Thus, the amount of cache data contained in each data array depends on the length of the data index and the length of the data row. For example, if each data row contains 512 bits (64 bytes) of data and the data index is 8 bits (a maximum of 256 data rows can be retrieved), each data array can manage 16K bytes of cache data. In step S330, n cache data rows can be retrieved as the search result.

[0079] Step S340 is executed synchronously with step S330. In step S340, a tag corresponding to the tag index is retrieved from the tag array group 112 of the cache 110. The tag array group 112 also includes multiple tag arrays (number n). The tag arrays correspond one-to-one with the data arrays, and each tag array further includes multiple sub-tag arrays (number m). Each sub-tag array includes a predetermined number of tags. The number of tags depends on the length of the tag index used to index the sub-tag arrays. Each tag is retrieved by the corresponding tag index and contains at least the physical address corresponding to the cache data line in the data array group 114. The tag may also contain other characteristics of the cache data line, such as the status information of the cache data line (including status information such as the cache line's valid bit, dirty bit, or shared bit). In step S340, n*m tags can be retrieved as the search result.

[0080] Step S350 is executed synchronously with steps S330 and S340. In step S350, the physical address corresponding to the virtual address in step S320 is obtained. Step S350 can be performed using the memory management unit 220, particularly the TLB therein. The TLB maintains a correspondence between virtual addresses and physical addresses. Thus, in step S350, the physical address corresponding to the virtual address obtained in step S320 can be retrieved from the TLB. According to one embodiment, the virtual address processed in step S350 is a tag based on a portion of the virtual address. As described above, when the virtual address is 32 bits, the tag index uses bits 7 to 12 of the virtual address. The remaining 20 most significant bits of the virtual address, i.e., bits 13 to 32 (which can be represented as [31:12]), can be used as the tag. The TLB establishes a correspondence between the tag and the physical address, so that the corresponding physical address can be obtained based on the tag.

[0081] Subsequently, in step S360 , the physical address obtained in step S350 is compared with the physical addresses contained in the n*m ​​tags obtained as the search result in step S340 to determine whether any tag contains the same physical address, ie, whether there is a hit tag.

[0082] In addition, in step S360, when it is determined that there is a hit tag, it is further determined whether the position of the sub-tag array where the hit tag is located in the tag array is consistent with the sub-tag index generated in step S320. In other words, it is determined whether the tag index corresponding to the hit tag is the original index.

[0083] If it is determined in step S360 that there is a hit tag, and the tag index corresponding to the hit tag is the original index, then in step S370, from the cache data lines retrieved in step S330, a cache data line from the data array corresponding to the tag array where the hit tag is located is selected as the data to be accessed.

[0084] Alternatively, considering that the output may not be an entire cache data line, in step S320, a data offset is further determined based on the virtual address. For example, the data offset can be generated based on the lowest bits of the virtual address (when the data cache line is 512 bits, 6 bits can be used as the data offset). Furthermore, method 300 further includes step S375, wherein the data cache line selected in step S370 is retrieved based on the data offset calculated in step S320 to select the data at the offset as the cache data to be ultimately output.

[0085] If it is determined in step S360 that a hit tag exists, but the tag index corresponding to the hit tag is not the original index, method 300 proceeds to step S380. As described above, when each tag array includes four sub-tag arrays, there may be one tag index and three alias indexes. In this case, the tag index is an alias index, and the data to be read is already cached in the data array but is not indicated by the appropriate tag. Therefore, in step S380, it is necessary to update the tag and move the cached data within the data cache so that the cached data is subsequently indicated by the appropriate tag. Specifically, a new data index corresponding to the hit tag is determined, that is, a new data index is calculated based on the tag index and the sub-array position where the hit tag is located. Subsequently, using the new data index, the corresponding new cached data line is retrieved from the same way data array (i.e., corresponding to the tag array of the hit way), and the retrieved new cached data line is written to the same way data array at the location indicated by the previous data index. In addition, the content of the hit tag is written to the corresponding position in the subtag array indicated by the original index in the same tag array, that is, the position indicated by the same tag index. In other words, the content of the hit tag is moved from the subtag array indicated by the alias index to the same position in the subtag array indicated by the original index. According to one embodiment, when the tag is moved, the corresponding state information can also be modified according to the state change of the cached data.

[0086] Subsequently, in step S385, the acquired data row is output, or further in step S375, the data to be ultimately output is acquired from the data row. There are various ways to acquire the data row in step S385. According to one embodiment, the acquired data row can be directly output after acquiring the appropriate cached data. According to another embodiment, the process starting from step S320 can be re-executed after moving the cached data row and tag, so that the cached data can be acquired from the appropriate data array and output according to the process of step S370.

[0087] If it is determined in step S360 that there is no hit tag, method 300 proceeds to step S390. In step S390, the data line at the physical address determined in step S350 is retrieved from memory 120 coupled to instruction processing apparatus 100, cached, and output as the data to be accessed. To cache the read data line in cache 110, in step S390, a tag is first created based on the physical address and written to the tag array at a location indicated by the tag index in the subtag array corresponding to the subtag index generated in step S320 (i.e., forming the original index). Subsequently, the retrieved data line is written to the data array corresponding to the tag array at a location indicated by the data index generated in step S320.

[0088] Optionally, after obtaining the data row, the process may proceed to step S375 to obtain and output corresponding cache data according to the data offset.

[0089] Use reference Figure 3 The described data access method can further refine the tag array into multiple sub-tag arrays when managing cache data in a tag array and a data array. In this way, even if data aliasing problems occur because different virtual addresses can be mapped to the same physical address, the problem can be resolved by backfilling the cache data to the correct index location.

[0090] As described above, the instruction processing device according to the present invention can be implemented as a processor core, and the instruction processing method can be executed in the processor core. The processor core can be implemented in different ways in different processors. For example, the processor core can be implemented as a general-purpose in-order core for general-purpose computing, a high-performance general-purpose out-of-order core for general-purpose computing, and a specialized core for graphics and / or scientific (throughput) computing. The processor can be implemented as a CPU (central processing unit) and / or a coprocessor, where the CPU may include one or more general-purpose in-order cores and / or one or more general-purpose out-of-order cores, while the coprocessor may include one or more specialized cores. Such combinations of different processors can lead to different computer system architectures. In one computer system architecture, the coprocessor is on a separate chip from the CPU. In another computer system architecture, the coprocessor is in the same package as the CPU but on a separate die. In yet another computer system architecture, the coprocessor is on the same die as the CPU (in this case, such a coprocessor is sometimes referred to as specialized logic, such as integrated graphics and / or scientific (throughput) logic, or as a specialized core). In another computer system architecture called a system on a chip, the CPU described (sometimes called an application core or application processor), the coprocessor described above, and additional functions can be included on the same die. Figure 6A-9 to describe exemplary core architectures, processors, and computer architectures.

[0091] Figure 6A 1 is a schematic diagram illustrating an instruction processing pipeline according to an embodiment of the present invention, wherein the pipeline includes an in-order pipeline and an out-of-order issue / execution pipeline. Figure 6B A schematic diagram illustrating a processor core architecture according to an embodiment of the present invention, including an in-order architecture core and an out-of-order issue / execution architecture core associated with register renaming. Figure 6A In and 6B , the in-order pipeline and in-order cores are shown in solid boxes, while the optional additions in dashed boxes show out-of-order issue / execution pipelines and cores.

[0092] like Figure 6A As shown, the processor pipeline 900 includes a fetch stage 902, a length decode stage 904, a decode stage 906, an allocation stage 908, a rename stage 910, a schedule (also called a dispatch or issue) stage 912, a register read / memory read stage 914, an execute stage 916, a write back / memory write stage 918, an exception handling stage 922, and a commit stage 924.

[0093] like Figure 6B As shown, processor core 990 includes an execution engine unit 950 and a front end unit 930 coupled to the execution engine unit 950. Both the execution engine unit 950 and the front end unit 930 are coupled to a memory unit 970. The core 990 can be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As another option, the core 990 can be a special-purpose core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processor unit (GPGPU) core, or a graphics core (GPU), etc.

[0094] The front end unit 930 includes a branch prediction unit 934, an instruction cache unit 932 coupled to the branch prediction unit 934, an instruction translation lookaside buffer (TLB) 936 coupled to the instruction cache unit 932, an instruction fetch unit 938 coupled to the instruction translation lookaside buffer 936, and a decode unit 940 coupled to the instruction fetch unit 938. The decode unit (or decoder) 940 can decode an instruction and generate as output one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals decoded from, or otherwise reflecting, or derived from, the original instruction. The decode unit 940 can be implemented using a variety of different mechanisms, including but not limited to a lookup table, hardware implementation, a programmable logic array (PLA), a microcode read-only memory (ROM), and the like. In one embodiment, the core 990 includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in the decode unit 940 or otherwise within the front end unit 930). The decode unit 940 is coupled to the rename / allocator unit 952 in the execution engine unit 950 .

[0095] The execution engine unit 950 includes a rename / allocator unit 952. The rename / allocator unit 952 is coupled to a retirement unit 954 and one or more scheduler units 956. The scheduler unit 956 represents any number of different schedulers, including reservation stations, central instruction windows, and the like. The scheduler unit 956 is coupled to various physical register file units 958. Each physical register file unit 958 represents one or more physical register files. Different physical register files store one or more different data types, such as scalar integers, scalar floating point, packed integers, packed floating point, vector integers, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), and the like. In one embodiment, the physical register file units 958 include a vector register unit, a write mask register unit, and a scalar register unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file unit 958 is overlaid by the retirement unit 954 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using a reorder buffer and retirement register files; using a future file, a history buffer, and retirement register files; using a register map and a register pool, etc.). The retirement unit 954 and the physical register file unit 958 are coupled to an execution cluster 960. The execution cluster 960 includes one or more execution units 962 and one or more memory access units 964. The execution units 962 can perform various operations (e.g., shifts, additions, subtractions, multiplications), and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include multiple execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. In some embodiments, because separate pipelines are created for certain types of data / operations (e.g., scalar integer pipelines, scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipelines, and / or memory access pipelines each with its own scheduler unit, physical register file unit, and / or execution cluster), there may be multiple scheduler units 956, physical register file units 958, and execution clusters 960. It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution, and the remaining pipelines may be in-order issue / execution.

[0096] The memory access unit 964 is coupled to a memory unit 970, which includes a data TLB unit 972, a data cache unit 974 coupled to the data TLB unit 972, and a level 2 (L2) cache unit 976 coupled to the data cache unit 974. In an exemplary embodiment, the memory access unit 964 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 972 in the memory unit 970. The instruction cache unit 932 may also be coupled to the level 2 (L2) cache unit 976 in the memory unit 970. The L2 cache unit 976 is coupled to one or more other levels of cache and ultimately to main memory.

[0097] As an example, refer to Figure 6B The core architecture described above can be implemented in the following way Figure 6A Pipeline 900 is depicted as follows: 1) instruction fetch unit 938 performs fetch stage and length decode stage 902 and 904; 2) decode unit 940 performs decode stage 906; 3) rename / allocator unit 952 performs allocate stage 908 and rename stage 910; 4) scheduler unit 956 performs schedule stage 912; 5) physical register file unit 958 and memory unit 970 perform register read / memory read stage 914; execution cluster 960 performs execute stage 916; 6) memory unit 970 and physical register file unit 958 perform write back / memory write stage 918; 7) various units may be involved in exception handling stage 922; and 8) retirement unit 954 and physical register file unit 958 perform commit stage 924.

[0098] The core 990 may support one or more instruction sets (e.g., the x86 instruction set (with certain extensions added with newer versions); the MIPS instruction set from MIPS Technologies; the ARM instruction set from ARM Holdings (with optional additional extensions such as NEON)), including the instructions described herein. It will be understood that the core may support multithreading (executing two or more sets of operations or threads in parallel) and may accomplish this in a variety of ways, including time-division multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that the physical core is simultaneously multithreading), or a combination thereof (e.g., time-division fetch and decode followed by simultaneous multithreading such as with hyperthreading).

[0099] Figure 7 FIG. 1 shows a schematic diagram of a processor 1100 according to an embodiment of the present invention. Figure 7As shown in the solid line box in FIG, according to one embodiment, the processor 1100 includes a single core 1102A, a system agent unit 1110, and a bus controller unit 1116. Figure 7 As shown in the dashed box in , according to another embodiment of the present invention, the processor 1100 may further include multiple cores 1102A-N, an integrated memory controller unit 1114 in the system agent unit 1110, and a dedicated logic 1108.

[0100] According to one embodiment, processor 1100 may be implemented as a central processing unit (CPU), wherein specialized logic 1108 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores), and cores 1102A-N are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, or a combination thereof). According to another embodiment, processor 1100 may be implemented as a coprocessor, wherein cores 1102A-N are multiple specialized cores for graphics and / or scientific (throughput). According to yet another embodiment, processor 1100 may be implemented as a coprocessor, wherein cores 1102A-N are multiple general-purpose in-order cores. Thus, processor 1100 may be a general-purpose processor, a coprocessor, or a specialized processor, such as, for example, a network or communications processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput many-integrated-core (MIC) coprocessor (including 30 or more cores), or an embedded processor. The processor may be implemented on one or more chips. Processor 1100 may be part of and / or implemented on one or more substrates using any of a number of processing technologies such as, for example, BiCMOS, CMOS, or NMOS.

[0101] The memory hierarchy includes one or more levels of cache within each core, one or more shared cache units 1106, and external memory (not shown) coupled to an integrated memory controller unit 1114. The shared cache unit 1106 may include one or more intermediate level caches, such as a level 2 (L2), level 3 (L3), level 4 (L4), or other level of cache, a last level cache (LLC), and / or combinations thereof. Although in one embodiment, a ring-based interconnect unit 1112 interconnects the integrated graphics logic 1108, the shared cache unit 1106, and the system agent unit 1110 / integrated memory controller unit 1114, the present invention is not limited thereto, and any number of well-known techniques may be used to interconnect these units.

[0102] The system agent unit 1110 includes components that coordinate and operate the cores 1102A-N. The system agent unit 1110 may include, for example, a power control unit (PCU) and a display unit. The PCU may include logic and components necessary to adjust the power state of the cores 1102A-N and the integrated graphics logic 1108. The display unit is used to drive one or more externally connected displays.

[0103] Cores 1102A-N may have the above reference Figure 1 and 6B The core architectures described herein may be homogeneous or heterogeneous in terms of the architecture instruction set. That is, two or more of the cores 1102A-N may be capable of executing the same instruction set, while other cores may be capable of executing only a subset of the instruction set or a different instruction set.

[0104] Figure 8 A schematic diagram of a computer system 1200 according to one embodiment of the present invention is shown. Figure 8 The computer system 1200 shown can be applied to laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices. The present invention is not limited to this, and all systems that can incorporate the processor and / or other execution logic disclosed in this specification are within the scope of protection of the present invention.

[0105] like Figure 8 As shown, computer system 1200 may include one or more processors 1210, 1215. These processors are coupled to a controller hub 1220. In one embodiment, controller hub 1220 includes a graphics memory controller hub (GMCH) 1290 and an input / output hub (IOH) 1250 (which may be on separate chips). GMCH 1290 includes a memory controller and a graphics controller coupled to memory 1240 and coprocessor 1245. IOH 1250 couples input / output (I / O) devices 1260 to GMCH 1290. Alternatively, the memory controller and graphics controller are integrated into the processor, so that memory 1240 and coprocessor 1245 are directly coupled to processor 1210, and controller hub 1220 includes only IOH 1250.

[0106] The optional nature of the additional processor 1215 is indicated by dashed lines in Figure 8 Each processor 1210, 1215 may include one or more of the processing cores described herein and may be Figure 7A version of processor 1100 is shown.

[0107] The memory 1240 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub 1220 communicates with the processors 1210, 1215 via a multi-drop bus such as a front side bus (FSB), a point-to-point interface such as a Quick Path Interconnect (QPI), or similar connection 1295.

[0108] In one embodiment, the coprocessor 1245 is a special purpose processor such as, for example, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, or an embedded processor, etc. In one embodiment, the controller hub 1220 may include an integrated graphics accelerator.

[0109] In one embodiment, processor 1210 executes instructions that control general types of data processing operations. Embedded within these instructions may be coprocessor instructions. Processor 1210 recognizes these coprocessor instructions as being of a type that should be executed by attached coprocessor 1245. Accordingly, processor 1210 issues these coprocessor instructions (or control signals representing coprocessor instructions) to coprocessor 1245 over a coprocessor bus or other interconnect. Coprocessor 1245 accepts and executes the received coprocessor instructions.

[0110] Figure 9 A schematic diagram of a system on chip (SoC) 1500 is shown according to one embodiment of the present invention. Figure 9 The system-on-chip shown contains Figure 7 The processor 1100 shown is therefore Figure 7 Similar parts have the same reference numerals. Figure 9 As shown, interconnect unit 1502 is coupled to application processor 1510, system agent unit 1110, bus controller unit 1116, integrated memory controller unit 1114, one or more coprocessors 1520, static random access memory (SRAM) unit 1530, direct memory access (DMA) unit 1532, and display unit 1540 for coupling to one or more external displays. Application processor 1510 includes a set of one or more cores 1102A-N and a shared cache unit 1106. Coprocessor 1520 includes integrated graphics logic, image processor, audio processor, and video processor. In one embodiment, coprocessor 1520 includes a special-purpose processor, such as, for example, a network or communication processor, a compression engine, a GPGPU, a high-throughput MIC processor, or an embedded processor.

[0111] The system-on-chip (SoC) according to the present invention can be used in various smart devices to implement corresponding functions. Such smart devices include, but are not limited to, in-vehicle devices, smart speakers, smart display devices, IoT devices, mobile terminals, and personal digital assistants. All systems that can incorporate the accelerated computing system and / or other execution logic disclosed in this specification are within the scope of protection of the present invention.

[0112] The system on chip (SoC) or accelerated computing system according to the present invention can be used in various smart devices to implement corresponding functions in the smart devices, including but not limited to executing relevant control programs, performing data analysis, calculation and processing, network communication, and controlling peripherals in the smart devices.

[0113] Such intelligent devices include specialized intelligent devices, such as mobile terminals and personal digital assistants, etc. These devices include one or more systems on a chip according to the present invention to process data or control peripherals in the devices.

[0114] Such smart devices also include specialized devices designed to implement specific functions, such as smart speakers and smart displays. These devices include a system-on-chip (SoC) according to the present invention to control the speakers and displays, thereby giving them additional communication, perception, and data processing capabilities.

[0115] Such smart devices also include various IoT and AIoT devices. These devices include a system-on-chip according to the present invention for data processing, such as AI computing, data communication and transmission, thereby achieving a denser and more intelligent device distribution.

[0116] Such smart devices can also be used in vehicles, for example, they can be implemented as vehicle-mounted devices, or can be embedded in vehicles, thereby providing data processing capabilities for the vehicle's intelligent driving.

[0117] Such smart devices can also be used in the home and entertainment fields, for example, they can be implemented as smart speakers, smart air conditioners, smart refrigerators, smart display devices, etc. These devices include the system-on-chip according to the present invention to perform data processing and peripheral control, thereby realizing the intelligence of home and entertainment devices.

[0118] The various embodiments of the mechanisms disclosed herein can be implemented in hardware, software, firmware, or a combination of these implementation methods. Embodiments of the present invention can be implemented as a computer program or program code executed on a programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0119] It should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Accordingly, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the invention.

[0120] Those skilled in the art will appreciate that the modules, units, or components of the devices in the examples disclosed herein may be arranged in the device described in the embodiment, or alternatively may be located in one or more devices different from the devices in the examples. The modules in the foregoing examples may be combined into one module or further divided into multiple submodules.

[0121] Those skilled in the art will appreciate that the modules in the devices of the embodiments can be adaptively modified and installed in one or more devices different from the embodiments. The modules, units, or components in the embodiments can be combined into a single module, unit, or component, and furthermore, they can be divided into multiple sub-modules, sub-units, or sub-components. All features disclosed in this specification (including the accompanying claims, abstract, and drawings), and all processes or units of any method or device disclosed therein, can be combined in any combination, unless at least some of such features and / or processes or units are mutually exclusive. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0122] Furthermore, those skilled in the art will appreciate that although some embodiments described herein include certain features included in other embodiments but not other features, combinations of features from different embodiments are intended to be within the scope of the present invention and to form different embodiments. For example, in the claims below, any of the claimed embodiments may be used in any combination.

[0123] In addition, some of the embodiments are described herein as methods or combinations of method elements that can be implemented by a processor of a computer system or by other devices that perform the functions described. Thus, a processor having the necessary instructions for implementing the method or method element forms a device for implementing the method or method element. Furthermore, the elements described herein of the device embodiments are examples of devices for implementing the functions performed by the elements for the purpose of implementing the invention.

[0124] As used herein, unless otherwise specified, the use of ordinal numbers "first," "second," "third," etc. to describe common objects merely indicates that different instances of similar objects are involved and are not intended to imply that the objects so described must have a given order in time, space, ranking, or in any other manner.

[0125] Although the present invention has been described with respect to a limited number of embodiments, it will be apparent to those skilled in the art, having benefit of the foregoing description, that other embodiments are contemplated within the scope of the invention thus described. Furthermore, it should be noted that the language used in this specification has been selected primarily for readability and didactic purposes, rather than for the purpose of explaining or limiting the subject matter of the present invention. Consequently, many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the appended claims. The disclosure of the present invention is intended to be illustrative rather than restrictive of the scope of the invention, which is defined by the appended claims.

Claims

1. A cache comprising: a data array group, the data array group comprising a plurality of data arrays, each data array comprising a predetermined number of cache data rows, each cache data row having a corresponding data index; as well as a tag array group, the tag array group comprising a plurality of tag arrays, each tag array corresponding to a data array, and each tag array comprising a plurality of sub-tag arrays, each sub-tag array comprising a predetermined number of tags, each tag having a corresponding tag index and containing a physical address corresponding to a cache data line in the data array; Wherein, a tag index, a data index and a subtag index are generated based on a virtual address contained in a data access request, the data index is used to retrieve a corresponding cache data row in the data array group, and the tag index is used to retrieve a corresponding tag in the tag array group; when the physical address corresponding to the virtual address is the same as the physical address contained in the retrieved tag, the retrieved tag is a hit tag; when the subarray position of the subtag array where the hit tag is located in the tag array is consistent with the subtag index, the cache data row of the data array corresponding to the tag array where the hit tag is located is selected from the retrieved cache data rows as the data to be accessed.

2. The cache of claim 1, wherein: The tag index is generated based on the first part of the virtual address, the data index is generated based on the second part of the virtual address, the subtag index is generated based on the third part of the virtual address, and the second part of the virtual address includes at least the first part and the third part of the virtual address.

3. The cache of claim 2, wherein: When the subarray position is inconsistent with the subtag index, calculating a new data index according to the tag index and the subarray position; Retrieving a new cache data line corresponding to the new data index in a data array corresponding to the tag array where the hit tag is located; Writing the hit tag into the tag array where the hit tag is located, at a position indicated by the tag index in the sub-tag array corresponding to the sub-tag index; as well as The new cache data line is written to the same data array at a location indicated by the data index. 4 . The cache of claim 3 , wherein after the new cache data line is retrieved, the new cache data line is selected as the data to be accessed. 5 . The cache of claim 3 , wherein after the new cache data line is written to the location indicated by the data index, the new cache data line is read from the location indicated by the data index as data to be accessed.

6. The cache of any one of claims 2 to 5, wherein when it is determined that the hit tag does not exist, the data line at the physical address is retrieved from a memory; Creating a tag based on the physical address, and writing the created tag into the tag array at a location indicated by the tag index in the subtag array corresponding to the subtag index; as well as The acquired data row is written into the data array corresponding to the tag array at the location indicated by the data index.

7. The cache according to any one of claims 1 to 5, wherein the tag further includes status information of the cache data line.

8. An instruction processing device comprising the cache according to any one of claims 1 to 7 and a data access unit, wherein the data access unit is adapted to receive a data access request and process it to return the requested data, the data access unit comprising: an address generation unit, adapted to obtain, based on the data access request, a virtual address of data to be accessed by the data access request, and generate a tag index, a data index, and a subtag index based on the obtained virtual address, wherein the tag index is generated based on a first portion of the virtual address, the data index is generated based on a second portion of the virtual address, and the subtag index is generated based on a third portion of the virtual address, and the second portion of the virtual address includes at least the first portion and the third portion of the virtual address; a memory management unit, coupled to the address generation unit and adapted to obtain a physical address corresponding to the virtual address; a physical tag comparator coupled to the memory management unit and the tag array group in the cache, adapted to compare the physical address obtained by the memory management unit with the physical address included in the tag retrieved from the tag array group and corresponding to the tag index to determine a hit tag having the same physical address; as well as a data output unit adapted to select, from cache data rows retrieved from a data array group in the cache according to the data index, a cache data row from the data array corresponding to the tag array where the hit tag is located as data to be output when the subarray position of the subtag array where the hit tag is located in the tag array is consistent with the subtag index.

9. The instruction processing apparatus according to claim 8, further comprising: a backfill buffer adapted to calculate a new data index based on the tag index and the subarray position when the subarray position is inconsistent with the subtag index; Retrieving a new cache data line corresponding to the new data index in a data array corresponding to the tag array where the hit tag is located; writing the hit tag to a location indicated by the tag index in a subtag array corresponding to the subtag index in the tag array where the hit tag is located; and writing the new cache data line into the same data array at a location indicated by the data index.

10. The instruction processing apparatus according to claim 9, wherein after the backfill buffer retrieves the new cache data line, it selects the new cache data line and sends it to the data output unit, so that the data output unit selects the new cache data line as data to be output.

11. The instruction processing apparatus according to claim 9, wherein after the backfill buffer writes the new cache data line to the location indicated by the data index, the data output unit reads the new cache data line from the location indicated by the data index as data to be output.

12. The instruction processing apparatus according to any one of claims 9 to 11, wherein the backfill buffer is further adapted to: When the physical tag comparator determines that the hit tag does not exist, fetching a data row at the physical address from a memory coupled to the instruction processing device, so as to send the fetched data row to the data output unit as data to be output; Creating a tag based on the physical address, and writing the created tag into a tag array at a location indicated by the tag index in the subtag array corresponding to the subtag index; as well as The acquired data row is written into the data array corresponding to the tag array at the location indicated by the data index.

13. The instruction processing apparatus according to any one of claims 8 to 11, wherein the address generation unit is further adapted to generate a data offset based on the obtained virtual address, the data offset being generated based on a fourth portion of the virtual address; and The data output unit is further adapted to select data at a position indicated by the data offset in the cache data line as the data to be output.

14. The instruction processing apparatus according to claim 12, wherein the address generation unit is further adapted to generate a data offset based on the obtained virtual address, the data offset being generated based on a fourth portion of the virtual address; and The data output unit is further adapted to select data at a position indicated by the data offset in the cache data line as the data to be output.

15. The instruction processing apparatus according to claim 13 , wherein the fourth portion of the virtual address comprises a plurality of bits starting from the least significant bit of the virtual address, and the number of bits included in the fourth portion corresponds to the length of the data row; The first portion of the virtual address includes a plurality of bits immediately adjacent to the fourth portion in order of address bits from low to high; The third portion of the virtual address includes one or more bits adjacent to the first portion in order of address bits from low to high, and the number of bits included in the third portion corresponds to the number of subtag arrays; and The second portion of the virtual address includes the first portion and a third portion.

16. The instruction processing apparatus according to claim 14 , wherein the fourth portion of the virtual address comprises a plurality of bits starting from the least significant bit of the virtual address, and the number of bits included in the fourth portion corresponds to the length of the data line; The first portion of the virtual address includes a plurality of bits immediately adjacent to the fourth portion in order of address bits from low to high; The third portion of the virtual address includes one or more bits adjacent to the first portion in order of address bits from low to high, and the number of bits included in the third portion corresponds to the number of subtag arrays; and The second portion of the virtual address includes the first portion and a third portion. 17 . The instruction processing apparatus according to claim 8 , wherein the tag further includes status information of the cache data line.

18. A data access method, adapted to be executed in an instruction processing device comprising the cache according to any one of claims 1 to 7, the method comprising the steps of: Acquire, based on the data access request, a virtual address of data to be accessed by the data access request; generating a tag index, a data index, and a subtag index based on the obtained virtual address, wherein the tag index is generated based on a first portion of the virtual address, the data index is generated based on a second portion of the virtual address, and the subtag index is generated based on a third portion of the virtual address, wherein the second portion of the virtual address includes at least the first portion and the third portion of the virtual address; Retrieving a cache data row corresponding to the data index in the cache data array group; Retrieving a tag corresponding to the tag index from the tag array group in the cache; obtaining a physical address corresponding to the virtual address and comparing the obtained physical address with the physical address contained in the tag retrieved from each subtag array to determine a hit tag having the same physical address; as well as When the sub-array position of the sub-tag array where the hit tag is located in the tag array is consistent with the sub-tag index, a cache data line from the data array corresponding to the tag array where the hit tag is located is selected from the retrieved cache data lines as the data to be accessed.

19. The method of claim 18, further comprising the steps of: When the subarray position is inconsistent with the subtag index, calculating a new data index according to the tag index and the subarray position; Retrieving a new cache data line corresponding to the new data index in a data array corresponding to the tag array where the hit tag is located; Writing the hit tag into the tag array where the hit tag is located, at a position indicated by the tag index in the sub-tag array corresponding to the sub-tag index; as well as The new cache data line is written to the same data array at a location indicated by the data index.

20. The method of claim 19, further comprising the steps of: After the new cache data line is retrieved, the new cache data line is selected as data to be accessed.

21. The method of claim 19, further comprising the steps of: After writing the new cache data line to the location indicated by the data index, the new cache data line is read from the location indicated by the data index as data to be accessed.

22. The method according to any one of claims 18 to 21, further comprising the steps of: When it is determined that the hit tag does not exist, obtaining a data row at the physical address from a memory coupled to the instruction processing device, and using the obtained data row as data to be accessed; Creating a tag based on the physical address, and writing the created tag into a tag array at a location indicated by the tag index in the subtag array corresponding to the subtag index; as well as The acquired data row is written into the data array corresponding to the tag array at the location indicated by the data index.

23. The method according to any one of claims 18 to 21, further comprising the steps of: generating a data offset based on the obtained virtual address, the data offset being generated based on a fourth portion of the virtual address; and The selecting a cache data line from a data array corresponding to the tag array where the hit tag is located as data to be accessed comprises: The data at the position indicated by the data offset in the cache data line is selected as the data to be accessed.

24. The method of claim 22, further comprising the steps of: generating a data offset based on the obtained virtual address, the data offset being generated based on a fourth portion of the virtual address; and The selecting a cache data line from a data array corresponding to the tag array where the hit tag is located as data to be accessed comprises: The data at the position indicated by the data offset in the cache data line is selected as the data to be accessed.

25. The method of claim 23, wherein the fourth portion of the virtual address comprises a plurality of bits starting from the least significant bit of the virtual address, and the number of bits included in the fourth portion corresponds to the length of the data row; The first portion of the virtual address includes a plurality of bits immediately adjacent to the fourth portion in order of address bits from low to high; The third portion of the virtual address includes one or more bits adjacent to the first portion in order of address bits from low to high, and the number of bits included in the third portion corresponds to the number of subtag arrays; and The second portion of the virtual address includes the first portion and a third portion.

26. The method of claim 24, wherein the fourth portion of the virtual address comprises a plurality of bits starting from the least significant bit of the virtual address, and the number of bits included in the fourth portion corresponds to the length of the data row; The first portion of the virtual address includes a plurality of bits immediately adjacent to the fourth portion in order of address bits from low to high; The third portion of the virtual address includes one or more bits adjacent to the first portion in order of address bits from low to high, and the number of bits included in the third portion corresponds to the number of subtag arrays; and The second portion of the virtual address includes the first portion and a third portion.

27. The method of any one of claims 18 to 21, wherein the tag further comprises status information of the cache data line.

28. A system on chip, comprising the instruction processing device according to any one of claims 8 to 17.

29. An intelligent device comprising the system on chip according to claim 28.

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