Semiconductor Device and Method of Forming the Same

Abstract

The present invention provides a semiconductor device and a method for forming the same. The method for forming the same includes: providing a substrate on which fins are formed, and the fins include a dense region and a sparse region; forming a gate structure and source / drain doping layers across the fins on the substrate, and the source / drain doping layers are located in the fins on both sides of the gate structure; forming a dielectric layer on the substrate, and the dielectric layer covers the top of the gate structure; forming a first through hole in the dielectric layer on one side of the gate structure in the sparse region, and the bottom of the first through hole exposes the top sidewall of the gate structure. Since the depth of the formed first through hole becomes shallower, when filling the metal layer in the first through hole subsequently, the volume of the metal layer filled in the first through hole can be reduced, so that the parasitic capacitance generated at the connection between the gate structure and the source / drain doping layers is reduced, and the performance and quality of the formed semiconductor device are improved, and the sensitivity of use is enhanced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a semiconductor device and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration. As the most basic semiconductor device, the device is currently widely used. The traditional planar device has a weakened ability to control the channel current, resulting in a short-channel effect and leakage current, ultimately affecting the electrical performance of the semiconductor device.

[0003] To overcome the short-channel effect of the device and suppress leakage current, the prior art has proposed a fin field-effect transistor (Fin FET). The fin field-effect transistor is a common multi-gate device. The structure of the fin field-effect transistor includes: a fin portion and an isolation structure located on the surface of a semiconductor substrate. The isolation structure covers the sidewalls of part of the fin portion, and the surface of the isolation structure is lower than the top of the fin portion; a gate structure located on the surface of the isolation structure, and the top and sidewall surfaces of the fin portion; source regions and drain regions located in the fin portions on both sides of the gate structure.

[0004] However, with the reduction of the size of semiconductor devices and the increase of device density, the process difficulty of forming a fin field-effect transistor increases, and the performance of the formed fin field-effect transistor is also unstable. Summary of the Invention

[0005] The problem solved by the present invention is to provide a semiconductor device and a method for forming the same to improve the performance of the semiconductor device.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor device, including: providing a substrate on which a fin portion is formed, the fin portion including a dense region and a sparse region; forming a gate structure and source-drain doping layers across the fin portion on the substrate, the source-drain doping layers being located in the fin portions on both sides of the gate structure; forming a dielectric layer on the substrate, the dielectric layer covering the top of the gate structure; forming a first through hole in the dielectric layer on one side of the gate structure in the sparse region, the bottom of the first through hole exposing the top sidewall of the gate structure.

[0007] Optionally, the material of the dielectric layer includes: silicon oxide, silicon nitride, silicon boron nitride, silicon carbon oxide, or silicon oxynitride.

[0008] Optionally, the process for forming the first through hole is a dry etching process or a wet etching process.

[0009] Optionally, it further includes: etching the dielectric layer on top of the gate structure to form a second through hole in the dielectric layer, and the second through hole exposes the top of a part of the gate structure.

[0010] Optionally, the steps of forming the first through hole and the second through hole include: forming a first mask layer on the dielectric layer, and the opening of the first mask layer exposes the top of the dielectric layer on one side of the gate structure in the sparse region and a part of the dielectric layer on top of the gate structure; using the first mask layer as a mask, etching away the exposed dielectric layer to form the first through hole and the second through hole in the dielectric layer; removing the first mask layer.

[0011] Optionally, it further includes: etching the dielectric layer on the source-drain doping layer until the top of the source-drain doping layer is exposed, and forming a third through hole in the dielectric layer.

[0012] Optionally, the steps of forming the third through hole include: forming a second mask layer on the dielectric layer, and the opening of the second mask layer exposes the dielectric layer on top of the source-drain doping layer; etching away the exposed dielectric layer to form the third through hole in the dielectric layer; removing the second mask layer.

[0013] Optionally, after forming the third through hole, it further includes filling a metal layer in the first through hole, the second through hole, and the third through hole.

[0014] Optionally, the material of the metal layer includes tungsten, cobalt, titanium, or nickel.

[0015] Optionally, it further includes: forming an isolation layer, and the isolation layer is located on the substrate and covers a part of the sidewalls of the fin.

[0016] Optionally, before forming the dielectric layer on the substrate, it further includes: forming an etch stop layer, and the etch stop layer is formed on the substrate, a part of the sidewalls of the fin, the top and sidewalls of the source-drain doping layer, and the sidewalls of the gate structure.

[0017] Correspondingly, the present invention further provides a semiconductor device formed by using the above method, including: a substrate; fins, located on the substrate and including a dense region and a sparse region; a gate structure, located on the substrate and spanning the fins; source-drain doping layers, located in the fins on both sides of the gate structure; a dielectric layer, located on the substrate and covering the gate structure; a first through hole, located in the dielectric layer on one side of the gate structure between the sparse regions, and the bottom exposes the top sidewall of the gate structure.

[0018] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0019] After forming fins on a substrate, a gate structure spanning the fins, and source / drain doping layers within the fins on both sides of the gate structure, a dielectric layer is formed on the substrate. The dielectric layer covers the top of the gate structure. A first via hole is formed in the dielectric layer on one side of the gate structure between the fin sparse regions. The bottom of the first via hole exposes the top sidewall of the gate structure. Since the depth of the first via hole becomes shallower, when filling the subsequent metal layer in the first via hole, the volume of the metal layer that can be filled in the first via hole is reduced, thereby reducing the parasitic capacitance generated at the connection between the gate structure and the source / drain doping layers, improving the performance and quality of the formed semiconductor device, and enhancing the sensitivity of use. Description of the Drawings

[0020] Figures 1 to 11 is a schematic structural diagram of a semiconductor device in an embodiment;

[0021] Figures 12 to 27 is a schematic structural diagram of the formation process of a semiconductor device in an embodiment of the present invention. Detailed Embodiments

[0022] In the currently formed semiconductor device, during use, the parasitic capacitance between the gate structure and the connection of the source / drain doping layers is relatively large, seriously affecting the performance of the semiconductor device. For the specific formation process, refer to Figures 1 to 11 .

[0023] First, refer to Figure 1 , provide a substrate 100, and form a plurality of fins 110 on the substrate 100. The fins 110 include fin sparse regions 111 and fin dense regions 112.

[0024] Refer to Figure 2 , and form a gate structure 120 spanning the fins 110 on the substrate 100.

[0025] Refer to Figure 3 , Figure 3 is Figure 2 a cross-sectional view along the cutting line A - A, and form source / drain doping layers 130 within the fins 110 on both sides of the gate structure 120.

[0026] Refer to Figures 4 to 5 , Figure 5 is Figure 4 a top view of, and form a dielectric layer 140 on the substrate 100. The dielectric layer 140 covers the source / drain doping layers 130 and the gate structure 120, and the top surface is higher than the top surface of the gate structure 120.

[0027] A mask layer (not shown in the figure) is formed on the dielectric layer 140. The openings of the mask layer respectively expose the dielectric layer 140 on top of part of the gate structure 120, the dielectric layer 140 on top of the source-drain doping layer 130, and the dielectric layer 140 on one side of the gate structure 120 between the fins 120 of the sparse region 111.

[0028] Reference Figure 6 , Figure 6 is Figure 5 A cross-sectional view of removing the exposed dielectric layer 140 at the cross-section line A-A. The dielectric layer 140 on top of the gate structure 120 is etched to form a second through-hole 150, and the bottom of the second through-hole 150 exposes the top surface of the gate structure 120.

[0029] Reference Figure 7 , a metal layer 180 is filled in the second through-hole 150.

[0030] Reference Figure 8 , Figure 8 is Figure 5 A cross-sectional view of removing the exposed dielectric layer 140 at the cross-section line B-B. The dielectric layer 140 on one side of the gate structure 120 between the fin sparse regions 111 is etched to form a first through-hole 160, and the bottom surface of the first through-hole 160 exposes the surface of the substrate 100.

[0031] Reference Figure 9 , a metal layer 180 is filled in the first through-hole 160.

[0032] Reference Figure 10 , Figure 10 is Figure 5 A cross-sectional view of removing the exposed dielectric layer 140 at the cross-section line C-C. The dielectric layer 140 on the source-drain doping layers 130 on both sides of the gate structure 120 is etched to form a third through-hole 170, and the bottom of the third through-hole 170 exposes the top surface of the source-drain doping layer 130.

[0033] Reference Figure 11 , a metal layer 180 is filled in the third through-hole 170.

[0034] The inventors found that in the fin sparse region, the dielectric layer on one side of the gate structure is etched to form a first through hole, and the bottom surface of the first through hole exposes the surface of the substrate. A metal layer is filled in the first through hole to achieve electrical connection at the connection of the source-drain doping layers in the fins on both sides of the fin sparse region. However, since the bottom surface of the first through hole exposes the surface of the substrate, the depth of the formed first through hole is relatively large, the volume of the metal layer to be filled is relatively large, and the parasitic capacitance generated between the gate structure and the connection of the source-drain doping layers is very large, thereby reducing the sensitivity and stability of the semiconductor device during use and restricting the use of the semiconductor device.

[0035] The inventors' research found that in the fin sparse region, when forming a metal layer to electrically connect the source-drain doping layers in the fins of the sparse region, when etching the dielectric layer on one side of the gate structure to form a first through hole, only the top sidewall of the gate structure needs to be exposed at the bottom of the first through hole. In this way, when filling the metal layer in the first through hole, on the one hand, the electrical connection between the source-drain doping layers of the fins in the sparse region is achieved, and on the other hand, the volume of the metal layer filled in the first through hole is reduced, thereby reducing the parasitic capacitance generated between the gate structure and the connection of the source-drain doping layers, improving the performance and sensitivity of the formed semiconductor device, and expanding the use of the semiconductor device.

[0036] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically describes the embodiments of the present invention in detail with reference to the drawings.

[0037] Figures 12 to 27 It is a schematic structural diagram of the formation process of a semiconductor device in an embodiment of the present invention.

[0038] First, refer to Figure 12 , a substrate 200 is provided, and fins 300 are formed on the substrate 200. The fins include a sparse region 310 and a dense region 320.

[0039] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate 200 may also be semiconductor materials such as germanium, silicon germanide, gallium arsenide, indium gallium arsenide, etc., and may also be a semiconductor-on-insulator structure. The semiconductor-on-insulator structure includes an insulator and a semiconductor material layer located on the insulator. The material of the semiconductor material layer includes semiconductor materials such as silicon, germanium, silicon germanide, gallium arsenide, indium gallium arsenide, etc.

[0040] In this embodiment, the step of forming the fins 300 includes: forming a patterned layer (not shown in the figure) on the substrate 200. The patterned layer corresponds to the position of the fins 300 to be formed. Using the patterned layer as a mask, a part of the thickness of the substrate 200 is etched to form a plurality of discretely arranged fins 300 on the substrate 200, and the patterned layer is removed.

[0041] In other embodiments, a material layer of the fin portion 300 may also be deposited on the substrate 200, a patterned layer is formed on the material layer of the fin portion 300, the position of the fin portion 300 corresponding to the formed patterned layer, using the patterned layer as a mask, etching the material layer of the fin portion 300 until the surface of the substrate 200 is exposed, forming a plurality of discrete fin portions 300 on the substrate 200, and removing the patterned layer.

[0042] In this embodiment, an isolation layer 210 is formed on the substrate 200, and the isolation layer 210 covers a part of the sidewalls of the fin portions 300; in other embodiments, the isolation layer 210 may not be formed on the substrate 200.

[0043] In this embodiment, the material of the isolation layer 210 is silicon oxide; in other embodiments, the material of the isolation layer 210 may also be silicon nitride, silicon carbide, etc.

[0044] In this embodiment, the isolation layer 210 is used to isolate adjacent fin portions 300 to prevent subsequent leakage, short circuit and other phenomena.

[0045] The method for forming the isolation layer 210 includes: forming an isolation layer film (not shown) covering the fin portions 300 on the substrate 200; back-etching the isolation layer film to form the isolation layer 210.

[0046] The process for forming the isolation layer film is a deposition process, such as a fluid chemical vapor deposition process. Using the fluid chemical vapor deposition process to form the isolation layer film, the filling performance of the isolation layer film is better.

[0047] The steps of the fluid chemical vapor deposition process for forming the isolation layer film include: forming an isolation fluid layer on the substrate 200; performing water vapor annealing to form the isolation layer film from the isolation fluid layer.

[0048] The parameters of the water vapor annealing include: the gases used include oxygen, ozone and gaseous water, and the annealing temperature is 350 degrees Celsius to 750 degrees Celsius.

[0049] Reference Figures 13 to 14 and, a gate structure 400 and source / drain doping layers 500 spanning the fin portions 300 are formed on the substrate 200, and the source / drain doping layers 500 are located in the fin portions 300 on both sides of the gate structure 400.

[0050] Figure 14 is Figure 13 A cross-sectional view along the cutting line A-A.

[0051] In this embodiment, the gate structure 400 includes a gate dielectric layer and a gate layer located on the gate dielectric layer. The material of the gate dielectric layer is a high-K (K > 3.9) dielectric material, and the material of the gate layer is a metal, such as tungsten.

[0052] In this embodiment, a spacer layer (not shown in the figure) is formed on the sidewalls of the gate structure 400; in other embodiments, the spacer layer may not be formed on the sidewalls of the gate structure 400.

[0053] In this embodiment, the purpose of forming the spacer layer is to define the formation position of the source / drain doping layer.

[0054] In this embodiment, the process of forming the gate structure 400 is a back-gate process: first, a dummy gate structure spanning the fin 300 is formed on the substrate 200, and then the formed dummy gate structure is removed to form the gate structure 400; in other embodiments, a front-gate process may also be used, that is, the gate structure 400 spanning the fin 300 is directly formed on the substrate 200.

[0055] In this embodiment, grooves are formed in the fins 300 on both sides of the gate structure 400, and the source / drain doping layer 500 is formed in the grooves, and doping is performed using an ion implantation process.

[0056] In this embodiment, the source / drain doping layer 500 has source / drain ions. When the type of the semiconductor device is N-type, the conduction type of the source / drain ions is N-type, such as phosphorus ions; when the type of the semiconductor device is P-type, the conduction type of the source / drain ions is P-type, such as boron ions.

[0057] In this embodiment, an etch stop layer 220 is formed on the substrate 200, on partial sidewalls of the fin 300, on the top and sidewalls of the source / drain doping layer 500, and on the sidewalls of the gate structure 400; in other embodiments, the etch stop layer 220 may not be formed.

[0058] In this embodiment, the purpose of forming the etch stop layer 220 is to protect the substrate 200, the fin 300, the gate structure 400, and the source / drain doping layer 500 covered by the etch stop layer 220 from being damaged in subsequent processes.

[0059] In this embodiment, the material of the etch stop layer 220 is silicon oxynitride; in other embodiments, the material of the etch stop layer 220 may also be one or more of silicon nitride, silicon oxynitride, carbon oxynitride, carbon silicon nitride, or carbon oxynitride.

[0060] Reference Figures 15 to 16, a dielectric layer 600 is formed on the substrate 200, and the dielectric layer 600 covers the top of the gate structure 400.

[0061] Figure 15 is Figure 16 a cross-sectional view taken along the cutting line A-A, Figure 16 is Figure 15 a top view of.

[0062] In this embodiment, for convenience of representation, Figure 15 and 16 only one gate structure is shown.

[0063] In this embodiment, the material of the dielectric layer 600 is silicon oxide; in other embodiments, the material of the dielectric layer 600 can also be one or a combination of silicon oxide, silicon nitride, silicon boron nitride, silicon carbon oxynitride, or silicon oxynitride.

[0064] In this embodiment, the dielectric layer 600 is formed by chemical vapor deposition; in other embodiments, the dielectric layer 600 can also be formed by atomic layer vapor deposition or physical vapor deposition.

[0065] In this embodiment, after the dielectric layer 600 is formed, planarization is performed, and the planarization process is chemical mechanical polishing or back etching.

[0066] In this embodiment, the process parameters for forming the dielectric layer 600 include: the gases used include oxygen, ammonia (NH3), and N(SiH3)3 gas, the flow rate of oxygen is 20 sccm to 10000 sccm, the flow rate of ammonia (NH3) gas is 20 sccm to 10000 sccm, the flow rate of N(SiH3)3 gas is 20 sccm to 10000 sccm, the chamber pressure is 0.01 torr to 10 torr, and the temperature is 30 degrees Celsius to 90 degrees Celsius.

[0067] A first through hole 610 is formed in the dielectric layer 600 on one side of the gate structure 400 between the sparse regions 310 of the fin 300, and the bottom of the first through hole 610 exposes the top sidewall of the gate structure 400. For the specific formation process, refer to Figures 17 to 20 .

[0068] Refer to Figure 17 , a first mask layer 700 is formed on the dielectric layer 600, and the opening of the first mask layer 700 exposes the top of the dielectric layer 600 on one side of the gate structure 400 between the sparse regions 310 of the fin 300 and a part of the dielectric layer 600 on the top of the gate structure 400.

[0069] In this embodiment, the material of the first mask layer 700 is photoresist.

[0070] In this embodiment, the steps of forming the first mask layer 700 include: forming an initial first mask layer on the dielectric layer 600, forming a mask plate on the initial first mask layer, using the mask plate as a mask to develop the initial first mask layer, and removing the mask plate, thereby forming the first mask layer 700 that meets the requirements on the dielectric layer 600.

[0071] Reference Figures 18 to 20 , using the first mask layer 700 as a mask, etching away the exposed dielectric layer 600, forming the first through hole 610 and the second through hole 620 in the dielectric layer 600, and removing the first mask layer 700.

[0072] Figure 18 is Figure 19 and Figure 20 a top view of; Figure 19 is Figure 18 a cross-sectional view along the section line A - A; Figure 20 is Figure 18 a cross-sectional view along the section line B - B.

[0073] In this embodiment, reference Figure 19 , using the first mask layer 700 as a mask, etching away the exposed dielectric layer 600, and forming the first through hole 610 in the dielectric layer 600.

[0074] In this embodiment, the bottom of the first through hole 610 exposes the top sidewall of the gate structure 400, and is subsequently used to fill a metal layer to connect the source-drain doping layers 500 in the fins 300 on both sides of the sparse region 310, realizing the electrical connection between the joints of the source-drain doping layers 500.

[0075] Reference Figure 20 , using the first mask layer 700 as a mask, etching away the exposed dielectric layer 600, and forming the second through hole 620 in the dielectric layer 600,

[0076] In this embodiment, the bottom of the second through hole 620 exposes a part of the top of the gate structure 400, and is subsequently used to fill a metal layer to realize the electrical connection with the gate structure 400.

[0077] In this embodiment, a metal layer is filled in the first through hole 610 to achieve electrical connection between the source-drain doping layers 500 in the fin portions 300 on both sides of the sparse region 310. Since the top sidewall of the gate structure 400 is exposed at the bottom of the first through hole 610, the depth of the formed first through hole 610 is greatly reduced. In this way, the volume of the metal layer that can be filled in the first through hole 610 is greatly reduced. Thus, during the use of the semiconductor device, the parasitic capacitance generated at the connection between the gate structure 400 and the source-drain doping layer 500 of the sparse region 310 is reduced, thereby reducing the thermal noise generated during the use of the semiconductor device and improving the sensitivity and stability of the use performance of the semiconductor device, and greatly improving the quality of the formed semiconductor device.

[0078] In this embodiment, the process for forming the first through hole 610 and the second through hole 620 is a dry etching process; in other embodiments, a wet etching process may also be used to form the first through hole 610 and the second through hole 620.

[0079] In this embodiment, the process parameters for forming the first through hole 610 and the second through hole 620 include selecting helium (He), ammonia (NH3), and NF3 gas as the etching atmosphere. Among them, the gas flow rate range of the helium (He) is 600 sccm to 2000 sccm, the gas flow rate of the ammonia (NH3) is 200 sccm to 5000 sccm, the gas flow rate of the NF3 gas is 20 sccm to 2000 sccm, the etching pressure is 2 to 100 mTorr, and the etching treatment time is 20 to 1000 s.

[0080] In this embodiment, the first through hole 610 and the second through hole 620 are formed using the same mask layer, so that the formed first through hole 610 and the second through hole 620 can have the same depth, avoiding the depth of the formed first through hole 610 being too large. On the one hand, it is convenient to control the depth of the formed first through hole 610. On the other hand, there is no need to additionally form a mask layer to control the depth of the formed first through hole 610, saving costs and simplifying the process flow.

[0081] Reference Figures 21 to 22 , a second mask layer 800 is formed on the dielectric layer 600, and the opening of the second mask layer 800 exposes the dielectric layer 600 on top of the source-drain doping layer 500.

[0082] Figure 22 is Figure 21 a top view of Figure 21 is Figure 22 a cross-sectional view along the cutting line A - A.

[0083] In this embodiment, the material of the second mask layer 800 is also photoresist, and the formation steps are the same as those of the first mask layer 700, so no redundant description will be given here.

[0084] Reference Figure 23 , etch away the exposed dielectric layer 600 until the top surface of the source / drain doping layer 500 is exposed, form a third through-hole 630 in the dielectric layer 600, and remove the second mask layer 800.

[0085] In this embodiment, the process parameters for forming the third through-hole 630 include: using helium (He), ammonia (NH3), and NF3 gases as the etching atmosphere, where the gas flow rate range of the helium (He) is 600 sccm to 2000 sccm, the gas flow rate of the ammonia (NH3) is 200 sccm to 5000 sccm, the gas flow rate of the NF3 gas is 100 sccm to 2000 sccm, the etching pressure is 50 to 100 mTorr, and the etching treatment time is 500 to 1000 s.

[0086] Reference Figures 24 to 27 , fill the first through-hole 610, the second through-hole 620, and the third through-hole 630 with a metal layer 900, and remove the dielectric layer 600.

[0087] Figure 24 is Figures 25 to 27 the top view of Figure 25 is Figure 24 the cross-sectional view along the cutting line A-A, Figure 26 is Figure 24 the cross-sectional view along the cutting line B-B, Figure 27 is Figure 24 the cross-sectional view along the cutting line C-C.

[0088] In this embodiment, reference Figure 25 , fill the metal layer 900 in the first through-hole 610 to connect the source / drain doping layers 500 between the sparse regions 310, so as to realize the mutual electrical connection with the source / drain doping layers 500 between the sparse regions 310.

[0089] In this embodiment, reference Figure 26 , fill the metal layer 900 in the second through-hole 620 to realize the electrical connection with the gate structure 400.

[0090] In this embodiment, reference Figure 27 , fill the metal layer 900 in the third through-hole 630, and form a conductive structure on the source / drain doping layer 500 to realize the electrical connection with the source / drain doping layer 500.

[0091] In this embodiment, the material of the metal layer 900 is tungsten; in other embodiments, the material of the metal layer 900 can also be cobalt, titanium or nickel.

[0092] In this embodiment, the metal layer 900 is formed by atomic layer chemical vapor deposition; in other embodiments, the metal layer 900 can also be formed by chemical vapor deposition or physical vapor deposition.

[0093] In this embodiment, the reason for forming the metal layer 900 by atomic layer chemical vapor deposition is that atomic layer chemical vapor deposition has good material step coverage ability, and can form a high-quality metal layer 900 in the first through hole 610, the second through hole 620 and the third through hole 630, thereby improving the quality of the formed semiconductor device.

[0094] In this embodiment, before forming the metal layer 900, an adhesion layer (not shown in the figure) is further formed on the bottom and side walls of the first through hole 610, the second through hole 620 and the third through hole 630. The formed adhesion layer helps the subsequent adhesion of the formed metal layer 900 and improves the quality of the formed metal layer 900.

[0095] In this embodiment, the adhesion layer is a Ti / TiN layer, and 150 Å to 210 Å of Ti and 490 Å to 550 Å of TiN are deposited by physical vapor deposition. Gas Ar is introduced to bombard the Ti target to deposit the Ti film. Gas Ar and N2 are introduced to bombard the Ti target to deposit the TiN film. Annealing can be performed after forming the adhesion layer to repair the surface of the damaged substrate 200.

[0096] In this embodiment, the steps of forming the metal layer 900 include: first forming a seed layer of the metal layer 900 on the bottom and side walls of the first through hole 610, the second through hole 620 and the third through hole 630; then depositing a large amount of the material of the metal layer on the seed layer of the metal layer 900 to form the metal layer 900.

[0097] In this embodiment, the material of the metal layer 900 is W, and the gases used to form the metal layer 900 include WF6, SiH4 and H2, and the forming method is chemical vapor deposition.

[0098] Correspondingly, the present invention further provides a semiconductor device formed by using the above method, including: a substrate 200; a fin portion 300 located on the substrate 200 and including a dense region 320 and a sparse region 310; a gate structure 400 located on the substrate 200 and spanning the fin portion 300; source / drain doping layers 500 located in the fin portion 300 on both sides of the gate structure 400; a dielectric layer 600 located on the substrate 200 and covering the gate structure 400; a first via 610 located in the dielectric layer 600 on one side of the gate structure 400 between the sparse regions 310 of the fin portion 300, and the bottom of which exposes the top sidewall of the gate structure 400.

[0099] In this embodiment, only the top sidewall of the gate structure 400 is exposed at the bottom of the formed first via 610, reducing the depth of the formed first via 610. In this way, when filling the metal layer in the first via 610, the volume of the filled metal layer can be reduced, thereby reducing the parasitic capacitance generated between the gate structure and the connection between the source / drain doping layer in the fin portion of the sparse region during the use of the semiconductor device, and improving the performance and quality of the formed semiconductor device.

[0100] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor device, characterized in that, Including: Providing a substrate on which fins are formed, the fins including a dense region and a sparse region, the sparse region being located between adjacent dense regions; Forming a gate structure and source / drain doping layers across the fins on the substrate, the source / drain doping layers being located within the fins on both sides of the gate structure; Forming a dielectric layer on the substrate, the dielectric layer covering the top of the gate structure; Forming a first through hole in the dielectric layer on one side of the gate structure in the sparse region, the bottom of the first through hole exposing the top sidewall of the gate structure and a part of the dielectric layer, the first through hole being used to fill with a metal layer to connect the source / drain doping layers within the fins on both sides of the sparse region, so as to achieve electrical connection between the joints of the source / drain doping layers.

2. The forming method according to claim 1, wherein, The material of the dielectric layer includes: silicon oxide, silicon nitride, silicon boron nitride, silicon carbon oxynitride or silicon oxynitride.

3. The forming method according to claim 1, wherein The process of forming the first through hole is a dry etching process or a wet etching process.

4. The forming method according to claim 1, wherein Also including: Etching the dielectric layer on the top of the gate structure to form a second through hole in the dielectric layer, the second through hole exposing a part of the top of the gate structure.

5. The forming method according to claim 4, wherein The steps of forming the first through hole and the second through hole include: Forming a first mask layer on the dielectric layer, the opening of the first mask layer exposing the top of the dielectric layer on one side of the gate structure in the sparse region and a part of the dielectric layer on the top of the gate structure; Using the first mask layer as a mask to etch and remove the exposed dielectric layer to form the first through hole and the second through hole in the dielectric layer; Removing the first mask layer.

6. The forming method according to claim 4, wherein Also including: Etching the dielectric layer on the source / drain doping layer until the top of the source / drain doping layer is exposed to form a third through hole in the dielectric layer.

7. The forming method according to claim 6, wherein The steps of forming the third through hole include: Forming a second mask layer on the dielectric layer, the opening of the second mask layer exposing the dielectric layer on the top of the source / drain doping layer; Etching and removing the exposed dielectric layer to form the third through hole in the dielectric layer; Removing the second mask layer.

8. The forming method according to claim 6, characterized in that, After forming the third through hole, it further includes filling the first through hole, the second through hole and the third through hole with a metal layer.

9. The forming method according to claim 8, wherein The material of the metal layer includes tungsten, cobalt, titanium or nickel.

10. The forming method according to claim 1, wherein Also including: Forming an isolation layer, the isolation layer being located on the substrate and covering a part of the sidewalls of the fins.

11. The forming method according to claim 1, wherein Before forming the dielectric layer on the substrate, it further includes: forming an etch stop layer, the etch stop layer being formed on the substrate, a part of the sidewalls of the fins, the top and sidewalls of the source / drain doping layers, and the sidewalls of the gate structure.

12. A semiconductor device formed by the forming method according to any one of claims 1-11, characterized in that, Including: A substrate; Fins, located on the substrate and including a dense region and a sparse region, the sparse region being located between adjacent dense regions; A gate structure, located on the substrate and spanning across the fins; Source / drain doping layers, located within the fins on both sides of the gate structure; A dielectric layer, located on the substrate and covering the gate structure; A first through hole is located in the dielectric layer on one side of the gate structure between the sparse regions, and the top sidewall of the gate structure and a part of the dielectric layer are exposed at the bottom. The first through hole is used to fill a metal layer to connect the source / drain doping layers in the fins on both sides of the sparse region, so as to realize electrical connection between the joints of the source / drain doping layers.

Images