A multi-resolution output incremental optical encoder, chip and code disk

Abstract

A multi-resolution output incremental optical encoder, chip and code disk, through a composite optical sensing phase array and a zero position signal sensing array, can integrate multiple resolution capabilities, achieving the technical effect that a certain chip can realize user-selectable coding resolution.

Description

Technical Field

[0001] The present invention relates to photoelectric encoder chip technology, in particular to a multi-resolution output incremental photoelectric encoder and chip and code disk, which can integrate multiple resolutions through a composite light sensing phase array and a zero-position signal sensing array, achieving the technical effect that a certain chip can realize user-selectable encoding resolutions. Background Art

[0002] At present, with the rapid development of automation in my country, the demand for linear displacement and angular displacement measurement has spread to all areas of life and work, and photoelectric encoders are the core products for linear displacement and angular displacement measurement. Photoelectric encoders convert the mechanical geometric displacement on the output shaft into pulses or digital quantities through photoelectric conversion. This is the most widely used sensor at present. Photoelectric encoders are composed of light sources, optical code disks, and photosensitive elements. The optical code disk is actually a disk engraved with regular transparent and opaque lines. The light flux received by the photosensitive element changes synchronously with the transparent lines. The output waveform of the photosensitive element is shaped and becomes a pulse signal. A group of pulses is output for each rotation. According to the change of the pulse, the displacement of the equipment can be accurately measured and controlled. In actual production and life, according to different application requirements, the linear requirements of photoelectric encoders are varied, ranging from low requirements for 1 circle of 50 lines to high requirements for 1 circle of 10,000 lines. The overall resolution requirements span a wide range. In order to meet a variety of diverse needs, it is necessary to equip a variety of photoelectric encoders. Each photoelectric encoder that meets the requirements includes a photoelectric encoder chip that meets the requirements and a code disk that corresponds to the linear requirements of the photoelectric encoder chip. This virtually increases the cost of production and the difficulty of structural design, greatly limiting efficient product production and testing. This is a very troublesome thing for both the manufacturers of photoelectric encoders and the manufacturers who use photoelectric encoders. The inventor believes that reducing the restrictions on production caused by diverse requirements during the production process and reducing the complexity of the design structure can form the core technology of the manufacturer and improve the core competitiveness of the product. In view of this, the inventor has completed the present invention. Summary of the invention

[0003] In view of the defects or shortcomings in the prior art, the present invention provides a multi-resolution output incremental photoelectric encoder, chip and code disk, which can integrate multiple resolutions through a composite light sensing phase array and a zero-position signal sensing array, achieving the technical effect of realizing user-selectable coding resolution with a certain chip.

[0004] The technical solution of the present invention is as follows:

[0005] A multi-resolution output incremental optical encoder, characterized in that it includes an optical encoder chip and an optically modulated code disk adapted thereto. The optical encoder chip includes a composite optical sensing phase array and a zero position signal sensing array. The composite optical sensing phase array is connected to a frequency multiplication and division processing module through a first transimpedance amplifier and a hysteresis comparator combination module. The zero position signal sensing array is connected to a logic processing and selection module through a second transimpedance amplifier and a hysteresis comparator combination module. The logic processing and selection module is respectively connected to the frequency multiplication and division processing module and a signal output end. A plurality of grating tracks are arranged on the optically modulated code disk to adapt to the composite optical sensing phase array.

[0006] The composite optical sensing phase array includes a first-resolution photodiode array and a second-resolution photodiode array. A first grating track and its first zero position signal track, and a second grating track and its second zero position signal track are arranged on the optically modulated code disk. The zero position signal sensing array includes a first grating track zero position signal sensor and a second grating track zero position signal sensor.

[0007] The composite optical sensing phase array includes a third-resolution photodiode array. A third grating track and its third zero position signal track are arranged on the optically modulated code disk. The zero position signal sensing array includes a third grating track zero position signal sensor.

[0008] The optically modulated code disk is of a disk structure. The light-transmitting lines in the grating area on each grating track are evenly distributed along the circumference. The number of light-transmitting lines in the grating area is the intrinsic resolution line number of its corresponding grating track. The intrinsic resolution line number enables the corresponding resolution photodiode array to generate an intrinsic signal transmitted to the first transimpedance amplifier and the hysteresis comparator combination module. The intrinsic signal can be frequency-multiplied or frequency-divided in the frequency multiplication and division processing module.

[0009] The frequency multiplication and division processing module can perform signal processing of 1 / 2, 1 / 4, ×2, ×4 on the intrinsic signal to form multi-resolution optional coding resolution specifications.

[0010] The first grating track, the second grating track, the third grating track, the third zero position signal track, the second zero position signal track, and the first zero position signal track are sequentially distributed on the optically modulated code disk from outside to inside.

[0011] The number of light-transmitting lines in the grating area on the first grating track < the number of light-transmitting lines in the grating area on the second grating track < the number of light-transmitting lines in the grating area on the third grating track.

[0012] A multi-resolution output incremental photoelectric encoder chip, characterized in that it includes a composite light sensing phase array and a zero-position signal sensing array, the composite light sensing phase array is connected to a frequency multiplication and frequency division processing module through a first transimpedance amplifier and a hysteresis comparator combination module, the zero-position signal sensing array is connected to a logic processing and selection module through a second transimpedance amplifier and a hysteresis comparator combination module, and the logic processing and selection module are respectively connected to the frequency multiplication and frequency division processing module and a signal output end.

[0013] The composite optical sensing phase array includes a first resolution photodiode array, a second resolution photodiode array, and a third resolution photodiode array, and the zero position signal sensing array includes a first grating track zero position signal sensor, a second grating track zero position signal sensor, and a third grating track zero position signal sensor.

[0014] An optical signal modulation code disk, characterized in that it includes a first grating track and a first zero-position signal track thereof, a second grating track and a second zero-position signal track thereof, and a third grating track and a third zero-position signal track thereof, wherein the optical signal modulation code disk is a disk structure, and the grating area transmissive lines on each grating track are uniformly distributed along the circumference, and the number of the grating area transmissive lines is the number of intrinsic resolution lines of the grating track to which it belongs.

[0015] The technical effects of the present invention are as follows: The present invention is a multi-resolution output incremental photoelectric encoder and chip and code disk, based on a composite light sensing phase array structure, which integrates more than ten commonly used circular linear resolution application requirements on a single chip. The chip's phase light sensing array is 2 to 3 independent phase array track windows. Through the chip selection input terminal, a binary digital coding signal is used to select the required number of coded digital pulses that can be output per circular rotation, thereby achieving a user-selectable coding resolution with a certain chip.

[0016] The present invention has the following characteristics: 1. The present invention adopts a composite phased array structure, integrating the application requirements of more than a dozen commonly used circumferential linear resolutions, solving the problems of increased manufacturing costs and structural design difficulties due to the large variety in chip application design, and greatly improving the production and detection efficiency of products. 2. The digital logic selection method adopted by the present invention simplifies the cumbersome design structure in the application process. Each group of signals corresponding to the selected resolution requirements uniquely corresponds to a group of logic outputs, facilitating the structural design and detection scheme design of the optoelectronic encoder. 3. For the signal differential frequency doubling and clock frequency division processing method of the present invention, according to the preset design state (set resolution requirements), the signal processing circuit selects the corresponding processing, including the preset frequency doubling processing and the preset frequency division processing. At the same time, it is ensured that the frequency doubled or frequency divided signal still maintains an orthogonal state output. 4. For the Z signal processing method adopted by the present invention, the zero position signal corresponding to the output signal has an independent optical signal sensing channel, and according to the preset output signal state characteristics, the correct zero position signal information is output through digital logic selection. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram of the chip circuit structure of a multi-resolution output incremental optoelectronic encoder implementing the present invention.

[0018] Figure 2 is adapted to Figure 1 the chip circuit and is a schematic diagram of the optical signal modulation code disk structure. Figure 2 is a partial enlarged schematic diagram of the circumferential code disk.

[0019] The reference numerals are listed as follows: 1 - Compound optical sensing phase array; 2 - Zero - position signal sensing array; 3 - Trans - impedance amplifier and hysteresis comparator combination module (the hysteresis comparator is also known as the Schmitt trigger or the hysteresis comparator. The trans - impedance amplifier, TIA, trans - impedance amplifier, converts the low - level photodiode current signal into a voltage signal); 4 - Frequency - doubling and frequency - dividing processing module (for example, doubling 100Hz to 200Hz or to 400Hz, or dividing to 50Hz or to 25Hz); 5 - Logic processing and selection module; 6 - Signal output terminal; 11 - First - resolution photodiode array; 12 - Second - resolution photodiode array; 13 - Third - resolution photodiode array; 21 - First grating track zero - position signal sensor; 22 - Second grating track zero - position signal sensor; 23 - Third grating track zero - position signal sensor; 111 - First grating track (first grating area); 121 - Second grating track (second grating area); 131 - Third grating track (third grating area); 211 - First zero - position signal track; 221 - Second zero - position signal track; 231 - Third zero - position signal track; M - First resolution; N - Second resolution; P - Third resolution; Z - Zero - position signal; M - Z - First zero - position signal; N - Z - Second zero - position signal; P - Z - Third zero - position signal. Detailed implementation mode

[0020] The present invention will be described below in conjunction with the accompanying drawings ( Figure 1 - Figure 2 ).

[0021] Figure 1 is a schematic diagram of the chip circuit structure for implementing a multi - resolution output incremental optical encoder of the present invention. Figure 2 is adapted to Figure 1 the chip circuit and is a schematic diagram of the optical signal modulation code disk structure. Figure 2 is a partially enlarged schematic diagram of the circumferential code disk. Referring to Figure 1 to Figure 2 as shown, a multi - resolution output incremental optical encoder includes an optical encoder chip and an optical signal modulation code disk adapted thereto. The optical encoder chip includes a compound optical sensing phase array 1 and a zero - position signal sensing array 2. The compound optical sensing phase array 1 is connected to a frequency - doubling and frequency - dividing processing module 4 through a first trans - impedance amplifier and hysteresis comparator combination module 3 ( Figure 1 in the upper middle, with the trans - impedance amplifier on the top and the hysteresis comparator at the bottom), and the zero - position signal sensing array 2 is connected to a frequency - doubling and frequency - dividing processing module 4 through a second trans - impedance amplifier and hysteresis comparator combination module 3 ( Figure 1In the lower middle part, the transimpedance amplifier is above and the hysteresis comparator is below, which are connected to the logic processing and selection module 5 (also known as the logic control and selection processing module). The logic processing and selection module 5 is respectively connected to the frequency multiplication and division processing module 4 and the signal output terminal 6. A plurality of grating tracks are provided on the optical signal modulation code disk to adapt to the composite optical sensing phase array 1. The composite optical sensing phase array 1 includes a first resolution photodiode array 11 and a second resolution photodiode array 12. On the optical signal modulation code disk, a first grating track 111 and its first zero position signal track 211, and a second grating track 121 and its second zero position signal track 221 are provided. The zero position signal sensing array 2 includes a first grating track zero position signal sensor 21 and a second grating track zero position signal sensor 22. The composite optical sensing phase array 1 includes a third resolution photodiode array 13. On the optical signal modulation code disk, a third grating track 131 and its third zero position signal track 231 are provided. The zero position signal sensing array 2 includes a third grating track zero position signal sensor 23.

[0022] The optical signal modulation code disk is of a disk structure. The light-transmitting lines of the grating area on each grating track are evenly distributed along the circumference. The number of light-transmitting lines of the grating area is the intrinsic resolution line number of its corresponding grating track. The intrinsic resolution line number enables the corresponding resolution photodiode array to generate an intrinsic signal transmitted to the first transimpedance amplifier and hysteresis comparator combination module 3. The intrinsic signal can be frequency-multiplied or frequency-divided in the frequency multiplication and division processing module 4. The frequency multiplication and division processing module 4 can perform signal processing of 1 / 2, 1 / 4, ×2, ×4 on the intrinsic signal to form optional coding resolution specifications with multiple resolutions. On the optical signal modulation code disk, the first grating track 111, the second grating track 121, the third grating track 131, the third zero position signal track 231, the second zero position signal track 221, and the first zero position signal track 211 are distributed in sequence from outside to inside. The number of light-transmitting lines of the grating area on the first grating track 111 < the number of light-transmitting lines of the grating area on the second grating track 121 < the number of light-transmitting lines of the grating area on the third grating track 131.

[0023] A multi-resolution output incremental optical encoder chip, comprising a composite optical sensing phase array 1 and a zero signal sensing array 2. The composite optical sensing phase array 1 is connected to a frequency multiplication and division processing module 4 through a first transimpedance amplifier and a hysteresis comparator combination module 3. The zero signal sensing array 2 is connected to a logic processing and selection module 5 through a second transimpedance amplifier and a hysteresis comparator combination module 3. The logic processing and selection module 5 is respectively connected to the frequency multiplication and division processing module 4 and a signal output terminal 6. The composite optical sensing phase array 1 includes a first-resolution photodiode array 11 (with a resolution of M), a second-resolution photodiode array (with a resolution of N), and a third-resolution photodiode array (with a resolution of P). The zero signal sensing array includes a first grating track zero signal sensor 21 (M-Z, zero signal Z with a resolution of M), a second grating track zero signal sensor (N-Z, zero signal Z with a resolution of N), and a third grating track zero signal sensor (P-Z, zero signal Z with a resolution of P).

[0024] An optical signal modulation code disk, comprising a first grating track 111 and its first zero signal track 211, a second grating track 121 and its second zero signal track 221, and a third grating track 131 and its third zero signal track 231. The optical signal modulation code disk is of a disk structure, and the light-transmitting lines of the grating area on each grating track are evenly distributed along the circumference. The number of light-transmitting lines of the grating area is the number of intrinsic resolution lines of its corresponding grating track.

[0025] In view of the deficiency of the singularity existing in the existing products, the present invention provides a composite phase array structure, which has 2 to 3 independent phase array track windows. A solution is proposed that a photoelectric encoder chip of the same model, in cooperation with its paired optical code disk, can meet most of the resolution requirements. On the one hand, this solution reduces the production and detection costs that photoelectric encoder manufacturers need to invest to meet various resolution requirements. On the other hand, it reduces the design and testing difficulties of photoelectric encoder application manufacturers. It solves the cooperation difficulty that manufacturers need to invest in the case of a large number of resolution requirements. The present invention also provides a way to select the working state digitally. Through the chip selection input terminal, the number of encoded digital pulses that can be output per revolution can be selected by binary digital coding. The setting and operation are simple, and it can more flexibly meet the application requirements of different resolution products. The present invention also provides a flexible signal processing method, which integrates digital processing of frequency doubling and frequency division, and performs signal processing of 1 / 2, 1 / 4, ×2, and ×4 on the intrinsic signal. In cooperation with the corresponding differential amplifier, users can select the application conditions suitable for themselves from the numerous resolution specifications of this chip. The present invention also provides a method for discriminating zero position signals. In order to solve the independence and correlation of zero position signals. In one case, three groups of independent phase arrays correspond to three groups of independent zero position signals, and there is no interference between channels. The required precision output content is selected through the input selection port.

[0026] A design scheme of an incremental photoelectric encoder chip with multiple resolutions and programmable output. The chip design is based on a composite optical sensing phase array structure, which integrates the application requirements of up to more than a dozen common circumferential linear resolutions on a single chip. The phase optical sensing array of the chip has 2 to 3 independent phase array track windows. Through the chip selection input terminal, the number of encoded digital pulses that can be output per revolution is selected by binary digital coding signals. It achieves that a certain chip can realize the user-selectable coding resolution. It is characterized in that it includes a sensor part including 2 to 3 groups of independent phase array signal sensing units and 2 to 3 groups of independent zero position signal sensing units; the signal processing part includes a current sensing amplifier circuit and a comparator circuit, a signal differential frequency doubling and clock frequency division processing circuit, a signal output logic relationship selection circuit, and an internal test and debugging circuit. It is characterized in that the encoder chip and the code disk are used in a one-to-one manner, and the layout of the signal amplifier makes the matching of the paired channels very excellent, thus eliminating the need for signal calibration.

[0027] After the composite phase array sensing unit receives the optical signal modulated by the corresponding circular code disk, it is converted into a voltage signal by the internal cross-group amplifier unit. This voltage signal generates a digital signal through a precision voltage comparator with hysteresis. At the same time, the digital signal outputs three signals, namely, signals A, B, and Z of the optical encoder, through a differential push-pull driver. Among them, signals A and B are the output signals of the phase array sensor, and Z is the corresponding zero-position signal. Through the above-mentioned signals, after differential frequency multiplication and clock frequency division processing circuits, and then through the output logic relationship selection circuit, the corresponding resolution signal output and the corresponding zero-position signal output are selected and output through digital logic.

[0028] After the composite phase array sensing unit receives the optical signal modulated by the optical code disk, the obtained signal at this time is the intrinsic signal. The intrinsic signal is a group of orthogonal A and B signals. According to the states of signals A and B, the working state of the optical encoder can be judged. At this time, according to the preset design state (the required resolution), the signal processing circuit selects the corresponding processing, including the preset frequency multiplication processing and the preset frequency division processing. At the same time, it is ensured that the frequency multiplication or frequency division signal still maintains an orthogonal state output.

[0029] The composite phase array is composed of 2 to 3 sensing units. Each group of sensing units corresponds to a unique intrinsic signal, its corresponding processed signal (the signal processed by frequency multiplication and frequency division), and a zero-position signal corresponding to the output signal. And the characteristics of the zero-position signal satisfy the phase and pulse width logic relationship corresponding to the output signal. The zero-position signal corresponding to the output signal has an independent optical signal sensing channel. According to the preset output signal state characteristics, the correct zero-position signal information is selected and output through digital logic.

[0030] The composite phase array is composed of 2 to 3 sensing units. The zero-position signal detection part corresponding to the corresponding sensing unit is in the same detection channel. According to the different resolutions of the composite phase array, the corresponding zero-position relationship phases and pulse widths are also different. According to the preset output signal state characteristics, the corresponding zero-position signal is identified through signal characteristics.

[0031] The features of the present invention include: 1. The encoder chip is designed based on a composite optical sensing phase array structure, which integrates the application requirements of up to more than a dozen common circumferential linear resolutions on a single chip. The phase optical sensing array of the chip has 2 to 3 independent phase array track windows. Through the chip selection input terminal, a binary digital coding signal is used to select the number of coded digital pulses that can be output per revolution. This achieves that a single chip can realize user-selectable coding resolutions. Two groups of input selection ports are configured to select different grating regions and interpolation ratios. Three different grating regions can be selected; each grating region can further select 5 different resolution ratios, which can be combined into 15 resolution line number schemes. 2. The encoder chip integrates digital processing of frequency doubling and frequency division, performs signal processing of 1 / 2, 1 / 4, ×2, and ×4 on the intrinsic signal, and cooperates with the corresponding differential amplifier. Users can select the appropriate application conditions from the numerous resolution specifications of the chip. 3. The encoder chip and the code disk are used in a one-to-one manner, and the layout of the signal amplifier makes the pairing channels match very well, thus eliminating the need for signal calibration. 4. The independence and correlation of the zero position signal of the photoelectric encoder. The three groups of independent phase arrays correspond to three groups of independent zero position signals, and there is no interference between channels. The input selection port is used to select the relevant output content of the zero position signal required, including phase information and signal width information. 5. The zero position signal can not only be on three code tracks respectively, but also on the same code track. The characteristics of the three groups of zero position signals correspond to the corresponding main code tracks respectively. The sensing element areas and phase relationships of the three groups of zero position signals are different. Through signal feature selection, the zero position signals of the corresponding code tracks can be identified, and the feature lies in the accurate signal feature selection.

[0032] The content not described in detail in the specification of the present invention belongs to the prior art well-known to those skilled in the art. It is hereby pointed out that the above description helps those skilled in the art to understand the present invention, but does not limit the protection scope of the present invention. Any implementation that makes equivalent replacements, modifications and improvements, and / or simplifies the above description without departing from the substantial content of the present invention falls within the protection scope of the present invention.

Claims

1. A multi-resolution output incremental optical encoder, characterized in that, It includes an optoelectronic encoder chip and an optically modulated code disk adapted thereto. The optoelectronic encoder chip includes a composite optical sensing phase array and a zero position signal sensing array. The composite optical sensing phase array is connected to a frequency multiplication and division processing module through a first transimpedance amplifier and a hysteresis comparator combination module. The zero position signal sensing array is connected to a logic processing and selection module through a second transimpedance amplifier and a hysteresis comparator combination module. The logic processing and selection module is respectively connected to the frequency multiplication and division processing module and a signal output end. A plurality of grating tracks are arranged on the optically modulated code disk to adapt to the composite optical sensing phase array; The composite optical sensing phase array includes a first resolution photodiode array and a second resolution photodiode array. A first grating track and its first zero position signal track, and a second grating track and its second zero position signal track are arranged on the optically modulated code disk. The zero position signal sensing array includes a first grating track zero position signal sensor and a second grating track zero position signal sensor.

2. The multi-resolution output incremental optical encoder according to claim 1, wherein The composite optical sensing phase array includes a third resolution photodiode array. A third grating track and its third zero position signal track are arranged on the optically modulated code disk. The zero position signal sensing array includes a third grating track zero position signal sensor.

3. The multi-resolution output incremental optical encoder according to claim 1, characterized in that The optically modulated code disk is of a disk structure. The light-transmitting lines in the grating area on each grating track are evenly distributed along the circumference. The number of light-transmitting lines in the grating area is the intrinsic resolution line number of its corresponding grating track. The intrinsic resolution line number enables the corresponding resolution photodiode array to generate an intrinsic signal transmitted to the first transimpedance amplifier and the hysteresis comparator combination module. The intrinsic signal can be frequency-multiplied or frequency-divided in the frequency multiplication and division processing module.

4. The multi-resolution output incremental optical encoder according to claim 3, wherein The frequency multiplication and division processing module can perform signal processing of 1 / 2, 1 / 4, ×2, ×4 on the intrinsic signal to form multi-resolution optional coding resolution specifications.

5. The multi-resolution output incremental optical encoder according to claim 1, wherein The first grating track, the second grating track, the third grating track, the third zero position signal track, the second zero position signal track, and the first zero position signal track are sequentially distributed on the optically modulated code disk from outside to inside.

6. The multi-resolution output incremental optical encoder according to claim 5, wherein The number of light-transmitting lines in the grating area on the first grating track < the number of light-transmitting lines in the grating area on the second grating track < the number of light-transmitting lines in the grating area on the third grating track.

7. A multi-resolution output incremental optical encoder chip, characterized in that, It includes a composite optical sensing phase array and a zero position signal sensing array. The composite optical sensing phase array is connected to a frequency multiplication and division processing module through a first transimpedance amplifier and a hysteresis comparator combination module. The zero position signal sensing array is connected to a logic processing and selection module through a second transimpedance amplifier and a hysteresis comparator combination module. The logic processing and selection module is respectively connected to the frequency multiplication and division processing module and a signal output end; The composite optical sensing phase array includes a first resolution photodiode array, a second resolution photodiode array, and a third resolution photodiode array. The zero position signal sensing array includes a first grating track zero position signal sensor, a second grating track zero position signal sensor, and a third grating track zero position signal sensor.

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