Gates protected from side-channel attacks with low latency and reduced complexity

Abstract

The present disclosure relates to a gate protected from side-channel attacks with low latency and reduced complexity. A masked logic gate protected from side-channel attacks using a Boolean mask with d+1 shares for each input variable, where d is an integer at least equal to 1 representing a protection level, the gate comprising a first input, a second input, and an output with (d+1) shares, wherein the first input is configured to receive a plurality of shares yj (j=0, 1, 2...); the second input is configured to receive (d+1) shares. 2 shares xi (i=0,1,2…), the (d+1) 2 The shares xi represent intermediate results output by a level of a gate tree implementing low-latency masking with protection order d; and the output of (d+1) shares is obtained by applying the logic function of the masking gate to the first input and the second input using domain-oriented masking.

Description

Technical Field

[0001] The present invention relates to secure digital circuits protected from side channel attacks (SCA) using Boolean masking. Background Art

[0002] Using Boolean masking, each binary variable input to a logic function of a digital circuit is divided into d+1 shares, where d is an integer designated as the "protection level" and at least equal to 1. The shares of the variable are randomly initialized so that exclusive-oring (XORing) them together yields the original state of the variable.

[0003] Within a logic function, shares can be processed according to various techniques that try to prevent the state of variables from "leaking" from intermediate results. One such technique is called domain-oriented masking (DOM), which has relatively low complexity at the expense of increased latency. See, for example, [“Domain-Oriented Masking: Compact Masked Hardware Implementations with Arbitrary Protection Order”, Hannes Gross et al., October 2016, 2016 ACM Symposium].

[0004] It should be noted that the complexity and delay issues within logic functions are primarily caused by the use of nonlinear gates such as AND, NAND, OR, or NOR gates. In contrast, linear gates such as XOR are well suited for leakage-free designs.

[0005] Figure 1 The diagram shows a first-order masked AND gate implementing the DOM technique. This masked AND gate is designated by AND22_M2, where the first bit indicates the number of shares per input (here, two shares for each of the two inputs), and the second bit is the number of shares fused to the output (here, two shares). This masked AND gate includes four primitive AND gates. The first primitive AND gate receives the first shares x0 and y0 of the two input variables x and y, while the last primitive AND gate receives the second shares x1 and y1 of the same input variables. The two intermediate primitive AND gates receive the pairs (x0, y1) and (x1, y0), respectively.

[0006] Finally, the outputs of the two first primitive AND gates are XORed to generate a first share z0 of the output variable z, and the outputs of the two remaining primitive AND gates are XORed to generate a second share z1 of the output variable z.

[0007] The fact that each output share carries two shares of one of the input variables (e.g., y0 and y1 for z0) results in leakage of the state of that input variable. To avoid this problem, some intermediate results are "re-masked" with additional randomness. For example, the same random bit r0 is XORed into the outputs of two intermediate primitive AND gates. Each output share thus carries the same random bit r0 that masks the state of the input variable. Finally, when the outputs are XORed to restore their state, the random bit r0 present in both shares is eliminated.

[0008] The random bit r0 is typically provided by a random number generator that produces a new random word (e.g., a 32-bit word) at each cycle of the clock CK. Therefore, before the four branches of the masked AND gate are XORed to produce the output shares z0 and z1, they are synchronized to the clock CK by a hierarchy of flip-flops. Consequently, this masked AND gate introduces a delay of one clock cycle.

[0009] Figure 2 An example of a first order masked AND gate implementing the LOLA technique is shown. This masked AND gate is designated by AND22_M4, where the first bit indicates the number of shares per input (here two shares for each of the two inputs), and the second bit is the number of shares fused to the output (here four shares). This masked gate simply consists of Figure 1 The outputs of the primitive AND gates represent the four shares z0 to z3 of the output variable.

[0010] The state of the output variable can be obtained by XORing the four shares z0 to z3 together. No randomness is required, so no latency is introduced. However, subsequent logic levels are designed to handle four-share variables, which increases complexity quadratically with the number of levels in the logic function.

[0011] One consequence of the AND function being nonlinear is that the masked AND gate contains "domain crossing", i.e. the output shares z0 belonging to domain 0 contain the shares from domain 1, and in a reciprocal manner. In a first-order masked XOR gate, there is no domain crossing and the output shares z0 and z1 are simply and Summary of the Invention

[0012] The present disclosure generally relates to a masked logic gate protected from side-channel attacks using a Boolean mask with d+1 shares for each input variable, where d is an integer at least equal to 1 representing a protection order, the gate comprising a first input configured to receive a plurality of shares yj (j=0, 1, 2, ...), a second input configured to receive (d+1) shares, and an output having (d+1) shares. 2 Shares xi (i=0,1,2…), (d+1) 2 The shares represent intermediate results output by a level of a gate tree implementing low-latency masking with protection order d; and the output of the (d+1) shares is obtained by applying a logical function of a masking gate to the first input and the second input using domain-oriented masking.

[0013] The first input can also be configured to receive (d+1) 2 shares, the (d+1) 2 The shares represent the intermediate results output by a level of a tree of gates implementing a low-latency mask with protection order d.

[0014] The first input may additionally be configured to receive d+1 shares of the input variable.

[0015] The masking gate may have a structure represented by a matrix having (d+1) 2 rows and columns, (d+1) 2 The rows are respectively assigned to the shares xi of the second input, and the columns are respectively assigned to the shares yj of the first input, the masking gate structure includes: a primitive gate of the same type for each cell (i, j) of the matrix, the primitive gates of the same type being connected to operate on the shares xi and yj; a random bit selected from a group of independent random bits and an XOR gate for each cell (i, j) in a subset of cells of the matrix, the XOR gate being connected to inject the random bit into the output of the corresponding primitive gate, wherein the random bits are selected so that any random bit appears an even number of times in the matrix; and a corresponding XOR gate tree for each d+1 row slice in the matrix, the corresponding XOR gate tree generating the corresponding output shares of the masking gate from all cells of the slice.

[0016] The XOR gates of the tree may be connected such that any XOR gate of the tree contains at least one random bit an odd number of times.

[0017] When d=2 and the first input is configured to receive 9 shares, the masking gate has three output shares, each corresponding to three slices of the matrix, and the matrix has 9 rows and 9 columns. Using an independent random bit group including 12 random bits r0, r2...r11, the random bits can be distributed as follows: the same random bit from the range r0 to r8 appears three times in each of two of the three slices and does not appear in the remaining slices; and the same random bit from the range r9 to r11 appears twice in each slice, but does not appear an even number of times in the same column of the matrix and does not appear in the same 3×3 square.

[0018] Each row of the matrix can have the same number of random bits, while the random bits in each column are different.

[0019] When d=2 and the first input is configured to receive 3 shares, the masking gate has three output shares, each corresponding to three slices of a matrix having 9 rows and 3 columns. Using an independent random bit group including 6 random bits r0, r2…r5, the random bits can be distributed as follows: the same random bit in the range r0 to r2 appears twice in each of two of the three slices and does not appear in the remaining slices; and the same random bit in the range r3 to r5 appears once in each of two of the three slices and does not appear in the remaining slices; the random bit pairs used from the range r0 to r2 are different in each slice; and the random bit pairs used from the range r3 to r5 are different in each slice. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Other advantages and features will become more apparent from the following description of certain embodiments of the invention, which are provided for illustrative purposes only and are presented in the accompanying drawings, in which:

[0021] Figure 1 , as previously described, is an example of a first-order masked AND gate that implements the DOM technique;

[0022] Figure 2 , as previously described, is an example of a first-order masked AND gate that implements the LOLA technique;

[0023] Figure 3 is a block diagram of an exemplary complex logic function with first-order masking implemented using DOM technology;

[0024] Figure 4 The diagram shows the use of LOLA technology to achieve Figure 3 Block diagram of the same logic function;

[0025] Figure 5A The diagram is realized by mixing LOLA and DOM technology. Figure 3 Block diagram of the same logic function supported by masked gates implementing 4:2 share compression using DOM technology;

[0026] Figure 5B is a block diagram illustrating an alternative logic function of a masking gate using an alternative share compression;

[0027] Figure 6 The diagram shows a hybrid of LOLA and DOM techniques with second-order masking. Figure 3 A block diagram of a logic function supported by a masked gate for implementing 9:3 share compression using DOM technology;

[0028] Figure 7A and 7B are circuit diagrams of two alternative examples of masking gates for asymmetric 4:2 share compression;

[0029] Figure 8 is a circuit diagram of an exemplary symmetrical 4:2 share compression masking gate;

[0030] Figure 9 yes Figure 8 An alternative representation of a symmetrical masked compression gate in rectangular form;

[0031] Figure 10A 、 10B 10C is a diagram in matrix form of an alternative example of a masking gate for symmetric 9:3 fraction compression; and

[0032] Figure 11 FIG. 4 is a diagram in matrix form of a masking gate for an exemplary asymmetric 9:3 fraction compression. DETAILED DESCRIPTION

[0033] Figure 3 FIG1 is a block diagram of an exemplary complex logic function with first-order masking implemented using DOM (Domain Oriented Masking) technology. The function shown is an 8-input AND function. The 8-input AND function is traditionally implemented using 8 primitive AND gates organized in a three-level tree. With first-order masking and using DOM technology, each primitive AND gate is replaced by Figure 1 The type of masked AND gate is designated as AND22_M2.

[0034] As mentioned before, using DOM technology, each level of masked AND gates introduces a delay of one clock cycle. Therefore, the entire logic function introduces a delay of three clock cycles Cyc 0, Cyc 1, and Cyc 2.

[0035] Figure 4 Also corresponds to an 8-input AND function with first-order masking, but implemented using LOLA technology (Low Latency Masking). Each primitive AND gate in the first level is Figure 2 Each of these first-level gates produces an output with 4 shares. The second-level gates, designated AND44_M16, each process two inputs with 4 shares and produce an output with 16 shares. Finally, the remaining gates in the final level, designated AND1616_M256, process two inputs with 16 shares and produce an output with 256 shares. To obtain the actual output state of the function, these 256 bits are XORed together.

[0036] The masking logic function thus implemented has no latency other than the delay of the critical path, however this comes at the expense of a gate count that grows quadratically with the number of primitive gate levels required to implement the function.

[0037] In the present disclosure, we seek to mix DOM and LOLA technologies to implement complex logic functions while reducing the latency required for pure DOM implementation and reducing the complexity required for pure LOLA implementation.

[0038] To this end, multiple levels in a gate tree designed to implement complex logic functions alternately use LOLA and DOM techniques, with specific DOM gates configured to operate on power-of-two compression. For example, for first-order protection, specific gates operate on 4:2 compression, while for second-order protection, they operate on 9:3 compression.

[0039] Two types of compression gates are provided for each protection step d, such as those denoted as FN(d+1) 2 (d+1) 2 _M(d+1) symmetric gate, which has two (d+1) 2 The input of the fraction and the output of (d+1) fraction are denoted as FN(d+1) 2 (d+1)_M(d+1) asymmetric gate, which has a (d+1) 2 The "FN" designates the primitive logic function being implemented, which will be illustrated later as the AND function, the most commonly used nonlinear function. These two types of compression gates are the building blocks that allow the implementation of any complex logic function.

[0040] Figure 5A The diagram illustrates the application of this technique to a symmetrical 4:2 compression gate denoted AND44_M2. Figure 3 The first level consists of 4 Figure 2 Each LOLA gate AND22_M4 of the type 4 produces an output with a share of 4. Therefore, the compression gate AND44_M2 in the second level (C-DOM) each processes two inputs with a share of 4 and produces an output with a share of 2. The remaining LOLA gates in the final level, denoted as AND22_M4, process inputs with a share of 2 and produce outputs with a share of 4.

[0041] and Figure 3 Compared to the pure DOM implementation in , the resulting logic function has a latency of only one cycle instead of three. Figure 4 Compared to the pure LOLA implementation in

[15] , the number of gates increases linearly with the number of levels, rather than quadratically, because the maximum number of shares can be limited to 4 for LOLA gates.

[0042] Assuming that the logic function requires another level, the gates in the final level will be 4:2 compression gates, which introduce an extra cycle of delay but produce an output with only 2 shares.

[0043] The symmetric AND44_M2 compression gate is therefore suitable for processing intermediate results with shares of 4. In more general cases, for example because the number of inputs is not a power of 2, or because some inputs are processed by linear gates (which do not expand the number of shares), some intermediate results will have 4 shares and others will have 2 shares.

[0044] Figure 5B The diagram illustrates the use of an asymmetric compression gate, designated AND42_M2, for processing intermediate results with varying numbers of shares. The function to be implemented is a 6-input AND function, with each input having two shares. Four inputs are processed by a first level of LOLA AND22_M4 gates, each producing a 4-share output. The asymmetric compression gate AND42_M2 processes each of the 4-share outputs of the AND22_M4 gate and one of the remaining 2-share inputs.

[0045] Figure 6 The diagram illustrates the application of a 9:3 compression gate, designated AND99_M3, to an 8-input AND function using second-order protection. The first level includes four LOLA gates, AND33_M9, each producing an output with 9 shares. Thus, the compression gates AND99_M3 in the second level each process two inputs with 9 shares and produce an output with 3 shares. The remaining LOLA gates, designated AND33_M9, in the final level process these 3-share inputs and produce an output with 9 shares.

[0046] Figure 7AThe circuit diagram of an exemplary asymmetric 4:2 compression AND gate AND42_M2 is shown. This compression gate receives four shares x0 through x3 of the variable x and two shares y0 and y1 of the variable y. In the first level, eight primitive AND gates receive share pairs (x0, y0), (x0, y1), (x1, y0), (x1, y1), (x2, y0), (x2, y1), (x3, y0), and (x3, y1), respectively. The outputs of the first four primitive AND gates are XORed at 10 to produce a first share z0 of the output variable z. The outputs of the remaining four primitive AND gates are XORed at 12 to produce a second share z1 of the output variable z.

[0047] To avoid leaking the state of the input variables, the intermediate result is remasked using two independent random values, r0 and r1, such as two bits taken from a word produced by a random number generator. The value r0 is injected into the outputs of the first and fifth primitive AND gates by corresponding XOR gates, while the value r1 is injected into the outputs of the third and seventh primitive AND gates. Before the values ​​transmitted in the branches are XORed at 10 and 12, a hierarchy of eight flip-flops 14 is provided to synchronize the eight branches with the clock of the random number generator.

[0048] Each of the blocks 10 and 12 can be a tree of primitive XOR gates. In principle, the XOR gates of each tree can be organized in any way, i.e., the XOR gates of the first level of the tree can receive the outputs of any two flip-flops 14. However, to further improve leakage protection, the XOR gates are preferably organized so that each gate contains at least one of the random values ​​r0, r1.

[0049] Figure 7B This is an alternative form of the circuit of FIG7 , providing increased protection against leakage. Two additional independent random values ​​r2 and r3 are used, for example, two additional bits taken from a word produced by a random number generator. The value r2 is injected by corresponding XOR gates into the outputs of the second and sixth primitive AND gates, while the value r3 is injected into the outputs of the fourth and eighth primitive AND gates.

[0050] Figure 8is a circuit diagram of an exemplary symmetric 4:2 share compression AND gate AND44_M2. This compression gate receives four shares x0 through x3 of variable x and four shares y0 through y3 of variable y. The first level of 16 primitive AND gates, shown as two sets of eight primitive AND gates, receives corresponding share pairs (x0, y0), (x0, y1), (x0, y2), (x0, y3), (x1, y0), (x1, y1), (x1, y2), (x1, y3) and (x2, y0), (x2, y1), (x2, y2), (x2, y3), (x3, y0), (x3, y1), (x3, y2), (x3, y3). The outputs of the first set of primitive AND gates are XORed at 20 to produce a first share z0 of output variable z. The outputs of the second set of primitive AND gates are XORed at 22 to produce a first share z1 of output variable z.

[0051] To avoid leaking the states of the input variables, the intermediate results are re-masked using four independent random values ​​r0 to r3 generated by a random number generator. The value r0 is XORed into the output of the first primitive AND gate in each set. The value r1 is XORed into the output of the third primitive AND gate in each set. The value r2 is XORed into the output of the fifth primitive AND gate in each set. Finally, the value r3 is XORed into the output of the seventh primitive AND gate in each set.

[0052] The random values ​​are shown as being applied to each odd-numbered gate of each set. In an alternative form, they can be applied to each even-numbered gate of each set. In another alternative form, each random value is applied to an odd-numbered gate of each set, for example 3 gates, which means that multiple random values ​​can be applied to some gates.

[0053] Before the values ​​transferred in the branches are XORed at 20 and 22 , a level of 16 flip-flops 24 is provided to synchronize the 16 branches with the clock of the random number generator.

[0054] Each of blocks 20 and 22 can be a tree of primitive XOR gates. The XOR gates are preferably organized so that each contains at least one of the random values ​​r0 through r3. As a general rule applicable to any embodiment, the XOR gates of the tree are connected so that any XOR gate of the tree contains at least one random value an odd number of times. In fact, in more complex embodiments presented later, some random values ​​can be included twice or even times in branches upstream of the XOR gates, so that these random values ​​will be eliminated.

[0055] Figure 9 yes Figure 8An alternative matrix representation of a symmetric masked compression gate. The 4×4 matrix shown at the top illustrates the first level of primitive AND gates and their inputs. Each row of the matrix is ​​assigned to a corresponding share x0 through x3 of the input variable x. Each column of the matrix is ​​assigned to a corresponding share y0 through y3 of the input variable y. Matrix cell (i, j) thus corresponds to a primitive AND gate receiving shares xi and yj.

[0056] The two 4×4 matrices shown in the middle illustrate two alternative examples for re-masking intermediate results using random values. Here, the matrix cell (i, j) corresponds to the value appearing in that cell, denoted as r[i, j], being XORed with the corresponding cell of the top matrix, producing Where r[i,j] is a null value or one of the random values ​​r0, r1... When r[i,j] is a null value, no XOR operation is performed, that is, the unit represents a direct connection. The left matrix corresponds to Figure 8 The matrix on the right corresponds to an alternative form using 8 independent random values ​​r0 to r7, which provides improved leakage protection under some conditions.

[0057] The bottom 4x4 matrix illustrates the synchronization and XOR operations used to generate the output shares z0, z1. Each output share is generated by XORing the resulting bits of the corresponding 2-row slice of the matrix.

[0058] The final compression gate structure is thus obtained by superimposing the top matrix, one of the middle matrices, and the bottom matrix. In fact, the most variable characteristic of this compression gate is the distribution of random values, namely the middle matrix. Therefore, as will be shown later in this article, the complete circuit structure can be represented by only the middle matrix.

[0059] It can be noted that Figure 7A 、 7B The asymmetric compression gate structure can be made of Figure 9 It is represented by the first two or last two columns of the matrix.

[0060] Figure 10A 、 10B, 10C is a diagram in simplified matrix form of an alternative example of a symmetric 9:3 share compression masking gate. Each input x, y has 9 shares x0 to x8, y0 to y8. Shares x0 to x8 are applied to the rows of the 9×9 matrix, while shares y0 to y8 are applied to the columns of the 9×9 matrix. Each matrix cell (i, j) is therefore designed to perform the operation (xi & yj) ⊕ r[i, j], where, as above, r[i, j] is a null value or a random value taken from the bits of the word generated by the random number generator. Each of the three output shares z0 to z2 of the output variable z is generated by XORing the resulting bits of the slices of the corresponding three rows of the matrix. For example, the first slice including the top three rows produces share z0; the second slice including the middle three rows produces share z1; and the third slice including the bottom three rows produces share z2.

[0061] As mentioned above, to improve leakage protection, each output share may be generated from the corresponding slice by a corresponding tree of XOR gates connected such that any XOR gate in the tree contains at least one random value an odd number of times.

[0062] Figure 10A A first example of the distribution of random values ​​in the intermediate results is shown, which provides effective protection against input variable state leakage. The random values ​​are selected from twelve independent random bits r0 to r11. The following set of constraints can be used to find a suitable distribution of random values ​​in the matrix:

[0063] 1) Each random bit appears an even number of times in the matrix;

[0064] 2) the same random bit from the range r0 to r8 appears three times in each of two of the three slices and does not appear in the remaining slices; and

[0065] 3) The same random bit from the range r9 to r11d appears twice in each slice, but not an even number of times in the same column in the matrix, nor in the same 3x3 square.

[0066] Constraint (1) is generally applicable to all structures.

[0067] exist Figure 10A , another set of constraints is used, where:

[0068] 4) Each row of the matrix has the same number of random values; and

[0069] 5) The random values ​​in each row are different.

[0070] As an exemplary result of these constraints, as shown in the figure, each slice k (k=0, 1, 2) has:

[0071] the value r(3k) repeated in the cells of column 0, the value r(3k+1) repeated in the cells of column 3, and the value r(3k+2) repeated in the cells of column 6;

[0072] a different permutation of the values ​​r(3k+3), r(3k+4), r(3k+5) in each of columns 1, 4, and 7, where r(3k+3), r(3k+4), r(3k+5) are expressed modulo 9; and

[0073] The values ​​r10, r9 in the first two cells of column 2, the values ​​r11, r9 in the first and last cells of column 5, and the values ​​r10, r11 in the last two cells of column 8.

[0074] The constraints listed allow for a variety of other distributions of random values ​​that provide the desired degree of protection. For example, slices can be shuffled, and the rows within any slice can be shuffled. When the matrix is ​​divided into three groups of three consecutive columns, similar shuffling can be applied column by column.

[0075] However, it should be noted that the constraints listed, in particular the second set (4) and (5), are sufficient but not necessary, i.e., distributions that do not satisfy these constraints may also provide the desired degree of protection. Therefore, the disclosed constraints can be used by those skilled in the art as a guide to easily find a suitable distribution of random values, but other suitable distributions can be found using trial and error.

[0076] For example, Figure 10B An alternative distribution of random values ​​that does not satisfy the second set of constraints, but nonetheless provides the same degree of protection, is shown. Figure 10A In contrast, in column 5 of the slice, values ​​r9 and r11 have been placed in the first and third cells, respectively.

[0077] Figure 10C Shown Figure 10B The distribution of random values ​​with three additional random values ​​r12 to r14 provides improved leakage protection under some conditions. Figure 10B The empty values ​​of are distributed across the cells so that each value is used an even number of times in the matrix (here twice) and each value is used an odd number of times in each slice (here once).

[0078] Figure 11 is a diagram of an exemplary asymmetric 9:3 fractional compression masking gate in matrix form. In fact, unlike the asymmetric 4:2 compression gate structure derived from the symmetric 4:2 compression gate structure, the asymmetric 9:3 compression gate structure cannot be simply derived from the symmetric 9:3 compression gate structure.

[0079] Figure 11 The structure uses six independent random bits, r0 to r5. Each random bit in the range r0 to r2 appears twice in two of the three slices and does not appear in the remaining slices. Each bit in the range r3 to r5 appears once in two of the three slices and does not appear in the remaining slices. The bit pairs from the range r0 to r2 are different in each slice, and the bit pairs from the range r3 to r5 are also different in each slice.

[0080] One bit from the range r0 to r2 is placed in the first and last cells of the first row of the slice, while the other bits from the range r0 to r2 are placed in the middle cell of the middle row of the slice and the first cell of the last row of the slice.

[0081] Finally, one bit from the range r3 to r5 is placed in the middle cell of the first row of the slice, and the other bits from the range r3 to r5 are placed in the last cell of the last row of the slice.

[0082] Like the 9:3 symmetric compression structure, the slices can be shuffled, and the rows and columns within the slices can also be shuffled.

[0083] Many variations of the embodiments described above will be apparent to those skilled in the art. Although the compressed masking gates have been described as AND gates in essence, they can implement any other nonlinear function, such as NAND, OR, or NOR, by replacing the primitive AND gate with a primitive gate that performs the desired logic function.

Claims

1. A masked logic gate protected from side-channel attacks using a Boolean mask with d+1 shares for each input variable, where d is an integer at least equal to 1 representing a protection order, the gate comprising: The first input is configured to receive (d+1) or (d+1) of the input variable 2 Shares yj (j = 0, 1, 2…); The second input is configured to receive (d+1) 2 shares xi (i=0,1,2…), the (d+1) 2 The shares represent intermediate results output by a level of the gate tree implementing low-latency masking with protection order d; and (d+1) share outputs are obtained by applying a logic function of the masking logic gate to shares of the first input and the second input using domain-oriented masking.

2. The masked logic gate of claim 1 , wherein the (d+1) received by the first input 2 The shares represent the intermediate results output by a level of the gate tree implementing low-latency masking with protection order d.

3. The masked logic gate according to claim 1, having a structure that can be represented by a matrix, wherein the matrix has (d+1) 2 rows and (d+1) or (d+1) 2 columns, the (d+1) 2 rows are respectively allocated to the share xi of the second input, and the (d+1) or (d+1) 2 columns are respectively allocated to the share yj of the first input, and the masking logic gate structure includes: a primitive gate of the same type for each cell (i, j) of the matrix, the primitive gates being connected to operate on the share xi and the share yj; a random bit selected from a group of independent random bits (r0, r1, r2, ...) for each cell (i, j) in a subset of cells of the matrix, and an XOR gate connected to inject the random bit into an output of a corresponding primitive gate, wherein the random bits are selected such that any random bit appears an even number of times in the matrix; and For each d+1 row slice of the matrix, a corresponding XOR gate tree generates corresponding output shares (z0, z1, z2) of the masking logic gates from all cells of the slice.

4. The masking logic gate of claim 3, wherein the XOR gates of the tree are connected so that any XOR gate of the tree contains at least one random bit an odd number of times.

5. The masked logic gate of claim 3 , wherein d=2, and the first input is configured to receive 9 shares, whereby the masked logic gate has three output shares (z0, z1, z2), the three output shares corresponding to three slices of the matrix, respectively, and the matrix has 9 rows and 9 columns, and wherein: The group of independent random bits includes 12 random bits r0, r2...r11; the same random bit from the range r0 to r8 appears three times in each of two of the three slices and does not appear in the remaining slices; and The same random bit from the range r9 to r11 occurs twice in each of the three slices, but not an even number of times in the same column of the matrix, nor in the same 3x3 square.

6. The masked logic gate of claim 5 , wherein: Each row of the matrix has the same number of random bits; and The random bits in each row are different.

7. The masked logic gate of claim 3 , wherein d=2, and the first input is configured to receive 3 shares, whereby the masked logic gate has three output shares (z0, z1, z2), the three output shares corresponding to three slices of the matrix, respectively, and the matrix has 9 rows and 3 columns, and wherein: The group of independent random bits includes 6 random bits r0, r2...r5; each random bit in the range r0 to r2 appears twice in each of two of the three slices and does not appear in the remaining slices; each random bit in the range r3 to r5 occurs once in each of two of the three slices and does not occur in the remaining slices; The used pairs of random bits from the range r0 to r2 are different in each slice; and The used random bit pairs from the range r3 to r5 are different in each slice.

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