Verification Circuit for Line Driver Fault Detection

Abstract

The present invention is entitled "Verification Circuit for Row Driver Fault Detection". The present invention discloses an image sensor that may include an imaging pixel array and a verification circuit. A row control circuit including a row driver may provide control signals to pixels in the imaging pixel array. The verification circuit may test the correct operation of the row driver. The verification circuit may be configured to: pre-charge the first storage capacitor and the second storage capacitor to a first bias voltage; intentionally discharge the first storage capacitor and the second storage capacitor to a second bias voltage; reset only the first storage capacitor back to the first bias voltage; and use a first sample from the first storage capacitor and a second sample from the second storage capacitor to test the operation of the row driver. If the row driver operates correctly, a voltage swing will be detected between the two samples. If the row driver is stuck high or stuck low, the first sample and the second sample may be the same.

Description

[0001] This application claims the benefit and priority of Indian Patent Application No. 201911038711, filed on September 25, 2019, which is hereby incorporated by reference in its entirety. Field of the Invention

[0002] The present invention generally relates to imaging systems, and more particularly, to imaging systems having an image sensor and methods and circuits for testing the integrity of components in the image sensor. Background of the Invention

[0003] Image sensors are often used in electronic devices such as mobile phones, cameras, and computers to capture images. Conventional image sensors are fabricated on a semiconductor substrate using complementary metal oxide semiconductor (CMOS) technology or charge-coupled device (CCD) technology. An image sensor may include an image sensor pixel array, each pixel including a photodiode and other operating circuits, such as transistors formed in the substrate.

[0004] Image sensors may be prone to failure throughout the life of an electronic device. Conventional image sensors are sometimes provided with methods and circuits for testing the functionality of the image sensor. However, verifying the correct operation of an imaging system may require additional components that take up a significant amount of space on the image sensor, increase manufacturing complexity, etc.

[0005] Accordingly, there is a desire to provide a verification circuit for an improved imaging system. Brief Description of the Drawings

[0006] Figure 1 is a schematic diagram of an exemplary system including an imaging system and a host subsystem according to one embodiment.

[0007] Figure 2 is a schematic diagram of an exemplary image sensor according to one embodiment, the exemplary image sensor having an image pixel array, a verification circuit coupled to the image pixel array, and a control circuit coupled to the image pixel array.

[0008] Figure 3 is a circuit diagram of an exemplary pixel that may be included in an image sensor (such as Figure 2 the image sensor) according to some embodiments.

[0009] Figure 4 is a schematic diagram of an exemplary verification circuit that may be included in an image sensor (such as Figure 2 the image sensor) according to one embodiment.

[0010] Figure 5It is a circuit diagram of an exemplary verification circuit block for testing the correct operation of a row driver according to an embodiment.

[0011] Figure 6 It shows according to an embodiment Figure 5 The timing diagram of the operation of the verification circuit during the pre-charge phase and the discharge phase.

[0012] Figure 7 It shows according to an embodiment that when the row driver signal under test operates normally, Figure 5 The timing diagram of the operation of the verification circuit during the read phase.

[0013] Figure 8 It shows according to an embodiment that when the row driver signal under test is fixed at a high level, Figure 5 The timing diagram of the operation of the verification circuit during the read phase.

[0014] Figure 9 It shows according to an embodiment that when the row driver signal under test is fixed at a low level, Figure 5 The timing diagram of the operation of the verification circuit during the read phase. Detailed Description

[0015] Embodiments of the present invention relate to image sensors, and more particularly, to image sensors having a verification circuit. Those skilled in the art should recognize that exemplary embodiments of the present invention can be implemented in the absence of some or all of these specific details. In other instances, well-known operations have not been described in detail to avoid unnecessarily obscuring the embodiments of the present invention.

[0016] Imaging systems having a digital camera module are widely used in electronic devices such as digital cameras, computers, mobile phones, and other electronic devices. The digital camera module may include one or more image sensors that collect incident light to capture images.

[0017] In some cases, the imaging system may form part of a larger system that includes monitoring or security systems such as those in vehicles (e.g., cars, buses, or any other vehicle). In a vehicle safety system, the images captured by the imaging system can be used by the vehicle safety system to determine the environmental conditions around the vehicle. For example, the vehicle safety system may include systems such as a parking assistance system, an automatic or semi-automatic cruise control system, an automatic braking system, a collision avoidance system, a lane keeping system (sometimes referred to as a lane drift prevention system), a pedestrian detection system, etc.

[0018] In at least some cases, an imaging system can form part of a semi-autonomous or autonomous driverless vehicle. Such an imaging system can capture images and use these images to detect nearby vehicles. If a nearby vehicle is detected in the image, the vehicle safety system can sometimes turn on warning lights, issue a warning, or can activate braking, active steering, or other active collision avoidance measures. The vehicle safety system can use images continuously captured by an imaging system having a digital camera module to help avoid collisions with objects (e.g., other cars or other environmental objects), help avoid unwanted departures (e.g., crossing lane markings), or assist the vehicle in operating safely during any of its normal operating modes.

[0019] The image sensor can include an array of image pixels. The pixels in the image sensor can include photosensitive elements, such as photodiodes that convert incident light into charge. The image sensor can have any number (e.g., hundreds or thousands or more) of pixels. A typical image sensor can (e.g.) have hundreds, thousands, or millions of pixels (e.g., megapixels).

[0020] Figure 1 FIG. is a diagram of an exemplary imaging system that uses an image sensor to capture images. Figure 1 System 100 can be a vehicle safety system (e.g., an active braking system or other vehicle safety system), can be a monitoring system, or can be an electronic device (such as a camera, mobile phone, video camera, or other electronic device that captures digital image data).

[0021] As Figure 1 shown, system 100 can include an imaging system (such as imaging system 10) and a host subsystem (such as host subsystem 20). Imaging system 10 can include camera module 12. Camera module 12 can include one or more image sensors 14 and one or more lenses. The lenses in camera module 12 can (e.g.) include M*N individual lenses arranged in an M×N array. The individual image sensors 14 can (e.g.) be arranged in a corresponding M×N image sensor array. The values of M and N can each be greater than or equal to 1, can each be greater than or equal to 2, can exceed 10, or can be any other suitable value. Each image sensor in camera module 12 can be the same, or there can be different types of image sensors in a given image sensor array integrated circuit.

[0022] During an image capture operation, each lens may focus light onto an associated image sensor 14. The image sensor 14 may include photosensitive elements (i.e., pixels) that convert light into digital data. The image sensor may have any number (e.g., hundreds, thousands, millions, or more) of pixels. A typical image sensor may have millions of pixels (e.g., several megapixels), for example. For example, the image sensor 14 may include a bias circuit (e.g., a source follower load circuit), a sample and hold circuit, a correlated double sampling (CDS) circuit, an amplifier circuit, an analog-to-digital (ADC) converter circuit, a data output circuit, a memory (e.g., a buffer circuit), an address circuit, etc.

[0023] Static image data and video image data from the image sensor 14 may be provided via path 26 to the image processing and data formatting circuit 16. The image processing and data formatting circuit 16 may be used to perform image processing functions such as data formatting, adjusting white balance and exposure, implementing video image stabilization, face detection, etc. The image processing and data formatting circuit 16 may also be used to compress the original camera image file as needed (e.g., compressed into the Joint Photographic Experts Group format or simply the JPEG format). In a typical arrangement (sometimes referred to as a system-on-chip (SOC) arrangement), the camera sensor 14 and the image processing and data formatting circuit 16 are implemented on a common semiconductor substrate (e.g., a common silicon image sensor integrated circuit die). If desired, the camera sensor 14 and the image processing circuit 16 may be formed on separate semiconductor substrates. For example, the camera sensor 14 and the image processing circuit 16 may be formed on separate substrates that have been stacked.

[0024] The imaging system 10 (e.g., the image processing and data formatting circuit 16) may transfer the acquired image data to the host subsystem 20 via path 18. The host subsystem 20 may include an active control system that transfers control signals for controlling vehicle functions (such as braking or steering) to external devices. The host subsystem 20 may include processing software that is used to detect objects in the image, detect the movement of objects between image frames, determine the distance of objects in the image, filter or otherwise process the images provided by the imaging system 10. The host subsystem 20 may include an alarm system that is configured to disable the imaging system 10 and / or generate a warning (e.g., a warning light on the vehicle dashboard, an audible warning, or other warning) when verification data associated with the image sensor indicates that the image sensor is not operating properly.

[0025] If needed, system 100 can provide users with many advanced functions. For example, in a computer or a high-end mobile phone, the ability to run user applications can be provided to the user. To implement these functions, the host subsystem 20 of system 100 can have input-output devices 22 (such as a keypad, input-output ports, a joystick, and a display) and storage and processing circuitry 24. The storage and processing circuitry 24 can include volatile and non-volatile memories (e.g., random access memory, flash memory, hard disk drive, solid state drive, etc.). The storage and processing circuitry 24 can also include a microprocessor, a microcontroller, a digital signal processor, an application-specific integrated circuit, etc. During the operation of imaging system 10, camera module 12 can continuously capture image frames and provide them to host subsystem 20.

[0026] System 100 can be a vehicle safety system. In a vehicle safety system, the images captured by an image sensor can be used by the vehicle safety system to determine the environmental conditions around the vehicle. For example, the vehicle safety system can include systems such as a parking assistance system, an automatic or semi-automatic cruise control system, an automatic braking system, a collision avoidance system, a lane keeping system (sometimes called a lane drift avoidance system), a pedestrian detection system, etc. In at least some cases, the image sensor can form part of a semi-autonomous or autonomous driverless vehicle. Vehicle safety standards may require verifying that any component of the vehicle safety system (including the image sensor) operates properly before, during, and / or after vehicle operation. The verification operation of the image sensor can be performed by the imaging system before, during, and / or after vehicle operation (e.g., when starting and / or shutting down the imaging system).

[0027] Figure 2 An example of the arrangement of camera module 12 is shown. As Figure 2 shown, camera module 12 includes an image sensor 14 and control and processing circuitry 16. The image sensor 14 can include a pixel array (such as an array 30 of pixels 28 (sometimes referred to herein as image sensor pixels or image pixels 28)), row control circuitry 32, column control and readout circuitry 42, and verification circuitry 47. The control circuitry 16 can be coupled to the row control circuitry 32 and can be coupled to the column control and readout circuitry 42 via a global data path 44. The row control circuitry 32 can receive row addresses from the control circuitry 16 and can have row drivers 34 that supply corresponding row control signals (e.g., dual conversion gain control signals, pixel reset control signals, charge transfer control signals, halo control signals, row selection control signals, or any other desired pixel control signals) to the image pixels 28 through control paths 128. The verification circuitry 47 can also receive the row control signals and can verify the correct operation of the row control signals.

[0028] The column control and readout circuit 42 may be coupled to the columns of the pixel array 30 via one or more conductive lines such as column lines 40. The column lines 40 may be coupled to each column of image pixels 28 in the image pixel array 30 (e.g., each pixel column may be coupled to a corresponding column line 40). One or more column lines may also be coupled to the verification circuit 47. The column lines 40 may be used to read out image signals from the image pixels 28 and to supply bias signals (e.g., bias current or bias voltage) to the image pixels 28. During an image pixel readout operation, the row control circuit 32 may be used to select a row of pixels in the image pixel array 30, and the image data associated with the image pixels 28 of that pixel row may be read out by the circuit 42 on the column lines 40.

[0029] The column control and readout circuit 42 may include a number of column readout circuits 46. Each column readout circuit 46 may be coupled to a corresponding column line 40 and may read out and receive an image signal from the pixels 28 coupled to the corresponding column line. Each column readout circuit 46 may include column circuitry (such as a column amplifier for amplifying the signal read out from the array 30), a sample-and-hold circuit for sampling and storing the signal read out from the array 30, an analog-to-digital converter (ADC) circuit for converting the read-out analog signal into a corresponding digital signal, and a column memory for storing the read-out signal and any other desired data. The column readout circuit 46 may output the digital pixel values to the control and processing circuit 16 via line 44.

[0030] The array 30 may have any number of rows and columns. Generally, the size of the array 30 and the number of rows and columns in the array 30 will depend on the particular implementation of the image sensor 14. Although the rows and columns are generally described herein as horizontal and vertical, the rows and columns may refer to any grid-like structure (e.g., the features described herein as rows may be arranged vertically and the features described herein as columns may be arranged horizontally).

[0031] Over the lifetime of an image sensor, the image sensor may be prone to failure. Therefore, Figure 2 the image sensor 14 in may include a verification circuit 47 for testing the functionality of the image sensor. In some embodiments, the verification circuit 47 may include verification circuit blocks that are coupled to corresponding imaging pixel rows in the array 30. If desired, the verification circuit 47 may include logic circuitry, comparison circuitry, and / or latch circuitry.

[0032] If desired, the row control circuit 32 and the pixel array 30 may be integrated together in a single integrated circuit (by way of example). Alternatively, the row control circuit 32 and the pixel array 30 may be implemented in separate semiconductor substrates. In one example, the pixel array 30 and the verification circuit 47 may be formed in a first chip, while additional circuits (e.g., the row control circuit 32, the column control and readout circuit 42, etc.) are formed in a second chip. The first chip may sometimes be referred to as the pixel sensor chip. The second chip may be referred to as an application specific integrated circuit (ASIC) chip. The two chips may be connected by a conductive interconnect layer (e.g., bonding at hybrid bonding and / or peripheral contact pads). If desired, the pixels of the pixel array 32 may also be split between multiple semiconductor substrates.

[0033] In the foregoing embodiments where the stacked chip is used to implement the image sensor 14, it may be desirable for the verification circuit (e.g., the verification circuit 47 in the pixel sensor chip) to have only nMOS (n-channel metal oxide semiconductor) transistors. Including only nMOS transistors (and no pMOS transistors) in the pixel sensor chip can reduce the amount of implantation steps for forming the chip during manufacturing. Additionally, forming the pixel sensor chip to have only nMOS transistors (and no pMOS transistors) can reduce contamination. Thus, it may be desirable to use only nMOS transistors in the pixel sensor chip. Even if all the image sensors 14 are formed using a single semiconductor substrate, it may be desirable for the verification circuit 47 to have only nMOS transistors to reduce the manufacturing complexity of the image sensor.

[0034] Figure 3 is a circuit diagram showing Figure 3 an exemplary structure of the pixel 28 in. As Figure 3 shown, the pixel 28 includes a photodiode 54, a floating diffusion region (FD) 56, and a transfer transistor 58. The photodiode 54 can sense light by converting incident photons into electrons or holes. The transfer transistor 58 can be activated to transfer charge from the photodiode 54 to the floating diffusion region 56. A row selection transistor 64 is interposed between the drain of the source follower transistor 60 and the column output line 40. To read the charge from the floating diffusion region 56, the row selection transistor 64 is activated and a voltage corresponding to the charge at the floating diffusion region is read on the column output line 40. The floating diffusion region 56 is coupled to the source follower transistor 60 and a reset transistor 62. The source follower transistor is also coupled to a bias voltage source line 63 that provides a bias voltage (e.g., V AAPIX )).

[0035] After completing the charge-to-voltage conversion and transferring the resulting signal out of the pixel (by activating the row selection transistor 64), the pixel can be reset by activating the reset transistor 62 and coupling the floating diffusion region to the bias voltage source line 63. In some arrangements, all of the transistors in pixel 28 can be nMOS transistors. In other words, the transfer transistor 58, the reset transistor 62, the source follower transistor 60, and the row selection transistor 64 are all nMOS transistors. The transfer transistor 58 has a gate that receives a transfer control signal TX. The row selection transistor 64 has a gate that receives a row selection control signal RS. The reset transistor 62 has a gate that receives a reset control signal RST. Figure 3 The pixel structure shown is merely illustrative. If desired, pixel 28 can include any other desired pixel components (e.g., one or more storage diodes, one or more storage capacitors, anti-halo transistors, one or more dual conversion gain transistors, one or more dual conversion gain capacitors, etc.) in any desired configuration.

[0036] Figure 4 is a schematic diagram showing an exemplary verification circuit 47 that can be included in an image sensor. As shown, each imaging pixel row in the pixel array 30 can have an associated verification circuit block 47V. Each verification circuit block 47V can receive one or more row control signals (e.g., transfer control signal TX, row selection control signal RS, reset control signal RST, etc.) associated with that row. The verification circuit block 47V can verify the correct operation of the row control signals (e.g., to ensure that one or more of the row control signals are activated in a desired manner). The verification circuit block can be coupled to the column output line 40.

[0037] In Figure 4 , one verification circuit block is depicted for each imaging pixel row. This example is merely illustrative. If desired, each imaging pixel row can include two or more verification circuit blocks. If desired, verification circuit blocks can be shared among multiple imaging pixel rows. In Figure 4 , the verification circuit blocks share a common output line 40. This example is merely illustrative, and additional output lines can be included if desired.

[0038] Figure 4 The verification circuit block 47V of Figure 2 can be used to test the operation of the row driver (e.g., the row driver 34 in

[0039] Regardless of the specific control signals provided by the row driver, it is desirable to be able to verify the correct operation of the row driver. During normal operation, the control signals can be provided at a logic low level (e.g., a first voltage) or a logic high level (e.g., a second voltage different from the first voltage). The control signals can be switched between the low and high levels to control the transistors in the imaging pixels in a desired manner. However, in some cases, the row driver may not operate correctly and may not be able to switch the control signals between the low and high levels. The control signals can be provided at a high level all the time (e.g., in a "stuck high" scenario), or can be provided at a low level all the time (e.g., in a "stuck low" scenario). When the row driver is "stuck high" or "stuck low", the imaging pixels will not operate correctly. A verification circuit (such as Figure 5 the verification circuit block) can be used to verify that the row driver is operating normally and is not stuck high or stuck low.

[0040] Figure 5 The verification circuit block 47V of includes a first bias voltage source terminal 102. The bias voltage source terminal 102 can provide a bias voltage (V DDPRECH ). A transistor 104 (e.g., a precharge transistor 104) can be coupled to the bias voltage source terminal. The first transistor 104 is coupled between the transistor 106 and the bias voltage source terminal. The transistor 106 can be coupled between the transistor 104 and the node 107. The transistor 108 can be coupled between the node 107 and the node 109. The transistor 110 can be coupled between the node 109 and the transistor 112. The transistor 112 can be coupled between the transistor 110 and the bias voltage source terminal 124. The bias voltage source terminal 124 can provide a bias voltage different from V DDPRECH (V SSHLOGIC ).

[0041] The transistors 110 and 112 are thus serially coupled between the node 109 and the bias voltage source terminal 124. The transistors 114 and 116 can also be serially coupled between the node 109 and the bias voltage source terminal 124 (in parallel with the transistors 110 and 112).

[0042] A capacitor 118 is coupled to the node 107 at a voltage VS2. A transistor 120 is coupled between the capacitor 118 and the transistor 122. The transistor 122 is coupled between the transistor 120 and the node 149 (which is coupled to a capacitor 150).

[0043] The transistor 126 (e.g., the precharge transistor 126) can be coupled to a bias voltage source terminal. The first transistor 126 is coupled between the transistor 128 and the bias voltage source terminal 102. The transistor 128 can be coupled between the transistor 126 and the node 129. The transistor 130 can be coupled between the node 129 and the node 131. The transistor 132 can be coupled between the node 131 and the transistor 134. The transistor 134 can be coupled between the transistor 132 and the bias voltage source terminal 124.

[0044] The transistors 132 and 134 are thus serially coupled between the node 131 and the bias voltage source terminal 124. The transistors 136 and 138 can also be serially coupled between the node 131 and the bias voltage source terminal 124 (in parallel with the transistors 132 and 134).

[0045] The capacitor 140 is coupled to the node 129, which is at the voltage VS1. The transistor 142 is coupled between the capacitor 140 and the transistor 144. The transistor 144 is coupled between the transistor 142 and the node 149 (which is coupled to the capacitor 150).

[0046] The transistor 148 is interposed between the node 149 and the transistor 146. The transistor 146 is interposed between the bias voltage source terminal 102 and the transistor 148. The capacitor 150 (sometimes referred to as a floating diffusion region FD, a floating diffusion node FD, etc.) is coupled to the gate of the transistor 152 (sometimes referred to as a source follower transistor). The transistor 152 is coupled between the bias voltage source terminal 102 and the transistor 154. The transistor 154 is coupled between the source follower transistor 152 and the column output line 40. When the transistor 154 is enabled, an output voltage PIXOUT proportional to the voltage on the floating diffusion region 150 can be output on the column line 40.

[0047] The transistors 104 and 126 can have respective gates that receive a precharge control signal “prech”. Thus, these transistors can be referred to as precharge transistors or precharge control transistors. The transistors 106 and 128 can have respective gates that receive a control signal “convdd”. In one example, Convdd can be a control signal that is typically high during normal operation of the imaging pixel. The transistors 106 and 128 can be referred to as precharge transistors or precharge control transistors.

[0048] Transistors 108 and 130 may have respective gates that receive a row driver signal “rowdrv”. The row driver signal can be any control signal from a row driver in an image sensor. Verification circuit 47V tests whether the row driver signal “rowdrv” is operating correctly. The row driver signal can be a transfer transistor control signal (TX), a reset transistor control signal (RST), a row select transistor control signal (RS), a dual conversion gain transistor control signal, etc. Transistors 108 and 130 may be referred to as row driver transistors, test transistors, verification transistors, etc.

[0049] Transistors 110 and 132 may have respective gates that receive a row select read control signal “sel_row_rd”. These transistors may be referred to as read phase discharge enable transistors, read phase select transistors, discharge transistors, etc. Transistors 112 and 134 may have respective gates that receive a discharge read control signal “disch_rd”. These transistors may be referred to as read phase discharge enable transistors, read phase discharge transistors, discharge transistors, etc.

[0050] Transistors 114 and 136 may have respective gates that receive a row select shutter control signal “sel_row_sh”. These transistors may be referred to as shutter phase discharge enable transistors, shutter phase select transistors, discharge transistors, etc. Transistors 116 and 138 may have respective gates that receive a discharge control signal “disch”. These transistors may be referred to as shutter phase discharge enable transistors, discharge enable transistors, shutter phase discharge transistors, discharge transistors, etc.

[0051] Transistor 120 may have a gate that receives a capacitor transfer control signal CS2. Transistor 120 may be referred to as a transfer transistor, a capacitor transfer transistor, etc. Transistor 142 may have a gate that receives a capacitor transfer control signal CS1. Transistor 142 may be referred to as a transfer transistor, a capacitor transfer transistor, etc.

[0052] Transistors 122, 144, 148, and 154 may receive a row select control signal RS. The row select control signal may be made active when it is desired to test a pixel row that includes verification circuit 47. Transistors 122, 144, 148, and 154 may be referred to as row select transistors. Transistor 146 may have a gate that receives a reset control signal RST. Transistor 146 may be referred to as a reset transistor.

[0053] Figure 5 The depicted arrangement of the verification circuit is merely illustrative. If desired, it may be omitted Figure 5One or more of the transistors depicted in. For example, one or more of the transistors 104, 106, 108, 110, 112, 114, 116, 126, 128, 130, 132, 134, 136, 138, 120, 122, 142, 144, 146, 148, 152, and 154 may be omitted.

[0054] Figure 5 The operation of the verification circuit may have three phases. First, during the pre-charge phase, the capacitors 118 and 140 may be charged to V DDPRECH . Next, during the intentional discharge phase, the capacitors 118 and 140 may be discharged to V SSHLOGIC . Finally, a read phase may be used to verify whether the row driver being tested is operating correctly. These operation phases are discussed in more detail in conjunction with Figures 6 to 9 These operation phases are discussed in more detail.

[0055] Figure 6 is a timing diagram showing Figure 5 the operation of the verification circuit 47V during the pre-charge phase and the intentional discharge phase. As shown, during the pre-charge phase, the control signals prech and convdd may rise to a high level. This causes the transistors 104 and 106 to become effective, thereby charging the capacitor 118 from the bias voltage source terminal 102 to V VDDPRECH . This also causes the transistors 126 and 128 to become effective, thereby charging the capacitor 140 from the bias voltage source terminal 102 to V VDDPRECH .

[0056] During the pre-charge phase, the remaining control signals (e.g., sel_row_sh, disch, sel_row_rd, disch_rd, and rowdrv) may be kept low so that the capacitors 118 and 140 remain at the pre-charge level. Since multiple transistors in series must become effective for discharge to occur, one of these transistors (e.g., transistor 108 or transistor 130) may be raised to a high level during the pre-charge phase without causing discharge of the capacitor.

[0057] At t1 (after the end of the pre-charge phase), the capacitors 118 and 140 are charged to V DDPRECH . Next, there may be an intentional discharge phase. This may occur during the shutter operation phase of the imaging pixel that receives a signal from the row driver. During the intentional discharge phase, the control signals sel_row_sh and disch rise to a high level. This causes the transistors 114, 116, 136, and 138 to become effective. When the transistors 114 and 116 become effective, the effectiveness of the transistor 108 will cause the capacitor 118 to be discharged to V SSHLOGICWhen transistors 136 and 138 are active, the activation of transistor 130 will cause capacitor 140 to discharge to V SSHLOGIC The rowdrv control signal can be activated one or more times (if properly operated) during the intentional discharge phase, causing capacitors 118 and 140 to discharge.

[0058] Thus, at t2, if the row driver is operating properly and rowdrv is activated during the intentional discharge phase, both capacitors 118 and 140 will be at V SSHLOGIC If the row driver fails and rowdriv is fixed high, the capacitors will still discharge (due to the activation of transistors 108 and 130 during the intentional discharge phase). Thus, even if the row driver is fixed high, capacitors 118 and 140 will be at V at t2 SSHLOGIC If the row driver fails and rowdrv is fixed low, transistors 108 and 130 will not be activated during the intentional discharge phase. Thus, capacitors 118 and 140 will not be discharged, and both capacitors 118 and 140 will still be at the precharge level V at t2 DDPRECH .

[0059] After the intentional discharge phase, a read phase can be performed. Figure 7 Shows the read phase when the row driver is operating properly. Figure 8 Shows the read phase when the row driver is fixed high. Figure 9 Shows the read phase when the row driver is fixed low.

[0060] As Figure 7 shown, during the read phase, control signals sel_row_rd, rs, disch_rd, rst, and cs2 can rise to high level at t1. Activating sel_row_rd throughout the read phase causes transistors 110 and 132 to be activated throughout the read phase. Activating disch_rd throughout the read phase causes transistors 112 and 134 to be activated throughout the read phase. Since transistors 110 and 112 are both activated throughout the read phase, any activation of rowdrv will cause capacitor 118 to discharge to V SHHLOGIC Since transistors 132 and 134 are both activated throughout the read phase, any activation of rowdrv will cause capacitor 140 to discharge to V SHHLOGIC .

[0061] Activating the row select control signal RS throughout the read phase causes transistors 122, 144, 148, and 154 to be activated throughout the read phase. This enables sampling of PIXOUT onto column output line 40.

[0062] As Figure 7 shown, the reset control signal RST and the capacitor transfer signal CS2 rise to a high level between t1 and t2. Accordingly, the floating diffusion region 150 is reset to V DDPRECH . Since the row driver operates normally, capacitors 118 and 140 enter the read phase at V SSHLOGIC (e.g., before t1). However, transistors 120, 122, 148, and 146 all become active between t1 and t2. This causes capacitor 118 to be reset to V DDPRECH . However, at this time CS1 remains at a low level. Accordingly, transistor 142 is not active, and capacitor 140 remains at V SSHLOGIC .

[0063] After the control signals rst and cs2 fall to a low level (rendering transistors 120 and 146 inactive), the voltage at the floating diffusion 150 can be sampled at t3. This sample can be considered the reset level of the floating diffusion region and can be referred to as the sample and hold reset (SHR).

[0064] At t4, CS1 rises to a high level. This causes the voltage (V SSHLOGIC ) from capacitor 140 to be transferred to the floating diffusion region 150. Accordingly, the FD voltage drops, as Figure 7 shown. At t5, the FD voltage is sampled. This sample can be considered the signal level of the floating diffusion region and can be referred to as the sample and hold signal (SHS).

[0065] At t6, the control signals (e.g., CS1, sel_row_rd, rs, disch_rd) can return to a low level.

[0066] As Figure 7 shown, PIXOUT swings between the SHR at t3 and the SHS at t5. The difference between PIXOUT between these two samples indicates that the row driver signal being tested is operating correctly. As will be shown in Figure 8 and Figure 9 , when the row driver is fixed at a high level or fixed at a low level, PIXOUT may not change between t3 and t5.

[0067] Figure 8 is a timing diagram showing the read phase when the row driver is fixed at a high level. As discussed in connection with Figure 6 , when the row driver is fixed at a high level, capacitors 118 and 140 will still enter the read phase at V SSHLOGIC .

[0068] During the read phase, control signals sel_row_rd, rs, disch_rd, rst, and cs2 may rise to high level at t1. Enabling sel_row_rd throughout the read phase causes transistors 110 and 132 to be enabled throughout the read phase. Enabling disch_rd throughout the read phase causes transistors 112 and 134 to be enabled throughout the read phase. Since transistors 110 and 112 are both enabled throughout the read phase, any activation of rowdrv will cause capacitor 118 to be discharged to V SHHLOGIC . Since transistors 132 and 134 are both enabled throughout the read phase, any activation of rowdrv will cause capacitor 140 to be discharged to V SHHLOGIC .

[0069] Enabling the row select control signal RS throughout the read phase causes transistors 122, 144, 148, and 154 to be enabled throughout the read phase. This enables sampling of PIXOUT onto column output line 40.

[0070] As Figure 8 shown, the reset control signal RST and the capacitor transfer signal CS2 rise to high level between t1 and t2. Thus, the floating diffusion region 150 is reset to V DDPRECH . Between t1 and t2, transistors 120, 122, 148, and 146 are all enabled. This causes capacitor 118 to be reset to V DDPRECH . At this time, CS1 remains low. Thus, transistor 142 is not enabled, and capacitor 140 remains at V SSHLOGIC .

[0071] After the control signals rst and cs2 fall to low level (disabling transistors 120 and 146), due to the accidental discharge of the capacitor, the voltage VS2 at capacitor 118 may drop from V DDPRECH to V SSHLOGIC . Although the capacitor is reset to V DDPRECH at the start of the read phase, the fact that the row driver signal rowdrv is fixed at high level means that transistors 108, 110, and 112 are all enabled. Thus, although previously reset to V DDPRECH , the capacitor is inadvertently discharged back to V SHHLOGIC .

[0072] The voltage of the floating diffusion 150 can be sampled at t3. During this sample (SHR), due to the inadvertent discharge caused by rowdrv being fixed at high level, the floating diffusion is sampled at V SSHLOGIC .

[0073] At t4, CS1 rises to a high level. This causes the voltage (V SSHLOGIC ) from capacitor 140 to be transferred to the floating diffusion region 150. However, FD is already at V SSHLOGIC , so the FD voltage does not change. At t5, the FD voltage is sampled (SHS).

[0074] At t6, the control signals (e.g., CS1, sel_row_rd, rs, disch_rd) can return to a low level.

[0075] As Figure 8 shown, PIXOUT does not swing between SHR at t3 and SHS at t5. The lack of swing in PIXOUT between the two samples indicates that the tested row driver signal is not operating correctly.

[0076] Figure 9 is a timing diagram showing the read phase when the row driver is fixed at a low level. As discussed in connection with Figure 6 , when the row driver is fixed at a low level, capacitors 118 and 140 will enter the read phase at V DDPRECH .

[0077] During the read phase, the control signals sel_row_rd, rs, disch_rd, rst, and cs2 can rise to a high level at t1. Enabling sel_row_rd throughout the read phase causes transistors 110 and 132 to be enabled throughout the read phase. Enabling disch_rd throughout the read phase causes transistors 112 and 134 to be enabled throughout the read phase. Since transistors 110 and 112 are both enabled throughout the read phase, any activation of rowdrv will cause capacitor 118 to be discharged to V SHHLOGIC . Since transistors 132 and 134 are both enabled throughout the read phase, any activation of rowdrv will cause capacitor 140 to be discharged to V SHHLOGIC .

[0078] Enabling the row selection control signal RS throughout the read phase causes transistors 122, 144, 148, and 154 to be enabled throughout the read phase. This enables sampling of PIXOUT onto the column output line 40.

[0079] As Figure 9 shown, the reset control signal RST and the capacitor transfer signal CS2 rise to a high level between t1 and t2. Thus, the floating diffusion region 150 is reset to V DDPRECH . Between t1 and t2, transistors 120, 122, 148, and 146 are all enabled. If capacitor 118 has been correctly discharged during the intentional discharge phase, this will cause capacitor 118 to be reset to VDDPRECH However, since rowdrv is fixed at a low level, capacitor 118 is already at V DDPRECH , and the reset does not change the capacitor voltage level. At this time, CS1 remains at a low level. Transistor 142 is not effective and capacitor 140 also remains at V DDPRECH .

[0080] After the control signals rst and cs2 fall to a low level (rendering transistors 120 and 146 ineffective), the voltage at floating diffusion 150 can be sampled at t3. This sample can be considered the reset level of the floating diffusion region and can be referred to as sample and hold reset (SHR).

[0081] At t4, CS1 rises to a high level. This causes the voltage from capacitor 140 (V DDPRECH ) to be transferred to floating diffusion region 150. However, FD is already at V DDPRECH , so the FD voltage does not change. At t5, the FD voltage is sampled (SHS).

[0082] At t6, the control signals (e.g., CS1, sel_row_rd, rs, disch_rd) can return to a low level.

[0083] As Figure 9 shown, PIXOUT does not swing between the SHR at t3 and the SHS at t5. The lack of swing of PIXOUT between the two samples indicates that the row driver signal being tested is not operating correctly.

[0084] Therefore, Figure 5 the verification circuit can determine whether the row driver control signal switches correctly between a high level state and a low level state. The transistors used to form Figure 5 the verification circuit can all be n-channel metal oxide semiconductor (nMOS) transistors. Including only nMOS transistors (without pMOS transistors) in the pixel sensor chip can reduce the amount of implantation steps for forming the chip during manufacturing. Additionally, forming the pixel sensor chip to have only nMOS transistors (without pMOS transistors) can reduce contamination. Figure 5 the verification circuit can operate using only nMOS transistors. Additionally, Figure 5 the verification circuit can test the row driver control signal without any intermediate modification to the row driver control signal (e.g., no level shifter is required to shift the row driver control signal before testing). The verification circuit receives the row driver control signal in the same form as the pixel. This reduces the chance of a fault occurring within the verification circuit. Compared to an arrangement where a level shifter, latch circuit, or additional circuit is used, Figure 5The verification circuit can also occupy the smallest space on the pixel sensor chip.

[0085] It should be understood that in Figure 5 , two identical circuits are coupled to the floating diffusion region. For example, transistors 104, 106, 108, 110, 112, 114, 116, 120, and 122 and capacitor 118 form the first branch of the circuit. Transistors 126, 128, 130, 132, 134, 136, 138, 142, and 144 and capacitor 140 form the second branch of the circuit. The first branch and the second branch have the same structure. In some cases, one of the two branches can be omitted, and the verification circuit can include only a single branch. For example, if three-transistor readout (3T read) is used, only one branch may be required. If four-transistor readout (4T read) is used, two branches can be used as in Figure 5 to allow detection of the row driver signal fixed at a high level.

[0086] According to one embodiment, an image sensor may include: an imaging pixel array; a row driver that provides control signals to the imaging pixel array; and a verification circuit configured to test the operation of the row driver. The verification circuit may include: a storage capacitor; a first bias voltage source terminal; a first transistor interposed between the storage capacitor and the first bias voltage source terminal; a second bias voltage source terminal; and a second transistor and a third transistor serially coupled between the storage capacitor and the second bias voltage source terminal.

[0087] According to another embodiment, the second transistor may have a gate that receives the control signal from the row driver.

[0088] According to another embodiment, the verification circuit may further include: a floating diffusion region; and a fourth transistor interposed between the storage capacitor and the floating diffusion region.

[0089] According to another embodiment, the verification circuit may further include: a source follower transistor having a gate coupled to the floating diffusion region; and a row selection transistor coupled between the source follower transistor and the output line.

[0090] According to another embodiment, the verification circuit may further include a fifth transistor serially connected to the second transistor and parallely coupled to the third transistor between the storage capacitor and the second bias voltage source terminal.

[0091] According to another embodiment, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the storage capacitor may form at least a part of a first verification circuit branch, and the verification circuit may include a second verification circuit branch having the same layout as the first verification circuit branch.

[0092] According to another embodiment, the storage capacitor may be a first storage capacitor, and the verification circuit may further include: a second storage capacitor; a sixth transistor interposed between the second storage capacitor and the first bias voltage source terminal; a seventh transistor and an eighth transistor serially coupled between the second storage capacitor and the second bias voltage source terminal; a ninth transistor interposed between the second storage capacitor and the floating diffusion region; and a tenth transistor serially coupled with the seventh transistor and coupled in parallel with the eighth transistor between the second storage capacitor and the second bias voltage source terminal.

[0093] According to another embodiment, the second transistor may have a gate receiving the control signal from the row driver and the seventh transistor may have a gate receiving the control signal from the row driver.

[0094] According to another embodiment, the verification circuit may further include: an eleventh transistor, wherein the first transistor and the eleventh transistor are serially coupled between the first storage capacitor and the first bias voltage source terminal; and a twelfth transistor, wherein the sixth transistor and the twelfth transistor are serially coupled between the second storage capacitor and the first bias voltage source terminal.

[0095] According to another embodiment, the verification circuit may further include a reset transistor coupled between the floating diffusion region and the first bias voltage source terminal.

[0096] According to one embodiment, an image sensor may include: an imaging pixel array having a first row; a row driver configured to provide a control signal to the first row; and a verification circuit block configured to receive the control signal and test the operation of the row driver. The verification circuit block may include: a charge storage region; a precharge transistor coupled between the charge storage region and the first bias voltage source terminal; and a verification transistor coupled between the charge storage region and the second bias voltage source terminal and having a gate receiving the control signal.

[0097] According to another embodiment, the charge storage region, the precharge transistor, and the verification transistor may form at least a part of a first branch of the verification circuit block and the verification circuit block may include a second branch identical to the first branch.

[0098] According to another embodiment, the verification circuit block may further include a first transistor coupled to the precharge transistor. The precharge transistor and the first transistor may be serially coupled between the first bias voltage source terminal and the charge storage region.

[0099] According to another embodiment, the verification circuit block may further include the second transistor and the third transistor, which are serially coupled to the verification transistor between the charge storage region and the second bias voltage source terminal.

[0100] According to another embodiment, the verification circuit block may further include a fourth transistor and a fifth transistor, which are serially coupled to the verification transistor between the charge storage region and the second bias voltage source terminal. The fourth transistor and the fifth transistor may be coupled in parallel with the second transistor and the third transistor between the verification transistor and the second bias voltage source terminal.

[0101] According to another embodiment, the verification circuit block may further include: a floating diffusion region; and a sixth transistor and a seventh transistor, which are serially coupled between the charge storage region and the floating diffusion region.

[0102] According to another embodiment, the verification circuit block may include: an eighth transistor and a ninth transistor, which are serially coupled between the floating diffusion region and the first bias voltage source terminal; a source follower transistor having a gate coupled to the floating diffusion region; and a row selection transistor coupled between the source follower transistor and the column output line.

[0103] According to one embodiment, an image sensor may further include: an imaging pixel array; a row driver that provides control signals to the imaging pixel array; and a verification circuit that includes a first storage capacitor and a second storage capacitor and a first transistor and a second transistor having respective first gates and second gates that receive the control signals. The verification circuit may be configured to: precharge the first storage capacitor and the second storage capacitor to a first bias voltage, intentionally discharge the first storage capacitor and the second storage capacitor to a second bias voltage using the first transistor and the second transistor; reset only the first storage capacitor back to the first bias voltage; and test the operation of the row driver using a first sample from the first storage capacitor and a second sample from the second storage capacitor.

[0104] According to another embodiment, precharging the first storage capacitor and the second storage capacitor to the first bias voltage may include activating a first precharge transistor and a second precharge transistor interposed between the first storage capacitor and the second storage capacitor and a first bias voltage source terminal.

[0105] According to another embodiment, the first transistor and the second transistor may be coupled between the first storage capacitor and the second storage capacitor and a second bias voltage source terminal, and intentionally discharging the first storage capacitor and the second storage capacitor to the second bias voltage may include activating the first transistor and the second transistor.

[0106] The foregoing are merely illustrative descriptions of the principles of the present invention, and those skilled in the art can make various modifications. The above embodiments may be implemented individually or in any combination.

Claims

1. An image sensor, comprising: An imaging pixel array; A row driver that provides control signals to the imaging pixel array; And A verification circuit configured to test the operation of the row driver, wherein the verification circuit includes: A storage capacitor; A first bias voltage source terminal; A first transistor interposed between the storage capacitor and the first bias voltage source terminal; A second bias voltage source terminal; and A second transistor and a third transistor serially coupled between the storage capacitor and the second bias voltage source terminal, wherein the verification circuit is configured to pre-charge the storage capacitor, intentionally discharge the storage capacitor using the second transistor and the third transistor, and test the operation of the row driver using a sample from the storage capacitor.

2. The image sensor according to claim 1, wherein the second transistor has a gate that receives a control signal from the row driver.

3. The image sensor according to claim 1, wherein the verification circuit further includes: A floating diffusion region; A fourth transistor interposed between the storage capacitor and the floating diffusion region; A source follower transistor having a gate coupled to the floating diffusion region; And A row selection transistor coupled between the source follower transistor and a column output line.

4. The image sensor according to claim 3, wherein the verification circuit further includes: A fifth transistor coupled between the storage capacitor and the second bias voltage source terminal in series with the second transistor and in parallel with the third transistor.

5. The image sensor according to claim 4, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor and the storage capacitor form at least a part of a first verification circuit branch, and wherein the verification circuit includes a second verification circuit branch having the same arrangement as the first verification circuit branch.

6. The image sensor according to claim 4, wherein the storage capacitor is a first storage capacitor, and wherein the verification circuit further includes: A second storage capacitor; A sixth transistor interposed between the second storage capacitor and the first bias voltage source terminal; A seventh transistor and an eighth transistor serially coupled between the second storage capacitor and the second bias voltage source terminal; A ninth transistor interposed between the second storage capacitor and the floating diffusion region; A tenth transistor coupled between the second storage capacitor and the second bias voltage source terminal in series with the seventh transistor and in parallel with the eighth transistor, wherein the second transistor has a gate that receives the control signal from the row driver, and wherein the seventh transistor has a gate that receives the control signal from the row driver; An eleventh transistor, wherein the first transistor and the eleventh transistor are serially coupled between the first storage capacitor and the first bias voltage source terminal; and A twelfth transistor, wherein the sixth transistor and the twelfth transistor are serially coupled between the second storage capacitor and the first bias voltage source terminal.

7. The image sensor according to claim 4, wherein the verification circuit further comprises: A reset transistor coupled between the floating diffusion region and the first bias voltage source terminal.

8. An image sensor comprising: An imaging pixel array having a first row; A row driver configured to provide a control signal to the first row; and A verification circuit block configured to receive the control signal and test the operation of the row driver, wherein the verification circuit block comprises: a charge storage region; a precharge transistor coupled between the charge storage region and a first bias voltage source terminal; and a verification transistor coupled between the charge storage region and a second bias voltage source terminal and having a gate receiving the control signal.

9. The image sensor according to claim 8, wherein the verification circuit block further comprises: A first transistor coupled to the precharge transistor, wherein the precharge transistor and the first transistor are serially coupled between the first bias voltage source terminal and the charge storage region; A second transistor and a third transistor, the second transistor and the third transistor being serially coupled with the verification transistor between the charge storage region and the second bias voltage source terminal; A fourth transistor and a fifth transistor, the fourth transistor and the fifth transistor being serially coupled with the verification transistor between the charge storage region and the second bias voltage source terminal, wherein the fourth transistor and the fifth transistor are coupled in parallel with the second transistor and the third transistor between the verification transistor and the second bias voltage source terminal; A floating diffusion region; A sixth transistor and a seventh transistor, the sixth transistor and the seventh transistor being serially coupled between the charge storage region and the floating diffusion region; An eighth transistor and a ninth transistor, the eighth transistor and the ninth transistor being serially coupled between the floating diffusion region and the first bias voltage source terminal; A source follower transistor having a gate coupled to the floating diffusion region; and A row selection transistor coupled between the source follower transistor and a column output line.

10. An image sensor comprising: An imaging pixel array; A row driver that provides a control signal to the imaging pixel array; and Verification circuit, the verification circuit includes a bias voltage source terminal, a first storage capacitor and a second storage capacitor, and a first transistor and a second transistor having respective first and second gates, the first gate and the second gate receiving the control signal, wherein the first transistor is coupled between the first storage capacitor and the bias voltage source terminal, wherein the second transistor is coupled between the second storage capacitor and the bias voltage source terminal, and wherein the verification circuit is configured to: Precharge the first storage capacitor and the second storage capacitor to a first bias voltage; Use the first transistor and the second transistor to intentionally discharge the first storage capacitor and the second storage capacitor to a second bias voltage provided by the bias voltage source terminal; Reset only the first storage capacitor back to the first bias voltage; And Use a first sample from the first storage capacitor and a second sample from the second storage capacitor to test the operation of the row driver.

Images