A jtag control device and a method for implementing jtag control

Abstract

The application discloses a JTAG control device and a method for realizing JTAG control. The JTAG control device of the application simply realizes the support of connecting multiple sub JTAG TAP test control circuits to a main TAP control circuit, and effectively realizes JTAG test. The JTAG control device with a master-slave structure has good expansibility, and theoretically, unlimited slave TAP control units can be mounted.

Description

Technical Field

[0001] This application relates to, but is not limited to, electronic control technology, and in particular to a JTAG control device and a method for implementing JTAG control. Background Technology

[0002] The Joint Test Action Group (JTAG) provides a standard test access port, including: Test Data Input (TDI) port, Test Data Output (TDO) port, Test Mode Selection (TMS) port, Test Clock (TCK) port, and Test Reset (TRST) port. JTAG enables boundary scan testing and state control and observation of internal chip circuits. JTAG is the most commonly used test control technology in Design for Test (DFT). The JTAG protocol has evolved from the initial 1149.1 to later versions such as IEEE 1500 and IEEE 1687 (IJTAG, Internal JTAG). The IEEE 1500 protocol defines the standard Wrapper TAP interface and communication mechanism between the Test Access Port (TAP) and the module; the IEEE 1687 protocol defines the internal JTAG (IJTAG) interface and communication mechanism between the chip TAP and the module, or between modules.

[0003] Currently, chips are becoming increasingly larger and have more and more functional requirements. In order to simplify design complexity, modularization and intellectual property (IP) approaches are adopted. When performing DFT test design, sub-modules and IP may integrate JTAG TAP controllers. Such chips will have multiple JTAG TAP controllers. Neither the traditional 1149.1 protocol nor the later evolved IEEE1500 and IEEE1687 JTAG protocols can control the existing JTAG TAP in the control subsystem through the top-level JTAG TAP. Summary of the Invention

[0004] This application provides a JTAG control device and a method for implementing JTAG control, which can simply and effectively implement JTAG testing.

[0005] This application provides a Joint Test Behavior Organization (JTAG) control device, comprising: a master test access port (TAP) control unit and at least one slave TAP control unit;

[0006] The main TAP control unit includes at least: a TAP control module, an enable operation control module, and a selection module; wherein...

[0007] The TAP control module is used to connect to the chip's JTAG interface; the number of bits for the enable signal and output selection signal is determined based on the number of TAP control units.

[0008] The enable operation control module is used to configure the enable signal and the output selection signal according to the number of bits of the enable signal and the output selection signal;

[0009] The selection module is used to select the output of multiple input signals based on the enable signal and the output selection signal;

[0010] The TAP control unit includes at least: a conversion module and a test control module; wherein,

[0011] The conversion module is used to convert the interface between the main TAP control unit and the slave TAP control unit's JTAG TAP test control circuit.

[0012] The test control module is used to perform DFT test control on the generated JTAG test control vector after its own slave TAP control unit is enabled, and to map the JTAG test control vector to the selection module through the conversion module.

[0013] In one exemplary instance, the enabling operation control module is the data register group DR-Chain;

[0014] The configuration of the enable signal in the enable operation control module includes: writing a value into the DR-Chain and setting the enable signal of the slave TAP control unit that needs to acquire JTAG interface communication.

[0015] In one exemplary instance, the main TAP control unit further includes a data operation control module, configured to enable the operation control module to configure the enable signal and the output selection signal under the control of the main TAP control module.

[0016] In one exemplary instance, the selection module is specifically used to: select the output of a multi-input signal based on the enable control signal, the enable signal, and the output selection signal.

[0017] In one exemplary instance, the data operation control module is specifically configured to: connect to the TAP control module, wherein the connection signal includes the instruction-encoded operation signal of the TAP control module; and determine whether to enable the operation control module based on the instruction-encoded operation signal.

[0018] In one exemplary instance, the data operation control module includes: an instruction register group, an instruction comparison storage circuit, a first instruction comparison circuit, a second instruction comparison circuit, and a decision circuit; wherein,

[0019] The instruction register group is used to connect to the TAP control module, and the connection signals include the instruction encoding operation signals of the TAP control module; it stores the loaded IR instructions;

[0020] The first instruction comparison circuit has a preset expected instruction code. After the first IR instruction is loaded, it compares the code with the preset expected instruction code and outputs a first comparison result signal to the instruction comparison storage circuit.

[0021] The instruction compare-and-store circuit is controlled by the instruction register group. Before loading the next IR instruction, the first comparison result signal of the previous IR instruction is latched into the instruction compare-and-store circuit.

[0022] The second instruction comparison circuit has a preset expected instruction code. After the second IR instruction is loaded, it compares the code with the preset expected instruction code and outputs a comparison result signal to the instruction comparison storage circuit.

[0023] The decision circuit is used to receive a first comparison result signal from the instruction comparison storage circuit and a second comparison result signal from the second instruction comparison circuit. When both are enabled, it determines to enable the operation control module and outputs an enable control signal.

[0024] In one exemplary instance, the first IR instruction and the second IR instruction have different bit widths, and the first IR instruction and the second IR instruction need to be loaded sequentially in a pre-set order.

[0025] This application also provides a method for implementing JTAG control, including:

[0026] Different IR instructions are loaded sequentially in a pre-set order;

[0027] Each time an IR instruction is loaded, the loaded IR instruction is compared with the preset expected instruction code. When the loaded IR instruction is completely consistent with the preset expected instruction code, a valid comparison result is obtained.

[0028] When the comparison results of each IR command loaded in succession are valid, the data register encoding is loaded to enable the slave TAP control unit that needs to communicate with the master TAP control unit via the JTAG interface.

[0029] In one exemplary instance, the IR instructions include one or more.

[0030] In one exemplary instance, the loaded IR instruction is completely consistent with the preset expected instruction code, including: the length of the loaded IR instruction is consistent with the length of the preset expected instruction code.

[0031] This application's JTAG control device simply implements support for multiple sub-JTAG TAP test control circuits connected to the master TAP control circuit, effectively realizing JTAG testing. The master-slave structure of this JTAG control device has excellent scalability and theoretically can support an unlimited number of slave TAP control units.

[0032] In one exemplary instance, before triggering data operations by the master TAP control unit, the master TAP control unit must continuously load multiple specific instruction codes of different lengths, which effectively avoids instruction conflicts between the master TAP control unit and the slave TAP control unit.

[0033] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0034] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0035] Figure 1 This is a schematic diagram of the composition and structure of the JTAG control device of this application;

[0036] Figure 2 This is a schematic diagram illustrating the structural composition of an embodiment of the data operation control module of this application;

[0037] Figure 3 This is a schematic diagram illustrating the structural composition of an embodiment of the conversion module of this application;

[0038] Figure 4 This is a schematic diagram illustrating an application embodiment of the conversion module of this application;

[0039] Figure 5 This is a flowchart illustrating the method for implementing JTAG control in this application. Detailed Implementation

[0040] In a typical configuration of this application, the computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0041] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0042] Computer-readable media include both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include non-transitory computer-readable media, such as modulated data signals and carrier waves.

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0044] For chips with multiple JTAG TAP structures, a common serial solution is to daisy-chain all JTAG TAPs in the chip, linking TDI and TDO end-to-end, with TMS, TCK, and TRST shared. While this still allows the entire system to be controlled by five standard JTAG interfaces, as network chips become increasingly large, a design may contain a very large number of JTAG TAP controllers. The daisy-chain structure requires complex and lengthy instructions to encode any JTAG TAP, potentially leading to very low JTAG control efficiency. Furthermore, in some low-power tests, the power domain of certain JTAG TAPs needs to be shut down, which would break the JTAG chain and limit applications.

[0045] For parallel solutions involving multiple JTAG TAP structures in a chip, the star (STAR) connection method is used. This method shares only the three ports TMS, TCK, and TRST, while assigning independent pins to the TDI and TDO of each TAP. As the number of JTAG TAPs increases, the demand for test pins also increases. However, the availability of test pins is very limited, which is a characteristic of current chips. Therefore, the application of the STAR connection method is also limited.

[0046] In large-scale complex chips, many sub-modules (such as Harden blocks or IPs) use JTAG control in their DFT designs or DFT circuits generated by EDA tools. Some of these may have integrated JTAG TAP circuits, while others are based on IJTAG interfaces (IEEE 1687), WTAP interfaces (IEEE 1500), etc. Existing solutions such as daisy-chain or star topologies have limitations in their respective applications, and there is no efficient and concise way to unify the control of multiple JTAG TAP circuits. Furthermore, most chips now adopt modular designs. Current solutions use communication interfaces between sub-modules and the top-level TAP, such as the IEEE 1500 WTAP interface and IJTAG SIBs. These solutions have numerous interface signals, making it difficult to easily and efficiently map the verification vectors of sub-modules to the top level. Additionally, in large-scale chips, the number of sub-modules is very large, and each module has its own JTAG control circuit. Current designs control sub-modules serially, resulting in very low control efficiency.

[0047] As the design scale of high-end chips increases, the number of IPs used increases, and the complexity increases, the inventors of this application believe that the DFT design of chips requires a unified and efficient JTAG control system, while also being compatible with the control of existing JTAG TAP circuits in the chip.

[0048] Figure 1 This is a schematic diagram of the composition and structure of the JTAG control device of this application, as shown below. Figure 1 As shown, it includes at least: a master TAP control unit and at least one slave TAP control unit; wherein,

[0049] The main TAP control unit includes at least: a TAP control module, an enable operation control module, and a selection module; wherein,

[0050] The TAP control module is used to connect to the chip's JTAG interface (including TCK interface, TMS interface, TRST interface, TDI interface, and TDO interface); the bit length of the enable signal (TAP_E signal) and the output selection signal (Sub_TDO signal) is determined according to the number of TAP control units.

[0051] The enable operation control module is used to configure the enable signal (TAP_E signal) and the output selection signal (Sub_TDO signal) according to the number of bits of the enable signal (TAP_E signal) and the output selection signal (Sub_TDO signal);

[0052] The selection module is used to select the output of multiple input signals based on the enable signal and the output selection signal, namely the Sub_TDO signal.

[0053] The TAP control unit includes at least: a conversion module and a test control module; wherein...

[0054] The conversion module is used to convert the interface between the main TAP control unit and the slave TAP control unit's JTAG TAP test control circuit.

[0055] The test control module, after its own slave TAP control unit is enabled, performs DFT test control on the generated JTAG test control vector and maps the JTAG test control vector to the selection module through the conversion module. This is a standard JTAG control circuit; for a detailed description, please refer to the IEEE 1149.1 protocol.

[0056] In one exemplary instance, the TAP control module is part of the JTAG standard protocol, and the JTAG circuit will enter different control states depending on the different control sequences of the TMS signals.

[0057] In one exemplary instance, the number of bits for both the enable signal, TAP_E, and the output selection signal, Sub_TDO, is equal to the number of bits controlled by the TAP control unit.

[0058] In one exemplary instance, the enable operation control module can be a data register group (DR-Chain). By writing a value into the DR-Chain, the TAP_E signal of the slave TAP control unit that needs to acquire JTAG interface communication is set, for example, to 1. For example, assuming there are 5 slave TAP control units, the enable signal, i.e., the TAP_E signal, has 5 bits. If the first, third, and fourth slave TAP control units need to be enabled, then the value of the enable signal, i.e., the TAP_E signal, can be equal to 10110.

[0059] In one exemplary instance, the TCK, TMS, TRST, and TDI interfaces of the JTAG interface on the chip are connected to the TCK, TMS, TRST, and TDI interfaces of the conversion module, enabling the TAP_E and Sub_TDO signals on the operation control module to be connected to the TAP_E and TDOi signals of the conversion module, where i = 1, 2, 3…N.

[0060] This application's JTAG control device simply implements support for multiple sub-JTAG TAP test control circuits connected to the master TAP control circuit, effectively realizing JTAG testing. The master-slave structure of this JTAG control device has excellent scalability and theoretically can support an unlimited number of slave TAP control units.

[0061] In one exemplary embodiment, the main TAP control unit further includes a data operation control module, configured, under the control of the TAP control module in the main TAP control unit, to enable the enabling operation control module to configure the enable signal (TAP_E signal) and the output selection signal (Sub_TDO signal). In other words, the data operation control module generates an enable signal to enable the enabling operation control module, thereby enabling data operation of the main TAP control unit.

[0062] The data operation control module avoids conflicts between operation commands between different TAPs, such as preventing erroneous operations on the instruction register of the main TAP control unit when performing instruction encoding operations from the TAP control unit.

[0063] In one exemplary instance, the data manipulation control module is specifically used for:

[0064] It is connected to the TAP control module in the main TAP control unit, and the connection signal includes the instruction-encoded operation signal of the TAP control module; it determines whether to enable the enabling operation control module based on the instruction-encoded operation signal.

[0065] In one exemplary instance, Figure 2 This is a schematic diagram illustrating the structural composition of an embodiment of the data operation control module of this application, as shown below. Figure 2 As shown, the data operation control module may include: an instruction register set, an instruction comparison storage circuit, and at least one instruction comparison circuit. Figure 2 Taking a circuit comprising two instruction comparison circuits (i.e., a first instruction comparison circuit and a second instruction comparison circuit) as an example, a decision circuit is used; among which,

[0066] The instruction register group is used to connect to the TAP control module in the main TAP control unit. The connection signals include the instruction encoding operation signals of the TAP control module, such as: Capture_IR, Update_IR, Shift_IR, Select_IR (these signals correspond to the status signals output by the TAP control module, i.e., the signals of the TAP state machine in related technologies); it stores the loaded instruction register (IR) instructions;

[0067] The first instruction comparison circuit has a preset expected instruction code. After the first IR instruction is loaded, it compares the code with the preset expected instruction code and outputs a first comparison result signal to the instruction comparison storage circuit. Optionally, it compares and judges the encoding length of the loaded first IR instruction and the expected instruction code preset by the instruction comparison circuit itself (for example, it can be implemented by a counting function). If the contents are completely consistent, the first comparison result signal will be enabled (or effective).

[0068] The instruction compare-and-store circuit is controlled by the instruction register group (such as the Capture_IR signal). Before loading the next IR instruction, the first comparison result signal of the previous IR instruction is latched into the instruction compare-and-store circuit.

[0069] The second instruction comparison circuit has a preset expected instruction code. After the second IR instruction is loaded, it compares the code with the preset expected instruction code and outputs a comparison result signal to the instruction comparison storage circuit. Optionally, it compares and judges the encoding length of the loaded second IR instruction and the preset expected instruction code of the instruction comparison circuit itself (for example, it can be implemented by a counting function). If the contents are completely consistent, the output of the second comparison result signal will be enabled (or effective).

[0070] The decision circuit receives a first comparison result signal from the instruction comparison storage circuit and a second comparison result signal from the second instruction comparison circuit. When both are enabled, it determines to enable the enable operation control module and outputs an enable control signal, namely the Select_stap_en signal. In an exemplary instance, the decision circuit can be a gate circuit representing an AND logic relationship.

[0071] In one exemplary instance, the first IR instruction and the second IR instruction have different bit widths, and the first IR instruction and the second IR instruction need to be loaded sequentially in a pre-set order.

[0072] It should be noted that, in cases involving two or more instruction comparison circuits, the bit widths of the IR instructions loaded by each circuit in a pre-set order are different. This provides the present application with stronger anti-collision capabilities. Alternatively, there may be only one instruction comparison circuit. In this case, only by inputting instructions in a preset order and width will the operation control module be enabled, and only then can the data register (DR) instructions be loaded to operate the registers in the operation control module.

[0073] pass Figure 2In the illustrated embodiment of the data operation control module, the operation control module is only enabled and the DR instruction can be loaded to operate on the registers in the operation control module if two IR instructions are loaded consecutively, and the first IR instruction meets the preset comparison code requirements of the first IR instruction comparison circuit, and the second IR instruction meets the preset comparison code requirements of the second instruction comparison circuit. This processing in this application achieves anti-collision handling of the instruction encoding of the main TAP control unit. That is, before triggering data operation of the main TAP control unit, the main TAP control unit must continuously load multiple instructions (such as...). Figure 2 The two specific instruction codes of different lengths (in the TAP control unit) effectively avoid instruction conflicts between the master TAP control unit and the slave TAP control unit.

[0074] In one exemplary instance, where the main TAP control unit of this application includes a data operation control module, the selection module is used for:

[0075] The output selection of multiple input signals is achieved by using the enable control signal, enable signal, and output selection signal (Sub_TDO signal).

[0076] In one exemplary instance, the selection module is jointly controlled by the outputs of the data operation control module and the enable operation control module to achieve output selection of the multi-input signal, namely the Sub_TDO signal. In the default state (after TRST reset release), the TDO signal selection comes from the TDO output of a slave TAP control unit, such as TDO_i; it can also be selected from the output of the data operation control module circuit or the enable operation control module. When the control signal TAP_E of a slave TAP control unit is enabled, then the TDO signal selection comes from the TDO output of that slave TAP control unit.

[0077] Figure 3 This is a schematic diagram illustrating the structural composition of an embodiment of the conversion module of this application, as shown below. Figure 3 As shown, the conversion module may include some logic gate circuits and is an interface conversion circuit for the JTAG TAP test control circuit of the main TAP control unit and the slave TAP control unit. The interface connecting the main TAP control unit and the conversion module includes: TRST, TCK, TMS, TDI, TAP_E, and Sub_TDO. Among them, the TCK, TMS, TRST, and TDI signals are connected to the JTAG interface on the chip, and the TAP_E and TDO signals are connected to the TAP_E and Sub_TDO signals output by the enable control operation module, respectively. The TAP_E signal is the communication enable control signal of TMS and TDI, which is implemented through TMS and the first control logic circuit, and TDI and the second control logic circuit, respectively.

[0078] It should be noted that if the chip subsystem has control circuits based on the IJTAG interface (IEEE1687) or WTAP interface (IEEE1500), a JTAG TAP controller should first be added to the JTAG control device of this application. Figure 4 The iJTAG from the TAP controller or the IEEE 1500 from the TAP controller, and then through... Figure 3 The interface connection shown can be used to convert the JTAG TAP into an interface for connection to the TAP control circuit.

[0079] The master-slave JTAG control device provided in this application can control all test signals of the entire chip, and is highly compatible with existing JTAG TAP circuits in the IP or generated by EDA tools. The JTAG control device in this application has only six interfaces between the slave TAP control unit and the master TAP control unit (i.e., one slave TAP enable signal and five standard JTAG signals), and the control of the slave TAP control unit is also based on the JTAG protocol. Therefore, it highly efficiently maps the vectors of the slave TAP control unit to the master TAP control unit, greatly improving the vector generation efficiency of the master TAP control unit.

[0080] In one exemplary instance, parallel control can be achieved by broadcasting the same control signals from within the TAP control unit, which greatly improves control efficiency.

[0081] This application provides a method for implementing JTAG control, when the master TAP control unit needs to communicate with the slave TAP control unit's JTAG TAP test control circuit (i.e., Figure 1 When communicating with the test control module in the middle, such as Figure 5 As shown, it includes at least:

[0082] Step 500: Load different IR instructions sequentially according to a pre-set order.

[0083] In one exemplary instance, IR instructions may include one or more.

[0084] Step 501: Each time an IR instruction is loaded, the loaded IR instruction is compared with the preset expected instruction code. When the loaded IR instruction is completely consistent with the preset expected instruction code, a valid comparison result is obtained.

[0085] In one exemplary instance, loading an IR instruction that is completely consistent with a preset expected instruction code may include loading an IR instruction that has the same length as a preset expected instruction code.

[0086] Step 502: When the comparison results of each IR command loaded in succession are valid, load the data register code to enable the slave TAP control unit that needs to communicate with the master TAP control unit through the JTAG interface.

[0087] Thus, after the data register encoding and loading are completed, the JTAG interface and the JTAGTAP test control circuit of the TAP control unit are established. Specifically, in the Bottle-Up design, the JTAGTAP test control circuit of the TAP control unit already has a debugged JTAG application stimulus. At the top level, i.e., the master TAP control unit, it is only necessary to map the application stimulus of the sub-module to the top level based on the vector loading operations of steps 500 to 502 of the sub-module, i.e., the slave TAP control unit.

[0088] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A Joint Test Action Group (JTAG) control device, comprising: A master test access port (TAP) control unit and at least one slave TAP control unit are provided; The master TAP control unit comprises at least a TAP control module, an enable operation control module and a selection module; The TAP control module is configured to connect to a chip JTAG interface and determine the number of bits of the enable signal and the output selection signal according to the number of the slave TAP control units; The enable operation control module is configured to configure the enable signal and the output selection signal according to the number of bits of the enable signal and the output selection signal; The selection module is configured to realize output selection of the multi-input signals according to the enable signal and the output selection signal. The slave TAP control unit comprises at least a conversion module and a test control module; The conversion module is configured to realize interface conversion of the JTAG TAP test control circuit of the master TAP control unit and the slave TAP control unit; The test control module is configured to perform DFT test control on the generated JTAG test control vector after the slave TAP control unit to which the test control module belongs is enabled, and map the JTAG test control vector to the selection module through the conversion module; The master TAP control unit further comprises a data operation control module, and the data operation control module comprises an instruction register group, an instruction comparison storage circuit, a first instruction comparison circuit, a second instruction comparison circuit and a decision circuit. The instruction register group is connected to the TAP control module and stores the loaded IR instruction. The first instruction comparison circuit is preset with an expected instruction code, and compares the first IR instruction with the expected instruction code after the first IR instruction is loaded and outputs a first comparison result signal to the instruction comparison storage circuit. The instruction comparison storage circuit is controlled by the instruction register group, and the first comparison result signal of the previous IR instruction is latched into the instruction comparison storage circuit before the next IR instruction is loaded. The second instruction comparison circuit is preset with an expected instruction code, and compares the second IR instruction with the expected instruction code after the second IR instruction is loaded and outputs a second comparison result signal to the instruction comparison storage circuit. The decision circuit receives the first comparison result signal from the instruction comparison storage circuit and the second comparison result signal from the second instruction comparison circuit, and determines to enable the enable operation control module and output an enable control signal when both the first comparison result signal and the second comparison result signal are enabled.

2. The JTAG control device of claim 1, wherein, The enable operation control module is a data register group DR-Chain. The enable signal configuration in the enable operation control module comprises writing a value into the DR-Chain and setting the enable signal of the slave TAP control unit which needs to obtain JTAG interface communication.

3. The JTAG control device according to claim 1 or 2, wherein the data operation control module is configured to enable the enable operation control module to configure the enable signal and the output selection signal under the control of the TAP control module in the master TAP control unit.

4. The JTAG control device of claim 3, wherein, The selection module is specifically configured to realize output selection of the signals of the multiple paths according to the enable control signal, the enable signal and the output selection signal.

5. The JTAG control device of claim 3, wherein, The data operation control module is specifically configured to be connected with the TAP control module, and the connection signal includes an instruction encoding operation signal of the TAP control module; and whether to enable the enable operation control module is determined according to the instruction encoding operation signal.

6. The JTAG control device of claim 1, wherein, The first IR instruction and the second IR instruction have different bit widths, and the first IR instruction and the second IR instruction need to be loaded continuously in a preset order.

7. A method for implementing JTAG control, applied to the JTAG control device of any one of claims 2 to 6, and the method comprises: loading different IR instructions continuously in a preset order; comparing the loaded IR instruction with a preset expected instruction encoding each time the IR instruction is loaded, and when the loaded IR instruction is completely consistent with the preset expected instruction encoding, an effective comparison result is obtained; when the comparison results of the continuously loaded IR instructions are all effective, loading a data register group encoding, and enabling a slave TAP control unit which needs to communicate with a master TAP control unit through a JTAG interface.

8. The method of claim 7, wherein, The IR instruction includes one or more than one.

9. The method of claim 7, wherein, The loaded IR instruction is completely consistent with the preset expected instruction encoding, including that the length of the loaded IR instruction is consistent with the preset expected instruction encoding. The loaded IR instruction is completely consistent with the preset expected instruction encoding, including that the length of the loaded IR instruction is consistent with the preset expected instruction encoding.

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