Electronic device and method for operating the same

Abstract

An electronic device and an operating method of the electronic device are provided. The electronic device includes: a first equalization circuit configured to receive a data signal and generate a first equalization signal based on the data signal; a pulse generator configured to generate a first pulse signal and a second pulse signal in response to a rising edge and a falling edge of the data signal, respectively; a second equalization circuit configured to output a second equalization signal based on an inverted first pulse signal and an inverted second pulse signal, where the inverted first pulse signal and the inverted second pulse signal are an inversion of the first pulse signal and an inversion of the second pulse signal, respectively; and an output terminal configured to output an output signal obtained by adding the first equalization signal and the second equalization signal.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10 - 2019 - 0120904, filed on Sep. 30, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] Example embodiments of the inventive concept relate to an electronic device including an equalization circuit for correcting a data signal and / or an operation method of the electronic device. Background art

[0004] As the data transfer rate increases with the development of the electronics industry, the importance of data communication technology (e.g., inter - chip data communication) between internal components of an electronic device is also increasing. Inter - chip data communication technology can be, for example, communication between a memory interface and a storage device and / or communication between a radio frequency integrated chip (RFIC) and a processor. However, components inside the electronic device need to meet a high level of electrostatic discharge (ESD) conditions, and due to limitations on inductors caused by the high integration of the electronic device and the provision of a source voltage (Vss) termination, etc., the data transfer rate is limited. Therefore, due to the limited transfer rate of the electronic device, the chip size and cost increase. Summary of the invention

[0005] Example embodiments of the inventive concept provide an electronic device that improves the data transfer rate while overcoming trade - off conditions.

[0006] According to an example embodiment of the inventive concept, there is provided an electronic device including: a first equalization circuit configured to receive a data signal and generate a first equalization signal based on the data signal; a pulse generator configured to generate a first pulse signal and a second pulse signal in response to a rising edge and a falling edge of the data signal, respectively; a second equalization circuit configured to output a second equalization signal based on an inverted first pulse signal and an inverted second pulse signal, the inverted first pulse signal and the inverted second pulse signal being an inversion of the first pulse signal and an inversion of the second pulse signal, respectively; and an output terminal configured to output an output signal based on the first equalization signal and the second equalization signal.

[0007] According to another exemplary embodiment of the inventive concept, there is provided an electronic device including: a first equalization circuit configured to receive a data signal and generate a first equalization signal having a phase opposite to that of the data signal; a pulse generator configured to generate a negative pulse signal based on a falling edge of the data signal, generate a positive pulse signal based on a rising edge of the data signal, and generate a pulse signal including the negative pulse signal and the positive pulse signal; a second equalization circuit configured to output a second equalization signal based on an inverted pulse signal, which is an inversion of the pulse signal; and an output terminal configured to output an output signal based on the first equalization signal and the second equalization signal.

[0008] According to another exemplary embodiment of the inventive concept, there is provided a method of operating an electronic device, the method including: receiving a data signal; generating a first equalization signal having a phase opposite to that of the data signal; generating a negative pulse signal based on a falling edge of the data signal; generating a positive pulse signal based on a rising edge of the data signal; generating a pulse signal including the negative pulse signal and the positive pulse signal; outputting a second equalization signal based on an inverted pulse signal, which is an inversion of the pulse signal; and outputting an output signal obtained based on the first equalization signal and the second equalization signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram showing an electronic device according to an exemplary embodiment of the inventive concept;

[0011] Figure 2 and Figure 3 is a block diagram showing an equalization circuit according to an exemplary embodiment of the inventive concept;

[0012] Figure 4 is a circuit diagram showing an equalization module and an output terminal according to an exemplary embodiment of the inventive concept;

[0013] Figure 5 is a timing diagram of signals according to an exemplary embodiment of the inventive concept;

[0014] Figure 6 is a timing diagram of signals for correcting a data signal according to a comparative example;

[0015] Figure 7is a circuit diagram showing a source voltage termination according to an exemplary embodiment of the inventive concept;

[0016] Figure 8 is a waveform diagram showing an output voltage according to an exemplary embodiment of the inventive concept;

[0017] Figure 9 is a circuit diagram showing a pull - down circuit according to an exemplary embodiment of the inventive concept;

[0018] Figure 10 and Figure 11 is a timing diagram for describing signals and voltages according to an exemplary embodiment of the inventive concept;

[0019] Figure 12 is a flowchart of an operation method of an electronic device according to an exemplary embodiment of the inventive concept;

[0020] Figure 13 is a flowchart of an operation method of an electronic device according to an exemplary embodiment of the inventive concept;

[0021] Figure 14 is a flowchart of an operation method of an electronic device according to an exemplary embodiment of the inventive concept; and

[0022] Figure 15 is a flowchart of an operation method of an electronic device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0023] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0024] Figure 1 is a block diagram showing an electronic device 1 according to an exemplary embodiment of the inventive concept.

[0025] Referring to Figure 1 , the electronic device 1 may include a first chip 10 and a second chip 20. The first chip 10 may include an equalization circuit 100 and an output terminal OT, and the second chip 20 may include an input terminal IT. For example, the electronic device 1 may be included in at least one of a smart phone, a mobile device, an image display device, an image capture device, an image processing device, a measurement device, a smart TV, a drone, a robot such as an advanced driver assistance system (ADAS), a medical device, and an Internet of Things (IoT) device. As another example, the electronic device 1 may include a modem or an application processor (AP). The AP may include components (e.g., chips, logic, cores, etc.) that perform multiple functions, and may include a part or all of the first chip 10 and the second chip 20 as a logic circuit.

[0026] According to an exemplary embodiment of the inventive concept, the first chip 10 may include a radio frequency integrated chip (RFIC), and the second chip 20 may include a processing chip. For example, the first chip 10 may receive wireless communication signals of various frequencies and convert the received wireless communication signals into digital-type data signals DT. The equalization circuit 100 may output an output signal DO corrected from the data signal DT to the second chip 20 via an output terminal OT. The output signal DO may be transmitted to the second chip 20 through a channel CH connected between the first chip 10 and the second chip 20. Although the channel CH is shown as a conductive wiring for ease of description, a plurality of channels CH may be connected between the first chip 10 and the second chip 20. The second chip 20 may receive the output signal DO via an input terminal IT and may perform various operation processes based on the output signal DO.

[0027] According to an exemplary embodiment of the inventive concept, the first chip 10 may communicate by using at least one communication method (or communication protocol) among fifth generation (5G), long term evolution (LTE), third generation (3G), worldwide interoperability for microwave access (WiMax), global system for mobile communications (GSM), code division multiple access (CDMA), Bluetooth, near field communication (NFC), wireless fidelity (WiFi), and radio frequency identification (RFID). The second chip 20 may be implemented by using various types of processing chips such as a central processing unit (CPU), a digital signal processor (DSP), and a micro computing unit (MCU).

[0028] According to an exemplary embodiment of the inventive concept, the first chip 10 may include a memory interface device, and the second chip 20 may include a storage device. For example, the first chip 10 may receive write data from an external host, and the first chip 10 may provide read data to the external host. For example, the first chip 10 may receive write data and correct the write data by using the equalization circuit 100. The first chip 10 may output the corrected data as an output signal DO via an output terminal OT. The second chip 20 may receive the output signal DO via an input terminal IT. The second chip 20 may perform various types of storage operations based on the output signal DO, such as read operations, write operations, and refresh operations.

[0029] According to an exemplary embodiment of the inventive concept, the first chip 10 may perform data communication with the second chip 20 based on at least one protocol among a Peripheral Component Interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, a Serial Attached SCSI (SAS) protocol, a Universal Serial Bus (USB) protocol, a Multimedia Card (MMC) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Mobile Industry Processor Interface (MIPI) protocol, and a Universal Flash Storage (UFS) protocol. The second chip 20 may include a non-volatile memory such as a flash memory, a Magnetic RAM (MRAM), a Ferroelectric RAM (FeRAM), a Phase Change RAM (PRAM), and a Resistive RAM (ReRAM), and may include a Dynamic RAM (DRAM) such as a Double Data Rate (DDR) Synchronous DRAM (SDRAM) (DDR SDRAM), a Low Power (LP) DDR (LPDDR), an SDRAM, a Graphics DDR (GDDR), and a Rambus DRAM (RDRAM).

[0030] As described above, the first chip 10 is shown as an RFIC or a memory interface device, and the second chip 20 is shown as a processing chip or a storage device, but the exemplary embodiment is not limited thereto. In other words, the first chip 10 and the second chip 20 may be mounted on various types of electronic devices, and the equalization circuit 100 may correct various types of signals, as described below.

[0031] According to the description given above, an example of communication from the first chip 10 to the second chip 20 has been described, but the exemplary embodiment is not limited thereto, and the second chip 20 may also include the equalization circuit 100. For example, data processed by the second chip 20 may be output to the outside via the first chip 10. Due to data processing, the second chip 20 may generate a data signal DT, and the equalization circuit 100 of the second chip 20 may correct the data signal DT. The data signal DT corrected by the equalization circuit 100 of the second chip 20 may be output to the first chip 10 as an output signal DO via an input terminal IT of the second chip 20. The first chip 10 may receive the output signal DO via an output terminal OT.

[0032] According to an exemplary embodiment of the inventive concept, the equalization circuit 100 may correct a data signal DT that is a basis for various types of operation processing. The equalization circuit 100 may receive the data signal DT and correct the data signal DT based on rising edges and falling edges of the data signal DT. For example, the equalization circuit 100 may generate a negative pulse signal (e.g., Figure 5in the PSA). Additionally, the equalization circuit 100 may generate a positive pulse signal (e.g., Figure 5 in the PSB).

[0033] When the data signal DT is transmitted through the channel CH and the capacitance is large due to the long length of the channel CH or the high ESD condition of the electronic device, the gap between the logic high level and the logic low level of the data signal DT decreases, or the slew rate increases. In other words, when the length of the channel CH is large, observing the data signal DT on the eye diagram shows that the eye opening performance deteriorates and the rise time and fall time of the data signal DT increase. The equalization circuit 100 may generate a positive pulse signal and a negative pulse signal having a pulse width narrower than that of the data signal DT during the transition period (e.g., the rising edge generation period and the falling edge generation period) of the data signal DT, thereby increasing the difference between the logic high level and the logic low level while not affecting the original data, to improve the eye diagram performance. Thereafter, the equalization circuit 100 may generate an output signal DO having improved eye diagram performance by inverting the positive pulse signal and the negative pulse signal and adding the inverted signals to the data signal DT. Therefore, the equalization circuit 100 may output an output signal DO having the data signal DT corrected by applying the positive pulse signal and the negative pulse signal to the data signal DT.

[0034] Figure 2 and Figure 3 is a block diagram showing an equalization circuit 100 according to an exemplary embodiment of the inventive concept.

[0035] Referring to Figure 2 the equalization circuit 100 may include a receiver 120, an equalization module 130, and an output terminal OT. The equalization circuit 100 may receive an external signal AS and generate a data signal DT based on the external signal AS, and may generate a pulse signal PS based on the external signal AS or the data signal DT. The equalization circuit 100 may provide an output signal DO having the corrected data signal DT to the output terminal OT, and the equalization circuit 100 may output the output signal DO to the outside via the output terminal OT.

[0036] The receiver 120 may receive the external signal AS and output a data signal DT and a pulse signal PS. For example, the external signal AS may be an analog signal, and the data signal DT may be a signal obtained by converting the external signal AS, which is an analog signal, into a digital signal. Referring to Figure 3 this is described.

[0037] Referring to Figure 3, the receiver 120 may further include an analog-to-digital converter (ADC) 121 and a pulse generator 122. The signal source 110 may be included in the equalization circuit 100, but the signal source 110 may be an external structure of the equalization circuit 100 and the electronic device 1. For example, the signal source 110 may be a base station, an external electronic device, etc.

[0038] The ADC 121 may convert an analog signal into a digital signal by various known methods. For example, the external signal AS may be an analog signal. In this case, the ADC 121 may convert the analog signal into a binary digital signal having a logic high level or a logic low level with respect to a specific voltage (e.g., the logic level of an inverter). However, the example embodiments are not limited thereto, and the ADC 121 may be implemented using various devices, circuits, and logics that convert the external signal AS into a signal that can be processed by the electronic device 1.

[0039] The pulse generator 122 may generate a pulse signal ( Figure 2 PS in) based on the data signal DT, and the pulse signal PS may include a negative pulse signal PSA and a positive pulse signal PSB. For example, the pulse generator 122 may be implemented using a digital logic circuit. The pulse generator 122 may generate the negative pulse signal PSA and the positive pulse signal PSB by applying a selector using logic gates such as AND, OR, NOT, NAND, NOR, and XOR and a logic circuit such as a multiplexer and / or an adder to the data signal DT which is a digital type signal.

[0040] The pulse generator 122 may generate a negative pulse signal PSA having a negative pulse (e.g., Figure 5 NP in) at the timing of the falling edge of the data signal DT. For example, the negative pulse signal PSA may have a logic low level and a logic high level, and the negative pulse signal PSA may have a logic low level in response to the falling edge of the data signal DT. In addition, the pulse generator 122 may generate a negative pulse signal PSA having a pulse width smaller than the pulse width of the data signal DT. As an example, the negative pulse signal PSA may transition (or return) to a logic high level after a specific time, as another example, the negative pulse signal PSA may transition to a logic high level at the timing after the occurrence of the falling edge of the data signal DT, as another example, the negative pulse signal PSA may transition to a logic high level before the timing of the occurrence of the rising edge of the data signal DT.

[0041] The pulse generator 122 can generate a positive pulse signal PSB with a positive pulse at the timing of the rising edge of the data signal DT. For example, the positive pulse signal PSB can have a logic low level and a logic high level, and the positive pulse signal PSB can have a logic high level in response to the rising edge of the data signal DT. Additionally, the pulse generator 122 can generate a positive pulse signal PSB with a pulse width smaller than that of the data signal DT. As an example, the positive pulse signal PSB can transition (or return) to a logic low level after a specific time. As another example, the positive pulse signal PSB can transition to a logic low level at the timing after the rising edge of the data signal DT appears. As another example, the positive pulse signal PSB can transition to a logic low level before the timing when the falling edge of the data signal DT appears.

[0042] The negative pulse signal PSA and the positive pulse signal PSB can respectively have a negative pulse NP and a positive pulse, as described above. For example, the pulse width of the negative pulse NP that constitutes the negative pulse signal PSA can be smaller than the pulse width of the data signal DT. For example, the pulse width of the positive pulse that constitutes the positive pulse signal PSB can be smaller than the pulse width of the data signal DT. The following will refer to Figure 5 this for a detailed description.

[0043] Referring again to Figure 2 , the equalization module 130 can include a first equalization circuit 131 and a second equalization circuit 132. For example, the first equalization circuit 131 and the second equalization circuit 132 can be respectively implemented using a plurality of transistors. For example, the first equalization circuit 131 can include an inverter circuit or a buffer circuit having a plurality of transistors, and the second equalization circuit 132 can include an inverter circuit or a buffer circuit having a plurality of transistors.

[0044] The first equalization circuit 131 may receive a data signal DT and output a first equalization signal EQ1 whose phase of the data signal DT is inverted. For example, the first equalization circuit 131 may include an inverter circuit. The first equalization circuit 131 may receive the data signal DT and generate the first equalization signal EQ1 having a level of a driving voltage at a logic low level of the data signal DT. For example, the driving voltage may be a voltage applied to the first equalization circuit 131 from a voltage generator outside the equalization circuit 100. Additionally, the first equalization circuit 131 may generate the first equalization signal EQ1 having a level of a ground voltage at a logic high level of the data signal DT. For example, the ground voltage may be a voltage of a ground wire to which the first equalization circuit 131 is connected. In other words, the first equalization signal EQ1 may be a signal having a level of a driving voltage and a level of a ground voltage. The second equalization circuit 132 may receive a pulse signal PS and output a second equalization signal EQ2 by inverting the received pulse signal PS. For example, the second equalization circuit 132 may also include an inverter circuit. For example, the second equalization circuit 132 may invert a negative pulse signal PSA, invert a positive pulse signal PSB, add the two inverted signals (PSA and PSB), and output the added signal as the second equalization signal EQ2.

[0045] According to another exemplary embodiment of the inventive concept, the first equalization signal EQ1 may be substantially the same as the data signal DT. For example, the phase of the first equalization signal EQ1 may be the same as the phase of the data signal DT. In this case, the first equalization circuit 131 may include a buffer circuit, and the first equalization signal EQ1 may have the same phase as the data signal DT. When the first equalization circuit 131 includes a buffer circuit, the second equalization circuit 132 may also include a buffer circuit. The amplitude of the first equalization signal EQ1 may also be the same as the amplitude of the data signal DT. Alternatively, the first equalization signal EQ1 may be a logic signal having any voltage level. The second equalization circuit 132 may receive a negative pulse signal PSA and a positive pulse signal PSB, add them, invert the added signal, and output the inverted signal as the second equalization signal EQ2.

[0046] According to an exemplary embodiment of the inventive concept, the magnitude of the rising edge and the magnitude of the falling edge of a data signal DT may be increased by using a signal having a pulse in the same direction as the edge direction of the data signal DT. In other words, the equalization module 130 may compensate for the edge magnitude of the data signal DT. For example, the magnitude of the rising edge of the output signal DO output by the equalization module 130 may be greater than the magnitude of the falling edge of the data signal DT, and the magnitude of the falling edge of the output signal DO may be greater than the magnitude of the rising edge of the data signal DT. However, the exemplary embodiment is not limited thereto, and the magnitude of the rising edge and the magnitude of the falling edge of the output signal DO may be greater than the magnitude of the rising edge and the magnitude of the falling edge of the data signal DT, respectively.

[0047] The equalization module 130 may output an output signal DO to the output terminal OT by adding a first equalization signal EQ1 and a second equalization signal EQ2. The output terminal OT may provide the output signal DO to a channel (e.g., Figure 1 CH in), and the output signal DO may be transmitted to an external structure through the channel. For example, the output terminal OT may be implemented in various forms such as a data pin and a data pad.

[0048] The output signal DO may be a signal in which the difference between the logic high level and the logic low level of the first equalization signal EQ1 based on the data signal DT is increased. In other words, the difference between the logic high level and the logic low level of the output signal DO may be greater than the difference between the logic high level and the logic low level of the data signal DT. Accordingly, the inter-symbol interference (ISI) value of the output signal DO may be less than the ISI value of the data signal DT. In other words, the eye opening performance of the eye diagram may be improved.

[0049] Figure 4 is a circuit diagram showing an equalization module 130 and an output terminal OT according to an exemplary embodiment of the inventive concept.

[0050] Referring to Figure 4 the equalization module 130 may include a first equalization circuit 131 and a second equalization circuit 132. The first equalization circuit 131 may further include a first transistor TR1 and a second transistor TR2, and the second equalization circuit 132 may further include a third transistor TR3 and a fourth transistor TR4. For example, the first equalization circuit 131 may include an inverter or a buffer circuit having the first transistor TR1 and the second transistor TR2. In addition, the second equalization circuit 132 may include an inverter circuit or a buffer circuit having the third transistor TR3 and the fourth transistor TR4.

[0051] According to an exemplary embodiment of the inventive concept, the first transistor TR1 and the third transistor TR3 may include p-type metal oxide semiconductor (PMOS) transistors, and the second transistor TR2 and the fourth transistor TR4 may include n-type metal oxide semiconductor (NMOS) transistors. However, the exemplary embodiment is not limited thereto, and each of the first transistor TR1 to the fourth transistor TR4 may include a PMOS or an NMOS transistor.

[0052] The first equalization circuit 131 may include two input terminals (I1 and I2) and a first output terminal O1. The input terminals (I1 and I2) may receive the data signal DT together. In other words, the first gate terminal G1 of the first transistor TR1 and the second gate terminal G2 of the second transistor TR2 may receive the data signal DT.

[0053] The first transistor TR1 may have a first source terminal S1 receiving a driving voltage VDD, a first drain terminal D1 connected to the first output terminal O1, and a first gate terminal G1 connected to the first input terminal I1. The second transistor TR2 may include a second drain terminal D2 connected to the output terminal O1, a second source terminal S2 connected to the first ground node GN1, and a second gate terminal G2 connected to the second input terminal I2.

[0054] The first equalization circuit 131 may selectively receive the driving voltage VDD or the ground voltage VGND according to a logic high level and a logic low level of the data signal DT. For example, in response to the generation of the logic low level of the data signal DT, a first equalization signal EQ1 may be generated. In this case, the magnitude of the logic high level of the first equalization signal EQ1 may be based on the level of the driving voltage VDD. Additionally, in response to the generation of the logic high level of the data signal DT, a first equalization signal EQ1 may be generated. In this case, the magnitude of the logic high level of the first equalization signal EQ1 may be based on the level of the driving voltage VDD. For example, the level of the driving voltage VDD may be greater than the level of the ground voltage VGND.

[0055] The first equalization signal EQ1 may be a voltage signal having a logic high level based on the driving voltage VDD and a logic low level based on the ground voltage VGND. For example, the logic high level of the first equalization signal EQ1 may be substantially the same as the level of the driving voltage VDD. As another example, the logic high level of the first equalization signal EQ1 may be the same as the logic high level of the data signal DT. As another example, the logic high level of the first equalization signal EQ1 may be the level at which a coefficient regarding the device characteristics of the first transistor TR1 is applied to the driving voltage VDD.

[0056] The logic low level of the first equalization signal EQ1 may be substantially the same as the level of the ground voltage VGND. As another example, the logic low level of the first equalization signal EQ1 may be the same as the logic low level of the data signal DT. As another example, the logic low level of the first equalization signal EQ1 may be the level adopted when a coefficient regarding the device characteristics of the second transistor TR2 is applied to the ground voltage VGND.

[0057] The second equalization circuit 132 may include two input terminals (I3 and I4) and a second output terminal O2. The input terminals (I3 and I4) may receive a negative pulse signal PSA and a positive pulse signal PSB, respectively. In other words, the third gate terminal G3 of the third transistor TR3 and the fourth gate terminal G4 of the fourth transistor TR4 may receive the negative pulse signal PSA and the positive pulse signal PSB, respectively.

[0058] According to an exemplary embodiment of the inventive concept, the third transistor TR3 may include a third source terminal S3 receiving a driving voltage VDD and a third drain terminal D3 connected to the second output terminal O2 of the second equalization circuit 132. For example, the third transistor TR3 may include a p-type transistor. The fourth transistor TR4 may include a fourth source terminal S4 connected to the second ground node GN2 and a fourth drain terminal D4 connected to the second output terminal O2 of the second equalization circuit 132.

[0059] The second equalization circuit 132 may selectively receive the driving voltage VDD or the ground voltage VGND according to the logic high level and the logic low level of the negative pulse signal PSA and the positive pulse signal PSB, and thus, may generate a second equalization signal EQ2. The equalization module 130 may add the first equalization signal EQ1 and the second equalization signal EQ2, and may output an output signal DO to the output terminal OT by using the added signal. A detailed description of the second equalization signal EQ2 and the output signal OT will be made later with reference to Figure 5 and

[0060] The output terminal OT may be connected to the first equalization circuit 131 and the second equalization circuit 132 via a wiring, and may be connected to a channel ( Figure 1 CH in

[0061] Figure 5 is a timing diagram of signals according to an exemplary embodiment of the inventive concept. Hereinafter, a description will be given with reference to the reference numerals in Figure 3 and Figure 4 in the drawings.

[0062] Refer to Figure 5, the data signal DT can be a digital signal with a logic high level and a logic low level. For example, the logic high level of the data signal DT can indicate the data value "1", and the logic low level can indicate the data value "0".

[0063] The first equalization signal EQ1 can be a voltage signal in which the data signal DT is inverted. For example, the magnitude of the first equalization signal EQ1 can be determined based on the parameters or levels of the driving voltage VDD and the ground voltage VGND according to the components included in the first equalization circuit 131. As an example, the magnitude of the logic high level of the first equalization signal EQ1 can be determined based on the level of the driving voltage VDD. As another example, the magnitude of the logic low level of the first equalization signal EQ1 can be determined based on the level of the ground voltage VGND.

[0064] The pulse signal PS can include a negative pulse signal PSA and a positive pulse signal PSB. The negative pulse signal PSA and the positive pulse signal PSB can respectively include a negative pulse NP and a positive pulse PP. The negative pulse NP can be referred to as a logic low level pulse that appears in the negative pulse signal PSA. Additionally, as shown, the pulse width of the negative pulse NP can be smaller than the pulse width of the data signal DT. Similarly, the positive pulse PP can be referred to as a logic high level pulse that appears in the positive pulse signal PSB, and the pulse width of the positive pulse PP can be smaller than the pulse width of the data signal DT. For example, the pulse width of at least one of the negative pulse NP and the positive pulse PP can be smaller than half of the pulse width of the data signal DT. In other words, compared with the data signal DT, at least one of the negative pulse NP and the positive pulse PP can have a very narrow pulse width.

[0065] The negative pulse signal PSA can be generated in response to the generation of the falling edge of the data signal DT. The positive pulse signal PSB can be generated in response to the generation of the rising edge of the data signal DT. For example, the pulse generator 122 can generate the negative pulse signal PSA and the positive pulse signal PSB from the data signal DT by using a plurality of logic gates. For example, the magnitude of the logic high level of each of the negative pulse signal PSA and the positive pulse signal PSB can be substantially the same as the magnitude of the logic high level of the data signal DT.

[0066] The second equalization signal EQ2 can be generated based on the result of inverting the pulse signal PS. For example, the second equalization circuit 132 can add the negative pulse signal PSA and the positive pulse signal PSB, invert the added signal, and generate the inverted signal as the second equalization signal EQ2.

[0067] The logic high level AP of the second equalization signal EQ2 may be generated based on the negative pulse NP. For example, the logic high level AP of the second equalization signal EQ2 may have a magnitude that reflects the device characteristics of the second equalization circuit 132 in the voltage level of the negative pulse NP. The magnitude of the logic high level AP may be less than the magnitude of the negative pulse NP. As another example, the logic low level AN of the second equalization signal EQ2 may have a magnitude that reflects the device characteristics of the second equalization circuit 132 in the voltage level of the positive pulse PP. The magnitude of the logic low level AN may be less than the magnitude of the positive pulse PP.

[0068] The output signal DO may be a signal obtained by adding the first equalization signal EQ1 and the second equalization signal EQ2. For example, the equalization module 130 may transmit the first equalization signal EQ1 output from the first equalization circuit 131 and the second equalization signal EQ2 output from the second equalization circuit 132 to the output terminal OT via the same output line.

[0069] According to an exemplary embodiment of the inventive concept, since the output signal DO increases the magnitudes of the rising edge and the falling edge of the data signal DT, distortion during the process of converting an analog signal into a digital signal does not easily occur, and thus, signal accuracy may be improved.

[0070] According to an exemplary embodiment of the inventive concept, the second equalization circuit 132 may adjust the magnitudes of the amplitudes (i.e., AP and AN) of the second equalization signal EQ2. The second equalization circuit 132 may adjust the magnitudes of the amplitudes (AP and AN) by applying a specific gain to the amplitude of the pulse signal PS. For example, the gain may be determined by the device characteristics of the transistors (TR3 and TR4) included in the second equalization circuit 132. As another example, the second equalization circuit 132 may change the gain by using various external voltages, external signals, and external currents including the driving voltage VDD and the ground voltage VGN.

[0071] Figure 6 is a timing diagram for describing a signal for correcting a data signal according to a comparative example. Figure 6 is for explaining Figure 5 the advantages of the signal processing described above with reference to

[0072] with reference to Figure 6, the input data DTC can be a digital signal, and the delayed signal PSC can be a signal obtained by delaying the input data DTC by a specific time td. The compensation signal EQC can be a signal obtained by inverting and increasing the amplitude of the delayed signal PSC. In this case, the distortion correction signal DOC can be generated by adding the input data DTC and the compensation signal EQC. The distortion correction signal DOC can be a signal that is corrected to prevent distortion of the input data DTC. In this case, when the amplitude of the compensation signal EQC is excessively increased, it may not be possible to maintain the data value indicated by the input data DTC (i.e., the original data). For example, in the time period tx and the time period ty, the input data DTC or the original data may indicate the data value "0", but the distortion correction signal DOC will incorrectly indicate the data value "1". In other words, when the amplitude of the compensation signal EQC increases beyond a specific limit, the data of the distortion correction signal DOC will be distorted.

[0073] In contrast, referring back to Figure 5 , in one or more example embodiments, the pulse signal PS and the second equalization signal EQ2 may output the pulse signal only in the time periods when the rising edge and the falling edge occur. Therefore, the output signal DO can accurately indicate the digital data value indicated by the data signal DT or the original data, and since the magnitude of the edge of the output signal DO is large, ISI can be reduced, and the eye opening performance can be improved.

[0074] Figure 7 is a circuit diagram showing source voltage termination according to an example embodiment of the inventive concept, Figure 8 is a waveform diagram showing the output voltage according to an example embodiment of the inventive concept. Hereinafter, descriptions will be given with reference to Figure 1 the reference numerals in

[0075] Referring to Figure 7 , the electronic device 1 may further include a termination resistor RT. The termination resistor RT may be connected to the output terminal OT and the equalization circuit 130a. In other words, the electronic device 1 may implement source voltage termination (Vss termination).

[0076] According to an example embodiment of the inventive concept, when the data value of the data signal DT indicates "0", the voltage level of the output signal DO may be approximately 0. In this case, the voltages applied to both ends of the termination resistor RT may be approximately 0V. Therefore, the magnitude of the constant current IS flowing through the termination resistor RT may be approximately 0, and thus, when there is no input data (i.e., when the input data is continuously approximately 0 or empty), power consumption can be prevented.

[0077] Referring to Figure 8, as described above, when the data input to the electronic device 1 is approximately 0, the source voltage termination can prevent power consumption. However, as a compromise condition, the voltage level of the output signal DOx does not drop to a negative level. As described above with reference to Figures 1 to 6 , when the output signal DO has a negative level during a specific period, the difference between the edges increases, but the output signal DOx does not have a negative level due to the source voltage termination.

[0078] Figure 9 is a circuit diagram showing a pull-down circuit according to an exemplary embodiment of the inventive concept. Hereinafter, a description will be given with reference to the reference numerals in Figure 3 .

[0079] Referring to Figure 9 , the equalization circuit 100a may further include a pull-down circuit 140. The pull-down circuit 140 may be connected to at least one of the first equalization circuit 131 and the second equalization circuit 132, and may supply a negative-level voltage to at least one of the first ground node GN1 of the first equalization circuit 131 and the second ground node GN2 of the second equalization circuit 132. As described above with reference to Figure 8 , when the source voltage termination of the termination resistor RT is included in the electronic device 1, the output signal DO does not have a negative-level voltage. Therefore, the pull-down circuit 140 can immediately generate a negative pulse of the output signal DO by applying a negative-level voltage to the equalization module 130.

[0080] The pull-down circuit 140 may include a switch circuit 141 having a plurality of switches (SW1 to SW3) and a capacitor CB. One end of the capacitor CB (for example, the node to which the voltage VC1 is applied) may be connected to the switch circuit 141, and the other end of the capacitor CB (for example, the node to which the voltage VC2 is applied) may be connected to the first ground node GN1 of the first equalization circuit 131 and the second ground node GN2 of the second equalization circuit 132.

[0081] The switch circuit 141 may receive a clock signal CLK and a complementary clock signal CLKB, and the complementary clock signal CLKB may be a signal obtained by inverting the clock signal CLK. The switches (SW1 to SW3) may perform a switching operation (for example, turn on or off) based on the logic levels of the clock signal CLK and the complementary clock signal CLKB.

[0082] The switching circuit 141 can output a driving voltage or a ground voltage according to the conduction or disconnection of a plurality of switches (SW1 to SW3). For example, when the clock signal CLK is at a logic high level, the second switch SW2 and the third switch SW3 can be short-circuited, and the switching circuit 141 can apply the driving voltage VDD to the capacitor CB. In this case, the level of the voltage VC1 at one end of the capacitor CB can be the level of the driving voltage VDD, and the level of the voltage VC2 at the other end of the capacitor CB can be the level of the ground voltage. In other words, the capacitor CB can be charged based on the driving voltage VDD. When the clock signal CLK is at a logic low level, the first switch SW1 can be short-circuited. In this case, the level of the voltage VC1 at one end of the capacitor CB can be the level of the ground voltage. Due to the law of conservation of charge of the capacitor CB, the level of the voltage at the other end of the capacitor CB can be a negative level (for example, -VDD). Therefore, the pull-down circuit 140 can output a negative-level voltage to the first ground node GN1 and the second ground node GN2.

[0083] The clock signal CLK and the complementary clock signal CLKB can be received from, for example Figure 3 the pulse generator 122, as another example, can be received from a clock generator inside the electronic device 1, and as another example, can be received from outside the electronic device 1.

[0084] Figure 10 and Figure 11 are timing diagrams of signals and voltages for describing exemplary embodiments according to the inventive concept of the present invention.

[0085] Referring to Figure 3 、 Figure 9 and Figure 10 , the pull-down circuit 140 can receive the clock signal CLK and the complementary clock signal CLKB. For example, the pulse generator 122 can output the clock signal CLK and the complementary clock signal CLKB. The pulse generator 122 can receive a positive pulse signal PSB, and generate a clock signal CLK that transitions to a logic low level in response to the positive pulse signal PSB that has transitioned to a logic high level. The pulse generator 122 can generate the complementary clock signal CLKB by inverting the clock signal CLK.

[0086] Referring to Figure 9 and Figure 11, in response to a logic high level of the complementary clock signal CLKB or a logic low level of the clock signal CLK, the voltage VC2 at the other end of the capacitor CB can drop to a negative level. When the level of the voltage VC2 drops to a negative level, the first ground node GN1 of the first equalization circuit 131 and the second ground node GN2 of the second equalization circuit 132 connected to the other end of the capacitor CB can have a negative-level voltage. In other words, when the level of the voltage VC2 drops to a negative level, the second equalization signal EQ2 can have a negative level. Therefore, when the clock signal CLK transitions to a logic low level, the output signal DO output by the first equalization circuit 131 and the second equalization circuit 132 can have a negative level. As the difference AX between the edges of the output signal DO increases, the ISI of the electronic device 1 can be reduced, and thus, the eye opening performance can be improved.

[0087] Figure 12 is a flowchart of an operation method of the electronic device 1 according to an exemplary embodiment of the inventive concept. Hereinafter, descriptions will be given using reference numerals with reference to the above drawings.

[0088] In operation S310, the electronic device 1 according to an exemplary embodiment of the inventive concept can receive a data signal DT.

[0089] In operation S320, the first equalization circuit 131 can output a first equalization signal EQ1 having a phase that is inverted from the phase of the data signal DT.

[0090] In operation S330, the pulse generator 122 can generate a negative pulse signal PSA based on the falling edge of the data signal DT and generate a positive pulse signal PSB based on the rising edge of the data signal DT.

[0091] In operation S340, the pulse generator 122 can output a pulse signal PS including the negative pulse signal PSA and the positive pulse signal PSB.

[0092] In operation S350, the second equalization circuit 132 can invert the pulse signal PS and output a second equalization signal EQ2 based on the inverted pulse signal.

[0093] Therefore, in operation S360, the equalization module 130 can output an output signal DO in which the first equalization signal EQ1 and the second equalization signal EQ2 have been added.

[0094] Figure 13 is a flowchart of an operation method of the electronic device 1 according to an exemplary embodiment of the inventive concept. Hereinafter, descriptions will be given using reference numerals with reference to the above drawings.

[0095] Refer to Figure 13, in operation S331, the pulse generator 122 according to an exemplary embodiment of the inventive concept may change the negative pulse signal PSA to a logic low level in response to the generation of the falling edge of the data signal DT.

[0096] In addition, in operation S332, the pulse generator 122 may restore the negative pulse signal PSA to a logic high level before the rising edge of the data signal DT is generated. In response to the generation of the rising edge of the data signal DT, in operation S333, the electronic device 1 may change the positive pulse signal PSB to a logic high level. In addition, in operation S334, the positive pulse signal PSB may be returned to a logic low level before the falling edge of the data signal DT is generated.

[0097] Figure 14 is a flowchart of an operation method of the electronic device 1 according to an exemplary embodiment of the inventive concept. Hereinafter, descriptions will be given using reference numerals with reference to the above drawings.

[0098] Referring to Figure 14 , in operation S410, the pull - down circuit 140 may receive the clock signal CLK. In addition, the complementary clock signal CLKB obtained by inverting the clock signal CLK may be received. Based on the clock signal CLK and the complementary clock signal CLKB, a driving voltage VDD or a ground voltage may be applied to the capacitor CB.

[0099] In operation S420, the pull - down circuit 140 may generate a negative - level voltage in response to a change in the logic level of the clock signal CLK.

[0100] After that, in operation S430, the pull - down circuit 140 may output the negative - level voltage to at least one of the first ground node GN1 of the first equalization circuit 131 that outputs the first equalization signal EQ1 and the second ground node of the second equalization circuit 132 that outputs the second equalization signal EQ2.

[0101] In operation S440, when the logic level of the clock signal CLK changes, the pull - down circuit 140 may lower the voltage level of the output signal DO.

[0102] Figure 15 is a flowchart of an operation method of the electronic device 1 according to an exemplary embodiment of the inventive concept. Hereinafter, descriptions will be given using reference numerals with reference to the above drawings.

[0103] Referring to Figure 15 , in operation S431, when the clock signal CLK is at a logic high level, the pull - down circuit 140 according to an exemplary embodiment of the inventive concept may control a plurality of switches (SW1 to SW3) and output the driving voltage VDD to one end of the capacitor CB.

[0104] In operation S432, the pull-down circuit 140 may charge the capacitor CB by using the drive voltage VDD.

[0105] Thereafter, in operation S433, when the clock signal CLKB transitions to a logic low level, the pull-down circuit 140 may control a plurality of switches (SW1 to SW3) and output a ground voltage to one end of the capacitor CB.

[0106] In this case, since the voltage at one end of the capacitor CB transitions from the drive voltage to the ground voltage and the capacitor CB needs to store the charge amount, the voltage at the other end of the capacitor CB may drop from the ground voltage to a negative level voltage. In other words, in operation S434, in response to the voltage VC1 at one end of the capacitor CB dropping to the ground voltage level, the pull-down circuit 140 may output a negative level voltage via the other end of the capacitor CB.

[0107] The first chip 10, the second chip 20, and their sub-assemblies including one or more elements of the equalization circuits 100, 100a may include a processing circuit, which includes but is not limited to a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. The processing circuit may be a dedicated processing circuit that configures the equalization circuit 100 to generate a pulse signal PS and output a second equalization signal EQ2 including the pulse signal only during periods when the rising edge and the falling edge of the data signal DT occur, and generates an output signal DO based on the second equalization signal EQ2. Accordingly, the output signal DO may accurately indicate the digital data value indicated by the data signal DT or the original data, and because the magnitude of the edges of the output signal DO is large, the dedicated processing circuit may improve the performance of the electronic device 1 by reducing ISI and improving the eye opening performance.

[0108] Although the inventive concept has been shown and described with reference to some exemplary embodiments of the inventive concept, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. An electronic device, the electronic device comprising: A first equalization circuit configured to receive a data signal and generate a first equalization signal based on the data signal; A pulse generator configured to generate a first pulse signal and a second pulse signal in response to a rising edge and a falling edge of the data signal, respectively; A second equalization circuit configured to output a second equalization signal based on an inverted first pulse signal and an inverted second pulse signal, the inverted first pulse signal and the inverted second pulse signal being an inversion of the first pulse signal and an inversion of the second pulse signal, respectively; And An output terminal configured to output an output signal based on the first equalization signal and the second equalization signal, wherein the pulse generator is further configured to output the first pulse signal to the second equalization circuit in response to the rising edge of the data signal and output the second pulse signal to the second equalization circuit in response to the falling edge of the data signal, wherein the first pulse signal includes a positive pulse signal, the second pulse signal includes a negative pulse signal, and a pulse width of the first pulse signal and a pulse width of the second pulse signal are both less than a pulse width of the data signal, and wherein the second equalization circuit is further configured to add the inverted first pulse signal and the inverted second pulse signal and output the added signal as the second equalization signal.

2. The electronic device according to claim 1, wherein, The second equalization circuit further includes: A first transistor, a gate terminal of the first transistor being configured to receive the second pulse signal; and A second transistor, a gate terminal of the second transistor being configured to receive the first pulse signal.

3. The electronic device according to claim 1, wherein, The output terminal is configured to electrically connect the first equalization circuit and the second equalization circuit to an external device via a channel.

4. The electronic device according to claim 1, the electronic device further comprising: A pull-down circuit connected to at least one of the first equalization circuit and the second equalization circuit, the pull-down circuit being configured to reduce a voltage level of the output signal by providing a first voltage to a ground node of at least one of the first equalization circuit and the second equalization circuit.

5. The electronic device according to claim 4, wherein, The pull-down circuit is further configured to: Receive a clock signal, and Reduce the voltage level of the output signal to a negative level when the clock signal remains at a logic low level.

6. The electronic device according to claim 5, wherein, The pulse generator is further configured to cause the clock signal to transition to the logic low level in response to the first pulse signal transitioning to a logic high level.

7. The electronic device according to claim 4, wherein, The pull-down circuit includes: A switching circuit; and A capacitor, the capacitor including a first end and a second end, the first end being connected to the switching circuit, and the second end being connected to a ground node of at least one of the first equalization circuit and the second equalization circuit, wherein, The switching circuit is configured to regulate a voltage applied to the capacitor.

8. The electronic device according to claim 7, wherein, The switching circuit includes: Multiple switches, the multiple switches being configured to switch between an output drive voltage and an output ground voltage based on a clock signal, such that: When the clock signal is at a logic high level, the switch circuit applies the drive voltage to the first end of the capacitor, and When the clock signal transitions from the logic high level to a logic low level, the switch circuit reduces the voltage of the ground node of at least one of the first equalization circuit and the second equalization circuit to a negative level by applying the ground voltage to the first end of the capacitor.

9. The electronic device according to claim 8, wherein, The pull-down circuit is further configured to determine the voltage of the ground node of at least one of the first equalization circuit and the second equalization circuit based on the voltage at the first end of the capacitor.

10. An electronic device, the electronic device comprising: A first equalization circuit configured to receive a data signal and generate a first equalization signal having a phase opposite to the phase of the data signal; A pulse generator configured to: Generate a negative pulse signal based on a falling edge of the data signal, Generate a positive pulse signal based on a rising edge of the data signal, and Generate a pulse signal such that the pulse signal includes the negative pulse signal and the positive pulse signal; A second equalization circuit configured to output a second equalization signal based on an inverted pulse signal, the inverted pulse signal being an inversion of the pulse signal; And An output terminal configured to output an output signal based on the first equalization signal and the second equalization signal, Wherein the pulse generator is further configured to generate the negative pulse signal and the positive pulse signal such that the pulse width of the negative pulse signal and the pulse width of the positive pulse signal are both less than the pulse width of the data signal, and Wherein the second equalization circuit is further configured to add the inverted positive pulse signal and the inverted negative pulse signal and output the added signal as the second equalization signal.

11. The electronic device according to claim 10, wherein, The pulse generator is further configured to generate the negative pulse signal such that the negative pulse signal transitions to a logic low level in response to the generation of the falling edge of the data signal and returns to a logic high level before the rising edge of the data signal is generated.

12. The electronic device according to claim 10, wherein, The pulse generator is further configured to generate the positive pulse signal such that the positive pulse signal transitions to a logic high level in response to the generation of the rising edge of the data signal and returns to a logic low level before the falling edge of the data signal is generated.

13. The electronic device according to claim 10, wherein, The second equalization circuit includes: An inverter circuit including a first transistor and a second transistor, a gate terminal of the first transistor being configured to receive the negative pulse signal, and a gate terminal of the second transistor being configured to receive the positive pulse signal.

14. A method of operating an electronic device, the method comprising: Receiving a data signal; Generating a first equalization signal having a phase opposite to the phase of the data signal; Generate a negative pulse signal based on the falling edge of the data signal; Generate a positive pulse signal based on the rising edge of the data signal; Generate a pulse signal such that the pulse signal includes the negative pulse signal and the positive pulse signal, wherein the pulse width of the positive pulse signal and the pulse width of the negative pulse signal are both less than the pulse width of the data signal; Output a second equalization signal based on the inverted pulse signal, where the inverted pulse signal is the inversion of the pulse signal; and Output an output signal obtained based on the first equalization signal and the second equalization signal, where outputting the second equalization signal based on the inverted pulse signal includes: adding the inverted positive pulse signal and the inverted negative pulse signal, and outputting the added signal as the second equalization signal.

15. The method according to claim 14, the method further comprising: In response to the generation of the falling edge of the data signal, causing the negative pulse signal to transition to a logic low level; and Before generating the rising edge of the data signal, causing the negative pulse signal to return to a logic high level.

16. The method according to claim 14, the method further comprising: In response to the generation of the rising edge of the data signal, causing the positive pulse signal to transition to a logic high level; and Before generating the falling edge of the data signal, causing the positive pulse signal to return to a logic low level.

17. The method according to claim 14, wherein The first equalization signal is output by a first equalization circuit, and the second equalization signal is output by a second equalization circuit, the method further comprising: When the logic level of the clock signal changes, reducing the voltage level of the output signal by the following operations: Receiving the clock signal; In response to the change in the logic level of the clock signal, generating a negative-level voltage; and Outputting the negative-level voltage to the ground node of at least one of the first equalization circuit and the second equalization circuit.

18. The method according to claim 17, wherein, Outputting the negative-level voltage includes: When the clock signal is at a logic high level, outputting a drive voltage; Charging a capacitor with the drive voltage, the capacitor having a first terminal and a second terminal; When the clock signal transitions to a logic low level, outputting a ground voltage; and In response to the voltage at the first terminal of the capacitor dropping to the level of the ground voltage, outputting the negative-level voltage from the capacitor via the second terminal of the capacitor.

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