LED Driver Test Circuit

Abstract

An embodiment of the present invention discloses an LED driver test circuit, comprising: a driver module, a test pin, and a switch module, wherein the driver module is connected to the switch module, and the test pin is connected to the switch module; the driver module is configured to receive a test drive signal; the test pin is configured to connect to an LED chip under test; and the switch module is configured to drive the LED chip under test using the test drive signal in response to a control signal. This embodiment of the present invention enables testing of the driver chip before it is packaged with a Micro-LED chip array, reducing testing costs.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to an LED drive test circuit. Background Art

[0002] Micro-LEDs (Micro Light-Emitting Diodes, Micro-LEDs) have self-luminous display characteristics. They are all-solid-state light-emitting diodes with long life, high brightness, low power consumption, small size, and ultra-high resolution. They can be used in extreme environments such as high temperature or radiation. More and more manufacturers have planned them as the next generation of display technology.

[0003] Micro-LED display devices usually use a driver chip to drive the Micro-LED chip array to emit light. That is, after the driver chip is powered on, it sends a driving signal to the Micro-LED chip array to drive the Micro-LED chip to emit light as required. However, the quality of the driver chip varies. Currently, after the Micro-LED chip array and the driver chip are packaged, the packaged device is usually tested as a whole to detect the quality of the driver chip. When there is a quality problem with the driver chip and the driving function cannot be realized, the driver chip needs to be extracted from the packaged device again to investigate whether it is a problem with the circuit design or the semiconductor manufacturing. This detection method makes the detection cost higher and is prone to waste of resources. Summary of the Invention

[0004] In view of this, an embodiment of the present invention provides an LED driver test circuit to detect the driver chip before it is packaged with the Micro-LED chip array, thereby reducing the detection cost.

[0005] An embodiment of the present invention provides an LED drive test circuit, comprising: a drive module, a test pin, and a switch module, wherein the drive module is connected to the switch module, and the test pin is connected to the switch module;

[0006] The driving module is used to receive a test driving signal;

[0007] The test pin is used to connect to the LED chip to be tested;

[0008] The switch module is used to enable the test drive signal to drive the LED chip to be tested according to a control signal.

[0009] Furthermore, the switch module includes a first interface, a second interface and a third interface, the first interface is used to receive a control signal, the second interface is connected to the driving module, and the third interface is connected to the test pin.

[0010] Furthermore, the switch module is an NMOS tube, the first interface is the gate of the NMOS tube, the second interface is the drain of the NMOS tube, and the third interface is the source of the NMOS tube.

[0011] Optionally, the switch module is a transistor, the first interface is the base of the transistor, the second interface is the collector of the transistor, and the third interface is the emitter of the transistor.

[0012] Furthermore, the driving module includes a signal receiving circuit, a signal holding circuit and a regulating circuit, the signal receiving circuit is connected to the signal holding circuit, the signal holding circuit is connected to the regulating circuit, and the regulating circuit is connected to the switch module.

[0013] Furthermore, the signal receiving circuit includes a first NMOS tube and a second NMOS tube, the gate of the first NMOS tube and the gate of the second NMOS tube are connected and used to receive a first test drive signal, the drain of the first NMOS tube is used to receive a second test drive signal, and the drain of the second NMOS tube is used to receive a third test drive signal.

[0014] Furthermore, the first test drive signal is a row test drive signal, the second test drive signal is a first column test drive signal, the third test drive signal is a second column test drive signal, and the first column test drive signal and the second column test drive signal are opposite signals to each other.

[0015] Furthermore, the signal holding circuit includes a first PMOS transistor, a second PMOS transistor, a third NMOS transistor and a fourth NMOS transistor;

[0016] The gate of the first PMOS transistor, the gate of the third NMOS transistor, the drain of the second PMOS transistor and the drain of the fourth NMOS transistor are connected;

[0017] The gate of the second PMOS transistor, the gate of the fourth NMOS transistor, the drain of the first PMOS transistor and the drain of the third NMOS transistor are connected;

[0018] The gate of the third NMOS transistor is connected to the source of the first NMOS transistor, and the gate of the fourth NMOS transistor is connected to the source of the second NMOS transistor;

[0019] The drain of the first PMOS transistor is connected to the drain of the third NMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the fourth NMOS transistor;

[0020] The source of the first PMOS tube and the source of the second PMOS tube are both connected to the positive electrode of the working power supply;

[0021] The source of the third NMOS tube and the source of the fourth NMOS tube are both connected to the negative electrode of the working power supply.

[0022] Furthermore, the regulation circuit includes a third PMOS tube and a fourth PMOS tube, the gate of the third PMOS tube is used to receive the regulation signal, the source of the third PMOS tube is connected to the positive electrode of the working power supply, the drain of the third PMOS tube is connected to the source of the fourth PMOS tube, the gate of the fourth PMOS tube is connected to the gate of the third NMOS tube, and the drain of the fourth PMOS tube is connected to the switch module.

[0023] Furthermore, the test drive signal and the control signal are both generated by an FPGA circuit.

[0024] The LED driver test circuit provided in the embodiment of the present invention uses a driver module, a test pin, and a switch module, and the detection operation is simple and easy to implement. It realizes the detection of the driver chip before the driver chip and the Micro-LED chip array are packaged, thereby reducing the detection cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of a flow chart of an LED drive test circuit provided in the first embodiment of the present invention;

[0026] Figure 2 This is a flow chart of an LED drive test circuit provided in the second embodiment of the present invention. DETAILED DESCRIPTION

[0027] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0028] Before discussing the exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or procedures depicted as flowcharts. Although the flowcharts depict the steps as sequential processes, many of the steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operations are completed, but can also have additional steps not included in the accompanying figures. A process can correspond to a function, procedure, subroutine, subprogram, etc.

[0029] In addition, the terms "first", "second", etc. may be used in this article to describe various directions, actions, steps or elements, but these directions, actions, steps or elements are not limited by these terms. These terms are only used to distinguish a first direction, action, step or element from another direction, action, step or element. The terms "first", "second", etc. should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" or "batch" is at least two, for example, two, three, etc., unless otherwise clearly and specifically defined.

[0030] Example 1

[0031] Figure 1 This is a flow chart of an LED driving test circuit provided in the first embodiment of the present invention. This embodiment is applicable to the field of Micro-LED technology.

[0032] like Figure 1 As shown, the LED driver test circuit provided in the first embodiment of the present invention includes: a driver module 100, a test pin 300, and a switch module 200. The driver module 100 is connected to the switch module 200, and the test pin 300 is connected to the switch module 200. The driver module 100 is the driver circuit of the LED chip. When testing, the driver module 100 is used to receive a test drive signal, which refers to the drive signal for the LED chip under test during the test process. The test pin 300 is used to connect to the LED chip under test (i.e., the Micro-LED chip under test). The switch module 200 is used to drive the LED chip under test with the test drive signal according to a control signal. The control signal is a signal used to control whether the switch module 200 is turned on or off.

[0033] During testing, a pre-set test drive signal is input to the driver module 100, and a control signal is input to the switch module 200 to control the switch module 200 to open. The test drive signal received by the driver module 100 is then transmitted to the LED chip under test via the switch module 200. If the LED chip under test can be driven to emit light, the LED driver circuit performs well. If the LED chip under test fails to emit light, the LED driver circuit has a problem and cannot be used in practice.

[0034] Optionally, the test pin 300 can be connected to the LED chip to be tested and the oscilloscope at the same time. By observing the electrical signal output by the test pin 300 through the oscilloscope, it can also be determined whether the performance of the LED driving circuit is normal. For example, the test driving signal input by the driving module 100 is to scan and light up an LED chip to be tested every two frames. The LED chip to be tested is off in a single frame, and the LED chip to be tested is lit in a double frame. Then the graph displayed by the oscilloscope should be a square wave with a certain amplitude. When there is an abnormality in the oscilloscope graph, it can be determined that the performance of the LED driving circuit is abnormal. According to the degree of abnormality of the oscilloscope image, the problem of the LED driving circuit can be reflected. Compared with determining whether the performance of the LED driving circuit is abnormal only by the on and off of the LED chip to be tested, the problem of the LED driving circuit can be reflected more comprehensively and meticulously through the oscilloscope.

[0035] In this embodiment, the driver module 100 is a driver circuit for an LED chip, serving as a driver unit within the LED driver chip. The switch module 200 and test pin 300 can be integrated within the LED driver chip and soldered to the driver module 100. Alternatively, they can be independent modules from the LED driver chip, with a detachable connection to the driver module 100.

[0036] Furthermore, the switch module 200 includes a first interface, a second interface, and a third interface. The first interface is used to receive control signals, the second interface is connected to the driver module 100, and the third interface is connected to the test pin 300. When the first interface receives a control signal to control the switch module 200 to turn on, the second interface and the third interface are connected, connecting the driver module 100 to the test pin 300, so that the test drive signal received by the driver module 100 reaches the LED chip under test connected to the test pin 300.

[0037] Furthermore, the driver module 100 includes a signal receiving circuit 110, a signal holding circuit 120, and an adjustment circuit 130. The signal receiving circuit 110 is connected to the signal holding circuit 120, which is in turn connected to the adjustment circuit 130. The adjustment circuit 130 is connected to the switch module 200. A test drive signal is received by the signal receiving circuit 110. The signal holding circuit 120 transmits the test drive signal to the adjustment circuit 130 and can hold the test drive signal for a period of time. The adjustment circuit 130 can receive an adjustment signal used to adjust the brightness of the LED chip. The adjustment circuit 130 transmits both the test drive signal and the adjustment signal to the switch module 200.

[0038] The LED driver test circuit provided in the first embodiment of the present invention uses a driver module, a test pin, and a switch module, and the detection operation is simple and easy to implement. It realizes the detection of the driver chip before the driver chip and the Micro-LED chip array are packaged, thereby reducing the detection cost.

[0039] Example 2

[0040] Figure 2 This is a flow chart of a LED drive test circuit provided by the second embodiment of the present invention. This embodiment is a further refinement of the above embodiment. Figure 2 As shown, the LED driving test circuit provided by the second embodiment of the present invention includes: a driving module 100 , a test pin 300 and a switch module 200 .

[0041] The driver module 100 includes a signal receiving circuit, a signal holding circuit, and a regulation circuit. The signal receiving circuit includes a first NMOS transistor (NMOS1) and a second NMOS transistor (NMOS2). The gate of the first NMOS transistor (NMOS1) and the gate of the second NMOS transistor (NMOS2) are connected and configured to receive a first test drive signal. The drain of the first NMOS transistor (NMOS1) is configured to receive a second test drive signal, and the drain of the second NMOS transistor (NMOS2) is configured to receive a third test drive signal.

[0042] The signal holding circuit includes a first PMOS transistor PMOS1, a second PMOS transistor PMOS2, a third NMOS transistor NMOS3 and a fourth NMOS transistor NMOS4; the gate of the first PMOS transistor PMOS1, the gate of the third NMOS transistor NMOS3, the drain of the second PMOS transistor PMOS2 and the drain of the fourth NMOS transistor NMOS4 are connected; the gate of the second PMOS transistor PMOS2, the gate of the fourth NMOS transistor NMOS4, the drain of the first PMOS transistor PMOS1 and the drain of the third NMOS transistor NMOS3 are connected; the gate of the third NMOS transistor NMOS3 The gate is connected to the source of the first NMOS transistor NMOS1, and the gate of the fourth NMOS transistor NMOS4 is connected to the source of the second NMOS transistor NMOS2; the drain of the first PMOS transistor PMOS1 is connected to the drain of the third NMOS transistor NMOS3, and the drain of the second PMOS transistor PMOS2 is connected to the drain of the fourth NMOS transistor NMOS4; the source of the first PMOS transistor PMOS1 and the source of the second PMOS transistor PMOS2 are both connected to the positive working power supply VDD; the source of the third NMOS transistor NMOS3 and the source of the fourth NMOS transistor NMOS4 are both connected to the negative working power supply VSS.

[0043] The regulation circuit includes a third PMOS transistor PMOS3 and a fourth PMOS transistor PMOS4. The gate of the third PMOS transistor PMOS3 is used to receive the regulation signal Iref. The source of the third PMOS transistor PMOS3 is connected to the positive electrode of the working power supply. The drain of the third PMOS transistor PMOS3 is connected to the source of the fourth PMOS transistor PMOS4. The gate of the fourth PMOS transistor PMOS4 is connected to the gate of the third NMOS transistor NMOS3. The drain of the fourth PMOS transistor PMOS4 is connected to the switch module 200.

[0044] The switch module 200 is a fifth NMOS transistor NMOS5 , a gate of which receives a control signal globle, a drain of which is connected to the drain of the fourth PMOS transistor PMOS4 of the driving module 100 , and a source of which is connected to the test pin 300 .

[0045] In this embodiment, the first test drive signal is a row test drive signal Row, the second test drive signal is a first column test drive signal Data, and the third test drive signal is a second column test drive signal Data_n. The first column test drive signal Data and the second column test drive signal Data_n are connected to the input and output of an inverter, respectively, and are mutually inverse signals.

[0046] The row test drive signal Row controls the row where the LED chip to be tested is located, and the first column test drive signal Data and the second column test drive signal Data_n control the column where the LED chip to be tested is located. The row test drive signal Row, the first column test drive signal Data, and the second column test drive signal Data_n can determine the corresponding LED chip to be tested.

[0047] When the row test drive signal Row is 1, the drain and source electrodes of the first NMOS transistor NMOS1 and the drain and source electrodes of the second NMOS transistor NMOS2 are both conductive, allowing the first column test drive signal Data and the second column test drive signal Data_n to reach the signal holding circuit composed of the first PMOS transistor PMOS1, the second PMOS transistor PMOS2, the third NMOS transistor NMOS3, and the fourth NMOS transistor NMOS4. When the second column test drive signal Data_n is 0, the drain and source electrodes of the fourth PMOS transistor PMOS4 are conductive. The adjustment signal Iref causes the drain and source electrodes of the third NMOS transistor NMOS3 to be conductive. Simultaneously, the control signal Globle is set to 1, causing the drain and source electrodes of the fifth NMOS transistor NMOS5 to be conductive, connecting the driver module 100 to the test pin 300. The row test drive signal Row, the first column test drive signal Data, the second column test drive signal Data_n, and the adjustment signal Iref jointly drive the corresponding LED chip under test. Based on the light emission of the LED chip under test, it can be determined whether the performance of the LED driver circuit (i.e., the driver module 100) is abnormal.

[0048] In this embodiment, the row test drive signal Row, the first column test drive signal Data, the second column test drive signal Data_n, the adjustment signal Iref, and the control signal globle can all be generated by the FPGA circuit. Optionally, the control signal globle can be generated independently of other signals, which can more conveniently control the turning on and off of the test function.

[0049] In this embodiment, the test pin 300 is connected to a single LED chip under test. Alternatively, to save time, the Micro-LED chip matrix can be divided into multiple regions, each with an independent test pin 300. An FPGA circuit controls the simultaneous scanning of each region.

[0050] In an alternative embodiment, the switch module 200 may also be a transistor, the base of the transistor receives a control signal, the collector is connected to the drain of the fourth PMOS transistor PMOS4 of the driving module 100 , and the emitter is connected to the test pin 300 .

[0051] The LED driver test circuit provided in the second embodiment of the present invention uses a driver module, a test pin, and a switch module, and the detection operation is simple and easy to implement. It realizes the detection of the driver chip before the driver chip and the Micro-LED chip array are packaged, thereby reducing the detection cost.

[0052] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. An LED driver test circuit for testing a driver chip before packaging the driver chip with a Micro-LED chip array, characterized in that: include: An FPGA circuit, a driver module, a test pin, and a switch module. The driver module is a driver circuit in the LED driver chip to be tested and is connected to the switch module. The test pin is connected to the switch module. The test pin and the switch module are independent of the driver chip and are detachably connected to the driver module. The FPGA circuit generates a test drive signal and a control signal; The driving module is used to receive the test driving signal; The test pin is used to connect to the LED chip to be tested; The switch module is used to enable the test drive signal to drive the LED chip to be tested according to the control signal.

2. The LED drive test circuit according to claim 1, wherein: The switch module includes a first interface, a second interface and a third interface. The first interface is used to receive a control signal. The second interface is connected to the driving module. The third interface is connected to the test pin.

3. The LED drive test circuit according to claim 2, wherein: The switch module is an NMOS tube, the first interface is the gate of the NMOS tube, the second interface is the drain of the NMOS tube, and the third interface is the source of the NMOS tube.

4. The LED drive test circuit according to claim 2, wherein: The switch module is a transistor, the first interface is the base of the transistor, the second interface is the collector of the transistor, and the third interface is the emitter of the transistor.

5. The LED drive test circuit according to claim 1, wherein: The driving module includes a signal receiving circuit, a signal holding circuit and a regulating circuit. The signal receiving circuit is connected to the signal holding circuit, the signal holding circuit is connected to the regulating circuit, and the regulating circuit is connected to the switch module.

6. The LED drive test circuit according to claim 5, wherein: The signal receiving circuit includes a first NMOS transistor and a second NMOS transistor, the gate of the first NMOS transistor and the gate of the second NMOS transistor are connected and used to receive a first test drive signal, the drain of the first NMOS transistor is used to receive a second test drive signal, and the drain of the second NMOS transistor is used to receive a third test drive signal.

7. The LED driving test circuit according to claim 6, wherein: The first test drive signal is a row test drive signal, the second test drive signal is a first column test drive signal, the third test drive signal is a second column test drive signal, and the first column test drive signal and the second column test drive signal are opposite signals to each other.

8. The LED driving test circuit according to claim 6, wherein: The signal holding circuit includes a first PMOS transistor, a second PMOS transistor, a third NMOS transistor and a fourth NMOS transistor; The gate of the first PMOS transistor, the gate of the third NMOS transistor, the drain of the second PMOS transistor and the drain of the fourth NMOS transistor are connected; The gate of the second PMOS transistor, the gate of the fourth NMOS transistor, the drain of the first PMOS transistor and the drain of the third NMOS transistor are connected; The gate of the third NMOS transistor is connected to the source of the first NMOS transistor, and the gate of the fourth NMOS transistor is connected to the source of the second NMOS transistor; The drain of the first PMOS transistor is connected to the drain of the third NMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the fourth NMOS transistor; The source of the first PMOS tube and the source of the second PMOS tube are both connected to the positive electrode of the working power supply; The source of the third NMOS tube and the source of the fourth NMOS tube are both connected to the negative electrode of the working power supply.

9. The LED driving test circuit according to claim 8, wherein: The regulation circuit includes a third PMOS tube and a fourth PMOS tube, the gate of the third PMOS tube is used to receive a regulation signal, the source of the third PMOS tube is connected to the positive electrode of the working power supply, the drain of the third PMOS tube is connected to the source of the fourth PMOS tube, the gate of the fourth PMOS tube is connected to the gate of the third NMOS tube, and the drain of the fourth PMOS tube is connected to the switch module.

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