Method for forming interconnection layer and contact hole layer in semiconductor device
By increasing the compressive stress of the silicon oxide film and enhancing the bond between the tungsten and the sidewall silicon oxide dielectric layer, the problem of cobalt loss in semiconductor devices is solved, ensuring the retention rate of cobalt metal and the stability of the interconnection layer.
Patent Information
- Application Number
- CN202011477797.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-12-15
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2040-12-15
AI Technical Summary
In semiconductor devices with nodes of 7 nm and below, the bonding of the through-hole layer and the silicon oxide/silicon nitride dielectric layer on the sidewall is poor, resulting in corrosion of cobalt metal during chemical mechanical grinding, causing cobalt loss.
By increasing the compressive stress of the silicon oxide film, plasma bias bombardment or water vapor annealing process is adopted to enhance the bonding density of the tungsten and the sidewall silicon oxide dielectric layer to prevent corrosion of cobalt metal.
It effectively prevents tungsten from corrosion on the lower cobalt during chemical mechanical grinding, improves the cobalt retention rate, and meets the lower cobalt metal requirements.
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Figure CN112599473B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor integrated circuit process technology, and in particular to a method for forming an interconnection layer and a contact hole layer in a semiconductor device, which is used to solve the cobalt deficiency of the interconnection line layer in the manufacturing process of 7nm and below nodes. Background Art
[0002] As the size of semiconductor devices shrinks, the CD of contact holes or contact grooves shrinks, and the sheet resistance (RS) increases accordingly. The contribution of the bonding layer (Ti / TiN) to RS becomes more and more obvious. At present, many international research institutions have carried out research on the selective tungsten deposition process (selective W deposition) technology without a bonding layer, especially in the filling of the via layer Via 0 (V0) at 10nm and below technology nodes, and have achieved certain results. Since 7nm has begun to have higher requirements for the RS of the contact groove in the interconnect layer (M0), it is usually necessary to use cobalt metal with lower RS to replace the traditional tungsten metal.
[0003] In the prior art method for forming interconnection layers and contact hole layers in semiconductor devices, the through-hole layer adopts a selective metal tungsten deposition process without a bonding layer. However, it is clear to those skilled in the art that if the through-hole layer adopts a selective metal tungsten deposition process without a bonding layer, the through-hole layer and the silicon oxide / silicon nitride dielectric layer on the sidewall are not well bonded, which will cause the tungsten in the subsequent through-hole layer to be corroded by the CMP polishing liquid in the chemical mechanical polishing (W CMP) manufacturing process through this interface, resulting in a cobalt deficiency problem. Summary of the invention
[0004] The object of the present invention is to provide a method for forming an interconnect layer and a contact hole layer in a semiconductor device, which is used to solve the cobalt deficiency of nodes of 7nm and below, and enhances the adhesion between tungsten and the silicon oxide dielectric layer of the side wall by increasing the compressive stress of the silicon oxide film.
[0005] To achieve the above object, the technical solution of the present invention is as follows:
[0006] A method for forming an interconnection layer and a contact hole layer in a semiconductor device, comprising the following steps:
[0007] Step S1: providing a substrate including an interconnect layer structure, and forming a dielectric layer on the substrate, wherein the interconnect material in the interconnect layer structure includes metal cobalt, and the dielectric layer includes at least a silicon oxide layer located on the surface;
[0008] Step S2: performing a standard photolithography and etching process on the dielectric layer to form a patterned through-hole layer; wherein the through-holes in the through-hole layer penetrate the dielectric layer;
[0009] Step S3: depositing tungsten on the via layer by a selective tungsten deposition process to form a via tungsten plug in the via layer; wherein at least one of the via tungsten plugs is in contact with the interconnect layer structure;
[0010] Step S4: performing a compressive stress process on the surface of the through-hole layer to increase the compressive stress between the dielectric in the dielectric layer and the sidewall of the through-hole tungsten plug;
[0011] Step S5: depositing a TiN adhesion layer and a metal tungsten layer in sequence to form a through-hole tungsten plug covering layer on the through-hole layer;
[0012] Step S6: performing a tungsten chemical mechanical planarization process on the through-hole tungsten plug capping layer to form a planarized through-hole layer.
[0013] Preferably, the dielectric layer includes a contact hole etching stop layer and a silicon oxide layer from bottom to top, and the compressive stress process in step S4 is a plasma bias bombardment process, specifically including:
[0014] Step S41: bombarding the silicon oxide layer on the surface of the through-hole layer with plasma bias.
[0015] Preferably, the plasma bias bombardment process is a heavy ion plasma bias bombardment process.
[0016] Preferably, the heavy ions are Ar ions.
[0017] Preferably, the material of the contact hole etch stop layer is silicon nitride or nitrogen-doped silicon carbide.
[0018] Preferably, the silicon oxide layer is a FCVD (flow chemical vapor deposition) silicon oxide layer, and the step S4 further comprises:
[0019] Step S42: performing a water vapor annealing process on the FCVD silicon oxide layer to further increase the compressive stress between the dielectric in the dielectric layer and the sidewall of the through-hole tungsten plug.
[0020] Preferably, the dielectric layer includes a contact hole etching stop layer and a silicon oxide layer from bottom to top, and the compressive stress process in step S4 is a water vapor annealing process for the FCVD silicon oxide layer.
[0021] Preferably, the interconnection line layer structure is an interconnection line layer structure M0; and the through hole layer is a through hole layer V0.
[0022] It can be seen from the above technical scheme that the present invention provides a method for forming an interconnection layer and a contact hole layer in a semiconductor device. The technical scheme is to process the silicon oxide film on the side wall, such as using the characteristics of the expansion of the flowable chemical vapor deposition (Flowable CVD FCVD) silicon oxide film after steam annealing or the stronger compressive stress of the ordinary silicon oxide film after heavy ion (such as Ar) plasma bias bombardment to produce compression on the metal tungsten, thereby enhancing the tightness of the bonding between the metal tungsten and the silicon oxide dielectric layer on the side wall, so as to prevent the subsequent tungsten CMP polishing liquid in the through-hole layer from corroding the cobalt metal in the lower layer (metal interconnection layer M0) through this interface, thereby solving the cobalt missing problem. And from the perspective of process integration, it is not complicated. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 The flowchart of the method for forming the interconnection layer and the contact hole layer in the semiconductor device according to the embodiment of the present invention is shown.
[0024] Figure 2-Figure 7 FIG. 1 is a schematic diagram showing a process of forming an interconnection layer and a contact hole layer in a semiconductor device in a preferred embodiment of the present invention (Embodiment 1).
[0025] Figure 8-Figure 13 FIG. 1 is a schematic diagram showing a process of forming an interconnection layer and a contact hole layer in a semiconductor device in a preferred embodiment (Embodiment 3) of the present invention. DETAILED DESCRIPTION
[0026] The following is combined with Figure 1-13 , the specific implementation modes of the present invention are further described in detail.
[0027] The method for forming the interconnection layer and the contact hole layer in the semiconductor device of the present invention enhances the adhesion between tungsten and the silicon oxide dielectric layer on the side wall by increasing the compressive stress of the silicon oxide film. Specifically, the present invention generates a squeezing force on the tungsten plug of the through hole by processing the silicon oxide film in the silicon oxide layer on the side wall of the through hole tungsten plug, such as utilizing the characteristics of the expansion of the flow chemical vapor deposition (FCVD) silicon oxide film after steam annealing or the stronger compressive stress generated by the ordinary silicon oxide film after heavy ion (such as Ar) plasma bias bombardment, thereby enhancing the adhesion between tungsten and the silicon oxide dielectric layer on the side wall, and avoiding the problem of cobalt deficiency caused by the CMP polishing liquid corroding the cobalt in the lower layer (interconnection line layer) in the subsequent chemical mechanical polishing (W CMP) manufacturing process of tungsten in the through hole layer.
[0028] See also Figure 1 , Figure 1The flowchart of the method for forming the interconnection layer and the contact hole layer in the semiconductor device in the embodiment of the present invention is shown. In the embodiment of the present invention, the method for forming the interconnection layer and the contact hole layer in the semiconductor device specifically includes the following steps:
[0029] Step S1: providing a substrate including an interconnect layer structure, and forming a dielectric layer on the substrate, wherein the interconnect material in the interconnect layer structure includes metal cobalt, and the dielectric layer includes at least a silicon oxide layer located on the surface;
[0030] Step S2: performing a standard photolithography and etching process on the dielectric layer to form a patterned through-hole layer; wherein the through-holes in the through-hole layer penetrate the dielectric layer;
[0031] Step S3: depositing tungsten on the via layer by a selective tungsten deposition process to form a via tungsten plug in the via layer; wherein the via tungsten plug is in contact with the interconnect layer structure;
[0032] Step S4: performing a compressive stress process on the surface of the through-hole layer to increase the compressive stress between the dielectric in the dielectric layer and the sidewall of the through-hole tungsten plug;
[0033] Step S5: depositing a TiN adhesion layer and a metal tungsten layer in sequence to form a through-hole tungsten plug covering layer on the through-hole layer;
[0034] Step S6: performing a tungsten chemical mechanical planarization process on the through-hole tungsten plug capping layer to form a planarized through-hole layer.
[0035] The technical solution of the present invention is exemplified below by three specific embodiments. Preferably, the interconnect layer structure is an interconnect layer structure M0; and the through hole layer is a through hole layer V0.
[0036] Example 1
[0037] In an embodiment of the present invention, the dielectric layer includes a contact etch stop layer (CESL) and a silicon oxide layer from bottom to top, and the compressive stress process in step S4 is a plasma bias bombardment process. That is, step S4 specifically includes step S41, that is, bombarding the silicon oxide layer on the surface of the through-hole layer with plasma bias.
[0038] Furthermore, the plasma bias bombardment process is a heavy ion plasma bias bombardment process; the heavy ions may be Ar ions; and the material of the contact hole etch stop layer is silicon nitride (SiN) or nitrogen-doped silicon carbide (NDC: Nitrogen Doped Carbide).
[0039] See also Figure 2-Figure 7 ,like Figure 2 As shown, a substrate 1 containing an interconnect layer structure 2 is provided, and a dielectric layer 3 (silicon nitride 31 and silicon oxide 32) is formed on the substrate 1, wherein the interconnect material in the interconnect layer structure 2 includes metal cobalt, and the silicon nitride 31 is a contact hole etch stop layer (CESL).
[0040] like Figure 3 As shown in the figure, the result pattern after the dielectric layer is subjected to a standard photolithography and etching process, i.e., a patterned through-hole layer is formed; wherein the through-holes in the through-hole layer penetrate the dielectric layer, that is, the through-holes in the through-hole layer have been etched through the contact etch stop layer (CESL) and stopped on the surface of the interconnection line in the interconnection line layer structure.
[0041] like Figure 4 As shown in the figure, tungsten is deposited on the via layer using a selective tungsten deposition process to form a via tungsten plug in the via layer; wherein at least one of the via tungsten plugs is in contact with the interconnect layer structure.
[0042] like Figure 5 As shown in the figure, the dielectric layer includes a contact hole etch stop layer and a silicon oxide layer from bottom to top, and the compressive stress process in step S4 is a plasma bias bombardment process, specifically including: step S41: using heavy ion (such as Ar) plasma bias bombardment to bombard the silicon oxide layer on the surface of the through hole layer to increase the compressive stress between the dielectric in the dielectric layer and the side wall of the through hole tungsten plug.
[0043] like Figure 6 As shown in the figure, a TiN adhesion layer and a metal tungsten layer are deposited in sequence to form a through-hole tungsten plug covering layer on the through-hole layer.
[0044] like Figure 7 As shown, a tungsten chemical mechanical planarization process is performed on the via tungsten plug capping layer to form a planarized via layer.
[0045] Example 2
[0046] In an embodiment of the present invention, the silicon oxide layer is a FCVD silicon oxide layer, and the step S4 specifically includes the following steps:
[0047] Step S41: bombarding the silicon oxide layer on the surface of the through-hole layer with plasma bias;
[0048] Step S42: performing a water vapor annealing process on the FCVD silicon oxide layer to further increase the compressive stress between the dielectric in the dielectric layer and the sidewall of the through-hole tungsten plug.
[0049] That is to say, this embodiment adopts two compressive stress processes, namely, a plasma bias bombardment process for the FCVD silicon oxide layer and a water vapor annealing process for the FCVD silicon oxide layer, in order to obtain a better effect of increasing the compressive stress between the dielectric in the dielectric layer and the sidewall of the through-hole tungsten plug. Of course, the order of performing the plasma bias bombardment for the FCVD silicon oxide layer and the water vapor annealing process for the FCVD silicon oxide layer can be reversed.
[0050] Example 3
[0051] In an embodiment of the present invention, the dielectric layer includes a contact etch stop layer (CESL) and a FCVD silicon oxide layer from bottom to top, and the compressive stress process in step S4 is to perform a water vapor annealing process on the FCVD silicon oxide layer. That is, step S4 specifically includes step S42, i.e., performing a water vapor annealing process on the FCVD silicon oxide layer to increase the compressive stress between the dielectric in the dielectric layer and the side wall of the through hole tungsten plug.
[0052] See also Figure 8-Figure 13 ,like Figure 8 As shown, a substrate 1 containing an interconnect layer structure 2 is provided, and a dielectric layer 3 (a silicon nitride layer 31 and a FCVD silicon oxide layer 32) is formed on the substrate 1, wherein the interconnect material in the interconnect layer structure 2 includes metal cobalt, and the silicon nitride layer 31 is a contact hole etch stop layer (CESL).
[0053] like Fig. 9 As shown in the figure, the result pattern after the dielectric layer is subjected to a standard photolithography and etching process, i.e., a patterned through-hole layer is formed; wherein the through-holes in the through-hole layer penetrate the dielectric layer, that is, the through-holes in the through-hole layer have been etched through the contact etch stop layer (CESL) and stopped on the surface of the interconnection line in the interconnection line layer structure.
[0054] like Fig.10 As shown in the figure, tungsten is deposited on the via layer using a selective tungsten deposition process to form a via tungsten plug in the via layer; wherein at least one of the via tungsten plugs is in contact with the interconnect layer structure.
[0055] like Fig.11 As shown in the figure, the dielectric layer 3 includes a contact hole etch stop layer 31 and a silicon oxide layer 32 from bottom to top, and the compressive stress process in step S4 is a plasma bias bombardment process, specifically including step S42: performing a water vapor annealing process on the FCVD silicon oxide layer to increase the compressive stress between the dielectric in the dielectric layer and the side wall of the through-hole tungsten plug.
[0056] like Fig.12 As shown in the figure, a TiN adhesion layer and a metal tungsten layer are deposited in sequence to form a through-hole tungsten plug covering layer on the through-hole layer.
[0057] like Fig.13 As shown, a tungsten chemical mechanical planarization process is performed on the via tungsten plug capping layer to form a planarized via layer.
[0058] The above-described embodiments are only preferred embodiments of the present invention, and the embodiments are not intended to limit the patent protection scope of the present invention. Therefore, any equivalent structural changes made using the description and drawings of the present invention should also be included in the protection scope of the present invention.
Claims
1. A method for forming an interconnect layer and a contact hole layer in a semiconductor device, characterized in that: The steps include: Step S1: providing a substrate including an interconnect layer structure, and forming a dielectric layer on the substrate, wherein the interconnect material in the interconnect layer structure includes metal cobalt, and the dielectric layer includes at least a silicon oxide layer located on the surface of the dielectric layer; Step S2: performing a standard photolithography and etching process on the dielectric layer to form a patterned through-hole layer; wherein the through-holes in the through-hole layer penetrate the dielectric layer; Step S3: depositing tungsten on the via layer by a selective tungsten deposition process to form a via tungsten plug in the via layer; wherein the lower portion of the via tungsten plug contacts the metal cobalt in the interconnect layer structure; and the upper portion of the via tungsten plug is higher than the silicon oxide layer in the dielectric layer; Step S4: performing a compressive stress process on the surface of the through-hole layer to increase the compressive stress between the dielectric in the dielectric layer and the sidewall of the through-hole tungsten plug; Step S5: depositing a TiN adhesion layer and a metal tungsten layer in sequence to form a through-hole tungsten plug covering layer on the through-hole layer; wherein the TiN adhesion layer covers the upper portion of the through-hole tungsten plug higher than the dielectric layer and the surface of the dielectric layer; and the metal tungsten layer completely covers the TiN adhesion layer; Step S6: performing a tungsten chemical mechanical planarization process on the through-hole tungsten plug covering layer to form a planarized through-hole layer, wherein when performing the tungsten chemical mechanical planarization process on the through-hole tungsten plug covering layer, the through-hole tungsten plug covering layer and the upper portion of the through-hole tungsten plug higher than the dielectric layer are removed; The silicon oxide layer is a flow-type chemical vapor deposition silicon oxide layer, and the step S4 comprises: Step S42: performing a water vapor annealing process on the flow-type chemical vapor deposition silicon oxide layer to increase the compressive stress between the dielectric in the dielectric layer and the sidewall of the through-hole tungsten plug.
2. The method for forming an interconnect layer and a contact hole layer in a semiconductor device according to claim 1, characterized in that: The dielectric layer includes a contact hole etching stop layer and a silicon oxide layer from bottom to top, and the compressive stress process in step S4 also includes a plasma bias bombardment process, specifically including: Step S41: bombarding the silicon oxide layer on the surface of the through-hole layer with plasma bias.
3. The method for forming an interconnection layer and a contact hole layer in a semiconductor device according to claim 2, characterized in that: The plasma bias bombardment process is a heavy ion plasma bias bombardment process.
4. The method for forming an interconnection layer and a contact hole layer in a semiconductor device according to claim 3, characterized in that: The heavy ions are Ar ions.
5. The method for forming an interconnect layer and a contact hole layer in a semiconductor device according to claim 2, characterized in that: The material of the contact hole etching stop layer is silicon nitride or nitrogen-doped silicon carbide.
6. The method for forming an interconnection layer and a contact hole layer in a semiconductor device according to claim 1, characterized in that: The dielectric layer includes a contact hole etching stop layer and a silicon oxide layer from bottom to top, and the compressive stress process in step S4 is a water vapor annealing process for the flow chemical vapor deposited silicon oxide layer.
7. The method for forming an interconnection layer and a contact hole layer in a semiconductor device according to claim 1, characterized in that: The interconnection line layer structure is an interconnection line layer structure M0; the through hole layer is a through hole layer V0.