Transmit Fault Feedback Scheme for Crosstalk Reduction

Abstract

The present application is directed to transmission fault feedback associated with a memory device. The memory device may detect an error in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum of the received data and may detect a transmission error. The memory device may transmit an indication of the detected error to the controller and may transmit the indication using a line other than an error detection code EDC line. A low speed tracking clock signal may also be transmitted by the memory device via a line other than the EDC line. The memory device may transmit the generated checksum to the controller and apply a time offset to the checksum signaled via the EDC line.

Description

[0001] Cross Reference

[0002] This patent application claims priority to PCT Application No. PCT / US2019 / 046400, filed by Mayer et al. on August 13, 2019, entitled “TRANSMISSION FAILURE FEEDBACK SCHEMES FOR REDUCING CROSSTALK,” which claims priority to U.S. Patent Application No. 16 / 538,537, filed by Mayer et al. on August 12, 2019, entitled “TRANSMISSION FAILURE FEEDBACK SCHEMES FOR REDUCING CROSSTALK,” and U.S. Patent Application No. 16 / 538,537, filed by Mayer et al. on August 21, 2018, entitled “TRANSMISSION FAILURE FEEDBACK SCHEMES FOR REDUCING CROSSTALK,” which claims priority to U.S. Patent Application No. 16 / 538,537, filed by Mayer et al. on August 12, 2019, entitled “TRANSMISSION FAILURE FEEDBACK SCHEMES FOR REDUCING CROSSTALK,” and U.S. Patent Application No. 16 / 538,537, filed by Mayer et al. on August 21, 2018, entitled “TRANSMISSION FAILURE FEEDBACK SCHEMES FOR REDUCING CROSSTALK)" each of which is assigned to the present assignee and each of which is expressly incorporated herein by reference in its entirety.

[0003] TECHNICAL FIELD The present invention relates to a system including at least one memory device, and more particularly to a transmit failure feedback scheme for reducing crosstalk. Background Art

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming different states of the memory device. For example, a binary device can store one of two states, often represented by a logical 1 or a logical 0. In other devices, more than two states can be stored. To access the stored information, a component of the device can read or sense at least one stored state in the memory device. To store information, a component of the device can write or program a state in the memory device.

[0005] There are different types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory such as FeRAM can maintain its stored logic state for a long time, even if no external power source is present. Volatile memory devices (e.g., DRAM) may lose their stored state over time unless they are periodically refreshed by an external power source.

[0006] The memory device may include various channels for communicating information with other devices within the system (e.g., a controller). For example, the memory device may use one or more channels to transmit and / or receive data from the controller, but may require improved signaling between the controller and the memory device for error detection and other functions. Summary of the invention

[0007] A method is described. The method may include: receiving data to be written to a memory cell array of a memory device from a controller via a plurality of data lines; receiving, by the memory device, via an error detection code (EDC) line coupled to the controller, checksum information of the data received via the plurality of data lines; detecting, by the memory device, an error in the data based at least in part on the checksum information; and transmitting, to the controller, transmission failure information indicating the error in the data based at least in part on detecting the error.

[0008] An apparatus is described. The apparatus may include a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions may be executed by the processor to cause the apparatus to: receive data to be written to a memory cell array of a memory device from a controller via a plurality of data lines; receive, by the memory device, checksum information of the data received via the plurality of data lines via an EDC line coupled to the controller; detect, by the memory device, an error in the data based at least in part on the checksum information; and transmit, to the controller, transmission fault information indicating the error in the data based at least in part on the detection of the error.

[0009] Another apparatus is described. The apparatus may include: means for receiving data to be written to a memory cell array of a memory device from a controller via a plurality of data lines; means for receiving, by the memory device, via an EDC line coupled to the controller, checksum information of the data received via the plurality of data lines; means for detecting, by the memory device, an error in the data based at least in part on the checksum information; and means for transmitting, to the controller, transmission failure information indicating the error in the data based at least in part on detecting the error.

[0010] A non-transitory computer-readable medium storing code is described. The code may include instructions executable by a processor to: receive data to be written to a memory cell array of a memory device from a controller via a plurality of data lines; receive, by the memory device, via an EDC line coupled to the controller, checksum information of the data received via the plurality of data lines; detect, by the memory device, an error in the data based at least in part on the checksum information; and transmit, to the controller, transmission fault information indicating the error in the data based at least in part on the detection of the error.

[0011] A method is described. The method may include: receiving data to be written to a memory cell array of a memory device from a controller via a plurality of data lines; determining, by the memory device, a timing offset for transmitting a checksum of the data; and transmitting the checksum to the controller at a transmission time shifted according to the timing offset.

[0012] An apparatus is described. The apparatus may include a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions may be executed by the processor to cause the apparatus to: receive data to be written to a memory cell array of a memory device from a controller via a plurality of data lines; determine, by the memory device, a timing offset for transmitting a checksum of the data; and transmit the checksum to the controller at a transmission time shifted according to the timing offset.

[0013] Another apparatus is described. The apparatus may include: means for receiving data to be written to a memory cell array of a memory device from a controller via a plurality of data lines; means for determining, by the memory device, a timing offset for transmitting a checksum of the data; and means for transmitting the checksum to the controller at a transmission time shifted according to the timing offset.

[0014] A non-transitory computer-readable medium storing code is described. The code may include instructions executable by a processor to: receive data to be written to a memory cell array of a memory device from a controller via a plurality of data lines; determine, by the memory device, a timing offset for transmitting a checksum of the data; and transmit the checksum to the controller at a transmission time shifted according to the timing offset.

[0015] A method is described. The method may include transmitting data to be written to a memory cell array via a plurality of data lines coupled to a memory device, transmitting checksum information of the transmitted data via an EDC line coupled to the memory device, and receiving transmission failure information from the memory device indicating an error in the data based at least in part on the transmitted checksum information.

[0016] An apparatus is described. The apparatus may include a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions may be executed by the processor to cause the apparatus to: transmit data to be written to a memory cell array via a plurality of data lines coupled to a memory device; transmit checksum information of the transmitted data via an EDC line coupled to the memory device; and receive transmission failure information indicating an error in the data from the memory device based at least in part on the transmitted checksum information.

[0017] Another apparatus is described. The apparatus may include: means for transmitting data to be written to a memory cell array via a plurality of data lines coupled to a memory device; means for transmitting checksum information of the transmitted data via an EDC line coupled to the memory device; and means for receiving transmission failure information indicating an error in the data from the memory device based at least in part on the transmitted checksum information.

[0018] A non-transitory computer-readable medium storing code is described. The code may include instructions executable by a processor to: transmit data to be written to a memory cell array via a plurality of data lines coupled to a memory device; transmit checksum information of the transmitted data via an EDC line coupled to the memory device; and receive transmission failure information indicating an error in the data from the memory device based at least in part on the transmitted checksum information.

[0019] A device is described. The device may include: a memory cell array; a receiver coupled to a plurality of data lines and an EDC line, the receiver configured to receive data to be written to the memory cell array via the plurality of data lines and to receive checksum information about the data received via the plurality of data lines; a comparator configured to detect an error in the data based at least in part on the checksum information; and one or more lines coupled to a controller and configured to transmit at least one of a clock signal or transmission failure information indicating an error detected in the data, the one or more lines being different from the EDC line. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 An example of a system supporting a transmit failure feedback scheme for reducing crosstalk according to examples disclosed herein is shown.

[0021] Figure 2 A block diagram is shown of an apparatus supporting a transmit failure feedback scheme for reducing crosstalk according to examples disclosed herein.

[0022] Figure 3 An example of a system supporting a transmit failure feedback scheme for reducing crosstalk according to examples disclosed herein is shown.

[0023] Figure 4 An example of a system supporting a transmit failure feedback scheme for reducing crosstalk according to examples disclosed herein is shown.

[0024] Figure 5 A process flow in a system supporting a transmit failure feedback scheme for reducing crosstalk according to examples disclosed herein is shown.

[0025] Figure 6 A process flow in a system supporting a transmit failure feedback scheme for reducing crosstalk according to examples disclosed herein is shown.

[0026] Figures 7 to 9 One or more methods of supporting a transmit failure feedback scheme for reducing crosstalk according to examples disclosed herein are shown. DETAILED DESCRIPTION

[0027] A memory device may communicate with another device (e.g., a controller or host device such as a graphics processing unit (GPU), a general purpose GPU (GPGPU), a central processing unit (CPU)) via one or more channels. Such channels (e.g., corresponding to conductive lines) may couple pins of the memory device with pins of the other device. For example, these channels may couple data (DQ) pins of the memory device with corresponding pins of the other device, and may transfer data between the memory device and the other device via one or more data lines. As such, these data lines may be used to receive data to be written to a memory cell array at the memory device (e.g., for a write operation), and to transmit data from the memory device to the other device (e.g., for a read operation).

[0028] In some cases, an error detection code (EDC) line may enable different types of information to be transmitted from a memory device. For example, an EDC line may be used to transmit error detection information (e.g., a checksum) about data received from a controller during a write operation. In such cases, upon receiving data to be written to a memory cell array, the memory device may generate a checksum derived from the received data and used to identify a transmission error. This checksum may be transmitted back to the controller via the EDC line, and the controller may then compare the checksum received from the memory device with the checksum information of the transmitted data (e.g., known to the controller prior to transmission). Based on a comparison of the respective checksums, the controller may determine whether the data received at the memory device has an error, and the controller may retransmit the data if an error is detected. In other examples, the memory device may use the EDC line to transmit other types of signals (e.g., a clock signal representing the timing of the memory device, a keeper pattern).

[0029] However, information transmitted via the EDC line may cause interference to one or more signals transmitted on the data channel. For example, the EDC line may be located near (e.g., adjacent to) one or more data lines, and data transmission may be affected by crosstalk from various signals transmitted on or associated with the EDC line. This crosstalk may have an undesirable effect on data received on the data lines by coupling (e.g., capacitively coupling) the EDC signal to data sent on the one or more data lines. As a result, increased errors in the received data may result in more frequent rewriting of the data, thereby introducing inefficiencies and delays into the system and its operation.

[0030] As described herein, various techniques can allow information from a memory device to be fed back to another device (e.g., a controller) while reducing or eliminating crosstalk. For example, transmit error information (e.g., information indicating that an error has been detected for received data) can be transmitted from a memory device when an error is detected in the data, thus reducing the frequency of signaling transmitted against the received data (e.g., in the opposite direction of the received data). In some cases, the transmit error information can be sent on a line other than an EDC line (e.g., a line located away from the data line) to reduce or eliminate crosstalk onto the data line.

[0031] Transmission error information may be determined at the memory device by comparing checksum information received from another device (e.g., a controller transmitting data) with a checksum generated by the memory device. Based on the comparison, the memory device may identify errors in the received data, and then transmit the transmission error information (e.g., a binary indication sent using one bit) as needed. The memory device may also transmit a clock signal (e.g., a low-speed tracking clock) to other devices using a line other than the EDC line (which may be the same or different than the line used to transmit the transmission error information). Thus, the EDC line may not be used to transmit information from the memory device when receiving data at the memory device, thereby reducing crosstalk from signaling sent on the EDC line.

[0032] Additionally or alternatively, a delay or timing offset may be introduced to the signaling sent by the memory device on the EDC line, which may likewise be able to reduce or eliminate crosstalk. For example, when a generated checksum is transmitted to a controller via the EDC line, a fine-tunable offset may be applied to the timing of the checksum transmission. By shifting the signal transmitted on the EDC line in time, crosstalk may be reduced or eliminated via a consecutively introduced delay that reduces crosstalk from EDC signaling on data received at the memory device. In some cases, the timing offset may be selected (e.g., at power-up) from a determined set of offsets, where the determined offset may be based on one or more operating conditions of the memory device.

[0033] This article is in Figure 1 Features of the present disclosure are described at an exemplary memory system level in the context of Figure 2 The features of the present disclosure are further described in the context of an exemplary memory device. Figures 3 to 5 Specific examples of systems and techniques for transmitting error feedback are described in the context of Figure 7 and 8 The flowchart is shown and referenced Figure 7 and 8 Flowchart of FIG. 1 describes these and other features of the present disclosure relating to a transmit failure feedback scheme for reducing crosstalk.

[0034] Figure 1 An example of a system 100 including devices supporting a transmit failure feedback scheme for reducing crosstalk according to examples disclosed herein is shown. The system 100 may include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling the external memory controller 105 and the memory device 110. The system 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110.

[0035] System 100 may include aspects of an electronic device, such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, etc. Memory device 110 may be a system component configured to store data of one or more other components of system 100. In some examples, system 100 is configured for two-way wireless communication with other systems or devices using a base station or access point. In some examples, system 100 is capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

[0036] At least a portion of system 100 may be an example of a host device. Such a host device may be an example of a device that uses memory to perform a process, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, some other fixed or portable electronic device, etc. In some cases, a host device may refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 105. In some cases, external memory controller 105 may be referred to as a host or host device. In some examples, system 100 is a graphics card.

[0037] In some cases, memory device 110 may be a standalone device or component that is configured to communicate with other components of system 100 and provide physical memory addresses / spaces that may be used or referenced by system 100. In some instances, memory device 110 may be configurable to work with at least one or more different types of systems 100. Signaling between components of system 100 and memory device 110 may be operable to support modulation schemes used to modulate signals, different pin designs for transmitting signals, different packaging of system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions, and / or other factors.

[0038] The memory device 110 may support techniques for reducing crosstalk when transmitting or receiving information. As an example, and as described in further detail below, the memory device 110 may be configured with a channel (e.g., a dedicated channel) for error indication of clock signals and / or received data. In some cases, the channel may be different from the EDC channel (e.g., a channel used to transmit EDC information). In addition, the memory device 110 may be configured to detect errors in data to be written to the memory cell array, where the error detection may be based on information (e.g., checksum information) received from the device that transmitted the data (e.g., the external memory controller 105). In some examples, the memory device 110 may also be configured to introduce a timing offset in the signaling sent via the EDC channel.

[0039] The memory device 110 may be configured to store data for components of the system 100. In some cases, the memory device 110 may act as a slave device of the system 100 (e.g., responding to and executing commands provided by the system 100 via the external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. The memory device 110 may include two or more memory dies 160 (e.g., memory chips) that support a desired or specified capacity for data storage. A memory device 110 that includes two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0040] System 100 may further include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. The components of system 100 may be coupled or in electronic communication with each other using a bus 140.

[0041] Processor 120 may be configured to control at least a portion of system 100. Processor 120 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components. In such cases, processor 120 may be an instance of a CPU, a GPU, a GPGPU, or a system on a chip (SoC), among other instances.

[0042] BIOS component 125 may be a software component including BIOS operating as firmware that may initialize and run various hardware components of system 100. BIOS component 125 may also manage the flow of data between processor 120 and various components of system 100, such as peripheral components 130, I / O controller 135, etc. BIOS component 125 may include a program or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0043] Peripheral component 125 may be any input device or output device, or an interface for such a device, that may be integrated into or with system 100. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot (e.g., a Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) slot). Peripheral component 125 may be other components that are understood by those skilled in the art to be peripheral devices.

[0044] I / O controller 135 may manage data communications between processor 120 and peripheral components 13, input device 145, or output device 150. I / O controller 135 may manage peripheral devices that are not integrated into or with system 100. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0045] Input 145 may represent a device or signal that is external to system 100 and that can provide information, signals, or data to system 100 or its components. This may include a user interface or an interface with or between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0046] Output 150 may represent a device or signal external to system 100 that is configured to receive output from system 100 or any of its components. Examples of output 150 may include a display, an audio speaker, a printing device, or another processor on a printed circuit board, etc. In some cases, output 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0047] The components of system 100 may be composed of general or special purpose circuitry designed to perform their functions. This may include various circuit elements, such as wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements, configured to perform the functions described herein. In some cases, a memory device may include one or more comparators that may be coupled to a device (e.g., external memory controller 105 or memory device 110) or included in and used by the device to compare error detection information (e.g., checksums) to identify errors in data transmitted within system 100.

[0048] The memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). The memory array 170 may be a collection (e.g., a grid) of memory cells, where each memory cell is configured to store at least one bit of digital data. Reference Figure 2 Features of memory array 170 and / or memory cells are further described.

[0049] The memory device 110 may be an example of a two-dimensional (2D) memory cell array, or may be an example of a three-dimensional (3D) memory cell array. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked on top of each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a level, a tier, a layer, or a die. A 3D memory device may include any number of stacked memory dies 160-N (e.g., two, three, four, five, six, seven, eight). This can increase the number of memory cells that can be positioned on a substrate compared to a single 2D memory device, thereby reducing production costs, improving the performance of the memory array, or both. In some 3D memory devices, different levels may share at least one common access line, such that some levels may share at least one of a word line, a digit line, and / or a plate line.

[0050] The device memory controller 155 may include circuits or components configured to control the operation of the memory device 110. As such, the device memory controller 155 may include hardware, firmware, and software that enable the memory device 110 to execute commands, and may be configured to receive, transmit, or execute commands, data, or control information regarding the memory device 110. The device memory controller 155 may be configured to communicate with the external memory controller 105, the one or more memory dies 160, or the processor 120. In some cases, the memory device 110 may receive data and / or commands from the external memory controller 105.

[0051] For example, the memory device 110 may receive a write command indicating that the memory device 110 is to store specific data on behalf of a component of the system 100 (e.g., the processor 120), or a read command indicating that the memory device 110 is to provide specific data stored in the memory die 160 to a component of the system 100 (e.g., the processor 120). In some cases, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160. Examples of components included in the device memory controller 155 and / or the local memory controller 165 may include a receiver for demodulating signals received from the external memory controller 105, a decoder for modulating and transmitting signals to the external memory controller 105, logic, decoders, amplifiers, filters, and the like.

[0052] A local memory controller 165 (e.g., local to the memory die 160) may be configured to control the operation of the memory die 160. Moreover, the local memory controller 165 may be configured to communicate (e.g., receive and transmit data and / or commands) with the device memory controller 155. The local memory controller 165 may support the device memory controller 155 in controlling the operation of the memory device 110 as described herein. In some cases, the memory device 110 does not include a device memory controller 155, and the local memory controller 165 or the external memory controller 105 may perform the various functions described herein. Thus, the local memory controller 165 may be configured to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 105 or the processor 120.

[0053] The external memory controller 105 may be configured to enable the transfer of information, data, and / or commands between components of the system 100 (e.g., the processor 120) and the memory device 110. The external memory controller 105 may act as a liaison between the components of the system 100 and the memory device 110, so that the components of the system 100 may not need to know the operating details of the memory device. The components of the system 100 may present requests (e.g., read commands or write commands) to the external memory controller 105 that the external memory controller 105 satisfies. The external memory controller 105 may convert or translate communications exchanged between the components of the system 100 and the memory device 110. In some cases, the external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

[0054] In some cases, the external memory controller 105 or other components of the system 100, or the functionality thereof described herein, may be implemented by the processor 120. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 120 or other components of the system 100. Although the external memory controller 105 is depicted as being external to the memory device 110, in some cases, the external memory controller 105 or the functionality thereof described herein may be implemented by the memory device 110. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the device memory controller 155 or one or more local memory controllers 165.

[0055] In some cases, the external memory controller 105 may be distributed across the processor 120 and the memory device 110, such that portions of the external memory controller 105 are implemented by the processor 120 and other portions are implemented by the device memory controller 155 or the local memory controller 165. Likewise, in some cases, one or more functions attributed herein to the device memory controller 155 or the local memory controller 165 may in some cases be performed by the external memory controller 105 (separate from or included in the processor 120). In some examples, the external memory controller 105 may be configured to receive an indication of an error in data transmitted to the memory device 110 from the memory device 110. For example, the external memory controller 105 may receive a bit having a binary value indicating that an error exists in the data received at the memory device 110. As such, the external memory controller may determine to retransmit the data containing the error based on the received indication.

[0056] Components of system 100 may exchange information with memory device 110 using multiple channels 115. In some examples, channels 115 may enable communication between external memory controller 105 and memory device 110. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. For example, channel 115 may include a first terminal including one or more pins or pads at external memory controller 105 and one or more pins or pads at memory device 110. A pin may be an example of a conductive input or output point of a device of system 100, and a pin may be configured to act as part of a channel. In some cases, a pin or pad of a terminal may be part of a signal path of channel 115. Additional signal paths may be coupled to the terminals of a channel to route signals within components of system 100. For example, memory device 110 may include signal paths (e.g., signal paths internal to memory device 110 or its components, such as internal to memory die 160) that route signals from terminals of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

[0057] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting a specific type of information. In some cases, channel 115 may be an aggregate channel and thus may include multiple individual channels. For example, data channel 192 may be x4 (e.g., including four signal paths), x8 (e.g., including eight signal paths), x16 (including sixteen signal paths), etc. In some examples, channel 115 may correspond to a physical line (e.g., a conductive wire). For example, signaling transmitted between devices may be carried by channel 115 on one or more conductive wires located within system 100.

[0058] In some cases, channel 115 may include one or more command and address (CA) channels 186. CA channel 186 may be configured to transmit commands between external memory controller 105 and memory device 110, including control information associated with the commands (e.g., address information). For example, CA channel 186 may include a read command regarding the address of the desired data. In some cases, CA channel 186 may register on a rising clock signal edge and / or a falling clock signal edge. In some cases, CA channel 186 may include eight or nine signal paths.

[0059] In some cases, the channels 115 may include one or more clock signal (CK) channels 188. The CK channels 188 may be configured to transmit one or more common clock signals between the external memory controller 105 and the memory device 110. Each clock signal may be configured to adjust (e.g., oscillate) between a high state and a low state and coordinate the actions of the external memory controller 105 and the memory device 110. In some cases, the clock signals may be differential outputs (e.g., a CK_t signal and a CK_c signal), and the signal paths of the CK channels 188 may be configured accordingly.

[0060] In some cases, the clock signal may be single-ended. In some cases, the clock signal may be a 1.5 GHz signal. CK channel 188 may include any number of signal paths. In some cases, the clock signal CK (e.g., CK_t signal and CK_c signal) may provide a timing reference for command and addressing operations of memory device 110 or for other system-wide operations of memory device 110. The clock signal CK may therefore be referred to as a control clock signal CK, a command clock signal CK, or a system clock signal CK. The system clock signal CK may be generated by a system clock, which may include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors, etc.).

[0061] In some cases, channels 115 may include one or more data (DQ) channels 190. Data channels 190 may be configured to transfer data and / or control information between external memory controller 105 and memory device 110. For example, data channels 190 may transfer information to be written to memory device 110 (e.g., bidirectional) or information to be read from memory device 110. Data channels 190 may transfer signals that may be modulated using a variety of different modulation schemes (e.g., NRZ, PAM4).

[0062] In some cases, the channels 115 may include one or more other channels 192 that may be dedicated for other purposes. These other channels 192 may include any number of signal paths. In some cases, the other channels 192 may include one or more write clock signal (WCK) channels. Although the 'W' in WCK may nominally stand for "write", the write clock signal WCK (e.g., the WCK_t signal and the WCK_c signal) may provide a timing reference that is generally used for access operations of the memory device 110 (e.g., a timing reference for both read and write operations).

[0063] Therefore, the write clock signal WCK may also be referred to as the data clock signal WCK. The WCK channel may be configured to transmit a common data clock signal between the external memory controller 105 and the memory device 110. The data clock signal may be configured to coordinate access operations (e.g., write operations or read operations) of the external memory controller 105 and the memory device 110. In some cases, the write clock signal may be a differential output (e.g., a WCK_t signal and a WCK_c signal), and the signal path of the WCK channel may be configured accordingly. The WCK channel may include any number of signal paths. The data clock signal WCK may be generated by a data clock, which may include one or more hardware components (e.g., an oscillator, a crystal, a logic gate, a transistor, etc.).

[0064] Channel 115 may couple external memory controller 105 with memory device 110 using a variety of different architectures. Examples of various architectures may include a bus, a point-to-point connection, a crossbar switch, a high-density interposer such as a silicon interposer, or a channel formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path may at least partially include a high-density interposer such as a silicon interposer or a glass interposer.

[0065] The signals transmitted over the channel 115 may be modulated using a variety of different modulation schemes. In some cases, a binary symbol (or binary level) modulation scheme may be used to modulate the signals transmitted between the external memory controller 105 and the memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme, where M is equal to two. Each symbol of the binary symbol modulation scheme may be configured to represent one bit of digital data (e.g., a symbol may represent a logical 1 or a logical 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return to zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and the like.

[0066] In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals transmitted between the external memory controller 105 and the memory device 110. The multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to three. Each symbol of the multi-symbol modulation scheme may be configured to represent more than one bit of digital data (e.g., a symbol may represent a logical 00, a logical 01, a logical 10, or a logical 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM4, PAM8, etc., quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), etc. A multi-symbol signal or PAM4 signal may be a signal modulated using a modulation scheme that includes at least three levels to encode more than one bit of information. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or high-order modulation schemes and symbols.

[0067] In some cases, other channels 192 may include one or more EDC channels. The EDC channels may be configured for multiple functions, such as error correction during read and write operations, and feedback regarding timing shifts in memory device 110 during read operations. For example, the EDC line may be used to transmit back a checksum (e.g., a cyclic redundancy check (CRC) checksum) of data written to memory device 110. In such cases, an 8-bit checksum may be generated by memory device 110 for eight (8) data bits received via one or more data channels 190 (or data lines). In other cases, data received on multiple data channels 190 or during one or more data bursts may be combined when generating the checksum.

[0068] In any case, the memory device 110 may provide the generated checksum to the external memory controller 105 (e.g., GPU) via the EDC pin. The external memory controller 105 may also generate a checksum of the transmitted data, and determine whether the data is correctly received at the memory device 110 based on a comparison between the checksums. If an error is detected, any data including the error may be retransmitted to the memory device 110 to rewrite the information about the error.

[0069] In the absence of checksum data to be provided to the external memory controller 105, the EDC line may instead be used to communicate a timing signal (e.g., a clocked pattern) to the external memory controller 105 for tracking the timing of the memory device 110. Such clocked patterns may include retention patterns (e.g., EDC retention patterns) driven by EDC signaling and defined by one or more mode register settings (e.g., the number of bits in the mode register may define the retention pattern). The retention pattern may include a certain number of bits (e.g., four (4) bits) that may be repeatedly / continuously transmitted by the memory device 110 for clock and data recovery operations.

[0070] In some cases, the timing of memory device 110 may be affected by changes in temperature or supply voltage and other parameters that may result in changes in the operation of memory device 110 (e.g., increased voltage noise (e.g., due to thermal agitation of charge carriers), temperature-induced jitter). As a result, the clock pattern or clock signal of memory device 110 may drift with changes in temperature and / or supply voltage, causing the data eye position to shift away from the trained (e.g., optimal) data eye position, potentially increasing the probability of transmission errors.

[0071] In such cases, based on the clock signal sent (e.g., via the EDC channel), the external memory controller 105 may determine whether retraining is needed to account for shifts in the timing of the memory device 110, or whether a timing offset needs to be applied, such as on read data received from the memory device 110. Accordingly, the clocked pattern sent by the memory device 110 via the EDC pin may enable the external memory controller 105 to recognize and adapt to changes in memory timing and other conditions.

[0072] However, the EDC signal from memory device 110 may interfere with relatively weaker data signals from external memory controller 105 that are proximate to a receiver of memory device 110. For example, the EDC line may be located between or near one or more data lines (e.g., corresponding to data channel 190). When checksum information or a clocked pattern is transmitted on an EDC line that runs against (in the opposite direction of) data transmitted on one or more data lines, crosstalk may affect the data received at memory device 110.

[0073] As an example, a gapless write cycle may use continuous data transfer from the EDC line in the opposite direction as the one or more data lines (e.g., and at the same rate as the data is transmitted). If the EDC line is driven signaling out of the memory device 110 simultaneously or in parallel (or at nearly the same time) as the data is latched in the memory device 110, interference (e.g., near-end crosstalk, also known as backward crosstalk) may occur on one or more data channels.

[0074] Crosstalk may be referred to as a signal that inadvertently affects other signals (e.g., nearby signals) within a system via electromagnetic effects, and may correspond to the coupling of one signal to another signal (e.g., where two or more signals may be coupled such that a change in one signal may unexpectedly affect and be observed in another signal). The coupling may include capacitive, inductive, and / or conductive coupling between the signals, and may also include substrate coupling of the signals (e.g., coupling the signals via the substrate of an integrated circuit). Furthermore, crosstalk may be described in terms of an "aggressor" signal affecting a "victim" signal, where the "victim" signal may, for example, be the weaker (e.g., lower power) of the two. Crosstalk may occur in some systems that use high frequency transmissions, and crosstalk may introduce undesirable interference into the system 100, degrading the quality and efficiency of the transmitted information.

[0075] In some cases, the crosstalk caused by EDC signaling may create a tradeoff between using the EDC line in the presence of crosstalk and avoiding the use of the EDC line altogether. For example, the transmission of checksum information may interrupt the system to the point where it may be more efficient to perform periodic retraining (e.g., every 300 microseconds (μs)) rather than using the EDC line for error correction and timing tracking. As such, the negative effects of crosstalk from EDC signaling may be so great that periodic retraining (and any associated efficiency loss) may be more advantageous than operating without error detection capabilities (e.g., when avoiding the use of the EDC pin altogether). In this case, the external memory controller 105 may perform one or more actions (e.g., a sequence of steps) to synchronize the clocks of the external memory controller 105 and the memory device 110, and may further determine the data eye position for the input and output of the memory device 110. For example, the retraining may include modifying the delay in the clock signal sent via the CK channel 188 to align the respective clocks and identify the latency associated with one or more read and / or write operations. In some cases, various commands may thereafter be signaled to memory device 110 to determine the data eye location.

[0076] The system 100 may support techniques for reducing or eliminating crosstalk between different channels 115, such as described herein with reference to signaling transmitted over an EDC channel. As an example, the memory device 110 may detect errors in received data and transmit an indication of the error when detected, thereby reducing the frequency of error detection feedback from the memory device 110. In such cases, the error detection process may be performed at the memory device 110 rather than the external memory controller 105.

[0077] For example, the memory device may receive data via the data channel 190, and may also receive checksum information for the data via the EDC channel. In such cases, the data and checksum information may be transmitted from the external memory controller 105 to the memory device 110 simultaneously (e.g., in parallel) and in the same direction (e.g., from one device to another). The memory device 110 may accordingly generate a checksum for the received data, and detect a transmission error, such as by comparing the generated checksum to the checksum information received from the external memory controller 105. The memory device 110 may then transmit an indication of the error detected in the received data to the external memory controller 105, and the indication (e.g., a single bit) may be transmitted using a line other than the EDC line.

[0078] In some cases, the low-speed tracking clock signal may additionally or alternatively be transmitted by the memory device 110 via a line other than the EDC line. For example, to avoid the use of signaling on the EDC line against received data, the memory device 110 may transmit the clock signal or clock-like pattern on a different line located away from the data lines to eliminate crosstalk on one or more nearby data lines. The reduced rate of the clock-like pattern (e.g., compared to the data transfer rate of the system 100) may further reduce crosstalk in the system 100. Furthermore, the low-speed tracking clock signal may be a low voltage differential signal that achieves further reduction of crosstalk in the system 100.

[0079] Additionally or alternatively, the memory device 110 may transmit the generated checksum to the external memory controller 105 with a time offset applied to the checksum signaled via the EDC line. For example, the EDC signaling may be delayed to provide an offset between the edge transmitted on the data line and the EDC line. The specific offset in the EDC signaling may be selected from a set of offsets that may be determined (e.g., calculated) based on operating conditions at the memory device 110.

[0080] The described techniques for reducing crosstalk in system 100 may be used individually or in combination, or both, at different times. For example, transmitting a low-speed clock signal over a line other than the EDC line may be advantageous in some cases, while reducing the swing of the EDC signaling or adding a timing offset to the EDC signaling may be preferred in other cases. Implementation of the described solutions may save resources (e.g., printed circuit board (PCB) space) by using one or more of the described solutions, where circuitry for one or more of these techniques may be included on the PCB.

[0081] Figure 2 An example of a memory die 200 supporting a transmit fault feedback scheme for reducing crosstalk according to examples disclosed herein is shown. The memory die 200 may be a reference Figure 11. An example of a memory die 160 is described. In some cases, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205 that are programmable to store different logic states. Each memory cell 205 may be programmable to store two or more states. For example, the memory cell 205 may be configured to store one bit of digital logic at a time (e.g., logic 0 and logic 1). In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one bit of digital logic at a time (e.g., logic 00, logic 01, logic 10, or logic 11).

[0082] The memory cell 205 can store a charge representing a programmable state in a capacitor. A DRAM architecture can include a capacitor that includes a dielectric material to store a charge representing a programmable state. In other memory architectures, other storage devices and components are also possible. For example, nonlinear dielectric materials can be used.

[0083] Operations such as reading and writing can be performed on the memory cell 205 by activating or selecting access lines such as word lines 210 and / or digit lines 215. In some cases, digit lines 215 may also be referred to as bit lines. References to access lines, word lines, and digit lines or the like may be interchangeable without affecting understanding or operation. Activating or selecting word lines 210 or digit lines 215 may include applying a voltage to the corresponding line.

[0084] The memory die 200 may include access lines (e.g., word lines 210 and digit lines 215) arranged in a grid-like pattern. Memory cells 205 may be positioned at the intersections of the word lines 210 and the digit lines 215. By biasing the word lines 210 and the digit lines 215 (e.g., applying a voltage to the word lines 210 or the digit lines 215), a single memory cell 205 may be accessed at their intersections.

[0085] Access to the memory cell 205 may be controlled by a row decoder 220 or a column decoder 225. For example, the row decoder 220 may receive a row address from a local memory controller 260 and activate a word line 210 based on the received row address. The column decoder 225 may receive a column address from a local memory controller 260 and may activate a digit line 215 based on the received column address. For example, the memory die 200 may include a plurality of word lines 210 labeled WL_1 to WL_M and a plurality of digit lines 215 labeled DL_1 to DL_N, where M and N depend on the size of the memory array. Thus, by activating a word line 210 and a digit line 215, such as WL_1 and DL_3, a memory cell 205 at its intersection may be accessed. The intersection of a word line 210 and a digit line 215 in a two-dimensional or three-dimensional configuration may be referred to as the address of the memory cell 205.

[0086] Memory cell 205 may include a logic storage component, such as capacitor 230 and switch component 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A first node of capacitor 230 may be coupled to switch component 235, and a second node of capacitor 230 may be coupled to voltage source 240. In some cases, voltage source 240 is ground, such as Vss. In some cases, voltage source 240 may be an example of a plate line coupled to a plate line driver. Switch component 235 may be an example of a transistor or any other type of switching device that selectively establishes or stops electronic communication between two components.

[0087] Selecting or deselecting memory cell 205 can be achieved by activating or deactivating switch component 235. Capacitor 230 can be in electronic communication with digit line 215 using switch component 235. For example, capacitor 230 can be isolated from digit line 215 when switch component 235 is deactivated, and capacitor 230 can be coupled to digit line 215 when switch component 235 is activated. In some cases, switch component 235 is a transistor and its operation can be controlled by applying a voltage to the transistor gate, wherein the voltage difference between the transistor gate and the transistor source can be greater than or less than the threshold voltage of the transistor. In some cases, switch component 235 can be a p-type transistor or an n-type transistor. Word line 210 can be in electronic communication with the gate of switch component 235, and switch component 235 can be activated / deactivated based on the voltage applied to word line 210.

[0088] The word line 210 may be a conductive line in electronic communication with the memory cell 205 for performing an access operation on the memory cell 205. In some architectures, the word line 210 may be in electronic communication with a gate of a switching component 235 of the memory cell 205 and may be configured to control the switching component 235 of the memory cell. In some architectures, the word line 210 may be in electronic communication with a node of a capacitor of the memory cell 205 and the memory cell 205 may not include a switching component.

[0089] The digit line 215 can be a conductive line connecting the memory cell 205 and the sensing component 245. In some architectures, the memory cell 205 can be selectively coupled to the digit line 215 during portions of an access operation. For example, the word line 210 and the switching component 235 of the memory cell 205 can be configured to couple and / or isolate the capacitor 230 of the memory cell 205 and the digit line 215. In some architectures, the memory cell 205 can be in electronic communication (e.g., constant) with the digit line 215.

[0090] The sensing component 245 may be configured to detect a state (e.g., charge) stored on the capacitor 230 of the memory cell 205, and determine the logic state of the memory cell 205 based on the stored state. In some cases, the charge stored by the memory cell 205 may be extremely small. Thus, the sensing component 245 may include one or more sense amplifiers to amplify the signal output by the memory cell 205. The sense amplifier may detect small changes in the charge of the digit line 215 during a read operation, and may generate a signal corresponding to a logic state 0 or a logic state 1 based on the detected charge. During a read operation, the capacitor 230 of the memory cell 205 may output (e.g., discharge) a signal to its corresponding digit line 215. The signal may cause the voltage of the digit line 215 to change.

[0091] The sensing component 245 may be configured to compare the signal received from the memory cell 205 across the digital line 215 with a reference signal 250 (e.g., a reference voltage). The sensing component 245 may determine the storage state of the memory cell 205 based on the comparison. For example, in binary signaling, if the digital line 215 has a higher voltage than the reference signal 250, the sensing component 245 may determine that the storage state of the memory cell 205 is a logic 1, and if the digital line 215 has a lower voltage than the reference signal 250, the sensing component 245 may determine that the storage state of the memory cell 205 is a logic 0. The sensing component 245 may include various transistors or amplifiers to detect and amplify the difference in the signal. The detected logic state of the memory cell 205 may be output as an output 255 by the column decoder 225. In some cases, the sensing component 245 may be part of another component (e.g., column decoder 225, row decoder 220). In some cases, the sensing component 245 may be in electronic communication with the row decoder 220 or the column decoder 225.

[0092] The local memory controller 260 may control the operation of the memory cell 205 via various components (eg, the row decoder 220, the column decoder 225, and the sensing component 245). The local memory controller 260 may be a reference Figure 1 105 . In some cases, one or more of the row decoder 220, column decoder 225, and sense component 245 can be co-located with the local memory controller 260. The local memory controller 260 can be configured to receive data from the external memory controller 105 (or reference 105). Figure 1 The device memory controller 155 described herein receives commands and / or data, translates the commands and / or data into information usable by the memory die 200, performs one or more operations on the memory die 200, and transmits data from the memory die 200 to the external memory controller 105 (or the device memory controller 155) in response to performing the one or more operations.

[0093] The local memory controller 260 may generate row and column address signals to activate the target word lines 210 and the target digit lines 215. The local memory controller 260 may also generate and control various voltages or currents used during operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may be adjusted or varied and may be different for the various operations discussed in operating the memory die 200.

[0094] In some examples, the local memory controller 260 may detect errors in data received, for example, during an access operation (e.g., a write operation). For example, the local memory controller may compare checksum information of the data to be written to the memory unit 205, wherein the checksum associated with the data may be generated by the local memory controller 260 and may be compared with a checksum generated before the data was transmitted (e.g., as provided by another device). Based on the comparison, an error may be detected if the respective checksums are different, thereby indicating that the received data is different from the data being transmitted. In the event that an error is detected in the received data, the local memory controller 260 may transmit an indication indicating the error to the other device, which may trigger a retransmission of the data. In other cases, there may be no error detected via the checksum comparison (e.g., the checksums are the same), and the local memory controller 260 may continue with the access operation using the received data.

[0095] In some cases, the local memory controller 260 may be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired logic state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 260 may identify a target memory cell 205 on which a write operation is to be performed. The local memory controller 260 may identify a target word line 210 and a target digit line 215 that are in electronic communication with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 may activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. Local memory controller 260 may apply a particular signal (eg, voltage) to digit line 215 during a write operation to store a particular state (eg, charge) in capacitor 230 of memory cell 205, which may indicate a desired logic state.

[0096] In some cases, the local memory controller 260 can be configured to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During a read operation, a logic state stored in a memory cell 205 of the memory die 200 can be determined. In some cases, multiple memory cells 205 can be sensed during a single read operation. The local memory controller 260 can identify a target memory cell 205 on which the read operation is to be performed. The local memory controller 260 can identify a target word line 210 and a target digit line 215 that are in electronic communication with the target memory cell 205 (e.g., an address of the target memory cell 205).

[0097] The local memory controller 260 may activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The target memory cell 205 may pass a signal to the sensing component 245 in response to the biased access line. The sensing component 245 may amplify the signal. The local memory controller 260 may activate the sensing component 245 (e.g., latch the sensing component) and thereby compare the signal received from the memory cell 205 with the reference signal 250. Based on the comparison, the sensing component 245 may determine the logic state stored on the memory cell 205. The local memory controller 260 may transmit the logic state stored on the memory cell 205 to the external memory controller 105 (or the device memory controller 155) as part of a read operation.

[0098] In some memory architectures, accessing the memory cell 205 may degrade or destroy the logic state stored in the memory cell 205. For example, a read operation performed in a DRAM architecture may partially or completely discharge the capacitor of the target memory cell. The local memory controller 260 may perform a rewrite operation or a refresh operation to restore the memory cell to its original logic state. The local memory controller 260 may rewrite the logic state to the target memory cell after the read operation. In some cases, the rewrite operation may be considered as part of the read operation. In addition, activating a single access line (e.g., word line 210) may disturb the state stored in some memory cells that are electronically connected to the access line. Therefore, a rewrite operation or a refresh operation may be performed on one or more memory cells that may not have been accessed.

[0099] Memory die 200 shows a two-dimensional (2D) array of memory cells. In some cases, a memory device may include a three-dimensional (3D) array or memory cell. A 3D memory array may include two or more 2D memory arrays stacked one above the other. In some cases, a 2D memory array in a 3D memory array may be referred to as a level, a tier, a layer, or a die. A 3D memory array may include any number of stacked 2D memory arrays (e.g., two, three, four, five, six, seven, eight). Compared to a single 2D memory array, this can increase the number of memory cells that can be positioned on a single die or substrate, which in turn can reduce production costs or improve the performance of the memory array, or both. In some 3D memory arrays, different levels may share at least one common access line, so that some levels may share at least one of word lines 210 or digital lines 215.

[0100] Figure 3An example of a system 300 that supports a transmit failure feedback scheme for reducing crosstalk according to examples disclosed herein is shown. The system 300 can include a controller 305 and a memory device 310, each of which can implement aspects of the described techniques. For example, the controller 305 can be as described herein with reference to Figure 1 Examples of external memory controller 105 described herein (eg, GPU, GPGPU, CPU, etc.). In addition, memory device 310 may be as described in reference Figure 1 and 2 Examples of memory device 110 are depicted (eg, a graphics double data rate (GDDR) memory device).

[0101] The controller 305 and the memory device 310 are shown in the example of the system 300 coupled to each other via a plurality of lines (e.g., data lines 315-a and 315-b, and EDC line 320), where each line may correspond to a channel 115, as shown in reference Figure 1 It should be understood that controller 305 and memory device 310 may be coupled to each other and may exchange signals via any number of lines.

[0102] For example, the controller 305 and the memory device 310 may be coupled via one data line 315 or via multiple data lines 315 (eg, above the data line 315-a and / or below the data line 315-b, such as Figure 3 Each of the data line 315 and the EDC line 320 can be a unidirectional or multidirectional line for communication between the controller 305 and the memory device 310.

[0103] In some cases, data lines 315-a and 315-b may correspond to data channels (e.g., data channel 190, as shown in FIG. Figure 1 ), and the EDC line 320 may correspond to the example of the conductive line as described in reference Figure 1 Thus, the controller 305 may use one or more transmitters 325 to drive or transmit signals on each of the data lines 315. For example, the first transmitter 325-a or another transmitter 325-c or both may be configured to transmit data to be written to the memory cell array at the memory device 310 (e.g., as described in reference Figure 1 Data of the memory array 170) described.

[0104] In addition, the controller 305 may include a second transmitter 325-b configured to transmit information on the EDC line 320. The memory device 310 may include one or more receivers 330 (e.g., receivers 330-a, 330-b, and 330-c) configured to receive signals transmitted by the controller 305. As shown, the EDC line 320 may be located between the data line 315-a and the data line 315-b. As such, signaling sent from the memory device 310 to the controller 305 via the EDC line 320 may cause crosstalk on one or more data lines 315 (e.g., data line 315-a or data line 315-b or other data lines 315 not shown or any combination thereof).

[0105] In some aspects, the system 300 may implement techniques to reduce or eliminate crosstalk from the EDC lines 320 to the data lines 315. For example, the controller 305 may provide checksum information (e.g., a CRC checksum) for data sent via one or more data lines 315 (e.g., for a write operation from the controller 305 to the memory device 310). That is, the controller 305 may perform a checksum calculation on the data to be transmitted, and the controller 305 may provide the checksum information along with the data. The checksum information may be sent to the memory device 310 via the EDC lines 320. In such cases, the signaling on the EDC lines 320 (from the controller 305 to the memory device 310) may be aligned in time with the data sent on the data lines 315. Thus, the signaling being sent in the same direction as the data may result in reduced crosstalk at the memory device 310, and therefore fewer errors in the data to be written to the memory cell array.

[0106] In addition, the memory device 310 can generate a checksum of the received data and can identify errors in the received data. That is, the checksum comparison can be performed directly by the memory device 310. In some cases, the memory device 310 can include a comparator 335 for comparing the checksum of the received data with the checksum received from the controller 305.

[0107] In the event that a fault is identified in the received data, the memory device 310 may transmit an indication to the controller 305 to request that the data having the error (e.g., the data in which the fault occurred) be rewritten. In some examples, the indication of the data in which the fault occurred may be transmitted by the memory device 310 using the EDC line 320. Additionally or alternatively, the memory device 310 may include a transmitter 340 that receives (e.g., from the comparator 335) an indication of the data in which the fault occurred, and may then send information about the transmission fault to the controller 305 (e.g., via an error feedback line 345). For example, the error feedback line 345 may include an additional signal line on a die or substrate separate from the EDC line 320, and the error feedback line 345 may be configured for (e.g., dedicated to) the transmission of error feedback information (e.g., transmission error information). In some examples, the error feedback line 345 may be a Joint Test Action Group (JTAG) signal line or another line different from the EDC line.

[0108] In some examples, the transmission error information may include a single bit having a binary value (e.g., 0 or 1) that acts as a flag that the data received from the controller 305 has failed (e.g., the compared checksums are different). The single data bit may verify (or correspond to) a completed write process, which may eliminate per-byte or per-bit information fed back to the controller 305 (e.g., because a rewrite operation may rewrite an entire burst of data) and thus reduce crosstalk to signaling sent via the EDC line 320. In some examples, the indication transmitted with the transmission error information may be transmitted less frequently than continuous checksum transmissions from the memory device 310 to the controller 305.

[0109] In some cases, the number of errors may be relatively low (e.g., due in part to a reduction in return signaling from memory device 310), and any crosstalk that may result from infrequent return signaling (using EDC line 320 or error feedback line 345 or both) may be minimized accordingly. In some aspects, the binary indication may provide feedback (e.g., continuous feedback) to controller 305 regarding whether the transmitted data was received correctly, which may enable controller 305 to monitor the status of the data sent to memory device 310.

[0110] Additionally or alternatively, a low density (e.g., low frequency) clock signal may be used to feedback timing tracking between the memory device 310 and the controller 305. In such cases, the clock 350 may transmit the clock signal to the controller 305 using a timing feedback line 355 that is different from the EDC line 320. In such cases, the frequency (e.g., number of edges) of the clock signal driven by the clock 350 may be less than the frequency of the clock signal or clocked version transmitted via the EDC line 320. For example, the frequency of the clock signal may be reduced (e.g., by a factor of 10) so that fewer edges are transmitted from the memory device 310 to the controller 305 and, thus, reduce crosstalk in the system 300. In some cases, the clock signal may include a maintained version (e.g., a clocked signal) of the number of bits repeated by the memory device 310 (e.g., for providing feedback of the timing of the memory device 310).

[0111] In some cases, the clock signal driven by the clock 350 may be a differential signal having a low voltage swing (e.g., compared to the voltage swing of other signals transmitted within the system 300). For example, the clock signal may be a low swing differential clock signal (e.g., according to an industry standard or specification such as the Joint Electron Device Engineering Council (JEDEC) standard or the Low Voltage Differential Signaling (LVDS) standard), which may have a low voltage swing (e.g., the difference between a maximum output voltage and a minimum output voltage), operate at low power, run at high speeds, and transmit information using the difference between the voltages on a pair of wires or lines. Such signals may use a fraction of the voltage swing of other signals used within the system, but may still achieve high data rates and low power consumption. In this way, by reducing the voltage swing of the clock signal, or reducing the number of edges of the tracking clock signal from the memory device 310, or transmitting the signal on the timing feedback line 355, or any combination thereof, crosstalk within the system 300 may be reduced.

[0112] In some cases, any combination of lines may be used by the memory device 310 when sending transmission error information or clock signals, or both. For example, corresponding lines (e.g., both error feedback line 345 and timing feedback line 355) may be used for corresponding signals sent by the memory device 310, as shown in the system 300. In such examples, the separate lines may be driven at different speeds, or the signals sent on the corresponding lines may be different, or a combination thereof. For example, errors in the received data may not occur as frequently as the clock signal driven by the clock 350, and the clock signal may be sent on the timing feedback line 355 with a lower voltage swing than the transmission error information sent on the error feedback line 345. In other examples, various lines may be used independently or dynamically to switch between different functionalities and feedback schemes. In such cases, the memory device 310 may use the error feedback line 345 or the timing feedback line or the EDC line 320 or any combination thereof based on one or more conditions to transmit information to the controller 305.

[0113] Additionally or alternatively, a single line other than EDC line 320 may be used to transmit a low-speed clock and an error feedback report. That is, different types of information may be sent using the same signal. In such cases, different encoding / decoding schemes may be applied to each type of information. For example, a clock signal may use a first type of encoding, and if a fault in the received data is detected, a different encoding (e.g., a longer 0 phase or a longer 1 phase) may be used to transmit error information so that the controller 305 may identify the difference between the change in the clock signal and the indication of the error in the received data. Therefore, the error feedback information may be embedded in the low-speed clock signal, and the controller 305 may perform decoding of different types of signals according to the decoding scheme.

[0114] Figure 4 An example of a system 400 that supports a transmit fault feedback scheme for reducing crosstalk according to examples disclosed herein is shown. The system 400 may include a controller 405 and a memory device 410, each of which may implement aspects of the described techniques. For example, the controller 405 may be an example of an external memory controller 105 (e.g., a GPU), as described herein with reference to Figure 1 Furthermore, the memory device 410 may be an example of the memory device 110 (eg, a GDDR memory device), as described in reference Figures 1 to 3 described.

[0115] The controller 405 and the memory device 410 are shown in the example of the system 400 as being coupled to each other via a plurality of lines (e.g., data lines 415-a and 415-b, and EDC line 420), each of which may be or correspond to a channel 115, as described with reference to FIG. Figure 1However, it should be understood that the controller 405 and the memory device 410 can be coupled to each other and can exchange signals via any number of lines or channels 115. For example, the controller 405 and the memory device 410 can be coupled via one data line 415 or via multiple data lines 415 (e.g., located above the data line 415-a and / or below the data line 415-b, such as Figure 4 ).

[0116] Each of the data lines 415 and the EDC lines 420 may be unidirectional or multidirectional lines for communication between the controller 405 and the memory device 410. In some cases, the data lines 415-a and 415-b may be or correspond to data channels (e.g., data channel 190, as described in reference to FIG. Figure 1 ), and the EDC line 420 may be or correspond to the reference Figure 1 As such, the controller 405 may drive or transmit a signal on each of the data lines 415 using one or more transmitters 425 .

[0117] For example, the first transmitter 425-a or the second transmitter 425-b or both may be configured to transmit data to be written to a memory cell array (not shown) at the memory device 410. The memory device 410 may include one or more receivers 430 (e.g., including the first receiver 430-a and the second receiver 430-b) configured to receive signals transmitted by the controller 405. As shown, the EDC line 420 may be located between the data line 415-a and the data line 415-b. As such, signaling sent from the memory device 410 to the controller 405 via the EDC line 420 may generate crosstalk on one or more data lines 415 (e.g., the data line 415-a or the data line 415-b or another data line 415 not shown or any combination thereof).

[0118] In some cases, the system 400 may implement techniques to reduce or eliminate crosstalk 435 from the EDC line 420 to the data line 415. For example, the memory device 410 may shift an aggressor signal (e.g., transmitted via the EDC line 420) in time relative to a victim signal (e.g., on an adjacent data line) to reduce crosstalk in the system 400. For example, a timing offset (or programmable delay) may be added to the EDC feedback path (corresponding to an EDC pin) from the memory device 410 to the controller 405. The timing offset on the EDC path may move or adjust the edges of the EDC signal relative to the edges of the signal received via the data line 415.

[0119] Accordingly, the timing offset can adjust the timing of EDC signaling (e.g., checksum information, transmission error information, timing signals, clock-like patterns) from the memory device 410 so that the crosstalk 435 experienced on the data lines 415-a and 415-b can be minimized and the data eye can be optimized accordingly. Specifically, by offsetting the edges of the data signal sent on the data line 415 and the edges of the information sent on the EDC line 420, the coupling between the two signals can be minimized, thereby minimizing interference from the crosstalk 435.

[0120] As an illustrative example, memory device 410 may calculate a checksum 440 using data received on one or more data lines 415. The checksum may thus have a timing offset 445 (or programmable delay (d)) applied prior to transmission. For example, the time offset may be introduced into the signal using one or more inverters. However, it should be understood that any method for introducing a delay into the transmission path may be used. The offset signal (e.g., a signal with a timing offset applied) may then be transmitted to controller 405 via EDC line 420 using transmitter 450.

[0121] In some cases, the timing offset applied to the EDC signaling may be selected from a set of predefined timing offsets. For example, the memory device 410 may support multiple timing offsets that may be applied to the EDC signal, and the various timing offsets may be stored at the memory device 410 by a mode register. In such cases, one or more mode registers used by the memory device 410 may define different timing offsets, and different delay steps or offsets may be selected, which may, for example, select (e.g., add) or deselect (e.g., remove) inverters from the transmit path to apply a desired delay. That is, the transmit path may have a set of inverters that may be dynamically selected to achieve a programmable delay in the signaling. Thus, the timing of the EDC signaling may be shifted in time relative to the timing of the data transmission on the one or more data lines 415.

[0122] The predefined timing offsets may be configured based on various conditions at the memory device 410. For example, various EDC output timings may be configured to achieve the lowest crosstalk 435 (and corresponding largest data eye) from the EDC signal based on array-specific conditions of the memory device 410.

[0123] For example, the timing offset may be configured based on the speed at which the system 400 is running (e.g., operating speed, clock speed) or the temperature at which the system 400 is running, etc. In some cases, a certain number of capabilities may be stored in the mode register (e.g., driver strength of an off-chip driver (OCD), termination offset), which may be adjusted based on various conditions at the memory device 410, and these capabilities may be modified to find a timing offset that minimizes crosstalk. In some examples, predefined timing offsets may be stored in the BIOS and may be loaded into the mode register after the system is booted. Thus, when the system 400 boots up, the driver strength and termination offset may be identified, and a preferred timing offset may be selected from the mode register based on, among other parameters, these parameters, and used to minimize the crosstalk 435.

[0124] Figure 5 A process flow 500 is shown for supporting a transmit fault feedback scheme for reducing crosstalk according to examples disclosed herein. In some examples, aspects of the process flow 500 may be implemented by a controller 505 and a memory device 510, which may be referenced Figure 1-4 For example, the controller 505 may be a reference Figure 1 The example of the external memory controller 105 described above (eg, a GPU). In addition, the memory device 510 may be a reference Figure 1 An example of a memory device 110 is described. The process flow 500 may illustrate the use of one or more channels other than the EDC channel used to transmit EDC feedback information to the controller 505.

[0125] For example, at 515, the controller 505 may transmit and the memory device 510 may receive data to be written to the memory cell array via one or more data channels (e.g., corresponding to data lines) coupled to the memory device 510. In some cases, the data may be transmitted via a common data channel coupling the controller 505 and the memory device 510. In some examples, the one or more data channels may be examples of the data channels 190 described herein and may be unidirectional or bidirectional data channels.

[0126] At 520, the controller 505 may transmit and the memory device 510 may receive checksum information for the transmitted data. In some cases, the checksum information may be transmitted via an EDC channel coupled to the memory device 510 (eg, corresponding to a data line).

[0127] At 525, the memory device 510 may generate a checksum of the data received via each of the one or more data channels. For example, the memory device 510 may generate the checksum by partitioning the set of bits representing the received data and the set of bits representing the generator polynomial, where the remainder of the operation may include the checksum. In some cases, the checksum may be generated using software or hardware.

[0128] At 530, the memory device 510 may compare the generated checksum of the received data with the received checksum information. In some cases, due to the technology implemented in the system to reduce crosstalk by reducing or modifying the feedback signaling made by the memory device 510, and as described herein Figure 3 As described, errors detected via comparison may be relatively infrequent. If no errors are detected in the received data, the data may be written to the memory cell array at memory device 510.

[0129] However, in some cases, the memory device 510 may detect errors in the data based on the checksum information at 535. For example, detecting an error may be based on a comparison of a generated checksum of the received data with the received checksum information. If the compared checksums are different, an error in the received data may be identified. Thus, the memory device 510 may calculate the difference between the generated checksum and the received checksum information based on comparing the respective checksums to identify a fault in the received data.

[0130] At 540, based on detecting the error in the received data, memory device 510 may transmit transmission failure information indicating the error in the data to controller 505. In some cases, the transmission failure information may be transmitted via a first channel coupled to controller 505, where the first channel is different from the EDC channel.

[0131] Additionally or alternatively, the transmission failure information may be transmitted via the EDC channel. In the event that the EDC channel is not used, the memory device 510 may prevent the transmission of information to the controller 505 via the EDC channel to further minimize or eliminate crosstalk in the system. In some examples, the indication may include a logic value (e.g., a single bit providing a 1 or 0), and / or may indicate to the controller 505 whether the data transmitted at 515 was successfully received without error. As an example, a logic value of 1 (or alternatively, 0) may serve as a flag for the controller 505 that the data received at the memory device 510 failed.

[0132] At 545, the memory device 510 may also transmit a clock signal via a second channel coupled to the controller 505. The second channel may also be different from the EDC channel, and the clock signal may have a frequency that is different (e.g., lower) than the frequency of the received data. In other words, the clock signal may be a low speed tracking clock signal (e.g., a low swing differential signal or a holdover type or both) and may be used by the controller 505 to track the timing of the memory device 510.

[0133] In some cases, the clock signal and the transmit failure information may be transmitted via the same channel (e.g., a channel other than the EDC channel). In such cases, the clock signal and the transmit failure information may each be modulated in a different manner so that the controller 505 can identify each type of signal being sent by the memory device 510 based on the modulation used for the clock signal or the transmit failure information, or both.

[0134] At 550, memory device 510 may receive a retransmission of data to be written to the memory cell array from controller 505 based on the transmission failure information indicating the error. Memory device 510 may then continue writing data (eg, to the memory cell array at memory device 510) according to the access operation.

[0135] Figure 6 A process flow 600 is shown for supporting a transmit fault feedback scheme for reducing crosstalk according to examples disclosed herein. In some examples, aspects of the process flow 600 may be implemented by a controller 605 and a memory device 610, which may be referenced Figure 1-5 For example, the controller 605 may be a reference Figure 1 The example of the external memory controller 105 described above (eg, a GPU). In addition, the memory device 610 may be a reference Figure 1 An example of a memory device 110 is described. Process flow 600 may illustrate the use of a timing offset for signals transmitted via an EDC channel.

[0136] At 615, the controller 605 and the memory device 610 may perform an initialization sequence during which the memory device 610 may receive information setting one or more preconfigured timing offsets for transmitting EDC information. At 620, the memory device 610 may store the preconfigured timing offsets in a mode register configured by the controller 605.

[0137] At 625, the controller 605 may transmit and the memory device 610 may receive data to be written to the memory cell array of the memory device 610, wherein the data may be received via one or more data channels (e.g., corresponding to data lines). At 630, the memory device 610 may generate a checksum of the data received via each of the one or more data channels. At 635, the memory device 610 may determine a timing offset for transmitting the generated checksum. In some cases, the timing offset may be selected from the one or more predetermined timing offsets, such as stored in the mode register at 620.

[0138] At 640, the memory device may transmit the checksum at a transmission time that is shifted according to the timing offset. The checksum may be transmitted to the controller 605 via the EDC channel. In such cases, a timing offset (or delay) may be applied to the checksum transmission so that the transmission is shifted relative to the data received from the controller 605. By transmitting the checksum to the controller at the shifted transmission time, crosstalk from the EDC channel onto the data channel may be reduced or minimized.

[0139] Based on receiving the checksum information from the memory device 610, the controller 605 may determine whether the data received by the memory device 610 has failed by comparing the checksum received from the memory device 610 with the checksum generated by the controller 605 at 645. In the event that the data received by the memory device 610 has failed, the controller 605 may retransmit the data (e.g., at least a portion of the data received with errors) to the memory device 610. Alternatively, if the checksum comparison passes (e.g., the respective checksums are the same), the controller 605 may determine that the data transmitted at 625 was received at the memory device 610 without errors.

[0140] Figure 7 A flowchart is shown according to an example disclosed herein, which illustrates a method 700 for supporting a transmit failure feedback scheme for reducing crosstalk. The operations of the method 700 may be implemented by a memory device or a component thereof, such as reference Figure 1-6 For example, the operations of method 700 may be performed by memory device 310, as described in reference Figure 3 In some examples, a memory device may execute a set of instructions or codes to control functional elements of the memory device to perform the functions described herein.

[0141] At 705, the memory device may receive data to be written to the memory cell array of the memory device from the controller via a set of data lines. In some examples, the data may be received via one data line, or via multiple data lines (e.g., channels), which may correspond to one or more DQ pins. Figure 1-6 The method described performs the operation of 705 .

[0142] At 710, the memory device may receive checksum information for the data received via the plurality of data lines via an EDC line coupled to the controller. In some cases, the checksum information may be received simultaneously with the data received from the controller via the set of data lines, or may be received at a different time than the data is transmitted. In some examples, the checksum information may be a CRC checksum of the data transmitted by the controller, or may be another type of error detection code calculated by the controller. Figure 1-6 The method described performs the operation of 710 .

[0143] At 715, the memory device may detect errors in the data based on the checksum information. In some cases, the memory device may generate a checksum of the data received on the set of data lines, and may compare the generated checksum with the checksum information received from the controller to detect errors in the received data. Figure 1-6 The method described performs the operation of 715.

[0144] At 720, the memory device may transmit transmit failure information indicating an error in the data to the controller based at least in part on detecting the error in the data. The transmit failure information may provide an indication of whether an error is detected in the data received via the set of data lines. For example, the indication may include a bit value (e.g., 0 or 1) that acts as a flag to the controller that an error is detected based on a checksum comparison. The reference may be used to determine whether an error is detected in the data received via the set of data lines. Figure 1-6 The method described performs the operation of 720.

[0145] In some examples, an apparatus as described herein may perform one or more methods, such as method 700. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving data to be written to a memory cell array of a memory device from a controller via a set of data lines; receiving, by the memory device, via an EDC line coupled to the controller, checksum information of the data received via the set of data lines; detecting, by the memory device, an error in the data based on the checksum information; and transmitting, to the controller, transmission fault information indicating an error in the data based on detecting the error.

[0146] Some instances of the method 700, apparatus, and non-transitory computer-readable media described herein may further include operations, features, components, or instructions for: generating a checksum of data received via each data line of a set of data lines; and comparing the generated checksum of the received data with received checksum information, wherein detecting an error may be based on comparing the generated checksum of the received data with the received checksum information.

[0147] Some instances of the method 700, apparatus, and non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for determining a difference between a generated checksum and received checksum information based on comparing the generated checksum to the received checksum information, wherein detecting an error in the received data may be based on the determined difference between the generated checksum and the received checksum information.

[0148] Some examples of the method 700, apparatus, and non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for: transmitting the transmission fault information via a first line coupled to the controller, the first line being different from the EDC line. Some examples of the method 700, apparatus, and non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for: preventing the use of the EDC line to transmit a signal to the controller based on the transmission fault information transmitted via the first line.

[0149] Some examples of the method 700, apparatus, and non-transitory computer-readable medium described herein may further include operations, features, means, or instructions for transmitting a clock signal via a second line coupled to the controller, the second line being different from the EDC line, wherein the clock signal may have a first frequency that may be lower than a second frequency of the received data. In some examples of the method 700, apparatus, and non-transitory computer-readable medium described herein, the clock signal includes a low swing differential signal or a holdover type or both.

[0150] Some instances of the method 700, apparatus, and non-transitory computer-readable media described herein may further include operations, features, components, or instructions for: transmitting the transmission fault information via a first line coupled to a controller, the first line being different from the EDC line, wherein the transmission fault information may be transmitted using a first modulation scheme; and transmitting a clock signal via a first line coupled to the controller, wherein the clock signal may be transmitted using a second modulation scheme different from the first modulation scheme.

[0151] In some examples of the method 700, apparatus, and non-transitory computer-readable medium described herein, the clock signal includes a hold pattern. Some examples of the method 700, apparatus, and non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for the following operations: receiving a retransmission of data to be written to the memory cell array from a controller based on transmission failure information indicating an error. Some examples of the method 700, apparatus, and non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for the following operations: transmitting a logic value indicating an error detected in the received data.

[0152] Figure 8 A flowchart is shown according to an example disclosed herein, which illustrates a method 800 for supporting a transmit failure feedback scheme for reducing crosstalk. The operations of the method 800 may be implemented by a memory device or a component thereof, such as reference Figure 1-6 For example, the operations of method 800 may be performed by memory device 410, as described in reference Figure 4 In some examples, a memory device may execute a set of instructions or codes to control functional elements of the memory device to perform the functions described herein.

[0153] At 805, the memory device may receive data to be written to the memory cell array of the memory device from the controller via a set of data lines. In some examples, the data may be received via one data line, or via multiple data lines (or channels) (eg, corresponding to one or more DQ pins). Figure 1-6 The method described here performs the operation of 805 .

[0154] At 810, the memory device may determine a timing offset for transmitting a clock signal (or clock-like pattern) and a checksum of the data. For example, the timing offset may be selected for transmitting the clock signal and / or the checksum based on the timing of the data received at the memory device. In this way, the timing offset may shift the transmission timing of the clock signal and / or the checksum so as to minimize crosstalk. The timing offset may be selected based on the reference signal. Figure 1-6 The method described performs the operation of 810.

[0155] At 815, the memory device may transmit the checksum to the controller at a transmit time shifted according to the timing offset. That is, the selected timing offset may be applied to the transmit path for transmitting the checksum. Figure 1-6 The method described is to perform the operation of 815.

[0156] In some examples, an apparatus as described herein may perform one or more methods, such as method 800. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving data to be written to a memory cell array of a memory device from a controller via a set of data lines; determining, by the memory device, a timing offset for transmitting a checksum of a clock signal and data; and transmitting the checksum to the controller at a transmission time shifted according to the timing offset.

[0157] Some examples of the method 800, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for selecting the timing offset from one or more preconfigured timing offsets, wherein each preconfigured timing offset may be based on an operating condition at the memory device.

[0158] Some instances of the method 800, apparatus, and non-transitory computer-readable media described herein may further include operations, features, components, or instructions for receiving configuration information for setting the one or more preconfigured timing offsets during an initialization sequence, wherein selecting the timing offset from the one or more preconfigured timing offsets may be based on the configuration information.

[0159] Some examples of the method 800, apparatus, and non-transitory computer-readable medium described herein may further include operations, features, means, or instructions for: storing the one or more pre-configured timing offsets in a mode register configurable by a controller. In some examples of the method 800, apparatus, and non-transitory computer-readable medium described herein, the operating condition includes a data termination state or a driver strength or both.

[0160] Fig. 9 A flowchart is shown according to an example disclosed herein, which illustrates a method 900 for supporting a transmit failure feedback scheme for reducing crosstalk. The operations of the method 900 may be referred to as Figure 1-6 For example, the operations of method 900 may be performed by the controller or components described herein. Figure 3 The controller 305 described or as referenced Figure 4 The controller 405 described here performs. In some examples, the controller may execute a set of codes to control functional elements of a device (eg, memory device 310, which may include memory device 110) to perform the functions described herein.

[0161] At 905, the controller may transmit data to be written to the memory cell array via a set of data lines coupled to the memory device. That is, the data may be transmitted by the controller as part of a write operation (eg, including a gapless write cycle). Figure 1-6 The method described performs the operation of 905 .

[0162] At 910, the controller may transmit checksum information for the transmitted data via an EDC line coupled to the memory device. In some cases, the checksum information may be transmitted simultaneously with the data transmission. Figure 1-6 The method described performs the operation of 910.

[0163] At 915, the controller may receive transmission error information indicating an error in the data from the memory device based on the transmitted checksum information. For example, the memory device may identify a transmission error based on the checksum provided by the controller. In some cases, the controller may determine to rewrite the failed data based on the received transmission error information and the indicated error. Figure 1-6 The method described is to perform the operation of 915.

[0164] In some examples, an apparatus as described herein may perform one or more methods, such as method 900. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: transmitting data to be written to a memory cell array via a set of data lines coupled to a memory device; transmitting checksum information of the transmitted data via an EDC line coupled to the memory device; and receiving transmission failure information indicating an error in the data from the memory device based on the transmitted checksum information.

[0165] Some examples of the method 900, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for receiving transmit fault information via a first line coupled to a memory device, the first line being different from an EDC line.

[0166] Some examples of the method 900, apparatus, and non-transitory computer-readable media described herein may further include operations, features, components, or instructions for receiving a clock signal via a second line coupled to the memory device, the second line being different from the EDC line, wherein the clock signal may have a first frequency that is different from a second frequency of the received data.

[0167] Some examples of the method 900 , apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for retransmitting data to be written to the memory cell array based on the transmission failure information indicating an error.

[0168] Some examples of the method 900, apparatus, and non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for: receiving transmission failure information and a clock signal via a first line coupled to a memory device. Some examples of the method 900, apparatus, and non-transitory computer-readable medium described herein may further include operations, features, components, or instructions for: decoding the transmission failure information using a first modulation scheme, and decoding the clock signal using a second modulation scheme different from the first modulation scheme.

[0169] It should be noted that the methods described herein describe possible embodiments, and that the operations and steps may be rearranged or otherwise modified, and other embodiments are possible. Furthermore, two or more aspects from the methods may be combined.

[0170] In some examples, an apparatus or device may perform aspects of the functionality described herein. In some cases, the device may include: a memory cell array; a receiver coupled to a set of data lines and an EDC line, the receiver configured to receive data to be written to the memory cell array via the set of data lines and receive checksum information about the data received via the set of data lines; a comparator configured to detect an error in the data based on the checksum information; and one or more lines coupled to a controller and configured to transmit at least one of a clock signal or transmission failure information indicating an error detected in the data, the one or more lines being different from the EDC line.

[0171] In some examples, the device may include a first transmitter coupled to a first line of the one or more lines. The first transmitter is configured to transmit the transmission failure information via the first line of the one or more lines. In some cases, the device may include a clock, and a second transmitter coupled to a second line of the one or more lines, the second transmitter being configured to transmit a signal from the clock via the one or more lines.

[0172] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may show a signal as a single signal; however, one of ordinary skill in the art will understand that the signal may represent a signal bus, where the bus may have a variety of bit widths.

[0173] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device including the connected components, the conductive path between the components that are electronically connected (or in conductive contact or connected or coupled) to each other may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some cases, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0174] The term "coupled" refers to a condition of moving from an open circuit relationship between components, in which signals are currently unable to be transmitted between components via conductive paths, to a closed circuit relationship between components, in which signals are able to be transmitted between components via conductive paths. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between other components via conductive paths that previously did not permit signal flow.

[0175] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between them. For example, components separated by a switch positioned between two components are isolated from one another when the switch is open. When a controller isolates two components, the controller implements a change that prevents a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0176] As used herein, the term "substantially" means that the modified property (eg, a verb or adjective modified by the term substantially) is not necessarily absolute but is close enough so as to achieve the advantage of the property.

[0177] The devices including memory arrays discussed herein may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping means.

[0178] The switch component or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components via conductive materials such as metals. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., most carriers are signals), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0179] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred to" or "superior to" other examples. The specific implementation includes specific details that provide an understanding of the described technology. However, these technologies may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0180] In the drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dashed line and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0181] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0182] The various illustrative blocks and modules described in conjunction with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor; however, in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a combination of multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0183] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of the software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. The features of the implementation functions may also be physically located at various locations, including being distributed so that the various parts of the functions are implemented at different physical locations. Also, as used herein, included in the claims, the "or" used in the list of items (e.g., a list of items starting with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that (for example) a list of at least one of A, B, or C means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be understood to refer to a closed set of conditions. For example, without departing from the scope of the present disclosure, the exemplary steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0184] Computer-readable media include both non-transitory computer storage media and communication media, and the communication media include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device, or can be used to carry or store the desired program code components in the form of instructions or data structures and can be accessed by a general or special computer or a general or special processor. Any other non-transitory medium. And, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are used to transmit software from a website, server or other remote source, the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are included in the definition of medium. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0185] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for reducing crosstalk, comprising: receiving, by a memory device via a plurality of data lines from a controller, data to be written to a memory cell array of the memory device as part of a write operation; receiving, by the memory device during the write operation via a first line coupled to the controller, checksum information for the data received via the plurality of data lines; detecting, by the memory device, an error in the data based at least in part on the checksum information and the write operation; as well as Transmitting transmission failure information for the write operation indicating the error in the data from the memory device to the controller based at least in part on detecting the error, wherein the transmission failure information for the write operation is transmitted via a second line coupled to the memory device and the controller, the second line being different from the first line.

2. The method according to claim 1, further comprising: generating a checksum of the data received via each data line of the plurality of data lines; as well as A generated checksum of the received data is compared to received checksum information, wherein detecting the error is based at least in part on comparing the generated checksum of the received data to the received checksum information.

3. The method according to claim 2, further comprising: A difference between the generated checksum and the received checksum information is determined based at least in part on comparing the generated checksum to the received checksum information, wherein detecting the error in the received data is based at least in part on the determined difference between the generated checksum and the received checksum information.

4. The method according to claim 1, further comprising: Transmitting a signal to the controller using the first line is prevented based at least in part on the transmit failure information transmitted via the second line.

5. The method according to claim 1, further comprising: A clock signal is transmitted via a third line coupled to the controller, the third line being different from the first line, wherein the clock signal has a first frequency lower than a second frequency of the received data.

6. The method of claim 5, wherein the clock signal comprises a low swing differential signal or a hold type or both.

7. The method according to claim 1, wherein the transmission failure information is transmitted using a first modulation scheme, the method further comprising: A clock signal is transmitted via the second line coupled to the controller, wherein the clock signal is transmitted using a second modulation scheme different from the first modulation scheme. The method of claim 7 , wherein the clock signal comprises a hold pattern.

9. The method according to claim 1, further comprising: A retransmission of the data to be written to the memory cell array is received from the controller based at least in part on the transmit failure information indicative of the error.

10. The method according to claim 1, further comprising: Transmits a logic value indicating a detected error in the received data. The method of claim 1 , wherein the first line comprises an error detection code (EDC) line.

12. A method for reducing crosstalk, comprising: receiving, by a memory device via a plurality of data lines from a controller, data to be written to a memory cell array of the memory device; determining, by the memory device, a timing offset for transmitting a checksum of the data, wherein the timing offset is programmed by a plurality of mode registers; as well as The checksum is transmitted from the memory device to the controller at a transmission time that is shifted according to the timing offset.

13. The method according to claim 12, further comprising: The timing offset is selected from one or more preconfigured timing offsets, wherein each preconfigured timing offset is based at least in part on operating conditions at the memory device.

14. The method according to claim 13, further comprising: Configuration information setting the one or more preconfigured timing offsets is received during an initialization sequence, wherein selecting the timing offset from the one or more preconfigured timing offsets is based at least in part on the configuration information.

15. The method according to claim 13, further comprising: The one or more preconfigured timing offsets are stored in a first mode register of the plurality of mode registers.

16. The method of claim 13, wherein the operating condition comprises a data termination state or a driver strength or both.

17. A method for reducing crosstalk, comprising: transmitting, from a controller and via a plurality of data lines coupled to a memory device, data to be written to an array of memory cells of the memory device as part of a write operation; transmitting checksum information for the transmitted data via a first line coupled to the memory device; as well as Based at least in part on the transmitted checksum information, transmit failure information for the write operation is received from the memory device by the controller indicating an error in the data, wherein the transmit failure information for the write operation is received via a second line coupled to the controller and the memory device, the second line being different from the first line.

18. The method according to claim 17, further comprising: A clock signal is received via a third line coupled to the memory device, the third line being different from the first line, wherein the clock signal has a first frequency different from a second frequency of the received data.

19. The method of claim 17, further comprising: The data to be written to the memory cell array is retransmitted based at least in part on the transmission failure information indicating the error.

20. The method of claim 17, wherein the transmit fault information and a clock signal are received via the second line coupled to the memory device, the method further comprising: decoding the transmission failure information using a first modulation scheme; as well as The clock signal is decoded using a second modulation scheme different from the first modulation scheme.

21. The method of claim 17, wherein the first line comprises an error detection code (EDC) line.

22. An apparatus for reducing crosstalk, comprising: a memory cell array; a receiver coupled to the plurality of data lines and the first line, the receiver being configured to receive data to be written to the memory cell array via the plurality of data lines as part of a write operation and to receive checksum information during the write operation, the checksum information being related to the data received via the plurality of data lines; a comparator configured to detect an error in the data based at least in part on the checksum information and the write operation; as well as One or more lines coupled to a controller and configured to transmit, from the device to the controller, transmission failure information of the write operation indicating an error detected in the data, the one or more lines being different from the first line.

23. The apparatus of claim 22, further comprising: A first transmitter is coupled to a second line of the one or more lines, and the first transmitter is configured to transmit the transmission failure information via the second line of the one or more lines.

24. The apparatus of claim 22, further comprising: clock; as well as A second transmitter is coupled to a second line of the one or more lines, the second transmitter being configured to transmit a signal from the clock via the one or more lines.

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