write zero data

Abstract

The present disclosure relates to writing zero data. Disclosed are devices, methods of operating devices, interconnects for connecting devices to each other, and methods of operating interconnects. A host device can issue an individual all-zero data write transaction to an interconnect that specifies a data storage location, the interconnect communicates the individual all-zero data write transaction to a target device, and the target device writes all-zero data at the data storage location. No write data is conveyed with the individual all-zero data write transaction, so the individual all-zero data write transaction can be used to clear the data storage location without increasing congestion of write data lanes in the interconnect.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to data processing. In particular, the present disclosure relates to transactions carried on an interconnect. BACKGROUND

[0002] An interconnect of a data processing system can be required to carry many kinds of transactions between components of the system that are connected to each other via the interconnect. These transactions can include write transactions, read transactions, data coherency commands, and so on. Various interconnect transactions carry data, for example transmitted via a dedicated data bus, either as a result of a read transaction (sending the data to the device that issued the read transaction) or as write data (sending the data from the device that issued the write transaction to the destination to which the data should be written). Thus, as the size and complexity of such data processing systems increases and as the interconnect connects more and more devices together, the transmission of read and write data around the data processing system can become an important factor for the data processing system in terms of bandwidth and power consumption. SUMMARY

[0003] In one example embodiment described herein, there is provided an apparatus comprising: an interconnect interface; and an interconnect protocol signal generation circuit, wherein the interconnect protocol signal generation circuit is arranged to provide an individual all-zeros data write transaction specifying a data storage location to the interconnect interface, and the interconnect interface is responsive to the provision of the individual all-zeros data write transaction to cause the individual all-zeros data write transaction to be transmitted via the interconnect to a target device comprising the data storage location, to cause the target device to write all-zeros data at the data storage location.

[0004] In one example embodiment described herein, there is provided an apparatus comprising: an interconnect interface; and an interconnect protocol signal reception circuit, wherein the interconnect protocol signal reception circuit is responsive to an individual all-zeros data write transaction specifying a data storage location in the apparatus received from the interconnect interface to write all-zeros data at the data storage location.

[0005] In one example embodiment described herein, there is provided an interconnect system comprising: a master device; an interconnect; and a slave device, wherein the interconnect is responsive to an individual all-zeros data write transaction specifying a data storage location in the slave device received from the master device to communicate the individual all-zeros data write transaction to the slave device to cause the slave device to write all-zeros data at the data storage location.

[0006] In one example embodiment described herein, there is provided a method of operating an interconnect system, the method comprising the steps of: receiving in the interconnect an individual all-zeros data write transaction specifying a data storage location in a slave device from a master device; and communicating the individual all-zeros data write transaction to the slave device to cause the slave device to write all-zeros data at the data storage location.

[0007] In one example embodiment described herein, there is provided a method of operating an apparatus, the method comprising the steps of: generating an individual all-zeros data write transaction specifying a data storage location; providing the individual all-zeros data write transaction to an interconnect interface; and sending the individual all-zeros data write transaction to a target device comprising the data storage location via the interconnect to cause the target device to write all-zeros data at the data storage location. BRIEF DESCRIPTION OF DRAWINGS

[0008] The application will be further described, by way of example only, with reference to embodiments thereof illustrated in the following drawings in which:

[0009] Figure 1A schematically illustrates an apparatus arranged to generate all-zeros data write transactions according to some embodiments;

[0010] Figure 1B schematically illustrates an apparatus arranged to receive all-zeros data write transactions according to some embodiments;

[0011] Figure 2 schematically illustrates a data processing system in some embodiments in which an interconnect is arranged to communicate all-zeros data write transactions from a master device to a slave device;

[0012] Figure 3 schematically illustrates a 6x6 mesh topology interconnect in some embodiments;

[0013] Figure 4 schematically illustrates a data processing system comprising multiple levels of cache according to some embodiments;

[0014] Figure 5 schematically illustrates an example lane used in an interconnect of some embodiments;

[0015] Figure 6A and 6B schematically illustrates a master device issuing a c to a target slave device according to some embodiments, where the transaction is communicated via a home node;

[0016] Figure 7 schematically illustrates a data processing system in some example embodiments in which a master device references an address translation cache when performing its data processing operations and invalidates entries of the address translation cache on context switch;

[0017] Figure 8 schematically illustrates a data processing system in some example embodiments in which a snoop operation is performed;

[0018] Figure 9AVarious ways in which data storage location designations for all-zero data write transactions are specified in some embodiments are illustrated;

[0019] Figure 9B A multi-chip system in which all-zero data write transactions can be sent between component chips in some embodiments is schematically illustrated;

[0020] Figure 10 is a sequence of steps taken in the method of some embodiments when a master device undergoes a context switch; and

[0021] Figure 11 is a flowchart illustrating a sequence of steps taken according to the method of some embodiments when a slave device receives a transaction including an all-zero data write transaction in some example embodiments. DETAILED DESCRIPTION

[0022] Before the embodiments are discussed with reference to the drawings, the following description of the embodiments is provided.

[0023] According to one example configuration, there is provided an apparatus comprising: an interconnect interface; and an interconnect protocol signal generation circuit, wherein the interconnect protocol signal generation circuit is arranged to provide, to the interconnect interface, an individual all-zero data write transaction designating a data storage location, and the interconnect interface is responsive to the provision of the individual all-zero data write transaction to cause the individual all-zero data write transaction to be sent via the interconnect to a target device comprising the data storage location, to cause the target device to write all-zero data at the data storage location.

[0024] Thus, by the use of individual all-zero data write transactions, the apparatus can cause "all-zero" data to be written at a designated data storage location. Thus, in contrast to conventional write transactions which both designate a data storage location and explicitly provide data to be written at the data storage location, the apparatus only needs to send an individual all-zero data write transaction which designates this type of write transaction and the data storage location, and does not require an explicit data provision. As a result, the recipient of the transaction (i.e. the target device in which the data storage location is to be found) can then respond by zeroing the data storage location completely, without requiring any explicit provision of data (e.g. a complete set of zeros corresponding to the capacity of the data storage location). This provides an efficient mechanism to zero a designated data storage location, which in particular does not require the transmission of data between the issuer of the transaction and its recipient. This is beneficial in many data processing contexts, as data bandwidth is often at a premium, and the power consumed by the data processing system is reduced (relative to conventional data write transactions) as the data bus is not used.

[0025] The all-zero data write transaction can be applicable in a wide variety of scenarios, but in some embodiments the apparatus further comprises data processing circuitry to perform data processing operations, wherein the data processing operations comprise access to data storage locations, and wherein when the data processing operations undergo a context switch from the first context to the second context, the data processing circuitry controls the interconnect protocol signal generation circuitry to provide, in response to the context switch, an individual all-zero data write transaction to the interconnect interface specifying a data storage location. The use of the all-zero data write transaction thereby supports the security of data processed by the data processing operations in the first context, ensuring that the data storage location is completely zeroed when the data processing operations undergo a context switch from the first context to the second context.

[0026] In some embodiments the data processing operations of the first context comprise access to a plurality of data storage locations, and wherein when the data processing operations undergo a context switch from the first context to the second context, the data processing circuitry controls the interconnect protocol signal generation circuitry to provide, in response to the context switch, one or more individual all-zero data write transactions to the interconnect interface specifying a plurality of data storage locations. The all-zero data write transactions can thereby be used to efficiently zero all data storage locations used by the data processing operations in the first context when they switch to the second context. The security of data accessed by these data processing operations in the first context is thereby ensured for the second context.

[0027] The context switch can take a variety of forms, but in some embodiments the context switch comprises at least one of: a process switch; a thread switch; a switch to a virtual machine; and a switch from a secure context to a non-secure context. The present technology is not limited to use within any particular kind of context switch, and the ability to efficiently clear data storage location(s) can have applicability in a wide range of scenarios.

[0028] The target of the all-zero data write transaction can be variously specified, and the data storage location can be an individual data storage location having the smallest addressable granularity of the data processing system, while in other examples the transaction can specify a plurality of memory addresses. In some embodiments therefore the interconnect protocol signal generation circuitry is arranged to provide an individual all-zero data write transaction specifying a set of memory addresses including the data storage location. When this all-zero data write transaction is received, all memory addresses within the set of memory addresses will thereby be caused to be zeroed.

[0029] The set of memory addresses can be variously defined, but in some embodiments the set of memory addresses corresponds to a cache line including the data storage location.

[0030] Transactions can variously specify multiple memory addresses, where these memory addresses can be specified individually, or in some embodiments the interconnect protocol signal generation circuitry is arranged to provide individual all-zeros data write transactions that specify a range of memory addresses comprising data storage locations. Thus, when such an all-zeros data write transaction is received, any memory addresses falling within the specified range of memory addresses will be zeroed.

[0031] In some embodiments, the data processing circuitry is arranged to access data storage locations in data processing operations in dependence on address translations defined in the address translation cache, and wherein the data processing circuitry is further responsive to a context switch to cause the address translation definitions for the data storage locations to be invalidated. Thus, by the above mechanism, it can be provided that memory locations are both cleared (zeroed) and invalidated at the occurrence of a context switch, thereby further supporting the security demarcation between the first and second contexts.

[0032] The apparatus can be provided within a data processing system having a plurality of master devices that share access to certain data storage locations, so that consistent operations can be implemented to ensure data consistency across the distributed system. In this context, in some embodiments the interconnect protocol signal generation circuitry is arranged to provide, to the interconnect interface, individual all-zeros data write transactions as individual all-zeros data write unique transactions that specify data storage locations, and wherein the interconnect interface is responsive to provision of the individual all-zeros data write unique transactions to cause the individual all-zeros data write unique transactions to be sent via the interconnect to a target device to cause a snoop operation in the interconnect to be performed on any copies of data from the data storage locations that are held in other devices connected to the interconnect. Provision of this particular type of transaction provided by the present technology thus enables the apparatus to specify certain transactions, particularly with respect to certain data storage locations, that require a snoop operation to be performed for those data storage locations.

[0033] Similarly, in some embodiments the interconnect protocol signal generation circuitry is arranged to provide to the interconnect interface an individual all-zeros data write transaction as a specified data storage location individual all-zeros data write no-snoop transaction, and wherein the interconnect interface, in response to provision of the individual all-zeros data write no-snoop transaction, causes the individual all-zeros data write no-snoop transaction to be transmitted to a target device via the interconnect without triggering a snoop operation in the interconnect. Thus, this class of transaction of the present technology enables a device to explicitly specify that no snoop operation is required. In a cache coherent data processing system having a plurality of devices that interact with each other, some cache coherency operations will be required, but in certain regions of the system, this is not required. These cache coherency operations themselves require various transactions to be exchanged by the system components, thereby increasing the overall transaction bandwidth consumption, and it is beneficial, when possible, to avoid increasing this bandwidth consumption. Thus, the efficient transactional basis of these regions is supported by the write no-snoop class of transaction of the present technology, which does not trigger a snoop operation in the interconnect.

[0034] The interconnect can convey all-zeros data write transactions in a variety of ways, but in some embodiments a predetermined set of signals within the interconnect's multiple paths can be used to specify an "operation code", i.e. a unique combination (bit pattern) of signals that defines the nature of the transaction. Thus in some embodiments the interconnect protocol signal generation circuitry is arranged to provide an individual all-zeros data write transaction by asserting a predetermined operation code among the signals provided to the interconnect interface.

[0035] According to one example configuration there is provided a device comprising: an interconnect interface; and interconnect protocol signal reception circuitry, wherein the interconnect protocol signal reception circuitry, in response to receiving from the interconnect interface an individual all-zeros data write transaction specifying a data storage location in the device, writes all-zeros data at the data storage location.

[0036] Thus a device that receives an all-zeros data write transaction is efficiently communicated to, as it only requires identification of the nature of the transaction (i.e. that it is an "all-zeros data write" transaction) and a specified data storage location, and in response it writes all-zeros data at the data storage location. It is thus noted that when such an interconnect transaction is received, the recipient ignores any data provided on the write data bus, as this is not required for the transaction that is specified to be performed.

[0037] According to one example configuration there is provided an interconnect system comprising: a master device; an interconnect; and a slave device, wherein the interconnect, in response to receiving from the master device an individual all-zeros data write transaction specifying a data storage location in the slave device, communicates the individual all-zeros data write transaction to the slave device to cause the slave device to write all-zeros data at the data storage location.

[0038] In some embodiments, the interconnect system further comprises: an intermediate hub device coupled to the interconnect, wherein the interconnect is responsive to receiving an individual all-zero data write transaction from the master device to communicate the individual all-zero data write transaction to the intermediate hub device, and the intermediate hub device is responsive to receiving the individual all-zero data write transaction from the master device to communicate the individual all-zero data write transaction to the slave device.

[0039] In some embodiments, the master device is arranged to provide the individual all-zero data write transaction as an individual all-zero data write unique transaction for the specified data storage location, and wherein the intermediate hub device is responsive to receiving the individual all-zero data write unique transaction from the master device to participate in a snoop operation in the interconnect for any copies of data from the data storage location held in other devices connected to the interconnect.

[0040] In some embodiments, the master device is arranged to provide the individual all-zero data write transaction as an individual all-zero data write no-snoop transaction for the specified data storage location, and wherein the intermediate hub device is responsive to receiving the individual all-zero data write no-snoop transaction from the master device to send the individual all-zero data write no-snoop transaction to the slave device via the interconnect without triggering a snoop operation in the interconnect.

[0041] In some embodiments, the intermediate hub device is responsive to receiving the individual all-zero data write unique transaction from the master device to send the individual all-zero data write no-snoop transaction to the slave device via the interconnect. Thus, in the case that the intermediate hub device can be connected to multiple master devices, each of which can have a locally cached copy of data fetched from the data storage location, the intermediate hub device can cause any required snoop operations and cache coherency operations to be performed in response to receipt of the all-zero data write unique transaction. However, the slave device can be "off the coherency point" in the system, such that no snoop operations and cache coherency operations are required for transactions between the intermediate hub device and the slave device. In this case, the intermediate hub device can then send the individual all-zero data write no-snoop transaction to the slave device such that no (further) snoop operations and cache coherency operations are triggered by the transaction sent to the slave device.

[0042] The interconnect can provide connectivity between a number of interacting components, but in some embodiments the interconnect forms a component interconnect of at least one of: a mesh interconnect topology; an intra-chip communication link; and an inter-chip communication link.

[0043] According to one example configuration, there is provided a method of operating an interconnect system, comprising the steps of: receiving in the interconnect an individual all-zero data write transaction from a master device specifying a data storage location in a slave device; and communicating the individual all-zero data write transaction to the slave device to cause the slave device to write all-zero data at the data storage location.

[0044] According to one example configuration, there is provided a method of operating an apparatus, comprising the steps of: generating an individual all-zeros data write transaction specifying a data storage location; providing the individual all-zeros data write transaction to an interconnect interface; and sending the individual all-zeros data write transaction via the interconnect to a target device comprising the data storage location to cause the target device to write all-zeros data at the data storage location.

[0045] A specific embodiment will now be described with reference to the accompanying drawings.

[0046] Figure 1A An apparatus 10 in some embodiments is illustrated schematically. The apparatus comprises data processing circuitry 11 which performs data processing operations and has control over interconnect protocol signal generation circuitry 12. This interconnect protocol signal generation circuitry 12 is arranged to provide transactions to be communicated via an interconnect interface 13 to which the interconnect interface 13 is connected (not shown in the figure) over an interconnect. The data processing circuitry 11 can specifically cause the interconnect protocol signal generation circuitry 12 to generate an all-zeros data write transaction which is to be passed via the interconnect interface 13 onto the interconnect and thereby communicated to a specified target of the transaction. The data processing circuitry 11 can thereby make use of this all-zeros data write transaction to specify a data storage location in a data processing system of which the apparatus 10 forms a part, where in response to receipt of this transaction, a target device comprising the data storage location is to write all-zeros data at the data storage location. Figure 1A

[0047] An apparatus 20 in some embodiments is illustrated schematically. The apparatus 20 is a slave device in a data processing system, and is thereby arranged to receive transactions from other (master) devices, for example the apparatus 10 of Figure 1B Figure 1A The apparatus 20 is arranged to allow access to its stored data by these master devices. The apparatus 20 comprises a data storage 21 which is accessed by other (master) apparatus devices in the data processing system. The apparatus 20 comprises an interconnect interface 23 which receives transactions from an interconnect (not shown in the figure) to which it is coupled and which passes these transactions to interconnect protocol signal reception circuitry 22 of the apparatus 20. The interconnect protocol signal reception circuitry 22 interprets transactions received via the interconnect interface 23 and communicates required information to the data storage 21. Specifically, Figure 1B Figure 1B The apparatus 20 of is arranged to receive all-zeros data write transactions via the interconnect interface 23 and when such a type of transaction is identified by the interconnect protocol signal reception circuitry 22, it causes the data storage location specified in the transaction to have all-zeros data written to it in the data storage 21.

[0048] Figure 2 ​​A data processing system 30 is illustratively shown, comprising a master device 31, an interconnect 32 and a target (slave) device 33. The master device 31 can for example be provided by an apparatus 10 of Figure 1A and the target device 33 can for example be provided by an apparatus 20 of Figure 1B The apparatus 31 comprises data processing circuitry 34 to perform data processing operations and also comprises interconnect protocol signal generation circuitry 35 and an interconnect interface 36. The data processing circuitry 34 has control over the interconnect protocol signal generation circuitry 35 and thereby causes a number of different transactions to be communicated onto the interconnect 32 via the interconnect interface 36. Via the interconnect 32 they are then communicated to their respective targets. The target device 33 represents such a target and comprises a data store 37, where data processing operations of the data processing circuitry 34 of the apparatus 31 access the data store 37. Figure 2 The apparatus 31 is specifically arranged so that the data processing circuitry 34 can cause the interconnect protocol signal generation circuitry 35 to generate an all-zeros data write transaction specifying a data store location in the data store 37 of the target device 33. This transaction is communicated to the target device 33 via the interconnect 32 and in response the target device 33 writes all-zeros data to the specified data store location in the data store 37. Thus, the apparatus 31 has an efficient mechanism by which it can cause a specified location in the data store 37 to be cleared (zeroed) without requiring any explicit data value (e.g. a set of zeros) to be communicated over the interconnect 32. That is, the provision of the all-zeros data write transaction itself is sufficient to cause the target device to zero the data store location, regardless of the state of any data write bus. This has particular benefit because there can be several other master devices connected to the interconnect that are accessing this target device as well as other slave devices in the data processing system. Thus, the data transport bandwidth of the interconnect 32 can easily become congested. The all-zeros data write transaction of the present technique does not contribute to any data bandwidth congestion because no data is required to be communicated with the transaction.

[0049] The potential for data bandwidth congestion can significantly grow in a data processing system having multiple master devices and multiple slave devices. Figure 3 An example data processing system is illustratively shown in which an interconnect is provided in a 6x6 mesh topology (where the nodes of the interconnect are labelled "XP"), with 36 master devices (requester nodes - RNs), 28 intermediate devices (home nodes - HNs), and four slave devices (slave, nodes - SNs) sharing the interconnect lanes. Figure 3The nodes of the system shown in the figure are further labelled as either "F" (fully coherent) or "I" (I / O coherent), such that in addition to data transactions required in the system to support the many data processing operations being performed, data can also be required to be transferred around the system to support coherence operations. In this context, the ability of a requesting device (master) to clear (zero) a specified data storage location without having to provide explicit zero data as part of a transaction has significant benefits in terms of reducing data lane congestion.

[0050] Figure 4 A data processing system 50 in some example embodiments is schematically illustrated. In this example, three CPU devices 51, 52, 53 are shown, each of which is labelled as "RN (master)", indicating that these masters are "requesting nodes" in the system. These masters perform their data processing operations on data values that have been retrieved from a memory 55, which forms part of the data processing system 50. Access to the memory 55 is performed under the control of a memory controller 56, which is labelled as "SN" and is a "slave node" in the system. The CPUs 51, 52, 53 each have their own internal LI cache 57, 58, 59 and also have their own associated L2 cache 60, 61, 62. The CPUs share an L3 cluster cache 65, via which they are connected to an interconnect 66. The interconnect 66 is labelled as "HN", indicating that it is a home node in the system. The interconnect 66 also includes a system level cache 67. It will therefore be appreciated by those skilled in the art that the LI, L2, L3 cluster and system level caches 66, 67 thus represent a cache hierarchy, and that a data value retrieved from the memory 55 can result in a copy of that data value being cached at any or all of the levels of this cache hierarchy. In addition, the CPUs 51, 52, 53 are provided in the system 50 in accordance with the present technology, and thus for example as Figure 1A indicated in the figure. That is, each of the masters 51-53 is arranged to generate transactions which are communicated by the interconnect 66 to a specified target, such as the memory controller 56. The CPUs 51-53 are specifically arranged to generate all-zero data write transactions that specify a data storage location (e.g. within the memory 55). On receipt of such all-zero data write transactions, the memory controller 56 is arranged such that the specified data storage location is written with all-zeros, thereby clearing the storage location. In addition, on receipt of such all-zero data write transactions, the memory controller 56 is arranged to generate a corresponding coherence transaction to the system level cache 67, as Figure 4In the context of the illustratively depicted data processing system 50, it will be appreciated that a data write issued by one of the master devices 51, 52, 53 specifying a data storage location in the memory 55 can result in a number of write operations being performed to a plurality of cache levels that are intermediate between the master and the memory device. For example, assuming a cache line size of 64 bytes, a full cache line write of zero data to a specified location in the memory 55 will result in the Ll cache 59 performing a write operation with 64 bytes of zero data to the L2 cache 62; and the L2 cache 62 performing the same write operation to the L3 cluster cache 65; the L3 cluster cache 65 performing the same write operation to the system level cache 67; and the system level cache 67 performing the same write operation to the memory controller 56. Having explained this, it will be appreciated that if each of these write operations requires 64 bytes of zero data to be transferred as part of the respective write transaction between each cache level and then ultimately to the memory controller, then this places a non-trivial burden on the data bandwidth capabilities of the data processing system 50. This will then be contrasted with the all-zero data write transaction disclosed herein which only requires the respective caches to send the all-zero data write transaction to the next cache level and ultimately to the memory controller without the need to transfer explicit data. This thereby reduces the potential burden on the data bandwidth capabilities of the data processing system. Additionally, where the data processing apparatus can be provided in a context where power consumption is a concern (and note that contemporary data buses can have 256 bit wide data buses for example over the interconnect), then the avoidance of the need to use the data bus provided within the system can mean that power savings can be significant.

[0051] Figure 5 A master device 80 and a slave device 81 are illustratively depicted which are connected via an interconnect 84. Each of the master device 80 and the slave device 81 are connected to the interconnect 84 via their own interconnect interfaces 82 and 83 respectively. In general terms, the interconnect can be provided in a number of ways and includes an interconnect routing 85 which provides the required connection between the interconnect interface 82 of the master device 80 and the interconnect interface 83 of the slave device 81. Figure 5 The interconnect 84 in the above represents illustratively anything between the interconnect interface 82 and the interconnect interface 83. Of particular relevance to the present discussion is Figure 5The selection of channels shown in FIG. 1 is exemplary only, and includes miscellaneous control channels, an opcode channel, a write data channel, a read data channel, and an address channel. Thus, it will be appreciated that each of these channels is multi-bit, with the particular number of bits for each channel depending on its function. For example, the opcode channel needs to be wide enough to communicate the number of unique transactions indicated by a particular opcode in the defined protocol of the interconnect used by master 80 and slave 81 to communicate with each other, while the read and write data buses can be much larger, e.g., each can be a 256-bit data bus in contemporary systems. The address bus can be, e.g., 32-bit or 64-bit in contemporary implementations, but the present technology is in no way limited to a particular address size. The transactions carried by interconnect 84 are embodied as a coordinated set of signals carried by the individual channels, and Figure 5 The example transactions 86 and 87 shown in FIG. 1 demonstrate that all that is required to communicate an all-zero data write transaction of the present technology is the combination of an appropriate opcode asserted on the opcode channel and a specified data storage location (e.g., specified by an address) on the address channel. It is important to note that the data buses, particularly the write data bus, are inactive (or at least ignored) in the context of an all-zero data write transaction. Thus, master 80 can issue an all-zero data write transaction from its interconnect interface 82 onto interconnect 84, and this is communicated to slave 81's interconnect interface 83 via interconnect routing 85. In response, slave 81 will write all-zero data at the specified storage location(s). Slave 81 can also return one or more acknowledgement signals to master 80, as will be discussed below with reference to FIG. 2. Figure 6A and 6B are discussed in more detail.

[0052] Figure 6A and 6B A set of transactions that can be exchanged between devices in a data processing system according to the present technology in some embodiments is shown. Figure 6A The requesting node (RN) master in the example of FIG. 1 sends an all-zero data write transaction that specifies a memory controller (MC) as its target, which is a slave node within the system. This transaction passes through the home node (HN) and is communicated to the target MC via interconnect routing 85. The MC, in response, writes all-zero data at the specified storage location(s). Figure 6ATwo different types of all-zero data write transactions are used in the example. The first WriteUniqZero is the transaction sent from the master to the home node, and the second WriteNoSnpZero is used between the home node and the memory controller slave. These two different types of zero data write transactions have different implications for the cache coherency protocol that the data processing system adheres to. WriteUniqZero indicates that this is a coherent operation and thus the receipt of this command by the home node will cause any required cache coherency operations for this specified data location to be performed within the system, while the WriteNoSnpZero command is non-coherent and does not trigger any snoop operations. The home node uses the WriteNoSnpZero command for the memory controller slave because the memory controller is beyond the coherency point (the home node) and thus no coherency operations are required for this "last leg" step in the system to the slave. In each case, the recipient of the transaction responds with an acknowledgement, the home node returns a CompDBID acknowledgement signal to the master and the slave returns a CompDBID acknowledgement signal to the home node.

[0053] Figure 6B An alternative in the acknowledgements that can be sent when the master initiates the same transaction is represented, i.e., where in response to a WriteUniqZero command from the master, the home node returns a DBID acknowledgement signal first and then a Comp acknowledgement signal separately. In this example, the slave returns a combined compDBID acknowledgement signal to the home node only.

[0054] From Figure 6A and 6B It can also be seen that the transaction sending and acknowledgement exchange is compact, which is useful. This has a further benefit for the data tracking logic in the master, which tracks the master's components required to issue and complete a data modification command. In the example of Figure 6A and 6B The master must wait until a completion (CompDBID) with data buffer ID is received in the case of Figure 6A or until a completion (Comp) is received in the case of Figure 6Bdata buffer ID (DBID) and completion (Comp) until the data is received. These can be received quickly by the master in response to an all-zero data write transaction, and thus the master can quickly deallocate the relevant entry in its address tracker. This compares to an explicit data write transaction where the master holds the write data in an outbound data buffer and can only deallocate the data buffer once it has received the DBID or Comp DBID and has driven the write data onto the data channel. If the data bus is busy (this can easily happen when a large number of masters are driving data), the master (RN) has to wait for the data tenure to complete, resulting in longer entry lifetimes in the data tracker logic.

[0055] Figure 7 A data processing system 100 in some example embodiments is illustrated schematically. A master 101 is illustrated as being coupled to an interconnect 103 via its interconnect interface 102, the interconnect 103 further connecting to a memory controller 104 forming part of a memory 105. The master 101 performs data processing operations in a defined context, where this "context" is in Figure 7The graphical summary of the context switch can have several meanings. For example, this can correspond to a process switch, such that the graphical summary of the context switch 106 represents a switch between processes. It can involve a multi-threaded operation of data processing operations performed by the master device 101, such that the graphical summary of the context switch 106 represents a switch between threads. However, in other examples, the context switch corresponds to a switch to a virtual machine, i.e. a virtual machine which can be hosted on the master device 101 is invoked and starts its data processing operations. In other examples, the context switch 106 can be a switch from a secure context to a non-secure context, e.g. where the data processing apparatus 101 is arranged to perform data processing operations in a carefully defined security domain, where components operating within the non-secure domain are prevented from accessing data belonging to the secure domain. Thus, the switch can be from a secure context to a non-secure context. The master device 101 is arranged to issue a zero-out data write transaction specifying a data location 107 of data which has been accessed in the context prior to the context switch. When the data storage location specified in the zero-out data write transaction currently has an entry in the cache 110, this is evicted (and zeroed out). In addition, the master device also responds to the context switch by causing at least one corresponding entry 108 in the address translation cache 109 to be invalidated. The address translation cache 109 can for example be a translation lookaside buffer (TLB). Thus, when the context switch 106 occurs within the master device 101, not only is the data stored in the cache 110 zeroed out by the zero-out data write, the data in the original storage location 107 of that data is also zeroed out (and any intervening cache levels (not shown) are also evicted), and further the entry in the address translation cache 109 corresponding to this data storage location is also invalidated, such that data belonging to the previous context is both evicted and invalidated before being handed over to the subsequent context.

[0056] Figure 8 A data processing system 120 in some embodiments is schematically illustrated. Here, the data processing system is shown as comprising three master devices 121, 122, 123. Each of these comprises data processing circuitry 124, 125, 126 and an internal cache 127, 128, 129 respectively. Each master device is connected to an interconnect 130 via its interconnect interface 131, 132, 133. The interconnect 130 comprises a home node 135 with a snoop circuit filter 136. The interconnect also comprises a system cache 137. In Figure 8An example case is shown in which the master 121 issues a full zero data write transaction to the interconnect 130 specifying a data storage location in the slave 140 as its target, where the data storage location is within a memory 141 that forms part of the slave 140. The interconnect 130 thus communicates the transaction to the interconnect interface 142 of the slave 140, and from there it is received by the memory controller circuit 143. In response, the memory controller 143 causes the specified data storage location(s) to be zeroed in the memory 141. In Figure 8 In the example of a full zero data write transaction first sent from the master 121 to the home node 135 being a cache coherent transaction (like the WriteUniqZero transaction of Figure 6A In the example of a full zero data write transaction first sent from the master 121 to the home node 135 being a cache coherent transaction (like the WriteUniqZero transaction of Figure 6A In the example of a full zero data write transaction first sent from the master 121 to the home node 135 being a cache coherent transaction (like the WriteUniqZero transaction of

[0057] Figure 9A Three examples of ways in which one or more data storage locations can be specified in a full zero data write transaction are shown. The first full zero data write transaction includes a full zero data write transaction opcode 150 and a single data storage location 151. The second full zero data write transaction includes a full zero data write transaction opcode 150 and multiple data storage locations 152. These can be specified individually, or in any other way that the transaction has encoding space to represent. The third full zero data write transaction includes a full zero data write transaction opcode 150 and an address range 153. This address range can be specified, for example, by a lower and upper bound of the range, which can be specified by a base address and range size, or in any other way that the transaction has encoding space to represent. Regardless of which of these example transactions is used, the recipient can respond by writing full zero data to the specified (all) data location(s).

[0058] Figure 9BA multi-chip system is schematically illustrated in which a first chip 160 communicates with a second chip 161 via an inter-chip interconnect 162. Each chip can be seen as itself comprising a plurality of interconnected devices (which can be arranged in any data processing system as described elsewhere herein). The communication over the inter-chip interconnect 162 includes all-zero data write transactions as described herein. In this context, it is particularly noted that in chip-external protocols, it is possible that request, response, data and snoop channels all share one physical channel for communication between chips, and thus all-zero data write transactions of the present technology can have particular applicability in seeking to avoid shared bandwidth pressure when remote memory needs to be flushed.

[0059] Figure 10 is a flow diagram showing a sequence of steps that a master device can take according to some embodiments. The flow can be considered to start at step 200, in which the master device is performing data processing operations. At step 201 it is determined whether a context switch has been made. If not, the flow returns to step 200. When it is determined at step 201 that a context switch has been made, then the flow proceeds to step 202, in which the master device issues at least one all-zero data write transaction for all data storage locations that have been used in the context switch. The flow then proceeds to step 203, in which the master device determines whether a transaction confirmation(s) has been received. The flow waits at step 203 until such a situation occurs. Finally, when all such transaction confirmations have been received, the flow proceeds to step 204, and the master device switches to the new context, where it then knows that data has been flushed to memory before the new context takes over.

[0060] Figure 11 is a flow diagram showing a sequence of steps that a slave device performs according to some embodiments. The flow can be considered to start at step 250, in which it is determined whether a transaction has been received from the interconnect. When not, the flow waits at this step. When a transaction is received from the interconnect, at step 251 it is determined whether it is a write transaction, and if not, then at step 252 this other type of transaction is processed as required (details are not given here as this is not the focus of the present discussion). However, when this is a write transaction, at step 253 it is determined whether this is an all-zero data write. If not, then at step 254 the data provided via the write data communication connected to the slave device is written to the address specified in the write transaction, and the flow returns to step 250. However, if this is an all-zero data write transaction, then the flow proceeds via step 255, in which all-zeros are written to the specified address (i.e. the write data channel is ignored). The flow then returns to step 250.

[0061] Briefly summarized, apparatuses, methods of operating apparatuses, interconnects for connecting apparatuses to one another, and methods of operating interconnects are disclosed. A master apparatus can issue an individual all-zero data write transaction to an interconnect specifying a data storage location, the interconnect communicates the individual all-zero data write transaction to a target device, and the target device writes all-zero data at the data storage location. No write data is conveyed with the individual all-zero data write transaction, so the individual all-zero data write transaction can be used to clear a data storage location without increasing congestion of write data lanes in the interconnect.

[0062] In this application, the word "configured" is used to mean that an element of an apparatus has a configuration able to perform the defined operation. In this context, a "configuration" refers to an arrangement or interconnection of hardware or software. For example, a processor or other processing device can be programmed to perform a function by way of software. A "configuration" does not mean physical hardware that has been changed in any way. "Configured" does not mean that an element of an apparatus needs to be changed in any way to achieve the defined operation.

[0063] While the illustrative embodiments of the application have been described with reference to the accompanying drawings detailed description, it is to be understood that the application is not limited to those precise embodiments, and that various changes, additions and modifications can be practiced within the scope of the application as defined by the appended claims. For example, features of one claim can be combined with features of another claim while not being explicitly mentioned in the claims.

Claims

1. An apparatus comprising: an interconnect interface; and an interconnect protocol signal generation circuit, wherein the interconnect protocol signal generation circuit is arranged to provide an individual all-zeros data write transaction to the interconnect interface specifying a data storage location, and the interconnect interface, in response to provision of the individual all-zeros data write transaction, causes the individual all-zeros data write transaction to be sent via an interconnect to a target device comprising the data storage location to cause the target device to write all-zeros data at the data storage location, and wherein the apparatus further comprises data processing circuitry to perform a data processing operation, the data processing operation comprising an access to the data storage location, and wherein the data processing circuitry, in response to a context switch from a first context to a second context of the data processing operation, controls the interconnect protocol signal generation circuit to provide the individual all-zeros data write transaction to the interconnect interface specifying the data storage location. the data processing operation of the first context comprises an access to a plurality of data storage locations, and 2. The apparatus as claimed in claim 1, wherein, wherein the data processing circuitry, in response to a context switch from the first context to the second context of the data processing operation, controls the interconnect protocol signal generation circuit to provide one or more individual all-zeros data write transactions to the interconnect interface specifying the plurality of data storage locations. the context switch comprises at least one of:

3. The apparatus as claimed in claim 1, wherein, a process switch; a thread switch; a switch to a virtual machine; and a switch from a secure context to a non-secure context. the interconnect protocol signal generation circuit is arranged to provide the individual all-zeros data write transaction specifying a set of memory addresses, the set of memory addresses comprising the data storage location. the set of memory addresses corresponds to a cache line comprising the data storage location.

4. The apparatus as claimed in claim 1, wherein, the interconnect protocol signal generation circuit is arranged to provide the individual all-zeros data write transaction specifying a range of memory addresses, the range of memory addresses comprising the data storage location.

5. An apparatus as claimed in claim 4, wherein, the data processing circuitry is arranged to access the data storage location in the data processing operation in dependence on an address translation definition in an address translation cache, 6. The apparatus as claimed in claim 1, wherein, and wherein the data processing circuitry, in response to the context switch, further causes the address translation definition for the data storage location to be invalidated.

7. The apparatus as claimed in claim 1, wherein, the interconnect protocol signal generation circuit is arranged to provide the individual all-zeros data write transaction to the interconnect interface as an individual all-zeros data write unique transaction specifying the data storage location, and wherein the interconnect interface, in response to provision of the individual all-zeros data write unique transaction, causes the individual all-zeros data write unique transaction to be sent via the interconnect to the target device to cause a snoop operation in the interconnect to be performed on any copy of data from the data storage location held in other devices connected to the interconnect.

8. The apparatus as claimed in claim 1, wherein, ​ ​ 9. The apparatus as claimed in claim 1, wherein, the interconnect protocol signal generation circuitry is arranged to provide the individual all-zeros data write transaction to the interconnect as an individual all-zeros data write no-snoop transaction specifying the data storage location, and wherein the interconnect, in response to provision of the individual all-zeros data write no-snoop transaction, causes the individual all-zeros data write no-snoop transaction to be transmitted to the target device via the interconnect without triggering a snoop operation in the interconnect.

10. The apparatus as claimed in claim 1, wherein, the interconnect protocol signal generation circuitry is arranged to provide the individual all-zeros data write transaction by asserting a predetermined opcode amongst signals provided to the interconnect.

11. An interconnect system comprising: a master device; an interconnect; and a slave device, wherein the interconnect, in response to receiving an individual all-zeros data write transaction from the master device specifying a data storage location in the slave device, communicates the individual all-zeros data write transaction to the slave device to cause the slave device to write all-zeros data at the data storage location; the interconnect system further comprising: an intermediate hub device coupled to the interconnect; the interconnect, in response to receiving the individual all-zeros data write transaction from the master device, communicates the individual all-zeros data write transaction to the intermediate hub device; the intermediate hub device, in response to receiving the individual all-zeros data write transaction from the master device, communicates the individual all-zeros data write transaction to the slave device; wherein the master device comprises data processing circuitry to perform a data processing operation, the data processing operation comprising an access to the data storage location, wherein the data processing circuitry, in response to a context switch from a first context to a second context as the data processing operation undergoes the context switch, controls interconnect protocol signal generation circuitry of the master device to provide the individual all-zeros data write transaction to the interconnect specifying the data storage location. the master device is arranged to provide the individual all-zeros data write transaction as an individual all-zeros data write unique transaction specifying the data storage location, 12. An interconnection system as claimed in claim 11, wherein, and wherein the intermediate hub device, in response to receiving the individual all-zeros data write unique transaction from the master device, participates in a snoop operation in the interconnect for any copy of data from the data storage location held in other devices connected to the interconnect. the master device is arranged to provide the individual all-zeros data write transaction as an individual all-zeros data write no-snoop transaction specifying the data storage location, 13. An interconnection system as claimed in claim 11, wherein, and wherein the intermediate hub device, in response to receiving the individual all-zeros data write no-snoop transaction from the master device, transmits the individual all-zeros data write no-snoop transaction to the slave device via the interconnect without triggering a snoop operation in the interconnect. the intermediate hub device, in response to receiving the individual all-zeros data write unique transaction from the master device, transmits an individual all-zeros data write no-snoop transaction to the slave device via the interconnect.

14. An interconnection system as claimed in claim 12, wherein, the interconnect forms a component interconnect of at least one of:

15. An interconnection system as claimed in claim 11, wherein, a mesh interconnect topology; ​ intra-chip communication links; and inter-chip communication links.

16. A method of operating an interconnect system, comprising the steps of: receiving, at an interconnect, an individual all-zero data write transaction from a master device specifying a data storage location in a slave device; and communicating the individual all-zero data write transaction to the slave device to cause the slave device to write all-zero data at the data storage location; responding, at the interconnect, to receiving the individual all-zero data write transaction from the master device by communicating the individual all-zero data write transaction to an intermediate hub device coupled to the interconnect; responding, at the intermediate hub device, to receiving the individual all-zero data write transaction from the master device by communicating the individual all-zero data write transaction to the slave device; and providing the individual all-zero data write transaction by the master device, wherein the master device comprises data processing circuitry to perform a data processing operation, the data processing operation comprising an access to the data storage location, wherein the data processing circuitry controls interconnect protocol signal generation circuitry of the master device to provide the individual all-zero data write transaction specifying the data storage location to the interconnect in response to a context switch of the data processing operation from a first context to a second context.

17. A method of operating an apparatus, the apparatus comprising data processing circuitry to perform a data processing operation, the method comprising the steps of: generating an individual all-zero data write transaction specifying a data storage location; providing the individual all-zero data write transaction to an interconnect interface; and sending the individual all-zero data write transaction to a target device comprising the data storage location via an interconnect to cause the target device to write all-zero data at the data storage location; and wherein the data processing operation comprises an access to the data storage location; and wherein the data processing circuitry controls the interconnect protocol signal generation circuitry to provide the individual all-zero data write transaction specifying the data storage location to the interconnect interface in response to a context switch of the data processing operation from a first context to a second context.

18. A data processing apparatus, comprising: data processing circuitry to perform a data processing operation, the data processing operation comprising an access to a data storage location; an interconnect interface; and interconnect protocol signal generation circuitry to provide an individual all-zero data write transaction specifying the data storage location to the interconnect interface in response to a context switch of the data processing operation from a first context to a second context.

19. A data processing apparatus, comprising: data processing circuitry to perform a data processing operation, the data processing operation comprising an access to a data storage location; an interconnect interface; and interconnect protocol signal generation circuitry to provide an individual all-zero data write transaction specifying the data storage location to the interconnect interface in response to a context switch of the data processing operation from a first context to a second context.

20. A data processing apparatus, comprising: data processing circuitry to perform a data processing operation, the data processing operation comprising an access to a data storage location; an interconnect interface; and interconnect protocol signal generation circuitry to provide an individual all-zero data write transaction specifying the data storage location to the interconnect interface in response to a context switch of the data processing operation from a first context to a second context.

21. A data processing apparatus, comprising: data processing circuitry to perform a data processing operation, the data processing operation comprising an access to a data storage location; an interconnect interface; and interconnect protocol signal generation circuitry to provide an individual all-zero data write transaction specifying the data storage location to the interconnect interface in response to a context switch of the data processing operation from a first context to a second context.

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