Display Devices

Abstract

The present invention discloses a display device. The display device includes: a k-1th scan line and a k-th scan line parallel to each other; a j-th data line crossing the k-1th scan line and the k-th scan line; and a sub-pixel connected to the k-1th scan line, the k-th scan line and the j-th data line, wherein the sub-pixel includes: a driving transistor configured to control a driving current flowing from a first electrode of the driving transistor to a second electrode of the driving transistor according to a data voltage applied to a first gate electrode of the driving transistor, the driving transistor having a second gate electrode connected to the k-1th scan line; and a light-emitting element configured to emit light according to the driving current.

Description

Technical Field

[0001] An aspect of some example embodiments of the present disclosure relates to a display device. Background Art

[0002] With the development of the information society, consumer demand for display devices for displaying images has increased in various forms. For example, display devices can be used in various electronic devices such as smart phones, digital cameras, laptop computers, navigation systems, and smart TVs. The display device can be a flat panel display device, such as a liquid crystal display device, a field emission display device, an organic light emitting display device, etc. Among such flat panel display devices, the organic light emitting display device includes a light emitting element that allows each pixel of the display panel to emit light by itself, so that the organic light emitting display device can display an image even without a backlight unit that provides light for the display panel.

[0003] The organic light emitting display device may include a plurality of pixels, and each of the plurality of pixels may include a light emitting element, a driving transistor configured to adjust the amount of driving current supplied from a power line to the light emitting element according to a voltage of a gate electrode, and a scanning transistor configured to supply a data voltage of a data line to a gate electrode of the driving transistor in response to a scanning signal of a scanning line. In this case, when black brightness is displayed and then white brightness is displayed, because the current between the drain and source of the driving transistor may increase stepwise due to the hysteresis characteristics of the driving transistor, the white brightness of the pixel may also increase stepwise.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore, the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0005] Aspects of some example embodiments of the present disclosure include a display device capable of compensating for a threshold voltage of a driving transistor and, at the same time, also capable of minimizing or reducing a white brightness difference of a pixel that may occur due to a step-wise increase in current between a drain and a source of the driving transistor due to a hysteresis characteristic of the driving transistor when black brightness is displayed and then white brightness is displayed.

[0006] Additional features and characteristics of some example embodiments of the present disclosure will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts.

[0007] According to some example embodiments of the present disclosure, a display device includes: a k-1th scan line and a k-th scan line parallel to each other, where k is a positive integer of 2 or more; a j-th data line crossing the k-1th scan line and the k-th scan line, where j is a positive integer; and a sub-pixel connected to the k-1th scan line, the k-th scan line, and the j-th data line. The sub-pixel includes: a driving transistor configured to control a driving current flowing from a first electrode of the driving transistor to a second electrode of the driving transistor according to a data voltage applied to a first gate electrode of the driving transistor, the driving transistor having a second gate electrode connected to the k-1th scan line; and a light-emitting element configured to emit light according to the driving current.

[0008] According to some example embodiments, the display device may further include an initialization voltage line to which an initialization voltage is applied. The subpixel may further include a first transistor configured to be turned on by a k-1th scan signal of a k-1th scan line, the first transistor connecting a first gate electrode of the driving transistor and the initialization voltage line to each other.

[0009] According to some example embodiments, the subpixel may further include: a second transistor configured to be turned on by a kth scan signal of a kth scan line, the second transistor connecting the first electrode of the driving transistor and the jth data line to each other; a third transistor configured to be turned on by the kth scan signal, the third transistor connecting the first gate electrode of the driving transistor to the second electrode of the driving transistor; and a fourth transistor configured to be turned on by the kth scan signal, the fourth transistor connecting the first electrode of the light emitting element and the initialization voltage line to each other.

[0010] According to some example embodiments, the display device may further include: a kth light emitting line parallel to the k-1th scan line and the kth scan line; and a first driving voltage line to which a first driving voltage is applied. The subpixel may further include: a fifth transistor configured to be turned on by a kth light emitting signal of the kth light emitting line, the fifth transistor connecting the first electrode of the driving transistor and the first driving voltage line to each other; and a sixth transistor configured to be turned on by the kth light emitting signal, the sixth transistor connecting the second electrode of the driving transistor and the light emitting element to each other.

[0011] According to some example embodiments, the display device may further include an initialization voltage line to which an initialization voltage is applied. During a first period in which the initialization voltage may be applied to the first gate electrode of the driving transistor, a first level voltage of a k-1th scan signal of a k-1th scan line may be applied to the second gate electrode.

[0012] According to some example embodiments, during the first period, a first level voltage of the (k-1)th scan signal may be lower than an initialization voltage.

[0013] According to some example embodiments, during the first period, a voltage difference between the second gate electrode and the first electrode of the driving transistor may be lower than a voltage difference between the first gate electrode and the first electrode of the driving transistor.

[0014] According to some example embodiments, during a second period in which the data voltage of the jth data line may be applied to the first gate electrode of the driving transistor, a second level voltage of a k-1th scan signal of the k-1th scan line may be applied to the second gate electrode.

[0015] According to some example embodiments, during the second period, the second level voltage of the (k-1)th scan signal may be higher than the data voltage.

[0016] According to some example embodiments, during the second period, a voltage difference between the second gate electrode and the first electrode of the driving transistor may be higher than a voltage difference between the first gate electrode and the first electrode of the driving transistor.

[0017] According to some example embodiments, during a third period in which the light emitting element emits light according to the driving current of the driving transistor, a second level voltage of a k-1th scan signal of a k-1th scan line may be applied to the second gate electrode.

[0018] According to some example embodiments, during the third period, a voltage difference between the second gate electrode and the first electrode of the driving transistor may be higher than a voltage difference between the first gate electrode and the first electrode of the driving transistor.

[0019] According to some example embodiments, the display device may further include a first connection electrode connecting the (k-1)th scan line and the second gate electrode of the driving transistor to each other.

[0020] According to some example embodiments, the first connection electrode may be on the same layer as the second gate electrode of the driving transistor.

[0021] According to some example embodiments, the display device may further include at least one insulating film between the (k-1)th scan line and the first connection electrode.

[0022] According to some example embodiments, the at least one insulating film may include: a buffer film on the first connection electrode and the second gate electrode of the driving transistor; and a gate insulating film on the first electrode of the driving transistor.

[0023] According to some example embodiments, the (k-1)th scan line may be on the gate insulating film.

[0024] According to some example embodiments, the (k-1)th scan line may be connected to the first connection electrode via a first connection contact hole passing through the buffer film and the gate insulating film.

[0025] According to some example embodiments, the display device may further include an initialization voltage line to which an initialization voltage is applied. The subpixel may further include: a first transistor having a gate electrode connected to the k-1th scan line, a first electrode connected to the initialization voltage line, and a second electrode connected to the first gate electrode of the driving transistor; and a second connection electrode connecting the second electrode of the first transistor and the first gate electrode of the driving transistor to each other.

[0026] According to some example embodiments, the first connection electrode and the second connection electrode may overlap each other.

[0027] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are intended to provide further explanation of the subject matter of the present disclosure as claimed and its equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate aspects of some example embodiments of the disclosure and together with the description serve to explain the subject matter of the disclosure.

[0029] Figure 1 is a perspective view illustrating a display device according to some example embodiments.

[0030] Figure 2 is a plan view illustrating a display device according to some example embodiments.

[0031] Figure 3 is a block diagram illustrating a display device according to some example embodiments.

[0032] Figure 4 is a circuit diagram illustrating a sub-pixel according to some example embodiments.

[0033] Figure 5 is shown applied to Figure 4 Waveform diagram of signals of the k-1th scanning line, the kth scanning line and the kth light-emitting line.

[0034] Figures 6 to 8 is used to describe Figure 5 A circuit diagram of a method for driving sub-pixels during a plurality of first periods, a plurality of second periods, and a third period.

[0035] Fig. 9 is a graph showing a stepwise increase in the luminance of a light-emitting element due to the hysteresis characteristics of a driving transistor.

[0036] Fig.10 is a graph showing a current between the drain and the source of the driving transistor according to a voltage applied to the second gate electrode of the driving transistor.

[0037] Fig.11 is a graph showing the luminance of the light emitting element in the first frame relative to the luminance of the light emitting element in the fourth frame according to the voltage between the second gate electrode and the first electrode of the driving transistor.

[0038] Fig.12 : is a graph showing the current between the drain and the source of the driving transistor according to the presence or absence of the second electrode of the driving transistor.

[0039] Fig.13 is a graph showing a change amount of a voltage difference between a first gate electrode and a first electrode when black luminance is displayed and when white luminance is displayed to allow the same driving current to flow according to a voltage difference between a second gate electrode and a first electrode of a driving transistor.

[0040] Fig.14 is a graph showing a transient afterimage according to a voltage between a second gate electrode and a first electrode of a driving transistor.

[0041] Fig.15 is a plan view illustrating a sub-pixel according to some example embodiments.

[0042] Fig.16 It is shown along Fig.15 A cross-sectional view of the example taken along line II'.

[0043] Fig.17 It is shown along Fig.15 A cross-sectional view of the example taken along line II-II'. DETAILED DESCRIPTION

[0044] In the following description, for the purpose of illustration, many specific details are set forth to provide a more comprehensive understanding of the various example embodiments of the present disclosure. As used herein, "embodiment" is an interchangeable word for a non-limiting example of a device or method using one or more inventive concepts disclosed herein. However, it is apparent that the various example embodiments can be practiced without these specific details or under one or more equivalent arrangements. In other examples, various structures and devices can be shown in the form of block diagrams to avoid unnecessarily obscuring the various example embodiments, and descriptions of these structures and devices are not required to enable those of ordinary skill in the art to understand embodiments according to the present disclosure. In addition, the various example embodiments may be different, but not necessarily exclusive. For example, the specific shape, configuration and / or characteristics of the example embodiment may be used in another example embodiment or implemented in another example embodiment without departing from the subject matter of the present disclosure.

[0045] Unless otherwise specified, the illustrated example embodiments should be understood as providing example features of different details of some ways in which the subject matter of the present disclosure can be implemented in practice. Therefore, unless otherwise specified, the features, sensor devices, modules, layers, films, panels, regions and / or aspects of the various embodiments, etc. (hereinafter referred to as "elements" individually or collectively) may be combined, separated, interchanged and / or rearranged without departing from the subject matter of the present disclosure.

[0046] The use of cross hatching and / or shading in the drawings is generally provided to make the boundaries between adjacent elements clear. Therefore, unless otherwise specified, the presence or absence of cross hatching or shading does not express or indicate any preference or requirement for a specific material, material property, size, ratio, commonality between the illustrated elements and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or description purposes. When the example embodiments can be implemented differently, a particular process may be performed in an order different from the described order. For example, two processes described in succession may be performed substantially simultaneously, or in an order opposite to the described order. In addition, the same reference numerals represent the same elements.

[0047] When an element or layer is referred to as "being located on another element or layer", "being connected to" or "being coupled to" another element or layer, the element or layer may be directly located on another element or layer, directly connected to or coupled to another element or layer, or there may be an intermediate element or layer. However, when an element or layer is referred to as "being directly located on another element or layer", "being directly connected to" or "being directly coupled to" another element or layer, there is no intermediate element or layer. For this reason, the term "connection" may refer to a physical connection, an electrical connection and / or a fluid connection using or not using an intermediate element. In addition, the D1 axis, the D2 axis and the D3 axis are not limited to the three axes (such as, the x-axis, the y-axis and the z-axis) of a rectangular coordinate system, but may be interpreted in a broader sense. For example, the D1 axis, the D2 axis and the D3 axis may be mutually perpendicular, or may represent different directions that are not mutually perpendicular. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0048] Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, the first element discussed below can be referred to as the second element without departing from the teachings of the present disclosure.

[0049] For descriptive purposes, spatially relative terms such as "below," "below," "under," "down," "above," "up," "above," "higher," and "side" (e.g., as in "sidewall"), etc., may be used herein, and thereby describe the relationship of one element to another element as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device when in use, in operation, and / or in manufacture other than the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, an element described as being "below" or "below" other elements or features will subsequently be "above" the other elements or features. Thus, the exemplary term "below" may encompass both above and below orientations. Additionally, the device may be oriented in other directions (e.g., rotated 90 degrees or in other orientations), and therefore the spatially relative descriptors used herein should be interpreted accordingly.

[0050] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the singular forms of "a", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. In addition, the terms "include" and / or "comprise", when used in this specification, specify the presence of the described features, integral bodies, steps, operations, elements, sensor devices and / or combinations thereof, but do not exclude the presence or increase of one or more other features, integral bodies, steps, operations, elements, sensor devices and / or combinations thereof. It should also be noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms and are not used as terms of degree, and are therefore used to take into account the inherent deviations in the values ​​measured, calculated and / or provided that would be recognized by a person of ordinary skill in the art.

[0051] Various example embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations, which are schematic illustrations of idealized example embodiments and / or intermediate structures. Therefore, variations in the illustrated shapes may be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the example embodiments disclosed herein should not necessarily be interpreted as limited to the specific illustrated regional shapes, but will include deviations in shapes caused by, for example, manufacturing. In this way, the regions illustrated in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and are therefore not necessarily intended to be limiting.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure belongs. Terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0053] Figure 1 is a perspective view illustrating a display device according to some example embodiments. Figure 2 is a plan view illustrating a display device according to some example embodiments. Figure 3 is a block diagram illustrating a display device according to some example embodiments.

[0054] In this specification, "upper portion", "top" and "upper surface" indicate an upward direction from the display panel 100, that is, the Z-axis direction, and "lower portion", "bottom" and "lower surface" indicate a downward direction from the display panel 100, that is, a direction opposite to the Z-axis direction. In addition, "leftward", "rightward", "upward" and "downward" indicate directions when the display panel 100 is viewed in a plan view. For example, "leftward" indicates an opposite direction to the X-axis direction, "rightward" indicates the X-axis direction, "upward" indicates the Y-axis direction, and "downward" indicates an opposite direction to the Y-axis direction.

[0055] refer to Figures 1 to 3 The display device 10 is a device for displaying video (e.g., a moving image or a plurality of images displayed continuously at a set rate or a predetermined rate) or a stationary (e.g., static) image. The display device 10 can be used not only as a display screen of portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notepads, electronic books, portable multimedia players (PMPs), navigation systems, and ultra mobile PCs (UMPCs), but can also be used as a display screen of various other products such as televisions, laptops, monitors, billboards, Internet of Things (IoT) devices, or any other appropriate electronic devices that can use a display device to graphically display images or information to a user.

[0056] The display device 10 may be, for example, a light-emitting display device, such as an organic light-emitting display device using an organic light-emitting diode (OLED), a quantum dot light-emitting display device including a quantum dot emission layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro light-emitting display device using a micro LED. Hereinafter, a description will be given in the context of the display device 10 being an organic light-emitting display device, but embodiments according to the present invention are not limited thereto.

[0057] The display device 10 includes a display panel 100 , a display driving circuit 200 , and a circuit board 300 .

[0058] The display panel 100 may be formed of a rectangular plane having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). The angle at which the short side in the first direction (X-axis direction) intersects the long side in the second direction (Y-axis direction) may be formed as a circle (e.g., a rounded corner) to have a curvature (e.g., a set curvature or a predetermined curvature) or formed as a right angle. The plane form of the display panel 100 is not limited to a quadrilateral, and may also be other polygons, a circle or an ellipse. The display panel 100 may be formed to be flat, but the embodiment is not limited thereto. The display panel 100 may include a curved portion formed at the left and right ends and having a constant curvature or a variable curvature. In addition, the display panel 100 may be formed to be flexible so that the display panel 100 is bendable, foldable or rollable.

[0059] The display panel 100 may include a display area DA where sub-pixels SP are formed and thus images may be displayed, and a non-display area NDA which is a surrounding area of ​​the display area DA. In addition to the sub-pixels SP, scan lines SL, emission lines EML, data lines DL, and first drive voltage lines VDDL connected to the sub-pixels SP may be located in the display area DA. The scan lines SL and the emission lines EML may be formed in parallel in a first direction (X-axis direction), and the data lines DL may be formed in parallel in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). The first drive voltage lines VDDL may be formed in parallel in the second direction (Y-axis direction) in the display area DA. The first drive voltage lines VDDL formed in parallel in the second direction (Y-axis direction) in the display area DA may be connected to each other in the non-display area NDA.

[0060] Each sub-pixel SP may be connected to at least one of the scan lines SL, any one of the data lines DL, at least one of the emission lines EML, or the first driving voltage line VDDL. Figure 2 2 is a diagram illustrating a case where each sub-pixel SP is connected to two scan lines SL, a single data line DL, a single emission line EML, and a first driving voltage line VDDL, but the embodiments of the present disclosure are not limited thereto. For example, each sub-pixel SP may also be connected to three scan lines SL instead of two scan lines SL.

[0061] Each sub-pixel SP may include a driving transistor, at least one additional transistor, a light emitting element, and a capacitor. The transistor (e.g., the additional transistor other than the driving transistor) may be turned on when a scan signal is applied to the transistor from the scan line SL, and thus, a data voltage of the data line DL may be applied to the driving transistor DT (see Figure 4 ) of the gate electrode. The driving transistor DT may supply a driving current to the light emitting element according to the data voltage applied to the gate electrode. In this way, the light emitting element may emit light. The driving transistor DT and at least one additional transistor may be thin film transistors. The light emitting element may emit light according to the driving current of the driving transistor DT. The light emitting element may be an OLED including a first electrode, an organic emission layer, and a second electrode. A capacitor may be used to keep the data voltage applied to the gate electrode of the driving transistor DT constant.

[0062] The non-display area NDA may be defined as an area from the outside of the display area DA (e.g., the outer edge of the display area DA according to the plan view) to the edge of the display panel 100. The scan driving circuit 400 for applying a scan signal to the scan line SL, the fan-out line FL located between the data line DL and the display driving circuit 200, and the pad DP connected to the display driving circuit 200 may be located in the non-display area NDA. The display driving circuit 200 and the pad DP may be located at one side edge of the display panel 100. The pad DP may be arranged to be more adjacent to (e.g., closer to) one side edge of the display panel 100 than the display driving circuit 200.

[0063] The scan driving circuit 400 may be connected to the display driving circuit 200 via a plurality of scan control lines SCL. The scan driving circuit 400 may receive a scan control signal SCS and a light emission control signal ECS from the display driving circuit 200 via the plurality of scan control lines SCL.

[0064] like Figure 3 As illustrated in , the scan driving circuit 400 may include a scan driver 410 and an emission control driver 420 .

[0065] The scan driver 410 may generate scan signals according to the scan control signal SCS and sequentially output the scan signals to the scan lines SL. The emission control driver 420 may generate emission signals according to the emission control signal ECS and sequentially output the emission signals to the emission lines EML.

[0066] The scan driving circuit 400 may include a plurality of thin film transistors. The scan driving circuit 400 may be formed in the same layer as the thin film transistors of the sub-pixels SP. Figure 24 shows a case where the scan driving circuit 400 is formed on one side of the display area DA (e.g., the non-display area NDA on the left), but the embodiments of the present disclosure are not limited thereto. For example, the scan driving circuit 400 may be formed on both sides of the display area DA (e.g., the non-display areas NDA on the left and right).

[0067] like Figure 3 As illustrated in FIG. 1 , the display driving circuit 200 may include a timing controller 210 , a data driver 220 , and a power supply unit (or a power supply circuit or a power supply) 230 .

[0068] The timing controller 210 receives the digital video data DATA and the timing signal from the circuit board 300. The timing controller 210 may generate a scan control signal SCS for controlling the operation timing of the scan driver 410 according to the timing signal, generate a light emission control signal ECS for controlling the operation timing of the emission control driver 420, and generate a data control signal DCS for controlling the operation timing of the data driver 220. The timing controller 210 may output the scan control signal SCS to the scan driver 410 via a plurality of scan control lines SCL, and output the light emission control signal ECS to the emission control driver 420. The timing controller 210 may output the digital video data DATA and the data control signal DCS to the data driver 220.

[0069] The data driver 220 converts the digital video data DATA into analog positive / negative data voltages and outputs the analog data voltages to the data lines DL via the fan-out lines FL. The subpixels SP may be selected by the scan signals of the scan driving circuit 400, and the data voltages are supplied to the selected subpixels SP.

[0070] The power supply unit 230 may generate a first driving voltage and supply the generated first driving voltage to the first driving voltage line VDDL. In addition, the power supply unit 230 may generate a second driving voltage and supply the generated second driving voltage to the cathode electrode of the OLED of each sub-pixel SP. The first driving voltage may be a high potential voltage for driving the OLED, and the second driving voltage may be a low potential voltage for driving the OLED. That is, the first driving voltage may have a higher potential than the second driving voltage.

[0071] The display driving circuit 200 may be formed as an integrated circuit (IC) and attached to the display panel 100 using any suitable technique or mechanism for mounting an integrated circuit (e.g., a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method, but the embodiment is not limited thereto). For example, the display driving circuit 200 may be attached to the circuit board 300.

[0072] The circuit board 300 may be attached to the pad DP using an anisotropic conductive film. Therefore, the leads of the circuit board 300 may be electrically connected to the pad DP. According to some example embodiments, the circuit board 300 may be a flexible film such as a flexible printed circuit board, a printed circuit board, or a chip on film.

[0073] Figure 4 is a circuit diagram illustrating a sub-pixel according to some example embodiments in more detail.

[0074] refer to Figure 4 , the sub-pixel SP may be connected to the k-1th (where k is a positive integer of 2 or more) scan line Sk-1, the kth scan line Sk, and the jth (where j is a positive integer) data line Dj. In addition, the sub-pixel SP may be connected to the first driving voltage line VDDL to which the first driving voltage is supplied, the initialization voltage Vini (see Figure 6 ) is supplied to an initialization voltage line VIL and a second driving voltage line VSSL is supplied to a second driving voltage line VSSL.

[0075] The sub-pixel SP includes a driving transistor DT, a light emitting element EL, a switching element, and a capacitor C1. The switching element includes first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6.

[0076] The driving transistor DT may include a first gate electrode DT_G1, a second gate electrode DT_G2, a first electrode, and a second electrode. The first gate electrode DT_G1 may be a top gate electrode located at an upper portion of an active layer of the driving transistor DT, and the second gate electrode DT_G2 may be a bottom gate electrode located at a lower portion of the active layer of the driving transistor DT.

[0077] The second gate electrode DT_G2 of the driving transistor DT may be connected to the k-1th scan line Sk-1. The driving transistor DT controls the drain-source current Ids based on the data voltage applied to the first gate electrode DT_G1 (see Figure 8 , hereinafter referred to as “driving current”). As shown in Equation 1, the driving current Ids flowing through the channel of the driving transistor DT may be proportional to the square of the difference between the threshold voltage and the voltage difference Vgs between the first gate electrode DT_G1 and the source electrode of the driving transistor DT.

[0078] [Equation 1] Ids = k' × (Vgs - Vth) 2

[0079] In Equation 1, k′ represents a proportionality coefficient determined by the structure and physical characteristics of the driving transistor DT, Vgs represents a gate-source voltage of the driving transistor DT, and Vth represents a threshold voltage of the driving transistor DT.

[0080] The light emitting element EL emits light according to the driving current Ids. The amount of light emitted by the light emitting element EL may be proportional to the driving current Ids.

[0081] The light emitting element EL may be an OLED including an anode electrode, a cathode electrode, and an organic emission layer between the anode electrode and the cathode electrode. Alternatively, the light emitting element EL may be an inorganic light emitting element including an anode electrode, a cathode electrode, and an inorganic semiconductor between the anode electrode and the cathode electrode. Alternatively, the light emitting element EL may be a quantum dot light emitting element including an anode electrode, a cathode electrode, and a quantum dot emission layer between the anode electrode and the cathode electrode. Alternatively, the light emitting element EL may be a micro light emitting diode.

[0082] The anode electrode of the light emitting element EL may be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode electrode of the light emitting element EL may be connected to the second driving voltage line VSSL. A parasitic capacitor Cel may be formed between the anode electrode and the cathode electrode of the light emitting element EL.

[0083] The first transistor ST1 may be formed as a dual transistor including a 1-1 transistor ST1-1 and a 1-2 transistor ST1-2. The 1-1 transistor ST1-1 and the 1-2 transistor ST1-2 are turned on by a scan signal of a k-1 scan line Sk-1, and the gate electrode of the driving transistor DT and the initialization voltage line VIL are connected to each other. The gate electrode of the driving transistor DT may be discharged to the initialization voltage Vini of the initialization voltage line VIL. The gate electrode of the 1-1 transistor ST1-1 may be connected to the k-1 scan line Sk-1, the first electrode of the 1-1 transistor ST1-1 may be connected to the gate electrode of the driving transistor DT, and the second electrode of the 1-1 transistor ST1-1 may be connected to the first electrode of the 1-2 transistor ST1-2. A gate electrode of the 1-2nd transistor ST1-2 may be connected to the k-1th scan line Sk-1, a first electrode of the 1-2nd transistor ST1-2 may be connected to the second electrode of the 1-1st transistor ST1-1, and a second electrode of the 1-2nd transistor ST1-2 may be connected to the initialization voltage line VIL.

[0084] The second transistor ST2 is turned on by the scan signal of the kth scan line Sk, and connects the first electrode of the driving transistor DT and the jth data line Dj to each other. The gate electrode of the second transistor ST2 may be connected to the kth scan line Sk, the first electrode of the second transistor ST2 may be connected to the first electrode of the driving transistor DT, and the second electrode of the second transistor ST2 may be connected to the jth data line Dj.

[0085] The third transistor ST3 may be formed as a double transistor including a 3-1 transistor ST3-1 and a 3-2 transistor ST3-2. Therefore, according to some example embodiments, the third transistor ST3 may include, for example, two transistors coupled in series, wherein the gate electrodes are electrically coupled to each other. The 3-1 transistor ST3-1 and the 3-2 transistor ST3-2 are turned on by the scan signal of the k-th scan line Sk, and the gate electrode and the second electrode of the driving transistor DT are connected to each other. That is, when the 3-1 transistor ST3-1 and the 3-2 transistor ST3-2 are turned on, because the gate electrode and the second electrode of the driving transistor DT are connected to each other, the driving transistor DT is driven as a diode. The gate electrode of the 3-1 transistor ST3-1 may be connected to the k-th scan line Sk, the first electrode of the 3-1 transistor ST3-1 may be connected to the second electrode of the 3-2 transistor ST3-2, and the second electrode of the 3-1 transistor ST3-1 may be connected to the gate electrode of the driving transistor DT. A gate electrode of the 3-2nd transistor ST3-2 may be connected to the kth scan line Sk, a first electrode of the 3-2nd transistor ST3-2 may be connected to the second electrode of the driving transistor DT, and a second electrode of the 3-2nd transistor ST3-2 may be connected to the first electrode of the 3-1st transistor ST3-1.

[0086] The fourth transistor ST4 is turned on by the scan signal of the k-th scan line Sk, and connects the anode electrode of the light emitting element EL and the initialization voltage line VIL to each other. The anode electrode of the light emitting element EL can be discharged to the initialization voltage Vini. The gate electrode of the fourth transistor ST4 is connected to the k-th scan line Sk, the first electrode of the fourth transistor ST4 is connected to the anode electrode of the light emitting element EL, and the second electrode of the fourth transistor ST4 is connected to the initialization voltage line VIL.

[0087] The fifth transistor ST5 is turned on by the light emission signal of the k-th light emission line Ek, and connects the first electrode of the driving transistor DT and the first driving voltage line VDDL to each other. The gate electrode of the fifth transistor ST5 is connected to the k-th light emission line Ek, the first electrode of the fifth transistor ST5 is connected to the first driving voltage line VDDL, and the second electrode of the fifth transistor ST5 is connected to the first electrode of the driving transistor DT.

[0088] The sixth transistor ST6 is connected between the second electrode of the driving transistor DT and the anode electrode of the light emitting element EL. The sixth transistor ST6 is turned on by the light emitting signal of the k-th light emitting line Ek, and connects the second electrode of the driving transistor DT and the anode electrode of the light emitting element EL to each other. The gate electrode of the sixth transistor ST6 is connected to the k-th light emitting line Ek, the first electrode of the sixth transistor ST6 is connected to the second electrode of the driving transistor DT, and the second electrode of the sixth transistor ST6 is connected to the anode electrode of the light emitting element EL. When both the fifth transistor ST5 and the sixth transistor ST6 are turned on, the driving current Ids can be supplied to the light emitting element EL.

[0089] The capacitor C1 is formed or connected between the first gate electrode DT_G1 of the driving transistor DT and the first driving voltage line VDDL. One electrode of the capacitor C1 may be connected to the first gate electrode DT_G1 of the driving transistor DT, and the other electrode of the capacitor C1 may be connected to the first driving voltage line VDDL.

[0090] When the first electrode of each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5 and ST6 and the driving transistor DT is a source electrode, their second electrodes may be drain electrodes. Alternatively, when the first electrode of each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5 and ST6 and the driving transistor DT is a drain electrode, their second electrodes may be source electrodes.

[0091] The active layer of each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5 and ST6 and the driving transistor DT may be formed of any one of polycrystalline silicon, amorphous silicon and an oxide semiconductor. When the semiconductor layer of each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5 and ST6 and the driving transistor DT is formed of polycrystalline silicon, the process for forming the semiconductor layer may be a low temperature polycrystalline silicon (LTPS) process.

[0092] Furthermore, despite the above description Figure 4 , wherein it is assumed that each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5 and ST6 and the driving transistor DT is formed as a P-type metal oxide semiconductor field effect transistor (MOSFET), but the embodiment is not limited thereto, and each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5 and ST6 and the driving transistor DT may also be formed as an N-type MOSFET. When each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5 and ST6 and the driving transistor DT is formed as an N-type MOSFET, Figure 5 The timing shown in should be modified corresponding to the characteristics of N-type MOSFET.

[0093] In addition, according to some example embodiments, the number of transistors and capacitors may vary without departing from the spirit and scope of the embodiments according to the present disclosure. For example, according to some example embodiments, there may be additional components.

[0094] The first driving voltage of the first driving voltage line VDDL, the second driving voltage of the second driving voltage line VSSL, and the initialization voltage Vini of the initialization voltage line VIL may be set in consideration of characteristics of the driving transistor DT, characteristics of the light emitting element EL, etc. For example, a voltage difference between the initialization voltage Vini and a data voltage supplied to the source electrode of the driving transistor DT may be set to be lower than a threshold voltage of the driving transistor DT.

[0095] Figure 5 is shown applied to Figure 4 Waveform diagram of signals of the k-1th scanning line, the kth scanning line and the kth light-emitting line.

[0096] refer to Figure 5 , the k-1th scan signal SCANk-1 applied to the k-1th scan line Sk-1 is a signal for controlling the on and off of the first transistor ST1. The k-th scan signal SCANk applied to the k-th scan line Sk is a signal for controlling the on and off of each of the second transistor ST2, the third transistor ST3, and the fourth transistor ST4. The k-th light emitting signal EMk is a signal for controlling the fifth transistor ST5 and the sixth transistor ST6.

[0097] The k-1th scan signal SCANk-1, the kth scan signal SCANk, and the kth light emitting signal EMk may be generated every frame period. One frame period may be divided into a plurality of first periods t1, t1', and t1", a plurality of second periods t2, t2', and t2", a third period t3, a first off period toff1, and a second off period toff2. Each of the plurality of first periods t1, t1', and t1" is a period in which an initialization voltage Vini is applied to the first gate electrode DT_G1 of the driving transistor DT and thus the driving transistor DT is biased to be turned on, a plurality of second periods t2, t2', and t2" are periods in which a data voltage is supplied to the first gate electrode DT_G1 of the driving transistor DT and a threshold voltage of the driving transistor DT is sampled, and a third period t3 is a period in which the light emitting element EL emits light according to the voltage of the first gate electrode DT_G1 of the driving transistor DT. The first off period toff1 may be located before the earliest first period t1 in one frame period, and the second off period toff2 may be located between the third period t3 and the last second period t2" in one frame period. Each of the first off period toff1 and the second off period toff2 is a period in which the driving transistor DT and the first to sixth transistors ST1, ST2, ST3, ST4, ST5 and ST6 are all turned off.

[0098] The plurality of first time periods t1, t1' and t1" and the plurality of second time periods t2, t2' and t2" may be repeated alternately. For example, the plurality of first time periods t1, t1' and t1" and the plurality of second time periods t2, t2' and t2" may be arranged in the order of the first time period t1, the second time period t2, the first time period t1', the second time period t2', the first time period t1" and the second time period t2". Meanwhile, although in Figure 5 , a case where one frame period includes three first periods t1, t1', and t1", and three second periods t2, t2', and t2", is illustrated as an example, but the embodiment is not limited thereto. For example, one frame period may include a single first period t1 and a single second period t2, two first periods t1 and t1' and two second periods t2 and t2', or four or more first periods and four or more second periods. In one frame period, the number of first periods and the number of second periods may be the same.

[0099] The k-1th scan signal SCANk-1 may be outputted at a first level voltage V1 during a plurality of first periods t1, t1', and t1", and may be outputted at a second level voltage V2 during a plurality of second periods t2, t2', and t2". For example, the k-1th scan signal SCANk-1 may have a first level voltage V1 during a plurality of first periods t1, t1', and t1", and a second level voltage V2 during the remaining periods. The k-th scan signal SCANk may have a first level voltage V1 during a plurality of second periods t2, t2', and t2", and a second level voltage V2 during the remaining periods. The k-th emission signal EMk may have a first level voltage V1 during a third period t3, and a second level voltage V2 during the remaining periods.

[0100] exist Figure 5 Each of the plurality of first periods t1, t1' and t1", the plurality of second periods t2, t2' and t2", the first off period toff1 and the second off period toff2 is illustrated as one horizontal period. One horizontal period indicates a period in which a data voltage is supplied to each of the sub-pixels SP connected to any scan line of the display panel 100. Therefore, one horizontal period may be defined as one horizontal line scanning period. The data voltage may be supplied to the data line DL in synchronization with the first level voltage V1 of each of the scan signals.

[0101] The first level voltage V1 corresponds to a scan on voltage capable of turning on each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6. The second level voltage V2 corresponds to a scan off voltage capable of turning off each of the first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6. The first level voltage V1 may be about -8V, and the second level voltage V2 may be 7V. The initialization voltage Vini may be higher than the first level voltage V1 and lower than the second level voltage V2. The initialization voltage Vini may be about -3.5V.

[0102] Figures 6 to 8 is used to describe Figure 5 A circuit diagram of a method for driving sub-pixels during a plurality of first periods, a plurality of second periods, and a third period.

[0103] Hereinafter, the operation of the subpixel SP during the first off period toff1, the plurality of first periods t1, t1′ and t1″, the plurality of second periods t2, t2′ and t2″, the second off period toff2 and the third period t3 will be referred to. Figures 6 to 8 is described in more detail.

[0104] First, during the first turn-off period toff1 , the driving transistor DT and the first to sixth transistors ST1 , ST2 , ST3 , ST4 , ST5 , and ST6 of the subpixel SP are all turned off.

[0105] Second, in each of the plurality of first periods t1, t1′, and t1″, the k-1th scan signal SCANk-1 having the first level voltage V1 is supplied to the k-1th scan line Sk-1. In each of the plurality of first periods t1, t1′, and t1″, as shown in FIG. Figure 6 As illustrated in FIG. 1 , the first transistor ST1 is turned on by the k-1th scan signal SCANk-1 having the first level voltage V1. Since the first transistor ST1 is turned on, the initialization voltage Vini of the initialization voltage line VIL is applied to the first gate electrode DT_G1 of the driving transistor DT.

[0106] When trying to display black luminance and then display white luminance, the driving current Ids of the driving transistor DT increases stepwise due to the hysteresis characteristics of the driving transistor DT, and thus the luminance of the light emitting element EL also increases stepwise. Fig. 9 In the first frame period FR1, the light emitting element EL emits light with black brightness (or does not emit light, or emits low-level light) during a black display period, and the second frame period to the fifth frame period FR2 to FR5 correspond to the light emitting element EL emitting light with white brightness during a white display period. Fig. 9 , the X-axis indicates time, and the Y-axis indicates the brightness of the light emitting element EL.

[0107] When the light emitting element EL displays black brightness, the curve of the driving current Ids of the driving transistor DT may be positively shifted, and, when the light emitting element EL displays white brightness, the curve of the driving current Ids of the driving transistor DT may be negatively shifted. When the light emitting element EL displays black brightness and then displays white brightness, the curve of the driving current Ids of the driving transistor DT may be gradually negatively shifted. Therefore, even when the same data voltage is applied, the driving current Ids of the driving transistor DT supplied to the light emitting element EL in the second frame period to the fourth frame period FR2 to FR4 is also increased in a stepwise manner. Accordingly, as Fig. 9 As illustrated in FIG. 1 , the brightness of the light emitted by the light emitting element EL also increases stepwise in the second frame period to the fourth frame period FR2 to FR4.

[0108] In order to reduce the brightness difference between frame periods caused by the step-by-step increase in the brightness of the light emitting element EL due to the hysteresis characteristics of the driving transistor DT, the driving transistor DT is biased to be turned on in each of the multiple first periods t1, t1' and t1". When the initialization voltage Vini is applied to the first gate electrode DT_G1 of the driving transistor DT in each of the multiple first periods t1, t1' and t1", the driving transistor DT can be turned on because the voltage difference between the first gate electrode DT_G1 of the driving transistor DT and the first electrode is lower than the threshold voltage Vth of the driving transistor DT. That is, the driving transistor DT can be biased to be turned on.

[0109] In addition, in each of the plurality of first time periods t1, t1′, and t1″, the first level voltage V1 of the k-1th scan signal SCANk-1 is applied to the second gate electrode DT_G2 of the driving transistor DT. The first level voltage V1 may be lower than the initialization voltage Vini. Therefore, during the first time period t1, the voltage difference between the second gate electrode DT_G2 of the driving transistor DT and the first electrode may be lower than the voltage difference between the first gate electrode DT_G1 of the driving transistor DT and the first electrode.

[0110] The voltage difference Vbs (see Fig.10 ) is lower than 0V, according to the voltage difference Vgs (see Fig.12 ) is positively offset. In addition, when the voltage difference Vbs between the second gate electrode DT_G2 of the driving transistor DT and the first electrode is higher than 0V, the curve of the driving current Ids according to the voltage difference Vgs between the first gate electrode DT_G1 of the driving transistor DT and the first electrode is negatively offset.

[0111] Therefore, if Fig.10 As shown in FIG. 1 , in each of the plurality of first periods t1 , t1 ′, and t1 ″, the lower the voltage difference Vbs between the second gate electrode DT_G2 and the first electrode of the driving transistor DT is, the more the driving current Ids of the driving transistor DT increases. Fig.10 , the X-axis indicates the voltage difference Vbs between the second gate electrode DT_G2 and the first electrode of the driving transistor DT, and the Y-axis indicates the driving current Ids of the driving transistor DT.

[0112] Therefore, if Fig.11As illustrated in FIG. 1 , the smaller the voltage difference Vbs between the second gate electrode DT_G2 of the driving transistor DT and the first electrode is in each of the plurality of first periods t1, t1′, and t1″, the more the brightness difference is minimized or reduced between the second frame period FR2 and the fifth frame period FR5 after three frame periods from the second frame period FR2, in which black brightness is displayed and then white brightness is displayed, as shown in FIG. Fig. 9 As shown in the figure. Fig.11 , the X-axis indicates the voltage difference Vbs between the second gate electrode DT_G2 and the first electrode of the driving transistor DT in each of the plurality of first time periods t1, t1' and t1", and the Y-axis indicates the brightness of the light emitting element EL in the second frame period FR2 compared with the brightness of the light emitting element EL in the fifth frame period FR5, i.e., the brightness ratio.

[0113] In each of the multiple first time periods t1, t1' and t1", the first level voltage V1 of the k-1th scan signal SCANk-1 applied to the second gate electrode DT_G2 of the driving transistor DT is lower than the initialization voltage Vini. Therefore, in each of the multiple first time periods t1, t1' and t1", the voltage difference Vbs between the second gate electrode DT_G2 of the driving transistor DT and the first electrode is lower than the voltage difference Vgs between the first gate electrode DT_G1 of the driving transistor DT and the first electrode. Accordingly, when the driving transistor DT includes the second gate electrode DT_G2, the driving current Ids of the driving transistor DT can be increased in each of the multiple first time periods t1, t1' and t1", compared with when the second gate electrode DT_G2 is omitted. Therefore, the step-by-step increase in the brightness of the light emitting element EL due to the hysteresis characteristics of the driving transistor DT can be reduced.

[0114] Third, in each of the plurality of second periods t2, t2' and t2", the kth scan signal SCANk having the first level voltage V1 is supplied to the kth scan line Sk. In each of the plurality of second periods t2, t2' and t2", as shown in FIG. Figure 7 As illustrated in FIG. 1 , each of the second transistor ST2 and the third transistor ST3 is turned on by the kth scan signal SCANk having the first level voltage V1 .

[0115] In each of the plurality of second time periods t2, t2', and t2", since the third transistor ST3 is turned on, the first gate electrode DT_G1 and the second electrode of the driving transistor DT are connected to each other, and the driving transistor DT is driven as a diode. Since the second transistor ST2 is turned on, the data voltage Vdata is supplied to the first electrode of the driving transistor DT. In this case, since the voltage (Vgs=Vini-Vdata) between the first gate electrode DT_G1 and the first electrode of the driving transistor DT is lower than the threshold voltage Vth, the driving transistor DT forms a current path until the voltage difference Vgs between the first gate electrode DT_G1 and the first electrode reaches the threshold voltage Vth. Therefore, in each of the plurality of second time periods t2, t2', and t2", the voltage difference between the first gate electrode DT_G1 and the second electrode of the driving transistor DT rises to a voltage (Vdata+Vth), which is equal to the sum of the data voltage Vdata and the threshold voltage Vth of the driving transistor DT. "Vdata+Vth" may be stored in the capacitor C1.

[0116] In addition, in each of the multiple second time periods t2, t2' and t2", the second level voltage V2 of the k-1th scan signal SCANk-1 is applied to the second gate electrode DT_G2 of the driving transistor DT. The second level voltage V2 can be higher than the data voltage Vdata. Therefore, in each of the multiple second time periods t2, t2' and t2", the voltage difference Vbs between the second gate electrode DT_G2 of the driving transistor DT and the first electrode can be higher than the voltage difference Vgs between the first gate electrode DT_G1 of the driving transistor DT and the first electrode.

[0117] Since the driving transistor DT is formed as a P-type MOSFET, the driving current Ids of the driving transistor DT is as follows: Fig.12 The portion where the voltage difference Vgs between the first gate electrode DT_G1 of the driving transistor DT and the first electrode is lower than 0V may be inversely proportional to the voltage difference Vgs between the first gate electrode DT_G1 of the driving transistor DT and the first electrode. In addition, since the driving transistor DT is formed as a P-type MOSFET, the threshold voltage Vth may be lower than 0V.

[0118] In addition, in each of the plurality of second periods t2, t2' and t2", the fourth transistor ST4 is turned on by the kth scan signal SCANk having the first level voltage V1. Since the fourth transistor ST4 is turned on, the voltage of the anode electrode of the light emitting element EL can be initialized to the initialization voltage Vini of the initialization voltage line VIL.

[0119] At the same time, since the plurality of first time periods t1, t1' and t1" and the plurality of second time periods t2, t2' and t2" are alternately repeated, as shown in FIG. Figure 5 As illustrated in the figure, the driving transistor DT can be biased to be turned on in each of the multiple first time periods t1, t1' and t1". Therefore, when one frame period includes multiple first time periods t1, t1' and t1", compared with when one frame period includes a single first time period, the step-by-step increase in the brightness of the light-emitting element EL caused by the hysteresis characteristics of the driving transistor DT can be further reduced.

[0120] Fourth, during the second off period toff2, the driving transistor DT and the first to sixth transistors ST1, ST2, ST3, ST4, ST5 and ST6 of the subpixel SP are all turned off. During the second off period toff2, the first gate electrode DT_G1 of the driving transistor DT can maintain the voltage "Vdata+Vth" due to the capacitor C1.

[0121] Fifth, during the third period t3, the kth light emitting signal EMk having the first level voltage V1 is supplied to the kth light emitting line Ek. Figure 8 As illustrated in FIG. 1 , each of the fifth transistor ST5 and the sixth transistor ST6 is turned on by the kth light emitting signal EMk having the first level voltage V1.

[0122] Since the fifth transistor ST5 is turned on, the first electrode of the driving transistor DT is connected to the first driving voltage line VDDL. Since the sixth transistor ST6 is turned on, the second electrode of the driving transistor DT is connected to the anode electrode of the light emitting element EL.

[0123] When both the fifth transistor ST5 and the sixth transistor ST6 are turned on, a driving current Ids flowing according to a voltage of the gate electrode of the driving transistor DT may be supplied to the light emitting element EL. The driving current Ids may be defined as in Equation 2.

[0124] [Equation 2] Ids = k' x (ELVDD - (Vdata + Vth) - Vth) 2

[0125] In Equation 2, k' represents a proportionality coefficient determined by the structure and physical characteristics of the driving transistor DT, Vth represents a threshold voltage of the driving transistor DT, ELVDD represents a first driving voltage of the first driving voltage line VDDL, and Vdata represents a data voltage. The gate voltage of the driving transistor DT is equal to (Vdata+Vth), and the voltage of the first electrode is ELVDD. When Equation 2 is simplified, Equation 3 is derived.

[0126] [Equation 3] Ids = k' × (ELVDD-Vdata) 2

[0127] Finally, the driving current Ids does not depend on the threshold voltage Vth of the driving transistor DT as shown in Equation 3. That is, the threshold voltage Vth of the driving transistor DT is compensated.

[0128] In addition, during the third period t3, the second level voltage V2 of the k-1th scan signal SCANk-1 is applied to the second gate electrode DT_G2 of the driving transistor DT. The second level voltage V2 may be higher than the first driving voltage of the first driving voltage line VDDL. Therefore, during the third period t3, the voltage difference Vbs between the second gate electrode DT_G2 of the driving transistor DT and the first electrode may be higher than the voltage difference Vgs between the first gate electrode DT_G1 of the driving transistor DT and the first electrode.

[0129] When the voltage difference Vbs between the second gate electrode DT_G2 of the driving transistor DT and the first electrode is lower than 0V, the curve of the driving current Ids according to the voltage difference Vgs between the first gate electrode DT_G1 of the driving transistor DT and the first electrode is positively shifted. In addition, when the voltage difference Vbs between the second gate electrode DT_G2 of the driving transistor DT and the first electrode is higher than 0V, the curve of the driving current Ids according to the voltage difference Vgs between the first gate electrode DT_G1 of the driving transistor DT and the first electrode is negatively shifted. When the voltage difference Vbs between the second gate electrode DT_G2 of the driving transistor DT and the first electrode is 2V ( Fig.12 When BML (Vbs = 2V) in the circuit, the second gate electrode DT_G2 is omitted ( Fig.12 Compared with the case of Ref in FIG. 1 , the curve of the driving current Ids according to the voltage difference Vgs between the first gate electrode DT_G1 and the first electrode of the driving transistor DT is negatively shifted. Fig.12 , the X-axis indicates the voltage difference Vgs between the first gate electrode DT_G1 and the first electrode of the driving transistor DT, and the Y-axis indicates the driving current Ids of the driving transistor DT.

[0130] In addition, if Fig.13 As shown in FIG, during the third period t3, the higher the voltage difference Vbs between the second gate electrode DT_G2 and the first electrode of the driving transistor DT, the smaller the voltage change ΔV between Vgs when displaying black brightness and Vgs when displaying white brightness. That is, the offset of the curve of the driving current Ids of the driving transistor DT due to the hysteresis characteristics of the driving transistor DT between when black brightness is displayed and when white brightness is displayed can be reduced. Fig.13, the X-axis indicates the voltage difference Vbs between the second gate electrode DT_G2 and the first electrode of the driving transistor DT, and the Y-axis indicates the voltage change ΔV between “Vgs” when displaying black brightness and “Vgs” when displaying white brightness for allowing the same driving current Ids to flow.

[0131] Finally, due to the hysteresis characteristics of the driving transistor DT, the curve of the driving current Ids of the driving transistor DT may be positively shifted when the light emitting element EL displays black brightness, and the curve of the driving current Ids of the driving transistor DT may be negatively shifted when the light emitting element EL displays white brightness. However, by controlling the voltage difference Vbs between the second gate electrode DT_G2 and the first electrode of the driving transistor DT to be higher than 0V during the third period t3 in which the light emitting element EL emits light, the curve of the driving current Ids according to the voltage difference Vgs between the first gate electrode DT_G1 and the first electrode of the driving transistor DT may be as shown in FIG. Fig.10 Accordingly, even when the light emitting element EL displays black brightness during the third period t3, the positive shift of the curve of the driving current Ids of the driving transistor DT due to the hysteresis characteristic of the driving transistor DT can be minimized.

[0132] Further, during the third period t3, the higher the voltage difference Vbs between the second gate electrode DT_G2 of the driving transistor DT and the first electrode is, the more the offset of the curve of the driving current Ids due to the hysteresis characteristics of the driving transistor DT is reduced between when displaying black brightness and when displaying white brightness. Therefore, during the third period t3, the higher the voltage difference Vbs between the second gate electrode DT_G2 of the driving transistor DT and the first electrode is, the more the time (s) when the instantaneous afterimage is generated is reduced. The time (s) when the instantaneous afterimage is generated indicates that after the black brightness BL is displayed in the first area A1 of the display panel 100 and then the white brightness WL is displayed in the second area A2 of the display panel 100 for about 10 seconds, the white brightness WL is displayed in both the first area A1 and the second area A2 of the display panel 100 (such as in Fig.14 The time at which the afterimage (as shown in FIG. 1 ) is generated. Fig.14 , the X-axis indicates the voltage difference Vbs between the second gate electrode DT_G2 and the first electrode of the driving transistor DT during the third period t3, and the Y-axis indicates the time (s) when the instantaneous afterimage is generated.

[0133] As described above, by connecting the second gate electrode DT_G2 of the driving transistor DT to the k-1th scan line Sk-1, the voltage difference Vbs between the second gate electrode DT_G2 of the driving transistor DT and the first electrode can be controlled to be lower than the threshold voltage Vth of the driving transistor DT when the driving transistor DT is biased to be turned on in each of the plurality of first time periods t1, t1' and t1". Therefore, the driving current Ids of the driving transistor DT can be increased. Accordingly, the brightness difference in the light emitting element that occurs due to the hysteresis characteristics of the driving transistor DT when the light emitting element displays black brightness and then displays white brightness can be reduced.

[0134] In addition, since the voltage difference Vbs between the second gate electrode DT_G2 and the first electrode of the driving transistor DT during the third period t3 can be controlled to be higher than 0V, the curve of the driving current Ids of the driving transistor DT can be negatively offset. Therefore, the offset of the curve of the driving current Ids of the driving transistor DT that occurs due to the hysteresis characteristics of the driving transistor DT between when displaying black brightness and when displaying white brightness can be reduced. Accordingly, not only the brightness difference of the light-emitting element that occurs due to the hysteresis characteristics of the driving transistor DT when the light-emitting element displays black brightness and then displays white brightness can be reduced, but also the time (s) when the instantaneous afterimage is generated can be reduced.

[0135] Fig.15 is a plan view illustrating a sub-pixel according to some example embodiments in more detail.

[0136] refer to Fig.15 , the sub-pixel SP may include a driving transistor DT, first to sixth transistors ST1 to ST6 , and a capacitor C1 .

[0137] The driving transistor DT may include an active layer DT_ACT, a gate electrode DT_G, a first electrode DT_S, and a second electrode DT_D. The active layer DT_ACT of the driving transistor DT may overlap with the gate electrode DT_G of the driving transistor DT. The gate electrode DT_G of the driving transistor DT may include a first gate electrode DT_G1 and a second gate electrode DT_G2. The first gate electrode DT_G1 may be located on the active layer DT_ACT of the driving transistor DT, and the second gate electrode DT_G2 may be located under the active layer DT_ACT of the driving transistor DT.

[0138] The first gate electrode DT_G1 may be connected to the second connection electrode BE2 via the second connection contact hole BCNT2. The second connection electrode BE2 may be connected to the first electrode S1-1 of the 1-1th transistor ST1-1 via the second contact hole CNT2. The second connection electrode BE2 may cross the kth scan line Sk.

[0139] The second gate electrode DT_G2 may be directly connected to the first connection electrode BE1. The second gate electrode DT_G2 and the first connection electrode BE1 may be formed of the same material on the same layer. The first connection electrode BE1 may be connected to the k-1th scan line Sk-1 via the first connection contact hole BCNT1. The first connection electrode BE1 may overlap with the second connection electrode BE2. The first connection electrode BE1 may cross the kth scan line Sk.

[0140] The first electrode DT_S of the driving transistor DT may be connected to the first electrode S2 of the second transistor ST2. The second electrode DT_D of the driving transistor DT may be connected to the first electrode S3-1 of the 3-1st transistor ST3-1 and the first electrode S6 of the sixth transistor ST6.

[0141] The first transistor ST1 may be formed as a double transistor. The first transistor ST1 may include a 1-1 transistor ST1-1 and a 1-2 transistor ST1-2.

[0142] The 1-1 transistor ST1-1 may include an active layer ACT1-1, a gate electrode G1-1, a first electrode S1-1, and a second electrode D1-1. The gate electrode G1-1 of the 1-1 transistor ST1-1 is a portion of the k-1 scan line Sk-1, and may be an overlap region where the active layer ACT1-1 of the 1-1 transistor ST1-1 and the k-1 scan line Sk-1 overlap each other. The first electrode S1-1 of the 1-1 transistor ST1-1 may be connected to the second connection electrode BE2 via the second contact hole CNT2. The second electrode D1-1 of the 1-1 transistor ST1-1 may be connected to the first electrode S1-2 of the 1-2 transistor ST1-2.

[0143] The 1-2 transistor ST1-2 may include an active layer ACT1-2, a gate electrode G1-2, a first electrode S1-2, and a second electrode D1-2. The gate electrode G1-2 of the 1-2 transistor ST1-2 is a portion of the k-1 scan line Sk-1, and may be an overlap region where the active layer ACT1-2 of the 1-2 transistor ST1-2 and the k-1 scan line Sk-1 overlap each other. The first electrode S1-2 of the 1-2 transistor ST1-2 may be connected to the second electrode D1-1 of the 1-1 transistor ST1-1. The second electrode D1-2 of the 1-2 transistor ST1-2 may be connected to the initialization connection electrode VIE via the fourth contact hole CNT4.

[0144] The second transistor ST2 may include an active layer ACT2, a gate electrode G2, a first electrode S2, and a second electrode D2. The gate electrode G2 of the second transistor ST2 is a portion of the k-th scan line Sk (where k is a positive integer of 2 or more), and may be an overlap region where the active layer ACT2 of the second transistor ST2 and the k-th scan line Sk overlap each other. The first electrode S2 of the second transistor ST2 may be connected to the first electrode DT_S of the driving transistor DT. The second electrode D2 of the second transistor ST2 may be connected to the data line DL via the third contact hole CNT3.

[0145] The third transistor ST3 may be formed as a double transistor. The third transistor ST3 may include a 3-1st transistor ST3-1 and a 3-2nd transistor ST3-2.

[0146] The 3-1 transistor ST3-1 may include an active layer ACT3-1, a gate electrode G3-1, a first electrode S3-1, and a second electrode D3-1. The gate electrode G3-1 of the 3-1 transistor ST3-1 is a portion of the k-th scan line Sk, and may be an overlap region where the active layer ACT3-1 of the 3-1 transistor ST3-1 and the k-th scan line Sk overlap each other. The first electrode S3-1 of the 3-1 transistor ST3-1 may be connected to the second electrode D3-2 of the 3-2 transistor ST3-2. The second electrode D3-1 of the 3-1 transistor ST3-1 may be connected to the second connection electrode BE2 via the second contact hole CNT2.

[0147] The 3-2 transistor ST3-2 may include an active layer ACT3-2, a gate electrode G3-2, a first electrode S3-2, and a second electrode D3-2. The gate electrode G3-2 of the 3-2 transistor ST3-2 is a portion of the k-th scan line Sk, and may be an overlap region where the active layer ACT3-2 of the 3-2 transistor ST3-2 and the k-th scan line Sk overlap each other. The first electrode S3-2 of the 3-2 transistor ST3-2 may be connected to the second electrode DT_D of the driving transistor DT. The second electrode D3-2 of the 3-2 transistor ST3-2 may be connected to the first electrode S3-1 of the 3-1 transistor ST3-1.

[0148] The fourth transistor ST4 may include an active layer ACT4, a gate electrode G4, a first electrode S4, and a second electrode D4. The gate electrode G4 of the fourth transistor ST4 is a portion of the k-th scan line Sk, and may be an overlapped region where the active layer ACT4 of the fourth transistor ST4 and the k-th scan line Sk overlap each other. The first electrode S4 of the fourth transistor ST4 may be connected to the anode connection electrode ANDE via a sixth contact hole CNT6. The anode electrode 171 of the light emitting element (see Fig.16) may be connected to the anode connection electrode ANDE via the anode contact hole AND_CNT. The second electrode D4 of the fourth transistor ST4 may be connected to the initialization connection electrode VIE via the fourth contact hole CNT4. The initialization voltage line VIL may be connected to the initialization connection electrode VIE via the fifth contact hole CNT5, and the initialization connection electrode VIE may be connected to the second electrode D1-2 of the 1-2 transistor ST1-2 and the second electrode D4 of the fourth transistor ST4 via the fourth contact hole CNT4. The initialization connection electrode VIE may be arranged to cross the k-th scan line Sk.

[0149] The fifth transistor ST5 may include an active layer ACT5, a gate electrode G5, a first electrode S5, and a second electrode D5. The gate electrode G5 of the fifth transistor ST5 is a portion of the k-th light emitting line Ek, and may be an overlapping region where the active layer ACT5 of the fifth transistor ST5 and the k-th light emitting line Ek overlap each other. The first electrode S5 of the fifth transistor ST5 may be connected to the 1-2 driving voltage line VDDL2 via the seventh contact hole CNT7. The second electrode D5 of the fifth transistor ST5 may be connected to the first electrode DT_S of the driving transistor DT.

[0150] The sixth transistor ST6 may include an active layer ACT6, a gate electrode G6, a first electrode S6, and a second electrode D6. The gate electrode G6 of the sixth transistor ST6 is a portion of the k-th light emitting line Ek, and may be an overlapping region where the active layer ACT6 of the sixth transistor ST6 and the k-th light emitting line Ek overlap each other. The first electrode S6 of the sixth transistor ST6 may be connected to the second electrode DT_D of the driving transistor DT. The second electrode D6 of the sixth transistor ST6 may be connected to the anode electrode 171 of the light emitting element via the sixth contact hole CNT6.

[0151] The first electrode of the capacitor C1 is part of the second electrode DT_D of the driving transistor DT, and the second electrode of the capacitor C1 may be the 1-1st driving voltage line VDDL1 overlapping the second electrode DT_D of the driving transistor DT. The 1-1st driving voltage line VDDL1 may be connected to the 1-2nd driving voltage line VDDL2 via the eighth contact hole CNT8. The 1-2nd driving voltage line VDDL2 may be arranged in parallel with the jth data line Dj, and the 1-1st driving voltage line VDDL1 may be arranged in parallel with the kth scan line Sk.

[0152] Fig.16 It is shown along Fig.15 A cross-sectional view of the example taken along line II'. Fig.17 It is shown along Fig.15 A cross-sectional view of the example taken along line II-II'.

[0153] refer to Fig.16 and Fig.17 , a thin film transistor layer, a light emitting element layer, and an encapsulation layer TFE may be sequentially formed on the first substrate SUB1 in this order.

[0154] The thin film transistor layer includes a light shielding layer, a buffer film BF, an active layer, a first gate layer GTL1 , a second gate layer GTL2 , a data metal layer DTL, a gate insulating film 130 , a first interlayer insulating film 141 , a second interlayer insulating film 142 , a protective film 150 , and a planarization film 160 .

[0155] The light shielding layer may be formed on one surface of the first substrate SUB1. The light shielding layer may include a first connection electrode BE1 and a second gate electrode DT_G2 of the driving transistor DT. The light shielding layer may be formed of a single layer or a multilayer, and the single layer or the multilayer is formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof.

[0156] The buffer film BF may be formed on the light shielding layer. The buffer film BF may be formed on one surface of the first substrate SUB1 to protect the organic emission layer 172 of the thin film transistor and the light emitting element layer from penetrating through the first substrate SUB1 susceptible to moisture penetration. The buffer film BF may be formed of a plurality of inorganic films alternately stacked. For example, the buffer film BF may be formed of a multilayer film in which one or more inorganic films of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The buffer film BF may be omitted.

[0157] The active layer may be formed on the first substrate SUB1 or the buffer film BF. The active layer may include polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, amorphous silicon or an oxide semiconductor. When the active layer is formed of polycrystalline silicon, the active layer doped with ions may have conductivity. Therefore, the active layer may include not only the active layers DT_ACT and ACT1-1 to ACT6 of the driving transistor DT and the first to sixth transistors ST1 to ST6, but also their source electrodes DT_S, S1-1, S1-2, S2, S3-1, S3-2, S4, S5 and S6 and drain electrodes DT_D, D1-1, D1-2, D2, D3-1, D3-2, D4, D5 and D6.

[0158] The gate insulating film 130 may be formed on the active layer. The gate insulating film 130 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0159] The first gate layer GTL1 may be formed on the gate insulating film 130. The first gate layer GTL1 may include not only the first gate electrode DT_G1 of the driving transistor DT and the gate electrodes G1-1 to G6 of the first to sixth transistors ST1 to ST6, but also the scan lines Sk-1 and Sk and the light emitting line Ek. The first gate layer GTL1 may be formed of a single layer or a multilayer formed of any one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or an alloy thereof.

[0160] The first interlayer insulating film 141 may be formed on the first gate layer GTL1. The first interlayer insulating film 141 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating film 141 may include a plurality of inorganic films.

[0161] The second gate layer GTL2 may be formed on the first interlayer insulating film 141. The second gate layer GTL2 may include an initialization voltage line VIL and a 1-1 th driving voltage line VDDL1. The second gate layer GTL2 may be formed of a single layer or a multilayer formed of any one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or an alloy thereof.

[0162] The second interlayer insulating film 142 may be formed on the second gate layer GTL2. The second interlayer insulating film 142 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating film 142 may include a plurality of inorganic films.

[0163] The data metal layer DTL may be formed on the second interlayer insulating film 142. The data metal layer DTL may include a data line DL, a second connection electrode BE2, an anode connection electrode ANDE, and an initialization connection electrode VIE. The data metal layer DTL may be formed of a single layer or a multilayer formed of any one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or an alloy thereof.

[0164] A planarization film 160 for planarizing a step formed by the active layer, the first gate layer GTL1, the second gate layer GTL2, and the data metal layer DTL may be formed on the data metal layer DTL. The planarization film 160 may be formed of an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0165] Meanwhile, a protection film 150 may be additionally formed between the data metal layer DTL and the planarization film 160. The protection film 150 may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0166] The driving transistor DT and the first to sixth transistors ST1 to ST6 are Figure 8 , it is illustrated as being formed as a top-gate transistor with a gate electrode located above the active layer, but it should be noted that the embodiment is not limited thereto. That is, the driving transistor DT and the first to sixth transistors ST1 to ST6 may also be formed as bottom-gate transistors with a gate electrode located below the active layer, or may be formed as dual-gate transistors with gate electrodes located above and below the active layer.

[0167] The first connection contact hole BCNT1 may be a hole that passes through the buffer film BF and the gate insulating film 130 and exposes the first connection electrode BE1. Fig.17 The k-1th scan line Sk-1 may be connected to the first connection electrode BE1 via the first connection contact hole BCNT1.

[0168] The second connection contact hole BCNT2 may be a hole that passes through the first and second interlayer insulating films 141 and 142 and exposes the first gate electrode DT_G1 of the driving transistor DT. Fig.16 and Fig.17 The second connection electrode BE2 may be connected to the first gate electrode DT_G1 of the driving transistor DT via the second connection contact hole BCNT2.

[0169] The second contact hole CNT2 may be a hole passing through the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142 and exposing the second electrode D3-1 of the 3-1st transistor ST3-1. The second connection electrode BE2 may be connected to the second electrode D3-1 of the 3-1st transistor ST3-1 via the second contact hole CNT2.

[0170] The third contact hole CNT3 may be a hole that passes through the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142 and exposes the first electrode S2 of the second transistor ST2. The data line DL may be connected to the first electrode S2 of the second transistor ST2 via the third contact hole CNT3.

[0171] The fourth contact hole CNT4 may be a hole that passes through the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142 and exposes the second electrode D1-2 of the 1-2 transistor ST1-2 and the second electrode D4 of the fourth transistor ST4. The initialization connection electrode VIE may be connected to the second electrode D1-2 of the 1-2 transistor ST1-2 and the second electrode D4 of the fourth transistor ST4 via the fourth contact hole CNT4.

[0172] The fifth contact hole CNT5 may be a hole that passes through the second interlayer insulating film 142 and exposes the initialization voltage line VIL. The initialization connection electrode VIE may be connected to the initialization voltage line VIL via the fifth contact hole CNT5.

[0173] The sixth contact hole CNT6 may be a hole passing through the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142 and exposing the second electrode D6 of the sixth transistor ST6. The anode connection electrode ANDE may be connected to the second electrode D6 of the sixth transistor ST6 via the sixth contact hole CNT6.

[0174] The seventh contact hole CNT7 may be a hole passing through the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142 and exposing the first electrode S5 of the fifth transistor ST5. The 1-2nd driving voltage line VDDL2 may be connected to the first electrode S5 of the fifth transistor ST5 via the seventh contact hole CNT7.

[0175] The eighth contact hole CNT8 may be a hole that passes through the second interlayer insulating film 142 and exposes the 1-1th driving voltage line VDDL1. The 1-2th driving voltage line VDDL2 may be connected to the 1-1th driving voltage line VDDL1 via the eighth contact hole CNT8.

[0176] The anode contact hole AND_CNT may be a hole that passes through the protection film 150 and the planarization film 160 and exposes the anode connection electrode ANDE.

[0177] The light emitting element layer is formed on the thin film transistor layer and includes a light emitting element 170 and a pixel defining film 180 .

[0178] The light emitting elements 170 and the pixel defining film 180 are formed on the planarization film 160. Each of the light emitting elements 170 may include a first electrode 171, an organic emission layer 172, and a second electrode 173.

[0179] The first electrode 171 may be formed on the planarization film 160. The first electrode 171 may be connected to the anode connection electrode ANDE via an anode contact hole AND_CNT penetrating the protection film 150 and the planarization film 160.

[0180] In a top emission structure in which light is emitted from the organic emission layer 172 toward the second electrode 173, the first electrode 171 may be formed of a conductive material having a high reflectivity such as a stacked structure of Al and Ti (Ti / Al / Ti), a stacked structure of Al and indium tin oxide (ITO) (ITO / Al / ITO), an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0181] The pixel defining film 180 may be formed to divide the first electrode 171 on the planarization film 160, thereby defining the emission area EA of each of the sub-pixels SP. The pixel defining film 180 may be formed to cover the edge of the first electrode 171. The pixel defining film 180 may be formed of an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0182] The emission area EA of each of the subpixels SP indicates a region where the first electrode 171, the organic emission layer 172, and the second electrode 173 are sequentially stacked in this order, and holes from the first electrode 171 and electrons from the second electrode 173 are combined with each other in the organic emission layer 172 so that light is emitted.

[0183] The organic emission layer 172 is formed on the first electrode 171 and the pixel defining film 180. The organic emission layer 172 may include an organic material and emit light of a color (e.g., a set color or a predetermined color). For example, the organic emission layer 172 may include a hole transport layer, an organic material layer, and an electron transport layer. The organic emission layer 172 of the first sub-pixel may emit light of a first color, the organic emission layer 172 of the second sub-pixel may emit light of a second color, and the organic emission layer 172 of the third sub-pixel may emit light of a third color. Alternatively, the organic emission layer 172 of the sub-pixel SP may emit white light. In this case, the first sub-pixel may overlap with the color filter layer of the first color, the second sub-pixel may overlap with the color filter layer of the second color, and the third sub-pixel may overlap with the color filter layer of the third color. In this specification, for ease of description, it will be described by assuming that the first color is red, the second color is green, and the third color is blue.

[0184] The second electrode 173 is formed on the organic emission layer 172. The second electrode 173 may be formed to cover the organic emission layer 172. The second electrode 173 may be a common layer commonly formed in the sub-pixels SP. A cover layer may be formed on the second electrode 173.

[0185] In the top emission structure, the second electrode 173 may be formed of a transparent conductive material (TCO) such as ITO and indium zinc oxide (IZO) or a semi-transmissive conductive material such as magnesium (Mg), Ag, or an alloy of Mg and Ag. When the second electrode 173 is formed of a semi-transmissive conductive material, light output efficiency may be improved through the microcavity.

[0186] The encapsulation layer TFE may be formed on the light emitting element layer. The encapsulation layer TFE may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light emitting element layer. In addition, the encapsulation layer TFE may include at least one organic film to prevent the light emitting element layer from being affected by foreign matter such as dust.

[0187] Alternatively, the second substrate may be arranged on the light emitting element layer instead of the encapsulation layer TFE, and the space between the light emitting element layer and the second substrate may be empty in vacuum or filled with a filling film. The filling film may be an epoxy filling film or a silicon filling film.

[0188] According to some example embodiments, Figures 15 to 17 As illustrated in FIG. 1 , the second gate electrode DT_G2 of the driving transistor DT may be connected to the k-1th scan line Sk-1 via the first connection electrode BE1. The first connection electrode BE1 may be formed on the first substrate SUB1. Accordingly, the first connection electrode BE1 may intersect the k-1th scan line Sk, the second electrode D1-2 of the 1-2nd transistor ST1-2, and the second electrode D3-2 of the 3-2nd transistor ST3-2 located between the k-1th scan line Sk-1 and the second gate electrode DT_G2 of the driving transistor DT, and connect the k-1th scan line Sk-1 and the second gate electrode DT_G2 of the driving transistor DT to each other.

[0189] According to some example embodiments of the present disclosure, since the voltage difference between the second gate electrode and the first electrode of the driving transistor can be controlled to be lower than the threshold voltage of the driving transistor when the driving transistor is biased to be turned on by connecting the second gate electrode of the driving transistor to the k-1th scan line, the driving current of the driving transistor can be increased. Accordingly, the brightness difference in the light emitting element that occurs due to the hysteresis characteristics of the driving transistor when the light emitting element displays black brightness and then displays white brightness can be reduced.

[0190] In addition, according to some example embodiments of the present disclosure, since the voltage difference between the second gate electrode and the first electrode of the driving transistor during the period in which the light-emitting element emits light can be controlled to be higher than 0V, the driving current curve of the driving transistor can be negatively offset. Therefore, the offset of the driving current curve of the driving transistor due to the hysteresis characteristics of the driving transistor between when black brightness is displayed and when white brightness is displayed can be reduced. Accordingly, not only can the brightness difference of the light-emitting element due to the hysteresis characteristics of the driving transistor when black brightness is displayed and then white brightness is displayed be reduced, but also the time when the instantaneous afterimage is generated can be reduced.

[0191] Further, according to some example embodiments of the present disclosure, the second gate electrode of the driving transistor may be connected to the k-1th scan line through the first connecting electrode. The first connecting electrode may be formed on the first substrate. Accordingly, the first connecting electrode may connect the k-1th scan line and the second gate electrode of the driving transistor to each other by crossing the k-1th scan line, the second connecting electrode, the second electrode of the 1-2 transistor, and the second electrode of the 3-2 transistor between the k-1th scan line and the second gate electrode of the driving transistor.

[0192] The use of “may” when describing embodiments of the present invention means “one or more embodiments of the present invention.” Additionally, the term “exemplary” is intended to refer to an example or illustration.

[0193] Although certain example embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the subject matter of the embodiments according to the present disclosure is not limited to the example embodiments, but is limited to the broader scope of the attached claims and their equivalents, which is apparent to those of ordinary skill in the art.

Claims

1. A display device, comprising: A k-1th scanning line and a kth scanning line parallel to each other, wherein k is a positive integer of 2 or more; The jth data line intersects the k-1th scan line and the kth scan line, wherein j is a positive integer; a sub-pixel connected to the k-1th scan line, the kth scan line and the jth data line; and an initialization voltage line, configured to receive an initialization voltage, Wherein, the sub-pixel comprises: a driving transistor configured to control a driving current flowing from a first electrode of the driving transistor to a second electrode of the driving transistor according to a data voltage applied to a first gate electrode of the driving transistor, the driving transistor having a second gate electrode connected to the k-1th scan line, and a light emitting element configured to emit light according to the driving current, wherein, during a first period in which the initialization voltage is applied to the first gate electrode of the driving transistor, a first level voltage of a k-1th scan signal of the k-1th scan line is applied to the second gate electrode, and During the first period, the first level voltage of the (k-1)th scan signal is lower than the initialization voltage.

2. The display device according to claim 1, further comprising an initialization voltage line, the initialization voltage line being configured to receive an initialization voltage, in, The subpixel further includes a first transistor configured to be turned on in response to a (k-1)th scan signal of the (k-1)th scan line, wherein the first transistor is configured to connect the first gate electrode of the driving transistor to the initialization voltage line.

3. The display device according to claim 2, wherein: The sub-pixel further comprises: a second transistor configured to be turned on in response to a kth scan signal of the kth scan line, wherein the second transistor is configured to connect the first electrode of the driving transistor to the jth data line; a third transistor configured to be turned on in response to the kth scan signal, wherein the third transistor is configured to connect the first gate electrode of the driving transistor to the second electrode of the driving transistor; and A fourth transistor is configured to be turned on in response to the kth scan signal, wherein the fourth transistor is configured to connect the first electrode of the light emitting element to the initialization voltage line.

4. The display device according to claim 3, further comprising: a kth light emitting line parallel to the k-1th scanning line and the kth scanning line; and A first driving voltage line is configured to receive a first driving voltage, Wherein, the sub-pixel further comprises: a fifth transistor configured to be turned on in response to a kth light emitting signal of the kth light emitting line, wherein the fifth transistor is configured to connect the first electrode of the driving transistor to the first driving voltage line; and a sixth transistor configured to be turned on in response to the kth light emitting signal, wherein the sixth transistor is configured to connect the second electrode of the driving transistor to the light emitting element.

5. The display device according to claim 1, wherein: During the first period, a voltage difference between the second gate electrode and the first electrode of the driving transistor is lower than a voltage difference between the first gate electrode and the first electrode of the driving transistor.

6. The display device according to claim 1, wherein: During a second period in which the data voltage of the jth data line is applied to the first gate electrode of the driving transistor, a second level voltage of the k-1th scan signal of the k-1th scan line is applied to the second gate electrode.

7. The display device according to claim 6, wherein: During the second period, the second level voltage of the (k-1)th scan signal is higher than the data voltage.

8. The display device according to claim 6, wherein: During the second period, a voltage difference between the second gate electrode and the first electrode of the driving transistor is higher than a voltage difference between the first gate electrode and the first electrode of the driving transistor.

9. The display device according to claim 1, wherein: During a third period in which the light emitting element emits light according to the driving current of the driving transistor, a second level voltage of the k-1th scan signal of the k-1th scan line is applied to the second gate electrode.

10. The display device according to claim 9, wherein: During the third period, a voltage difference between the second gate electrode and the first electrode of the driving transistor is higher than a voltage difference between the first gate electrode and the first electrode of the driving transistor. 11 . The display device according to claim 1 , further comprising a first connection electrode connecting the (k-1)th scan line to the second gate electrode of the driving transistor.

12. The display device according to claim 11, wherein: The first connection electrode is on the same layer as the second gate electrode of the driving transistor. 13 . The display device according to claim 11 , further comprising at least one insulating film between the (k-1)th scan line and the first connection electrode.

14. The display device according to claim 13, wherein: The at least one insulating film comprises: a buffer film on the first connection electrode and the second gate electrode of the driving transistor; and A gate insulating film is provided on the first electrode of the driving transistor.

15. The display device according to claim 14, wherein: The k-1th scanning line is on the gate insulating film.

16. The display device according to claim 14, wherein: The k-1th scan line is connected to the first connection electrode via a first connection contact hole that passes through the buffer film and the gate insulating film.

17. The display device according to claim 11, wherein: The sub-pixel further comprises: a first transistor having a gate electrode connected to the (k-1)th scan line and a first electrode connected to the initialization voltage line; and A second connection electrode connects the second electrode of the first transistor to the first gate electrode of the driving transistor.

18. The display device according to claim 17, wherein: The first connection electrode and the second connection electrode overlap each other.

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