Memory, storage system having the same and operating method thereof

Abstract

A storage system can be provided that includes a first central processing unit, a first storage module connected to the first central processing unit through a first channel, a second storage module connected to the first central processing unit through a second channel, and a third storage module connected to the first central processing unit through a third channel. Each of the first storage module, the second storage module, and the third storage module can be configured to write the same data into a data area thereof and a mirror data area thereof in response to an address in a mirror mode.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0123681, filed on October 7, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a memory for improving the reliability of data, a storage system having the memory, and / or a method of operating the memory. Background Technology

[0004] As dynamic random access memory (DRAM) processing is miniaturized, battery characteristics may degrade, and the likelihood of cell defects may increase. Memory failure can be a significant issue in applications such as data centers and autonomous vehicles. Therefore, devices for repairing such failures are desirable when unit or multi-bit errors occur in the memory. Summary of the Invention

[0005] The present invention provides a memory for improving the reliability of data, a storage system having the memory, and / or a method of operating the memory.

[0006] According to aspects of the present invention, a storage system may include: a first central processing unit; a first storage module connected to the first central processing unit via a first channel; a second storage module connected to the first central processing unit via a second channel; and a third storage module connected to the first central processing unit via a third channel. Each of the first, second, and third storage modules may be configured to write the same data in its data area and its mirrored data area in response to an address in mirrored mode.

[0007] According to aspects of the present invention, a storage system may include at least one memory and a memory controller for controlling the at least one memory. The at least one memory may include: a first storage region configured to store write data during a write operation in mirror mode; a second storage region configured to store write data during a write operation in mirror mode; and processing circuitry configured to generate a read failure signal when a read operation on the first storage region fails in mirror mode.

[0008] According to aspects of the inventive concept, a storage system can include at least one memory configured to generate an error detection signal when an error is detected in data output from a memory cell array during a read operation, and write the same data to a first storage area of the at least one memory and a second storage area of the at least one memory during a write operation in a mirror mode, and a memory controller configured to control the at least one memory with the error detection signal. The memory controller can be configured to monitor the error detection signal to determine whether the mirror mode of the at least one memory is activated.

[0009] According to aspects of the inventive concept, a method of operating a memory can include setting a mirror mode, writing the same data to a first storage area of the memory and a second storage area of the memory corresponding to a single address during a write operation, detecting an error of data read from the first storage area during a read operation, changing a data output path of the read operation when a number of the detected errors is equal to or greater than a reference value, and requesting a read-recovery to a memory controller when the number of the detected errors is equal to or greater than the reference value.

[0010] According to aspects of the inventive concept, a memory can include a memory cell array having a first storage area and a second storage area, the memory cell array having a plurality of memory cells connected to a word line and a bit line, a row decoder configured to select any one of the word lines in response to a row address, a sense amplifier circuit configured to sense data from the memory cells connected to the selected bit line during a read operation, a column decoder configured to select a selected bit line among the bit lines in response to a column address, an address buffer configured to store an address having the row address and the column address, and a processing circuit configured to correct an error of the sensed data, and generate a read failure signal when an error correction has failed, a mirror mode activation signal corresponding to a mirror mode in which the same write data is written to the first storage area and the second storage area during a write operation, and change a data output path of a read operation from a first data output path of the first storage area to a second data output path of the second storage area in response to a read retry command in the mirror mode. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above and other aspects, features, and advantages of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a diagram illustrating a normal operation of a general storage system.

[0013] Figure 2 is a diagram illustrating a lane mirroring operation of a general storage system.

[0014] Figure 3 is a diagram illustrating a storage system 10 according to example embodiments of inventive concepts.

[0015] Figure 4 is a diagram illustrating a storage module 12-1 according to example embodiments of inventive concepts.

[0016] Figure 5 is a diagram illustrating a memory 100 according to example embodiments of inventive concepts.

[0017] Figure 6 is a diagram illustrating a write operation of the memory 100 in the on-die mirror mode according to example embodiments of inventive concepts.

[0018] Figure 7 is a diagram illustrating a mirror mode activation signal generator 190 according to example embodiments of inventive concepts.

[0019] Figure 8A is a diagram illustrating a read failure handling in the on-die mirror mode according to example embodiments of inventive concepts, and Figure 8B is a diagram illustrating a read retry handling in the on-die mirror mode according to example embodiments of inventive concepts.

[0020] Figure 9 is a diagram illustrating a configuration of a row address RA according to example embodiments of inventive concepts.

[0021] Figure 10 is a diagram illustrating a storage system 20 according to example embodiments of inventive concepts.

[0022] Figure 11A is a diagram illustrating a read failure indicator 180 using an error correction circuit ECC, and Figure 11B is a diagram illustrating a read failure indicator 180 according to a data comparison method.

[0023] Figure 12A is a diagram illustrating sending of a read failure signal (RFS) to a memory controller 200 through an EIS pin of a memory 100, Figure 12B is a diagram illustrating sending of the RFS to the memory controller 200 through a DQS pin of the memory 100, and Figure 12C is a diagram illustrating sending of the RFS to the memory controller 200 through a mode register.

[0024] Figure 13 is a diagram illustrating a storage system 30 according to another example embodiment of inventive concepts.

[0025] Figure 14FIG. 1 is a diagram illustrating a result of monitoring error correction operations and on-die mirror activation portions according to example embodiments of the present inventive concepts.

[0026] Figure 15 FIG. 2 is a ladder diagram illustrating on-die mirror operations of a storage system according to example embodiments of the present inventive concepts.

[0027] Figure 16 FIG. 3 is a diagram illustrating a basic input / output system (BIOS) setting according to example embodiments of the present inventive concepts.

[0028] Figure 17 FIG. 4 is a diagram illustrating a TMRS setting according to example embodiments of the present inventive concepts.

[0029] Figure 18 FIG. 5 is a diagram illustrating a MR setting according to example embodiments of the present inventive concepts.

[0030] Figure 19 FIG. 6 is a diagram illustrating an electronic device 40 according to example embodiments of the present inventive concepts.

[0031] Figure 20 FIG. 7 is a flowchart illustrating an operating method of a memory according to example embodiments of the present inventive concepts.

[0032] Figure 21 FIG. 8 is a flowchart illustrating an operating method of a memory controller according to example embodiments of the present inventive concepts.

[0033] Figure 22 FIG. 9 is a flowchart illustrating an operating method of a storage system according to example embodiments of the present inventive concepts.

[0034] Figure 23 FIG. 10 is a block diagram illustrating a memory according to example embodiments of the present inventive concepts.

[0035] Figure 24 FIG. 11 is a diagram illustrating a computing system 2000 according to example embodiments of the present inventive concepts.

[0036] Figure 25 FIG. 12 is a diagram illustrating a mobile device 3000 according to example embodiments of the present inventive concepts.

[0037] Figure 26 FIG. 13 is a diagram illustrating a computing system 4000 according to example embodiments of the present inventive concepts.

[0038] Figure 27 FIG. 14 is a diagram illustrating a data server system 5000 according to example embodiments of the present inventive concepts. DETAILED DESCRIPTION

[0039] Hereinafter, example embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0040] Figure 1 is a diagram illustrating normal operation of a general storage system. Referring to Figure 1 , the storage system can include 2 CPUs (central processing units) (CPU1 and CPU2), 3 channels (CH1, CH2, and CH3) connected to CPU1, and 3 channels (CH4, CH5, and CH6) connected to CPU2, and 3-DIMMs (dual in-line memory modules). As Figure 1 illustrated, the storage system can include a plurality of DIMMs, three DIMMs connected to each of six channels CH1 to CH6, and in normal operation, the storage system can use a total of 18 DIMMs. For example, the storage system can employ a channel mirroring operation to improve reliability.

[0041] Figure 2 is a diagram illustrating a channel mirroring operation of a general storage system. Referring to Figure 2 , the channel mirroring operation has problems such as performance reduction and storage capacity reduction (1 / 2 of the total storage capacity of normal operation, or 1 / 3 in the worst case) according to the reduction of channels.

[0042] When the mirroring mode is not applied, as illustrated in Figure 1 , the storage system can completely operate the channels and the DIMMs, and thus can have an effect on the storage capacity and the performance. When the mirroring mode is applied, as shown in Figure 2 , reliability can be improved according to the mirroring operation of CH1 / CH2. Because CH1 is used for the mirroring mode operation, but CH2 is not used, the total capacity can be reduced to 1 / 3. In addition, because there is no channel operation, the overall performance can be reduced.

[0043] In addition, the channel mirroring operation requires an additional error correction code (ECC) configuration inside the storage module for bad reads. It can be difficult to apply this to a storage system that performs a storage operation without using channels and does not have an ECC configuration. For example, when a failure occurs during a memory access operation in an autonomous vehicle, a mobile system, and a graphics system to which a session initiation protocol (SIP) is applied, system suspension or abnormal data processing can cause a serious problem.

[0044] A storage system according to an example embodiment of the inventive concept can operate through an on-die mirroring technique that enables reliability to be achieved in a mirroring mode without causing reduction in performance and capacity. In this case, the on-die mirroring technique can be a method that performs a mirroring operation by itself in a storage module.

[0045] Figure 3 is a diagram illustrating a storage system 10 according to example embodiments of the present inventive concepts. Referring to Figure 3 , the storage system 10 can include a first CPU 11-1, a second CPU 11-2, three channels CH1 to CH3 and CH4 to CH6 connected to each of the first CPU 11-1 and the second CPU 11-2, and storage modules 12-1, 12-2, and 12-3 connected to each of the channels CH1 to CH3 and CH4 to CH6. It should be understood that the number of CPUs, the number of channels, and the number of storage modules are not limited thereto.

[0046] In some example embodiments, each of the storage modules 12-1, 12-2, and 12-3 can be implemented with a single inline memory module (SIMM), a dual inline memory module (DIMM), and a small outline DIMM (SODIMM), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FBDIMM), a rank-buffered DIMM (RBDIMM), a mini-DIMM, a micro-DIMM, a registered DIMM (RDIMM), or a load-reduced DIMM (LRDIMM). In example embodiments, each of the storage modules 12-1, 12-2, and 12-3 can include a volatile storage device or a non-volatile storage device.

[0047] In example embodiments, the storage system 10 can perform an on-die mirroring operation in each of the storage modules 12-1, 12-2, and 12-3 connected to the channels CH1, CH2, and CH3 in an on-die mirroring mode. In this case, the on-die mirroring operation can include a write operation to write the same data into a first region (which can be interchangeably referred to as a data area (DA) or a first storage region) and a second region (which can be interchangeably referred to as a mirror data area (MDA) or a second storage region) simultaneously in response to a single address, and a read operation to output data read from any one of the first region DA and the second region MDA in response to any one address.

[0048] In example embodiments, the storage system 10 can perform a read retry in each of the storage modules 12-1, 12-2, and 12-3 in the on-die mirroring mode. In this case, the read retry is to perform a read operation on the second region MDA when a read operation on the first region DA fails.

[0049] According to example embodiments of the present inventive concepts, the storage system 10 can include a plurality of storage modules 12-1, 12-2, and 12-3 performing an on-die mirroring operation, and thus can guarantee data reliability while minimizing a reduction in performance and capacity even in a mirroring mode.

[0050] Figure 4 is a diagram illustrating a storage module 12-1 according to an example embodiment of the inventive concept. Referring to Figure 4 , the storage module 12-1 can include a plurality of memories 100-1, 100-2, 100-3, and 100-4 and a registered clock driving circuit RCD 300.

[0051] Each of the memories 100-1 to 100-4 can include a volatile memory (e.g., a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a double data rate SDRAM (DDR SDRAM), a low power double data rate SDRAM (LPDDR SDRAM), a graphics double data rate SDRAM (GDDR SDRAM), a RAMBUS DRAM (RDRAM), or a static RAM (SRAM)) or a non-volatile memory (e.g., a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), or a flash memory). In an example embodiment, each of the plurality of memories 100-1 to 100-4 can be implemented as a DRAM according to various standards (e.g., DDR, DDR2, DDR3, DDR4, or DDR5). Although the number of memories of the storage module illustrated in Figure 4 is 4, it can be appreciated that the inventive concept is not limited thereto.

[0052] In an example embodiment, each of the plurality of memories 100-1 to 100-4 can be implemented to perform an on-die mirroring operation. As Figure 4 illustrated, each of the memories 100-1 to 100-4 can include a first area A and a second area B that store the same data in response to a single address.

[0053] The registered clock driving circuit RCD 300 can be implemented to receive a command, an address, and a clock from the CPU 11-1. The registered clock driving circuit RCD 300 can transmit the received command, address, and clock to the memories 100-1 to 100-4.

[0054] Figure 5 is a diagram illustrating a memory 100 according to an example embodiment of the inventive concept. Referring to Figure 5The memory 100 can include a memory cell array 110, a row decoder (or row decoder circuit) 120, a sense amplifier circuit SA 130, a column decoder (or column decoder circuit) 140, an address buffer 150, control logic 160, an input / output circuit 170, a read failure indicator 180, and a mirror mode activation signal generator 190. The control logic 160, the read failure indicator 180, and / or the mirror mode activation signal generator 190 can include processing circuitry such as hardware including logic circuits and the like; a hardware / software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry can more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), and the like.

[0055] The memory cell array 110 can include a plurality of memory banks having a plurality of memory cells arranged in a row direction and a column direction. In this case, the memory cells can be volatile / non-volatile memory cells, respectively. In an example embodiment, the memory cell array 110 can include a first area A (normal data area) and a second area B (mirror data area).

[0056] The row decoder 120 can be implemented to select any one of a plurality of word lines in response to a row address RA. For example, the row decoder 120 can decode the row address RA output from the address buffer 150 in a data write / read mode, and select a word line corresponding to the row address RA. In detail, the memory cells of the first area A and the memory cells of the second area B can be activated at the same time by the selection of the word line by the row decoder 120.

[0057] In addition, the row decoder 120 can refresh the word lines correspondingly based on a row address generated by a refresh control circuit 161.

[0058] The sense amplifier circuit 130 can be implemented to sense / amplify data of the selected memory cells. For example, the sense amplifier circuit 130 can sense data by sensing / amplifying a voltage of a bit line selected by the column decoder 140. When the memory bank includes a plurality of sub-arrays, the sense amplifier circuit 130 can include a plurality of sense amplifiers.

[0059] The column decoder 140 can be implemented to select a bit line connected to a memory cell in response to a column address CA. For example, the column decoder 140 can decode the column address CA output from the address buffer 150 in a data write / read mode, and select a bit line corresponding to the column address CA. In more detail, the column decoder 140 can be connected to the memory cell array 110 through a column selection line. The column decoder 140 can select the column selection line based on a write / read command. When the column decoder 140 selects the column selection line, a bit line BL can be selected.

[0060] The address buffer 150 can be implemented to receive an address ADD from an external device, for example, a memory controller. In this case, the address ADD can include a row address RA, a column address CA, a bank address, a bank group address, etc.

[0061] The control logic 160 can be implemented to control overall operations of the memory 100. The control logic 160 can include a refresh control circuit 161, a command decoder 162, and a mode register circuit (MRC) 163.

[0062] The refresh control circuit 161 can receive a decoded refresh signal from the command decoder 162, and can output an internal row address to the row decoder 120 to refresh one word line of the memory cell array 110.

[0063] The command decoder 162 receives a command CMD from an external device (a memory controller), and can internally generate a command signal, for example, an activate signal, a read signal, a write signal, a refresh signal, etc., by decoding the received command CMD.

[0064] The mode register circuit (MRC) 163 can set an internal mode register in response to a mode register set (MRS) / extended mode register set (EMRS) command for designating an operation mode of the memory 100. The mode register circuit (MRC) 163 can output an activate signal to the input / output circuit 170 depending on a write operation / read operation to control operations of the input / output circuit 170. In addition, the mode register circuit (MRC) 163 can include a register setting a mirror mode for performing an on-die mirroring operation. In Figure 5 In the embodiment, the on-die mirroring mode can be set by the mode register set (MRS), but it should be understood that the inventive concept can not be limited thereto.

[0065] On-die mirroring mode of the inventive concept can be set by data received through at least one dedicated or predetermined pin. In an example embodiment, test mode register setting (TMRS) can be set by a basic input / output system (BIOS) setting in a system to activate on-die mirroring operation, a standardized mode register (MR) setting can be issued to activate on-die mirroring operation, or a fuse can be blown to activate on-die mirroring operation with a default mirroring operation.

[0066] The input / output circuit 170 can receive data from the external device through the DQ pin during a write operation, and can deliver the received data to the sense amplifier circuit 130. Also, the input / output circuit 170 can receive data read by the sense amplifier circuit 130 from the memory cell corresponding to the address ADD during a read operation, and can output the received data to the external device through the DQ pin.

[0067] Also, the input / output circuit 170 can be implemented to change a data output path according to a read retry command of the external device (memory controller). For example, the input / output circuit 170 can select a first read output path (normal data output path) to output data of the first region A in a normal read operation, and can select a second read output path (mirrored data output path) to output data of the second region B in a read operation according to the read retry command. Although not illustrated, a switching circuit for selecting the first read output path and the second read output path can be provided.

[0068] The read failure indicator 180 can detect an error in the detected data during a read operation, and can generate a read failure signal (RFS) corresponding to the detected error. For example, when the number of detected errors is equal to or greater than a reference value, the read failure indicator 180 can generate the read failure signal (RFS).

[0069] The mirror mode activation signal generator 190 can generate an on-die mirroring mode activation signal OMMEN corresponding to the mirroring mode.

[0070] Although not illustrated in Figure 5 , the memory 100 can additionally include a clock circuit generating a clock signal, a power supply circuit generating or distributing an internal voltage by receiving an externally applied power supply voltage.

[0071] The memory 100 according to an example embodiment of the inventive concept can determine whether a read operation has failed, can transmit a read failure signal (RFS) corresponding to the result to the external device, and can output data of a mirrored region in response to a read retry command from the external device.

[0072] Figure 6 is a diagram illustrating a mirror mode activation signal generator 190 according to an example embodiment. Referring to Figure 6 , the mirror mode activation signal generator 190 can include a first logic circuit 191 and a second logic circuit 192.

[0073] The first logic circuit 191 can be implemented to perform an OR operation on a TMRS code value and a fuse cut information. In this case, the fuse cut information can be generated by a fuse cut corresponding to the on-die mirror mode in a test operation described with reference to Figure 3 and Figure 4 Thus, the fuse cut information can be determined in the test operation.

[0074] The second logic circuit 192 can generate a mirror mode activation signal OMMEN by performing an OR operation on a BIOS / MR value and an output value of the first logic circuit 191.

[0075] Figure 7 is a diagram illustrating a write operation of the memory 100 in the on-die mirror mode according to an example embodiment. Referring to Figure 7 , in response to a row address RA and a column address CA, write data can be written to a memory cell connected to a selected word line WL and a selected bit line BL in each of the first area A and the second area B. The same data can be written to two memory cells corresponding to one row address RA.

[0076] The first area A and the second area B illustrated in Figure 7 may be accessed by a column decoder 140 shared by corresponding row decoders 121 and 122, but the structure of the row decoder / column decoder is not limited thereto.

[0077] Figure 8A is a diagram illustrating a read failure handling in the on-die mirror mode according to an example embodiment, and Figure 8B is a read retry handling in the on-die mirror mode according to an example embodiment.

[0078] Referring to Figure 8A , for example, when a memory cell of the first area A is defective, there can be a failure in reading read data. When the read fails, the memory 100 can transmit a read failure signal (RFS) to an external device (a memory controller).

[0079] Referring to Figure 8B , when a read retry request is received from the external device, the memory 100 can output data read from a memory cell of the second area B as the read data.

[0080] It should be noted that example embodiments are not limited to read retry. Upon a read failure in the first area A, the memory according to example embodiments can immediately output data of the storage unit of the second area B to the external device without sending a read failure signal (RFS) for requesting read retry to the external device.

[0081] Figure 9 is a diagram illustrating a configuration of a row address RA according to example embodiments. Referring to Figure 9 , the row address RA can include k row address bits ADD1, ADD2, ADD3,..., and ADDk. According to example embodiments, the row decoder 120 of the memory 100 can ignore (not care about) the most significant bit (MSB) of the row address ADD, for example, the first address bit ADD1. For example, the memory 100 can access the first area A and the second area B through k-1 address bits.

[0082] In example embodiments, a pin that transmits the most significant bit MSB (ADD1) of the row address RA in the memory 100 can be used as a pin that transmits a read failure signal (RFS). For example, when a storage unit is defective, the pin that transmits the most significant bit MSB of the row address RA can output a high-level signal to the memory controller.

[0083] To implement the on-die mirror memory according to example embodiments of the inventive concept, the most significant bit of the row address can be ignored. It should be understood that the inventive concept is not limited thereto. In some example embodiments, the on-die mirror memory of the inventive concept can be implemented to ignore other bits in addition to the most significant bit of the row address.

[0084] The row address can be used to implement the on-die mirror memory according to example embodiments of the inventive concept. It should be understood that the inventive concept is not limited thereto. Some example embodiments of the inventive concept can perform the on-die mirroring function according to at least one of various types of addresses (for example, a column address, a bank address, or a bank group address) depending on the design of the memory.

[0085] Figure 3 to Figure 9 is a diagram illustrating an on-die mirroring scheme applied to a storage system 10 using a channel. In addition to the storage system 10 using a channel, the on-die mirroring scheme according to example embodiments of the inventive concept can be applied to a storage system that does not require a channel.

[0086] Figure 10 is a diagram illustrating a storage system 20 according to example embodiments of the inventive concept. Referring to Figure 10The memory system 20 can include a memory (DRAM) 100 and a memory controller 200 that controls the memory chip. The memory controller 200 can include processing circuitry such as hardware including logic circuits; a hardware / software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry can more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), and the like.

[0087] The memory 100 can include an array of memory cells 110 having a first area A and a second area B to which the same data is written in response to a single address, and a read failure indicator 180 that detects a read failure in a read operation of the first area A / second area B.

[0088] In an example embodiment, the read failure indicator 180 can generate a read failure signal (RFS) during a read operation of any one of the first area (A) and the second area (B), and can transmit the read failure signal (RFS) to the memory controller 200.

[0089] The memory controller 200 can receive the read failure signal (RFS) from the memory 100, and request a read retry to the memory 100. The memory 100 can output data read from an area (e.g., the second area B) other than an area in which a read failure has occurred (e.g., the first area A) to the memory controller 200 in response to the read retry command.

[0090] Figure 11A is a diagram illustrating a read failure indicator 180 using an error correction circuit ECC, and Figure 11B is a diagram illustrating a read failure indicator 180 according to a data comparison method.

[0091] Referring to Figure 11A The read failure indicator 180 can include an error correction circuit 181. The error correction circuit 181 can be implemented to correct an error of read data. Meanwhile, the error correction circuit 181 can generate a read failure signal (RFS) when error correction is not possible (e.g., when error correction has failed). Referring to Figure 11BThe read failure indicator 180 can include a logic circuit 182. Normal area data and mirror area data can be output from the first area A and the second area B in response to the same address ADD. The logic circuit 182 can output a read failure signal (RFS) by performing an XOR operation on the normal area data and the mirror area data. For example, the read failure signal (RFS) can be output when the normal area data and the mirror area data are different from each other. The read failure signal (RFS) can be used for a read retry request of the memory controller 200.

[0092] The memory 100 can generate a read retry request in response to the read failure signal (RFS), and can transmit the read retry request to the controller 200 in various ways. For example, the memory 100 can transmit the read retry request to the controller 200 through an additional pin, can transmit the read retry request to the controller 200 through a DQS dummy signal, or can transmit the read retry information to the controller 200 by using a mode register (MR) read operation of the controller 200.

[0093] In addition, the memory 100 can directly transmit the read failure signal (RFS) to the memory controller 200 in various ways in response to the read failure signal (RFS) without generating a read retry request. For example, the read failure signal (RFS) can be transmitted to the memory controller 200 through a separate error indication signal (EIS) pin, or the read failure signal (RFS) can be transmitted to the memory controller 200 by loading an additional bit in the DQS line. In some example embodiments, the memory controller 200 can check the state of the memory 100 through a mode register MR.

[0094] Figure 12A FIG. 2 is a diagram illustrating transmission of a read failure signal (RFS) to a memory controller 200 through an EIS pin of a memory 100, Figure 12B FIG. 3 is a diagram illustrating transmission of an RFS to a memory controller 200 through a DQS pin of a memory 100, and Figure 12C FIG. 4 is a diagram illustrating transmission of an RFS to a memory controller 200 through a mode register.

[0095] Referring to Figure 12A The read failure signal (RFS) generated from the read failure indicator 180 can be transmitted to the memory controller 200 through a separate EIS pin of the memory 100.

[0096] Referring to Figure 12B The read failure signal (RFS) generated from the read failure indicator 180 can be transmitted to the memory controller 200 through a DQS pin.

[0097] Referring to Figure 12CThe read failure signal (RFS) generated from the read failure indicator 180 can be stored in the mode register 163-1, and the memory controller 200 can receive the read failure signal (RFS) by periodically or non-periodically reading the mode register 163-1. In an example embodiment, the memory controller 200 can read the mode register 163-1 of the memory 100 according to an internal policy.

[0098] Referring to Figure 10 , FIG. 11, Figure 12A , Figure 12B and Figure 12C The read retry operation in the on-die mirror mode has been described for the storage system 20 described in FIGS. 11, 12, and 13. In some example embodiments, the inventive concept storage system can set the on-die mirror mode during system operation.

[0099] Figure 13 is a diagram illustrating a storage system 30 according to another example embodiment of the inventive concept. Referring to Figure 13 , the storage system 30 can include a memory 100a and a memory controller 200a.

[0100] The memory 100a can include an error correction circuit ECC 182a that detects an error in read data and generates an error signal (ES). The error signal (ES) can be transmitted to the memory controller 200a.

[0101] The memory controller 200a can include an on-die mirror activation determiner (or on-die mirror activation determination circuit) 210 that receives the error signal (ES) from the memory 100a and determines whether the on-die mirror operation is activated. The memory controller 200a can monitor the error correction operation of the memory 100a, check a deterioration state of the storage unit, and quantify the likelihood of failure occurrence. When the likelihood of failure occurrence exceeds a certain threshold, the memory controller 200a can use a BIOS / MR / TRMS, etc. to activate the on-die mirror mode of the memory 100a in an on-the-fly manner.

[0102] Figure 14 is a diagram illustrating a result of monitoring the error correction operation and the on-die mirror activation part according to an example embodiment of the inventive concept. Referring to Figure 14 , it can be seen that the number of failure cases gradually increases over time.

[0103] As illustrated in Figure 14 , the on-die mirror activation part can include a first activation part 0~N1 and a second activation part N2~N3.

[0104] The first active portion 0~N1 can be a portion having a high probability of occurrence of double error correction (DEC). The second active portion N2~N3 can be a portion that can be rescued by a cell but activates an on-die mirroring operation in consideration of a deterioration time. For example, when a first time T1 has passed and the number of failure cases in DEC exceeds N1, an on-die mirroring mode can be entered. When a second time T2 has passed and the number of failure cases in single error correction (SEC) is between N2 and N3, an on-die mirroring mode can be entered.

[0105] It should be understood that the on-die mirroring active portion of the inventive concept is not limited thereto. The on-die mirroring activation can be considered in advance or initially set considering various environmental information.

[0106] Figure 15 is a ladder diagram illustrating an on-die mirroring operation of a memory system according to an example embodiment of the inventive concept. Referring to Figure 15 , the on-die mirroring operation of the memory system 20 (see Figure 10 ) can proceed as follows.

[0107] When the on-die mirroring operation is expected for the memory, the memory controller 200 (see Figure 10 ) can perform a BIOS setting control change (S10). The memory controller 200 can generate test mode register set (TMRS) / mode register (MR) setting information for the on-die mirroring operation of the memory 100 (S11). The TMRS / MR setting information can be transmitted from the memory controller 200 to the memory 100.

[0108] The memory 100 can receive the TMRS / MR setting information and can set an on-die mirroring mode (S20). Thereafter, the memory 100 can perform the on-die mirroring operation (S21). For example, the same data can be written in the normal area A and the mirror area in a single write command.

[0109] When the memory 100 enters the on-die mirroring mode (S12), the memory controller 200 can change the memory address mapping. For example, although the access to the memory 100 can be performed using a full address in a normal mode, the access to the memory 100 can be performed by ignoring the most significant bit of a row address in the on-die mirroring mode. For example, the storage capacity of the memory 100 in the on-die mirroring mode can be adjusted to half of its storage capacity in the normal mode.

[0110] In the on-die mirroring mode, the memory controller 200 can issue a read command (S13). The memory controller 200 can transmit the read command to the memory 100. The memory 100 can perform a read operation in response to the read command, and when the read operation fails, can generate a read failure signal (RFS) from the read failure indicator 180 (see FIG. 10). Figure 10 ) When the read failure signal (RFS) is generated, the memory 100 can transmit the read failure signal (RFS) to the memory controller 200 for read retry.

[0111] The memory controller 200 can receive the read failure signal (RFS) from the memory 100, and can issue a read retry command (S14). The memory controller 200 can transmit the read command to the memory 100.

[0112] The memory 100 can perform a read retry operation of outputting data of the mirrored area as read data in response to the read retry command (S23).

[0113] The on-die mirroring memory with a read failure indicator according to the example embodiments of the inventive concept can be activated in connection with a system reliability operation. For an application requiring high reliability such as a data center or a vehicle, etc., a vendor regarding the application can initially set up a BIOS from an initial stage to perform an on-die mirroring operation using half of the memory.

[0114] Figure 16 is a diagram illustrating a BIOS setting according to the example embodiments of the inventive concept. Referring to FIG. 11, Figure 16 , among high-level BIOS feature items, a setting item for loading into a high-reliability memory can be added.

[0115] When an on-die mirroring operation is desired during normal operation, the storage system according to the example embodiments of the inventive concept can set a mode register (TMRS / MR) in real time.

[0116] Figure 17 is a diagram illustrating a TMRS setting according to the example embodiments of the inventive concept. Referring to FIG. 12, Figure 17 , when an on-die mirroring operation is desired, the on-die mirroring operation can be activated by setting a TMRS in a run-time manner while performing a boot or a system operation. In the example embodiments, an on-die mirroring related TMRS value determined according to a DRAM vendor can be applied, and the memory can perform a half memory and an on-die mirroring operation.

[0117] Figure 18 is a diagram illustrating a MR setting according to the example embodiments of the inventive concept. Referring to FIG. 13, Figure 18On-chip mirroring operation can be activated by setting the MR of the reserved area. As shown in Figure 18 When the value of OP[0] of MR9 (MR[7:0]=09 H ) is set to '1', the memory can perform the on-chip mirroring operation in a run-time manner. For example, a on-chip mirroring set bit can be added to the reserved area of the vendor-specific test resistance. In an example embodiment, such an MR can be mentioned in the JEDEC standard, and can be commonly used by all memory vendors and system vendors.

[0118] As described above, when entering the on-chip mirroring mode according to the BIOS setting or TMRS / MR setting for the memory, the memory mapping of the system can be remapped by half of the size of the memory. For example, the most significant bit of the row address can be ignored (not cared).

[0119] In the case of a data center or a vehicle in which reliability can be important in a system application, the on-chip mirroring operation can be performed at the beginning. In this case, the storage capacity can be modified to half. Further, for applications such as mobile devices, consumer devices, clients, etc., the system can monitor the memory failure pre-forecast, such as the memory usage period or the number of ECC operations, and can enable the on-chip mirroring operation at a certain point of memory deterioration. For example, the system can initially not use half of the DRAM capacity as a default, can monitor the application and memory state (e.g., the duration or frequency of failure), and can activate the on-chip mirroring operation to ensure system stability if desired.

[0120] The inventive concept can also be applied to an electronic device using an application processor (AP).

[0121] Figure 19 is a diagram illustrating an electronic device 40 according to an example embodiment of the inventive concept. Referring to Figure 19 , the electronic device 40 can include a storage device DDR 100b and a processor 200b. In an example embodiment, the electronic device 40 can be a single product, such as a mobile device, a consumer device, an autonomous device, etc.

[0122] The storage device 100b can be implemented to perform the on-chip mirroring operation. The storage device 100b can write data to the first area A and the second area B at the same time in response to a write command. When a read failure is read as a result of a read operation on the first area A in response to a read command, the storage device 100b can transmit a read request to the processor 200b.

[0123] The processor 200b can request a read-reclaim from the storage device 100b in response to a read request of the storage device 100b. The storage device 100b can perform a read-reclaim operation on the read command. The read-reclaim operation can include an operation of outputting data of the second area B of the storage device 100b to the processor 200b.

[0124] Figure 20 is a flowchart illustrating an operation method of a memory according to an example embodiment of the inventive concept. Referring to Figure 20 , the memory 100 (see Figure 10 ) can operate as follows.

[0125] The memory 100 can be set to an on-die mirroring mode (S110). The memory 100 can enter the on-die mirroring mode through a BIOS setting and a TMRS / MR setting.

[0126] The memory 100 can write the same data to the first area A and the second area B in response to an external write command (S120). The first area A can store write data, and the second area B can store mirroring data corresponding to the write data.

[0127] Thereafter, the memory 100 can perform a read operation in response to a read command. As a result of the read operation, error detection of data in the first area A can be performed (S130). When the detected error is not correctable, a defect of a storage cell of the first area A corresponding to the read command can be determined, the memory 100 can change a data output path (S140), and the memory controller 200 (see Figure 10 ) can request a read-reclaim (S150).

[0128] Figure 21 is a flowchart illustrating an operation method of a memory controller according to an example embodiment of the inventive concept. Referring to Figure 21 , the memory controller 200 (see Figure 10 ) can perform a read-reclaim operation as follows.

[0129] The memory controller 200 can transmit on-die mirroring mode setting information to the memory 100 requiring high reliability (S210). During the on-die mirroring operation of the memory 100, the memory controller 200 can receive a read-reclaim request from the memory 100 (S220). The memory controller 200 can transmit a read command for read-reclaim to the memory 100 in response to the read-reclaim request (S230). The memory 100 can output mirroring data in response to the read command.

[0130] Figure 22is a flowchart illustrating an operating method of a storage system according to an example embodiment of the inventive concept. Referring to Figure 22 , the storage system 20 can perform a read retry operation as follows.

[0131] The storage system 20 can be system-on (S310) according to applied power. The storage system 20 can determine whether an operation mode is a system-on mirror mode (S320). When the operation mode is not the system-on mirror mode, the storage system 20 can operate in a normal mode (S325). When the operation mode is the system-on mirror mode, the storage system 20 can set the memory 100 connected to the memory controller 200 to one half of the memory for the on-die mirror operation. In this case, an error detection indicator (EDI) pin can be activated in the memory 100, and a simultaneous write-read operation can be performed (S330).

[0132] In the read operation of the memory 100, it can be determined whether a read failure is detected (S340). When the read failure is not detected, S330 can continue. When the read failure is detected, the memory 100 can send a read retry request to the memory controller 200, and can change an output data area from a normal area to a mirror area (S350). Thereafter, the memory controller 200 can send a read command to the memory 100 in response to the read retry request, and the memory 100 can perform a read retry operation of outputting data of the mirror area in response to the re-sent read command (S360).

[0133] The memory of the inventive concept can be implemented in a stack type.

[0134] Figure 23 is a block diagram illustrating a memory according to an example embodiment of the inventive concept. Referring to Figure 23 , the memory 1000 can include first to third memory dies 1100 to 1300 and a through silicon via (TSV) stacked in a vertical direction on a substrate. In this case, the number of memory dies of the stack will not be limited to Figure 23 illustrated in FIG. 1. For example, the first and second memory dies 1100 and 1200 can be slave dies, and the third memory die 1300 can be a master die or a buffer die.

[0135] The first memory die 1100 can include a first memory cell array 1110 and a first pass-through electrode region 1120 for accessing the first memory cell array 1110. The second memory die 1200 can include a second memory cell array 1210 and a second pass-through electrode region 1220 for accessing the second memory cell array 1210. In this case, the first pass-through electrode region 1120 can denote a region in which pass-through electrodes for communication between the first memory die 1100 and the third memory die 1300 are arranged in the first memory die 1100. Similarly, the second pass-through electrode region 1220 can denote a region in which pass-through electrodes for communication between the second memory die 1200 and the third memory die 1300 are arranged in the second memory die 1200. The pass-through electrodes can provide an electronic path between the first to third memory dies 1100 to 1300. The first to third memory dies 1100 to 1300 can be electrically connected to each other through the pass-through electrodes. For example, the number of pass-through electrodes can be several hundreds to several thousands, and the pass-through electrodes can be arranged in a matrix arrangement. The third memory die 1300 can include a first peripheral circuit 1310 and a second peripheral circuit 1320. In this case, the first peripheral circuit 1310 can include a circuit for accessing the first memory die 1100, and the second peripheral circuit 1320 can include a circuit for accessing the second memory die 1200.

[0136] The storage module of the present inventive concept can be applicable to a computing system additionally including a non-volatile dual in-line memory module (NVDIMM).

[0137] Figure 24 is a diagram illustrating a computing system 2000 according to an example embodiment of the present inventive concept. Referring to Figure 24 , the computing system 2000 can include at least one storage module (DIMM) 2100, at least one non-volatile storage module (NVDIMM) 2200, and at least one processor 2300.

[0138] The computing system 2000 can be used as a computer, a portable computer, an ultra mobile PC (UMPC), a workstation, a data server, a netbook, a personal digital assistant (PDA), a tablet, a wireless phone, a mobile phone, a smartphone, an e-book, a portable multimedia player (PMP), a digital camera, a digital camcorder / recorder, a digital camcorder / recorder / player, a portable game console, a navigation system, a black box, a 3D TV, a device receiving information from and sending information to a wireless environment, any one of various electronic devices constituting a home network, any one of various electronic devices constituting a computer network, any one of various electronic devices constituting a telecommunication network, an RFID, or any one of various electronic devices constituting a computing system.

[0139] The at least one storage module 2100 can be implemented to perform the on-die mirroring operation described with reference to FIGS. 1 to 3. Figure 1 to Figure 23 In an example embodiment, the storage module 2100 can be connected to the processor 2300 along a DDRx interface.

[0140] The at least one non-volatile storage module 2200 can include at least one non-volatile memory. In an example embodiment, the at least one non-volatile memory can include a NAND flash memory, a vertical NAND (VNAND), a NOR flash memory, a resistive random access memory (RRAM), a phase change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), a thyristor random access memory (TRAM), or the like. In an example embodiment, the non-volatile storage module 2200 can be connected to the processor 2300 along a DDR interface.

[0141] The at least one processor 2300 can be implemented to control the storage module 2100 and the non-volatile storage module 2200. In an example embodiment, the processor 2300 can include a general purpose microprocessor, a multi-core processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or a combination thereof.

[0142] The computing system 2000 according to an example embodiment of the inventive concept can significantly improve data reliability by performing an on-die mirroring operation according to a reliability request.

[0143] Meanwhile, the inventive concept can be applied to a mobile device.

[0144] Figure 25 FIG. 3 is a diagram illustrating a mobile device 3000 according to an example embodiment. Referring to FIG. 3, the mobile device 3000 can include a processor 3100, a memory 3200, a communication interface 3300, a display 3400, a user input interface 3500, and a power supply 3600. Figure 25The mobile device 3000 can include an application processor 3100, at least one DRAM 3200, at least one storage device 3300, at least one sensor 3400, a display device 3500, an audio device 3600, a network processor 3700, and at least one input / output device 3800. For example, the mobile device 3000 can be implemented as a laptop computer, a mobile phone, a smart phone, a tablet personal computer, or a wearable computer.

[0145] The application processor 3100 can be implemented to control overall operations of the mobile device 3000. The application processor 3100 can execute applications providing an Internet browser, a game, a video, etc. In an example embodiment, the application processor 3100 can include a single core or multiple cores. For example, the application processor 3100 can include multiple cores such as dual cores, quad cores, hexa cores, etc. In an example embodiment, the application processor 3100 can additionally include a cache memory located internally or externally.

[0146] The application processor 3100 can include a controller 3110, a neural processing unit (NPU) 3120, and an interface 3130. In an example embodiment, the NPU 3120 can be optionally provided.

[0147] In an example embodiment, the application processor 3100 can be implemented as a system on chip (SoC). A kernel of an operating system running in the system on chip (SoC) can include an input / output (I / O) scheduler and a device driver controlling the storage device 3300. The device driver can control an access performance of the storage device 3300 with reference to a number of synchronization queues managed by the input / output scheduler, or can control a CPU mode, a DVFS level, etc. in the SoC (system on chip).

[0148] The DRAM 3200 can be connected to the controller 3110. The DRAM 3200 can store data desired for operations of the application processor 3100. For example, the DRAM 3200 can temporarily store an operating system (OS) and application data, or can be used as an execution space of various software codes.

[0149] The DRAM 3200 can perform the on-die mirroring operation described with reference to Figure 3 to Figure 1 1 or can be implemented as an on-die mirroring memory. The DRAM 3200 can be connected to the NPU 3120. The DRAM 3200 can store data related to artificial intelligence (AI) computations.

[0150] The DRAM 3200 can have a relatively faster latency and bandwidth (BW) compared to the I / O devices or the flash memory. The DRAM 3200 can be initialized upon a mobile power-on, can be used as a temporary storage location for OS and application data by loading the OS and application data, or can be used as an execution space for various software codes. The mobile system performs a multitasking operation of simultaneously loading several applications and switching between the applications, and the execution speed can be used as a performance indicator of the mobile system. The storage device 3300 can be connected to the interface 3130. In an example embodiment, the interface 3130 can operate in any one communication protocol among DDR, DDR2, DDR3, DDR4, low power DDR (LPDDR), universal serial bus (USB), multimedia card (MMC), embedded MMC, peripheral component interconnect (PCI), non-volatile memory express (NVMe), peripheral component interconnect express (PCIe), serial at attachment (SATA), small computer system interface (SCSI), serial attached SCSI (SAS), universal storage bus (USB) attached SCSI (UAS), internet small computer system interface (iSCSI), Fibre Channel, and Ethernet Fibre Channel (FCoE). In an example embodiment, any one storage device 3300 can be included in the mobile device 3000 in an embedded form. In another example embodiment, any one storage device 3300 can be included in the mobile device 3000 in a detachable manner.

[0151] The storage device 3300 can be implemented to store user data. For example, the storage device 3300 can store data collected from the sensor 3400, or can store data network data, augmented reality (AR) / virtual reality (VR) data, or high definition (HD) 4K content. The storage device 3300 can include at least one non-volatile storage device. For example, the storage device 3300 can include a solid state drive (SSD), an embedded multimedia card (eMMC), or the like.

[0152] In an example embodiment, the storage device 3300 can be implemented as a separate memory in the application processor 3100, or can be implemented with the application processor 3100 as a single package.

[0153] In example embodiments, various types of packaging can be used to mount the storage device 3300. For example, the storage device 3300 can be mounted using packaging such as a package on package (PoP), a ball grid array (BGA), a chip scale package (CSP), a plastic leaded chip carrier (PLCC), a plastic dual-in-line package (PDIP), a die in a socket, a die in a wafer form, a chip on board (COB), a ceramic dual-in-line package (CERDIP), a plastic metric quad flat package (MQFP), a thin quad flat package (TQFP), a small outline (SOIC), a shrink small outline package (SSOP), a thin small outline package (TSOP), a system in package (SIP), a multi-chip package (MCP), a wafer level package (WFP), or a wafer level processed stack package (WSP).

[0154] The sensor 3400 can be implemented to sense an external environment of the mobile device 3000. In example embodiments, the sensor 3400 can include an image sensor that senses an image. In this case, the sensor 3400 can transmit generated image information to the application processor 3100. In another example embodiment, the sensor 3400 can include a biological sensor that senses biological feature information. For example, the sensor 3400 can sense a fingerprint, an iris pattern, a blood vessel pattern, a heart rate, a blood sugar level, etc., and can generate sensing data corresponding to the sensed information. On the other hand, the sensor 3400 is not limited to the image sensor and the biological sensor. For example, the sensor 3400 can include any sensor such as an illumination sensor, an acoustic sensor, or an acceleration sensor.

[0155] The display device 3500 can be implemented to output data. For example, the display device 3500 can output image data sensed using the sensor 3400 or output data calculated using the application processor 3100.

[0156] The audio device 3600 can be implemented to output voice data to the outside or sense external voice.

[0157] The network processor 3700 can be implemented to communicate with an external device through a wired or wireless communication method.

[0158] The input / output device 3800 can be implemented to input data to the mobile device 3000 or output data from the mobile device 3000. The input / output device 3800 can include a device that provides digital input and output functions such as a USB, a storage, a digital camera, an SD card, a touch screen, a DVD, a modem, or a network adapter.

[0159] Example embodiments of the inventive concept can be applied to various computing systems such as CPU / GPU / NPU platforms.

[0160] Figure 26 is a diagram illustrating a computing system 4000 according to an example embodiment of the inventive concepts. Referring to Figure 26 , the computing system 4000 can include a central processing unit (CPU) 4110, a graphics processing unit (GPU) 4120, or a neural processing unit (NPU) 4130 (or a dedicated processing unit) connected to a system bus 4001, a storage device 4210 or a storage device 4220 connected to the system bus 4001, and an input / output device 4310, a modem 4320, a network device 4330, or a storage device 4340 connected to an extension bus 4002. In this case, the extension bus 4002 can be connected to the system bus 4001 through an extension bus interface 4003.

[0161] In an example embodiment, the CPU 4110, the GPU 4120, and the NPU 4130 can include on-chip caches 4111, 4121, and 4131, respectively.

[0162] In an example embodiment, the CPU 4110 can include an off-chip cache 4112. Although not illustrated in Figure 26 , each of the GPU 4120 and the NPU 4130 can also include an off-chip cache. In an example embodiment, the off-chip cache 4112 can be internally connected to the CPU 4110, the GPU 4120, and the NPU 4130 through a different bus.

[0163] In an example embodiment, the on-chip / off-chip cache can include a volatile memory (e.g., a dynamic random access memory (DRAM), or a static random access memory (SRAM)), or a non-volatile memory (e.g., a NAND flash memory, a phase random access memory (PRAM), or a resistance random access (RRAM)).

[0164] In example embodiments, main memories 4114, 4124, and 4134 can be connected to CPUs 4110, GPUs 4120, and NPUs 4130 through corresponding memory controllers 4113, 4123, and 4133. In example embodiments, memories 4116, 4126, and 4136 can be connected to CPUs 4110, GPUs 4120, and NPUs 4130 through bridges 4115, 4125, and 4135. Bridges 4115, 4125, and 4135 can include memory controllers (not shown) that control corresponding memories 4116, 4126, and 4136. In example embodiments, bridges 4115, 4125, and 4135 can be implemented as network devices, wireless network devices, switches, buses, clouds, or optical channels, respectively.

[0165] In example embodiments, memories 4124 and 4126 can include GPU memories. GPU memories can hold instructions and data that can interact with GPUs. Commands and data can be copied from main memories or storage. GPU memories can store image data and can have greater bandwidth compared to memories. GPU memories can be clocked separately from CPUs. GPUs can read and process image data in GPU memories and can then write in GPU memories. GPU memories can be configured to accelerate graphics processing.

[0166] In example embodiments, memories 4134 and 4136 can include NPU memories. NPU memories can hold instructions and data that can interact with NPUs. Commands and data can be copied from main memories or storage. NPU memories can maintain weight data for neural networks. NPU memories can have greater bandwidth compared to memories. NPU memories can be clocked separately from CPUs. NPUs can read and update weight data in NPU memories during training and can then write in NPU memories. NPU memories can be configured to accelerate machine learning, such as neural network training and inference.

[0167] In some example embodiments, each of main memories 4114, 4116, 4124, 4126, 4134, 4136, and 4210 can be implemented to perform the references Figure 3 to Figure 23 The described on-die mirror operation of memories.

[0168] In example embodiments, main memories can include volatile memories (e.g., DRAM, or SRAM) or non-volatile memories (e.g., NAND flash memory, PRAM, or RRAM). Main memories have lower latency and lower capacity compared to latencies and capacities of secondary storage 4210 and 4220.

[0169] The CPU 4110, the GPU 4120, or the NPU 4130 can access the secondary storages 4210 and 4220 through the system bus 4001. The storage device 4210 can be controlled by the memory controller 4211. In this case, the memory controller 4211 can be connected to the system bus 4001. The storage device 4220 can be controlled by the storage controller 4221. The storage controller 4221 can be connected to the system bus 4001.

[0170] The storage device 4220 can be implemented to store data. The storage controller 4221 can be implemented to read data from the storage device 4220 and transmit the read data to the host. The storage controller 4221 can be implemented to store the transmitted data in the storage device 4220 in response to a request from the host. Each of the storage device 4220 and the storage controller 4221 can include a buffer that stores metadata, reads a cache for frequently accessed data, or stores a cache for improving write efficiency. For example, a write cache can receive and process a certain number of write requests.

[0171] The storage device 4220 can include a volatile memory such as a hard disk drive (HDD), and a non-volatile memory such as NVRAM, SSD, SCM, or a new memory.

[0172] The storage device 4340 can be implemented to store data. The storage controller 4341 can be implemented to read data from the storage device 4340 and transmit the read data through the expansion bus 4002.

[0173] Example embodiments of the inventive concept can be applied to a data server system.

[0174] Figure 27 FIG. 5 is a diagram illustrating a data server system 5000 according to an example embodiment of the inventive concept. Referring to FIG. 5, the data server system 5000 can include a first server 5100 (application server), a second server 5200 (storage server), a storage device 5310, and at least one storage device 5320. Figure 27

[0175] ​Each of the first server 5100 and the second server 5200 can include at least one processor and a memory. In an example embodiment, each of the first server 5100 and the second server 5200 can be implemented as a memory-processor pair. In another example embodiment, each of the first server 5100 and the second server 5200 can be implemented with different numbers of processors and memories as appropriate for use. Each of the first server 5100 and the second server 5200 can include one or more interfaces for communication with another server or a storage device over a network.

[0176] In an example embodiment, the first server 5100 and the second server 5200 can perform communication over the first network 5010. In an example embodiment, each of the first server 5100 and the second server 5200 can access the storage device 5310 over the first network 5010 and / or the second network 5020. In an example embodiment, each of the first server 5100 and the second server 5200 can access the storage device 5320 directly or indirectly over the first network 5010 and the second network 5020.

[0177] In an example embodiment, the interface I / F of the storage device 5320 can include SATA, SAS, PCIe, DIMM, HBM, HMC, or NVDIMM. In an example embodiment, the second network 5020 can be a connection type of a direct attached storage (DAS), a network attached storage (NAS), and a storage area network (SAN) scheme.

[0178] In an example embodiment, the storage device 5310 and the storage device 5320 can respectively transmit device information to the second server 5200 by a command or by itself. In an example embodiment, the storage device 5310 can perform reference Figure 3 to Figure 23 The described on-die mirroring operation or can include an on-die mirroring memory.

[0179] The data server system 5000 can perform a big data AI computation. In this case, the big data can include audio, photo, video, or weight / training data.

[0180] The on-die mirroring device according to an example embodiment of the inventive concept can include a memory failure determination device and an output region change device to a mirroring region when a failure occurs.

[0181] A storage system according to an embodiment of the inventive concept can be implemented by using a failure indicator device, a system delivery method, and a stream of receiving a failure occurrence signal and performing a read retry by reading a mirror area instead of a current failure area when a failure occurs during system operation. Accordingly, normal data can be read to expect an increase in reliability of the system. Accordingly, the storage system of the inventive concept can improve prevention of a decrease in performance, inefficient management of memory usage, etc. in applications occurring in RAS (Reliability, Availability, and Serviceability) channel mirroring operations, etc.

[0182] A die-mirror DRAM according to an embodiment of the inventive concept can be applied to automotive and mobile / consumer applications using a package (PKG), a multi-chip PKG (MCP), etc., data centers (DCs) using various DRAM modules, personal computers (PCs), etc. In addition, the die-mirror DRAM according to an example embodiment of the inventive concept can be applied to all PKG / module types including graphics applications with a system-in-PKG (SiP) using a high bandwidth memory (HBM) assembly, and all application systems using such a memory.

[0183] The die-mirror DRAM according to an example embodiment of the inventive concept can be divided into two, a low area and a high area of a last row address in the same memory bank. The system can operate by "not caring" at the highest row address during a die-mirror operation.

[0184] The die-mirror DRAM can simultaneously write a low area and a high area of the highest row address in the memory bank. When a defect is determined, a failure in writing data can be referred to as a Fail when data of a mirror area and data as an EXOR exist, and in the case of an on-die ECC memory, by the memory itself as a "correctable error (CE)" and an "uncorrectable error (UE)". When a defect in the memory is confirmed, the die-mirror DRAM can change a current data output path to a mirror area, and, at the same time, can generate a read request to a system host.

[0185] In an example embodiment, H / W as a read request means can add an additional pin (an error indication signal (EIS)) or can use a pin performing "not caring" when a mirror mode is applied when a failure occurs. In the case where a failure occurs, whether it fails or not can be transmitted by a phase of the pin. For example, when the pin is at a high level, it will be referred to as "Fail", and, when the pin is at a low level, it will be referred to as "Pass". Logic to change a data area can be included.

[0186] In an example embodiment, H / W as a read request means can make a dummy read CLK in DQS to send whether the current read data is "pass / fail" when a failure occurs. In an example embodiment, S / W as a read request means can use a mode register (MR) when a failure occurs.

[0187] The on-die mirroring operation according to example embodiments of the present inventive concept can be applied to a package on package (PoP), a multi-chip package (MCP), and a system in package (SiP), and can be included in all single unit mounting and modules, etc. A system according to example embodiments of the present inventive concept can apply a test mode register set (TMRS) or can apply an on-die mirroring operation by using a BIOS setting mode register (MR) issue.

[0188] The memory according to example embodiments of the present inventive concept, the storage system having the same, and the operating method thereof can improve reliability of data by performing an on-die mirroring operation.

[0189] Any decoder, controller, or processor recited in this disclosure can include processing circuitry, such as hardware including logic circuitry; a hardware / software combination, such as a processor executing software; or a combination thereof. For example, processing circuitry can more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), or the like.

[0190] While example embodiments have been illustrated and described above, it will be obvious to those skilled in the art that modifications and changes can be made without departing from the scope of the present inventive concept as defined in the appended claims.

Claims

1. A memory system comprising: a first central processing unit; a first memory module including a plurality of first memories and connected to the first central processing unit through a first channel; a second memory module including a plurality of second memories and connected to the first central processing unit through a second channel; and a third memory module including a plurality of third memories and connected to the first central processing unit through a third channel, wherein each of the first memories, the second memories, and the third memories includes a data area and a mirror data area, and is configured to write the same data into the data area thereof and the mirror data area thereof in response to an address in a mirror mode. Each of the first memories, the second memories, and the third memories includes processing circuitry configured to perform a read operation of data of the data area in response to a read command from the first central processing unit, determine whether the read operation of data of the data area fails, and generate a read failure signal as a result of the determination.

2. The storage system of claim 1, wherein, The processing circuitry is configured to perform a comparison operation of comparing data of the data area with data of the mirror data area in response to the read command, and generate the read failure signal in accordance with a result of the comparison operation.

3. The storage system of claim 2, wherein, The processing circuitry is configured to perform an error correction operation of data of the data area in response to the read command, and generate the read failure signal in accordance with a result of the error correction operation.

4. The storage system of claim 2, wherein, The first central processing unit is configured to send a read retry command corresponding to the read failure signal to a corresponding one among the first memory module, the second memory module, or the third memory module.

5. The storage system of claim 2, wherein, Each of the memories of the corresponding one among the first memory module, the second memory module, or the third memory module changes an output path of the read operation from the data area to the mirror data area in response to the read retry command.

6. The storage system of claim 5, wherein, Each of the first memories, the second memories, and the third memories is configured to ignore a highest bit of a row address at the address in the mirror mode.

7. The storage system of claim 1, wherein, 8. The memory system of claim 1, further comprising: a second central processing unit in communication with the first central processing unit; a fourth memory module connected to the second central processing unit through a fourth channel; a fifth memory module connected to the second central processing unit through a fifth channel; and a sixth memory module connected to the second central processing unit through a sixth channel.

9. A memory system comprising: at least one memory; and a memory controller configured to control the at least one memory, wherein the at least one memory includes, a first storage area configured to store write data during a write operation in a mirror mode; a second storage area configured to store write data during a write operation in the mirror mode; and processing circuitry configured to generate a read failure signal when a read operation of the first storage area fails in the mirror mode. The processing circuitry is configured to generate the read failure signal during the read operation by comparing first data output from the first storage area with second data output from the second storage area. ​ ​ 10. The storage system of claim 9, wherein, ​ 11. The storage system of claim 9, wherein, The processing circuitry is configured to perform an error correction operation that corrects errors of data output from the first storage area during the read operation, and to generate the read failure signal in accordance with a result of the error correction operation.

12. The storage system of claim 9, wherein, The at least one memory further comprises an error indication signal pin, and is configured to transmit the read failure signal to the memory controller using the error indication signal pin.

13. The storage system of claim 9, wherein, The at least one memory is configured to transmit the read failure signal to the memory controller using the at least one DQS pin.

14. The memory system of claim 9, wherein, The at least one memory further comprises a mode register configured to store the read failure signal, and The memory controller is configured to identify a failure of the read operation by reading the mode register.

15. The storage system of claim 9, wherein, The memory controller is configured to transmit a read retry command to the at least one memory in response to the read failure signal.

16. The storage system of claim 15, wherein, The at least one memory is configured to output data read from the second storage area to the memory controller in response to the read retry command.

17. The storage system of claim 9, wherein, The at least one memory is configured to generate a read retry request in response to the read failure signal, and to transmit the read retry request to the memory controller through one of a separate pin or a DQS dummy signal.

18. The memory system of claim 9, wherein, The at least one memory is configured to generate a read retry request in response to the read failure signal, and to store information related to the read retry request in a mode register, and The memory controller is configured to receive the read retry request by periodically or aperiodically reading the mode register.

19. A memory, comprising: a memory cell array having a first storage area and a second storage area, the memory cell array having a plurality of memory cells connected to word lines and bit lines; a row decoder configured to select any one of the word lines in response to a row address; a sense amplifier circuit configured to sense data from the memory cells connected to the selected bit line during a read operation; a column decoder configured to select the selected bit line among the bit lines in response to a column address; an address buffer configured to store an address having the row address and the column address; and processing circuitry configured to, correct errors of the sensed data, and generate a read failure signal when error correction has failed, generate a mirror mode activation signal corresponding to a mirror mode, write the same write data to the first storage area and the second storage area during a write operation in the mirror mode, and change a data output path of a read operation from a first data output path of the first storage area to a second data output path of the second storage area in response to a read retry command in the mirror mode. ​

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