DRAM Memory

Abstract

A DRAM memory comprises: a substrate; a plurality of memory banks arranged in rows and columns on the substrate, each memory bank being divided into three memory blocks in the column direction, and each memory block having a plurality of memory cells arranged in rows and columns. By dividing each memory bank into three memory blocks in the column direction, on the one hand, when the capacity of each memory bank is constant, each memory bank is divided into three memory blocks in the column direction, and the length of each memory block in the row direction will be shortened, so that the distance from the control line and the data transmission line to the corresponding memory cell in the storage array in each memory block will be shortened, so that a large drive is not required, and the parasitic resistance and parasitic capacitance generated by the data transmission line are reduced, so that the data transmission rate and data transmission accuracy are improved, and the power consumption is reduced.

Description

Technical Field

[0001] The present invention relates to the field of memory, and in particular to a DRAM memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. Its storage array area consists of many repeated storage cells. Each storage cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.

[0003] The existing DRAM memory organization structure includes several banks, each of which is divided into two equal-sized memory blocks. However, the existing organization structure DRAM memory has the problem of high power consumption during operation, and the data transmission rate and data transmission accuracy still need to be improved. Summary of the invention

[0004] The technical problem to be solved by the present invention is how to reduce the power consumption of DRAM memory and how to improve the data transmission rate and data transmission accuracy.

[0005] To this end, the present invention provides a DRAM memory, comprising:

[0006] substrate;

[0007] A plurality of storage bins are arranged in rows and columns on the substrate, each storage bin is divided into three storage blocks in the column direction, and each storage block has a plurality of storage units arranged in rows and columns.

[0008] Optionally, the three storage blocks include a first storage block, a second storage block and a third storage block arranged sequentially in a column direction.

[0009] Optionally, the first storage block, the second storage block and the third storage block in each storage block are connected to a first column decoding circuit, a second column decoding circuit and a third column decoding circuit respectively.

[0010] Optionally, the first storage block, the second storage block and the third storage block in each storage block are also connected to a first row decoding circuit and a second row decoding circuit.

[0011] Optionally, the first row decoding circuit is connected to all the storage cells in the first storage block and some storage cells in the second storage block, and is used to perform row addressing on all the storage cells in the first storage block and some storage cells in the second storage block, and the second row decoding circuit is connected to all the storage cells in the third storage block and some storage cells in the second storage block, and is used to perform row addressing on all the storage cells in the third storage block and some storage cells in the second storage block.

[0012] Optionally, the storage capacities of the first storage block, the second storage block and the third storage block are equal.

[0013] Optionally, there is a circuit area between two adjacent columns of storage bins, and the circuit area has a control circuit and a data transmission circuit. The control circuit is used to send control instructions and / or addresses to the corresponding storage bin, and the data transmission circuit is used to transmit data to a corresponding storage unit in the corresponding storage bin or read data from the storage unit.

[0014] Optionally, the substrate further has a pad area, and the pad area has a plurality of first pads and second pads, the first pads are connected to the control circuit, and the second pads are connected to the data transmission circuit.

[0015] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0016] The DRAM memory of the present invention comprises: a substrate; a plurality of storage banks arranged in rows and columns on the substrate, each storage bank is divided into three storage blocks in the column direction, and each storage block has a plurality of storage units arranged in rows and columns. By dividing each storage bank into three storage blocks in the column direction, on the one hand, when the capacity of each storage bank is constant, each storage bank is divided into three storage blocks in the column direction, and the length of each storage block in the row direction will be shortened (relative to the solution of dividing each storage bank into two storage blocks in the row direction), so that the length of the control line itself will be shortened and the distance from the control line to the corresponding storage unit in the storage array in each storage block will be shortened, so that a large drive is not required, and power consumption is reduced, and the length of the data transmission line itself will be shortened and the distance from the data transmission line to the corresponding storage unit in the storage array in each storage block will also be shortened, so that the parasitic resistance and parasitic capacitance generated by the data transmission line are reduced, so that the data transmission rate and data transmission accuracy are improved, and power consumption is reduced; on the other hand, the length of the storage block in the storage bank is shortened, which can optimize the layout of the storage bank in the DRAM memory, so that the length and width of the DRAM memory are more optimized, which is conducive to packaging.

[0017] Furthermore, the first storage block, the second storage block and the third storage block in each storage block are connected to the first column decoding circuit, the second column decoding circuit and the third column decoding circuit respectively, and the first storage block, the second storage block and the third storage block in each storage block are also connected to the first row decoding circuit and the second row decoding circuit. The first column decoding circuit, the second column decoding circuit and the third column decoding circuit are used to perform column addressing on the corresponding storage units in the first storage block, the second storage block and the third storage block respectively, and the first row decoding circuit and the second row decoding circuit perform row addressing on the corresponding storage units in the first storage block, the second storage block and the third storage block, so that the corresponding storage units in the three storage blocks in a storage bank can be accessed (including reading, writing or refreshing) at the same time, thereby improving the operation efficiency of the DRAM memory.

[0018] In one embodiment, the first row decoding circuit is connected to all storage cells in the first storage block and some storage cells in the second storage block, and is used to perform row addressing on all storage cells in the first storage block and some storage cells in the second storage block, and the second row decoding circuit is connected to all storage cells in the third storage block and some storage cells in the second storage block, and is used to perform row addressing on all storage cells in the third storage block and some storage cells in the second storage block. Therefore, the row decoding (decoding) of the storage cells in the three storage blocks in one storage bank can be shared and controlled, saving the chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of the structure of a DRAM memory in one embodiment of the present invention;

[0020] Figure 2 FIG. 4 is a schematic diagram of the structure of a DRAM memory in another embodiment of the present invention. DETAILED DESCRIPTION

[0021] As mentioned in the background art, the existing organizational structure DRAM memory has the problems of high power consumption during operation and the data transmission rate and data transmission accuracy still need to be improved.

[0022] refer to Figure 1 , Figure 1 The DRAM memory is a schematic diagram of a structure of a DRAM memory in an embodiment of the present invention, wherein the DRAM memory comprises: a plurality of rows and columns (row direction is Figure 1 In the X-axis direction, the column direction is Figure 1 The storage banks arranged along the Y axis are: Figure 1In the example, 8 memory banks BANK are used as an example for explanation, each memory bank BANK is divided into two memory blocks of the same size, including a first memory block 21 and a second memory block 22, the first memory block 21 and the second memory block 22 include a memory array or a plurality of memory cells arranged in rows and columns, the first memory block 21 and the second memory block 22 are respectively connected to the corresponding row decoding circuit YDEC and the column decoding circuit XDEC, and a control line and a data transmission line are arranged between the memory banks between adjacent rows, the control line is used to transmit a control signal to the corresponding memory bank BANK, and the data transmission line is used to transmit data to the corresponding memory cell. The aforementioned organizational structure DRAM memory has a long length along the row direction (X-axis direction), and the corresponding control line and data transmission line are also long, and the distance from the control line and the data transmission line to each memory cell is also long, thereby increasing power consumption, and increasing the parasitic resistance and parasitic capacitance generated by the control line and the data transmission line, so that the data transmission rate and data transmission accuracy are reduced. In addition, the length in the row direction (X-axis direction) is too long, so that the length-to-width ratio is not optimized enough, which will directly affect the packaging and may not meet the packaging requirements.

[0023] To this end, the present invention provides a DRAM memory, comprising: a substrate; a plurality of storage banks arranged in rows and columns on the substrate, each storage bank being divided into three storage blocks in the column direction, and each storage block having a plurality of storage units arranged in rows and columns. By dividing each storage bank into three storage blocks in the column direction, on the one hand, when the capacity of each storage bank is constant, each storage bank is divided into three storage blocks in the column direction, and the length of each storage block in the row direction will be shortened (relative to the solution of dividing each storage bank into two storage blocks in the row direction), so that the length of the control line itself will be shortened and the distance from the control line to the corresponding storage unit in the storage array in each storage block will be shortened, so that a large drive is not required, and power consumption is reduced, and the length of the data transmission line itself will be shortened and the distance from the data transmission line to the corresponding storage unit in the storage array in each storage block will also be shortened, so that the parasitic resistance and parasitic capacitance generated by the data transmission line are reduced, so that the data transmission rate and data transmission accuracy are improved, and power consumption is reduced; on the other hand, the length of the storage block in the storage bank is shortened, which can optimize the layout of the storage bank in the DRAM memory, so that the length and width ratio of the DRAM memory is more optimized, which is conducive to packaging.

[0024] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0025] Figure 2 FIG. 4 is a schematic diagram of the structure of a DRAM memory in another embodiment of the present invention.

[0026] refer to Figure 2 , the DRAM memory comprises:

[0027] a substrate (not shown);

[0028] A plurality of storage banks BANKs are arranged in rows and columns on the substrate, each storage bank BANK is divided into three storage blocks (31 / 32 / 33) in the column direction, and each storage block (31 / 32 / 33) has a plurality of storage units arranged in rows and columns.

[0029] DRAM memory is generally divided into several storage banks BANK. The number of storage banks BANK in a DRAM memory can be 4, 8, 16 or other numbers. The storage capacity of each storage bank BANK is the same. For example, if the DRAM memory capacity is 8Gb, when there are 8 storage banks BANK, the capacity of each storage bank BANK is 1Gb. Each storage bank BANK in the DRAM memory has its own bank address. When accessing the DRAM memory (such as reading, writing or refreshing), first find the corresponding storage bank BANK, and then find the corresponding storage unit in the storage bank BANK. In this embodiment, reference Figure 2 , taking a DRAM memory having 16 BANKs as an example for explanation.

[0030] Each storage memory BANK is divided into three storage blocks in the column direction, and each storage block has a storage array, and the storage array includes a plurality of storage units arranged in rows and columns. In this embodiment, the three storage blocks include a first storage block 31, a second storage block 32 and a third storage block 33 arranged in sequence in the column direction, and the first storage block 31, the second storage block 32 and the third storage block 33 are respectively connected to the corresponding row decoding circuit XDEC and the column decoding circuit YDEC (it should be noted that, in this embodiment, the column direction refers to the Y-axis direction, and the row direction refers to the X-axis direction). By dividing each storage bank BANK into three storage blocks (a first storage block 31, a second storage block 32 and a third storage block 33) in the column direction, on the one hand, when the capacity of each storage bank BANK is constant, each storage bank BANK is divided into three storage blocks in the column direction, and the length of each storage block in the row direction will be shortened (relative to the solution of dividing each storage bank into two storage blocks in the row direction), so that the length of the control line itself will be shortened and the distance from the control line to the corresponding storage unit in the storage array in each storage block will be shortened, so that a large drive is not required, reducing power consumption, and the length of the data transmission line itself will be shortened and the distance from the data transmission line to the corresponding storage unit in the storage array in each storage block will also be shortened, so that the parasitic resistance and parasitic capacitance generated by the data transmission line are reduced, so that the data transmission rate and data transmission accuracy are improved, and the power consumption is reduced; on the other hand, the length of the storage block in the storage bank BANK is shortened, which can optimize the layout of the storage bank BANK in the DRAM memory, so that the length and width of the DRAM memory are more optimized, which is conducive to packaging.

[0031] In one embodiment, the storage capacities of the first storage block 31 , the second storage block 32 and the third storage block 33 are equal.

[0032] In one embodiment, the first storage block 31, the second storage block 32 and the third storage block 33 in each storage block BANK are respectively connected to the first column decoding circuit (YDEC) 51, the second column decoding circuit (YDEC) 52 and the third column decoding circuit (YDEC) 53, and the first storage block 31, the second storage block 32 and the third storage block 33 in each storage block BANK are also connected to the first row decoding circuit (XDEC) 41 and the second row decoding circuit (XDEC) 42. The first column decoding circuit (YDEC) 51, the second column decoding circuit (YDEC) 52 and the third column decoding circuit (YDEC) 53 are respectively used to perform column addressing on the corresponding storage cells in the first storage block 31, the second storage block 32 and the third storage block 33, and the first row decoding circuit (XDEC) 41 and the second row decoding circuit (XDEC) 42 perform row addressing on the corresponding storage cells in the first storage block 31, the second storage block 32 and the third storage block 33, so that the corresponding storage cells in the three storage blocks in a storage library BANK can be accessed (including reading, writing or refreshing) at the same time, thereby improving the operating efficiency of the DRAM memory.

[0033] In one embodiment, the first row decoding circuit 41 is connected to all the storage cells in the first storage block 31 and part of the storage cells in the second storage block 32, and is used to perform row addressing on all the storage cells in the first storage block 31 and part of the storage cells in the second storage block 32. The second row decoding circuit 42 is connected to all the storage cells in the third storage block 33 and part of the storage cells in the second storage block 32, and is used to perform row addressing on all the storage cells in the third storage block 33 and part of the storage cells in the second storage block 32. Therefore, the row decoding (decoding) of the storage cells in the three storage blocks in one storage bank BANK can be shared and controlled, saving the chip area.

[0034] There is a circuit area 61 between the two adjacent columns of the storage banks BANK, and the circuit area 61 has a control circuit and a data transmission circuit. The control circuit is used to send control instructions and / or addresses to the corresponding storage banks, and the control instructions include write instructions, read instructions, refresh instructions and other instructions. The address includes the library address of each storage bank BANK and the row address and column address of the corresponding storage unit in the corresponding storage block in the storage bank BANK. The data transmission circuit is used to transmit data to the corresponding storage unit in the corresponding storage bank BANK or read data from the storage unit.

[0035] The substrate also has a pad area 71, which is generally located around the memory bank BANK array. The pad area 71 has a plurality of first pad areas and a plurality of second pad areas. The plurality of first pad areas are connected to the control circuit, and the plurality of second pad areas are connected to the data transmission circuit.

[0036] In one embodiment, the process of addressing the DRAM storage is generally to first specify the bank address of the memory bank BANK, then specify the row address, and then specify the column address.

[0037] It should be noted that other limitations or descriptions about the storage structure in this embodiment are not repeated in this embodiment. Please refer to the corresponding limitations or descriptions in the aforementioned storage structure formation process embodiment for details.

[0038] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A DRAM memory, characterized in that: include: substrate; A plurality of memory banks arranged in rows and columns on the substrate, each memory bank being divided into three memory blocks in the column direction, each memory block having a plurality of memory cells arranged in rows and columns; a first row decoding circuit and a second row decoding circuit being electrically connected to the three memory blocks and used for performing row addressing for all memory cells in the three memory blocks; The three storage blocks include a first storage block, a second storage block and a third storage block arranged sequentially in a column direction, the first row decoding circuit is connected to all storage cells in the first storage block and some storage cells in the second storage block, and is used to perform row addressing on all storage cells in the first storage block and some storage cells in the second storage block, the second row decoding circuit is connected to all storage cells in the third storage block and some storage cells in the second storage block, and is used to perform row addressing on all storage cells in the third storage block and some storage cells in the second storage block.

2. The DRAM memory according to claim 1, wherein: The first storage block is connected to a first column decoding circuit, the second storage block is connected to a second column decoding circuit, and the third storage block is connected to a third column decoding circuit.

3. The DRAM memory according to claim 1, characterized in that: The first row decoding circuit is located between the first storage block and the second storage block, and the second row decoding circuit is located between the second storage block and the third storage block.

4. The DRAM memory according to claim 1, wherein: There is a circuit area between two adjacent columns of storage bins, and the circuit area has control circuits and data transmission circuits. The control circuit is used to send control instructions and / or addresses to the corresponding storage bin, and the data transmission circuit is used to transmit data to the corresponding storage unit in the corresponding storage bin or read data from the storage unit.

5. The DRAM memory according to claim 4, characterized in that: The circuit area has a long side and a short side, the long side is parallel to the column direction, and the short side is parallel to the row direction. Different storage blocks among the three storage blocks are arranged parallel to each other and are perpendicular to the long side of the circuit area. The first row decoding circuit and the second row decoding circuit have the same extension direction and are perpendicular to the long side of the circuit area.

6. The DRAM memory according to claim 4, wherein: The device also has a pad area, in which a plurality of first pads and second pads are provided. The first pads are connected to the control circuit, and the second pads are connected to the data transmission circuit.

7. The DRAM memory according to claim 6, characterized in that: The pad area is located on a same side of the circuit area and the plurality of storage banks.

8. The DRAM memory according to claim 1, characterized in that: The storage capacities of the first storage block, the second storage block and the third storage block are equal.

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