Dopant injection method, silicon carbide power device and preparation method thereof

Abstract

The present invention relates to a dopant injection method, a silicon carbide power device and a method for preparing the same. The present invention first deposits amorphous SiC at room temperature and injects dopant, and then utilizes high-temperature thermal diffusion to infiltrate the SiC substrate. This process does not need to rely on high-temperature ion injection technology and expensive equipment, has a low degree of damage, and improves ohmic contact characteristics. The MPS diode, MOSFET and other power devices also use the above-mentioned ion injection method during the preparation process, which does not need to rely on high-temperature ion injection technology and expensive equipment, does not damage the SiC substrate, and improves the reverse bias leakage current of the device and the Schottky barrier reduction effect. At the same time, the ohmic contact characteristics of the anode metal and the grid layer are improved, and the device can be effectively protected in the case of large current surges.

Description

Technical Field

[0001] The present invention relates to the field of preparation of silicon carbide power devices, and in particular to a dopant injection method, a silicon carbide power device and a preparation method thereof. Background Art

[0002] Silicon carbide semiconductor material is a high-voltage and high-current power device because of its special properties and is therefore widely used. Figure 1 The figure shows a common silicon carbide power device, in which a P-type junction is formed on an N-type epitaxial layer. Figure 2 As shown, currently, ion implantation is generally used to form a P-type junction on the N-type epitaxial layer, and the temperature during ion implantation needs to be more than 500°C. In other words, the ion implantation of silicon carbide power devices is currently carried out at high temperatures. Because the N-type epitaxial layer is SiC crystal, ion implantation will generate relatively large pressure, which is easy to destroy the structure of SiC crystal at high temperature and high pressure, thereby affecting the semiconductor performance of SiC crystal, and further affecting the performance of silicon carbide power devices. Summary of the invention

[0003] In view of the problems existing in the prior art, the object of the present invention is to provide a method for doping a silicon carbide power device, a silicon carbide power device and a method for preparing the same, which can improve the performance of the silicon carbide device.

[0004] To achieve the above object, the technical solution adopted by the present invention is:

[0005] A method for implanting dopants into a silicon carbide power device comprises the following steps:

[0006] Step 1, growing an amorphous SiC layer on a SiC substrate and injecting dopants at room temperature; or, growing an amorphous SiC layer containing dopants on a SiC substrate;

[0007] Step 2: After defining the area where the dopant needs to be injected, photolithography is performed to remove the amorphous SiC layer in the area where the dopant does not need to be injected;

[0008] Step 3, depositing a covering layer on the SiC substrate and the amorphous SiC layer, and then performing heat treatment to form a polycrystalline SiC layer and a P-type junction or an N-type junction, wherein the polycrystalline SiC layer is transformed from the amorphous SiC layer at high temperature, and the P-type junction or the N-type junction is formed by the dopant in the amorphous SiC penetrating into the SiC substrate at high temperature; after the heat treatment is completed, removing the covering layer.

[0009] The SiC substrate is an N-type SiC substrate or a P-type SiC substrate; the dopant is a P-type dopant or an N-type dopant.

[0010] The material of the cover layer is photoresist, aluminum nitride or boron nitride.

[0011] A method for preparing a silicon carbide power device, wherein the silicon carbide power device prepared by the method is an MPS diode, and the preparation method is as follows:

[0012] Step 1, growing a SiC epitaxial layer on a SiC substrate;

[0013] Step 2: forming a polycrystalline SiC layer and a P-type junction or an N-type junction on the SiC epitaxial layer by the dopant implantation method as described above, wherein the P-type junction or the N-type junction is located in the active area of ​​the MPS diode to form a P-type or N-type grid, and is located in the peripheral area of ​​the MPS diode to form a P-type or N-type protection trench;

[0014] Step 3, growing an insulating film on the SiC epitaxial layer and the polycrystalline SiC layer; patterning the top insulating film, removing the insulating film in the active area; and then covering the active area and a portion of the adjacent peripheral area with an anode metal; the anode metal has a Schottky contact characteristic with the SiC epitaxial layer and an ohmic contact characteristic with the polycrystalline SiC layer;

[0015] Step 4: Cover the lower end of the SiC substrate with cathode metal to form ohmic contact characteristics.

[0016] A silicon carbide power device, which is an MPS diode, wherein the MPS diode is provided with an active region and a peripheral region;

[0017] The MPS diode comprises a SiC substrate and an N-type SiC epitaxial layer arranged on the SiC substrate, a plurality of polycrystalline SiC layers are formed on the upper end of the SiC epitaxial layer, a plurality of P-type junctions corresponding to the polycrystalline SiC layers are formed on the upper part of the SiC epitaxial layer, the P-type junctions located in the active area are P-type grids, the P-type junctions located in the peripheral area are P-type guard junctions, and the P-type grids and the P-type guard trenches are formed by diffusion of P-type dopants in the polycrystalline SiC layer into the epitaxial layer;

[0018] An insulating film is provided on the SiC epitaxial layer and the polycrystalline SiC layer, and the insulating film is located in the peripheral area; an anode metal is provided on the active area and a part of the adjacent peripheral area, and the anode metal has Schottky contact characteristics with the SiC epitaxial layer and ohmic contact characteristics with the polycrystalline SiC layer.

[0019] The SiC substrate is an N-type SiC substrate or a P-type SiC substrate, and the SiC epitaxial layer is an N-type SiC epitaxial layer or a P-type SiC epitaxial layer.

[0020] A method for preparing a silicon carbide power device, wherein the silicon carbide power device prepared by the method is a MOSFET device, and the preparation method is as follows:

[0021] Step 1, growing a SiC epitaxial layer on a SiC substrate;

[0022] Step 2: forming a polycrystalline SiC layer and a P-type body on the SiC epitaxial layer by adopting the above-mentioned dopant implantation method;

[0023] Step 3, removing the polycrystalline SiC layer, and continuing to use the above-mentioned dopant injection method to form a polycrystalline SiC layer, a P-type junction and an N-type junction on the P-type body, wherein the P-type junction is a P+ type band region, and the N-type junction is an N+ type source region;

[0024] Step 4, forming a gate insulating film on the P-type body and the SiC epitaxial layer, and then patterning the gate insulating film so that the gate insulating film covers a portion of the N+ type source region and is not included above the P+ type band region;

[0025] Step 5: forming a gate on the gate insulating film, then growing an insulating film on the gate and the N+ source region and the P+ type band region, and then patterning the insulating film to open a contact area, which is above the polycrystalline SiC layer;

[0026] Step 6: Set a source metal in the contact area to form the source of the MOSFET device; set a drain metal under the SiC substrate to form an ohmic contact, thereby forming the drain of the MOSFET device.

[0027] A silicon carbide power device, wherein the silicon carbide power device is a MOSFET device, and the MOSFET device includes a SiC substrate and a SiC epitaxial layer arranged above the SiC substrate.

[0028] A P-type body is provided on the SiC epitaxial layer, a plurality of N+-type polycrystals and P+-type polycrystals are provided above the P-type body, an N+-source region corresponding to the N+-type polycrystals is provided in the P-type body, and a P+-type band region corresponding to the P+-type polycrystals is also provided in the P-type body;

[0029] A gate insulating film is provided above the P-type body and the SiC epitaxial layer, the gate insulating film covers a portion of the N+ type source region and is not included above the P+ type band region; a gate is provided above the gate insulating film;

[0030] An insulating layer is provided above the gate, a contact region is provided on the insulating layer, the contact region is located above the N+ type polycrystalline and the P+ type polycrystalline, and a source is formed in the contact region;

[0031] A drain is formed under the SiC substrate.

[0032] The SiC substrate is an N-type SiC substrate or a P-type SiC substrate, and the SiC epitaxial layer is an N-type SiC epitaxial layer or a P-type SiC epitaxial layer.

[0033] After adopting the above scheme, the present invention first deposits amorphous SiC at room temperature and injects dopants, and then utilizes high-temperature thermal diffusion to infiltrate the SiC substrate. This process does not need to rely on high-temperature ion injection technology and expensive equipment, and the degree of damage is small, while improving the ohmic contact characteristics. The MPS diode, MOSFET and other power devices also use the above ion implantation method in the preparation process, which does not need to rely on high-temperature ion injection technology and expensive equipment, does not damage the SiC substrate, and improves the reverse bias leakage current of the device and the Schottky barrier lowering effect. At the same time, the ohmic contact characteristics of the anode metal and the grid layer, the source metal and the N+ source region or the P+ band region are improved, which can effectively protect the device in the case of large current surges. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic diagram of the structure of the existing silicon carbide JBS diode;

[0035] Figure 2 The present invention is a flow chart of the existing dopant injection method;

[0036] Figure 3 is a flow chart of the dopant injection method of the present invention;

[0037] Figure 4 It is a schematic diagram of the structure of the MPS power device of the present invention;

[0038] Figure 5 It is a schematic diagram of the structure of the MOSFET of the present invention. DETAILED DESCRIPTION

[0039] Embodiment 1

[0040] like Figure 3 As shown, this embodiment discloses a method for doping a silicon carbide power device, which is specifically as follows:

[0041] Step 1: growing an amorphous SiC layer on a SiC substrate and injecting dopants at room temperature; or growing an amorphous SiC layer containing dopants on a SiC substrate.

[0042] Among them, the SiC substrate can be either an N-type SiC substrate or a P-type SiC substrate. In this embodiment, an N-type SiC substrate is used. The amorphous SiC layer is grown on the SiC substrate by CVD (chemical vapor deposition), sputtering, epitaxy, etc. In this embodiment, the dopant is a P-type dopant, which can specifically be aluminum, boron, etc. If the dopant is an N-type dopant, nitrogen, phosphorus, arsenic, etc. can be used.

[0043] Step 2: After defining the area where the dopant needs to be injected, photolithography is performed to remove the amorphous SiC layer in the area where the dopant does not need to be injected.

[0044] In this embodiment, the photolithography may adopt a wet etching process (wet chemical wet etching).

[0045] Step 3: deposit a cover layer on the SiC substrate and the amorphous SiC layer, and then perform heat treatment: at a temperature above 1500°C, allow the dopant to penetrate into the SiC substrate to form a P-type junction or an N-type junction. At the same time, the amorphous SiC layer is transformed into a polycrystalline SiC layer at high temperature. After the heat treatment is completed, remove the cover layer.

[0046] The material of the cover layer can be photoresist, aluminum nitride (AlN), or boron nitride (BN).

[0047] The method of injecting dopants into the SiC substrate in the above manner does not require the dopants to be injected at high temperatures, nor does it require expensive equipment. In addition, ion implantation at room temperature does not damage the lattice of the SiC substrate, preventing the degradation of device electrical properties such as leakage current and Schottky barrier lowering effect. In addition, the polycrystalline SiC layer produced during the doping process can improve the ohmic contact characteristics and further improve the performance of silicon carbide power devices.

[0048] Embodiment 2

[0049] Based on the dopant injection method of the first embodiment, this embodiment discloses a method for preparing a silicon carbide power device. The silicon carbide power device prepared by the method is an MPS diode device. The preparation method is as follows:

[0050] Step 1: growing a SiC epitaxial layer 101 on a SiC substrate 100;

[0051] Step 2: Use the above-mentioned dopant implantation method to form a polycrystalline SiC layer 104, a P-type or N-type grid 102, and a P-type or N-type protection trench 103 on the SiC epitaxial layer 101. The P-type or N-type grid 102 is located in the active region 120 of the MPS diode, and the P-type or N-type protection trench 103 is located in the peripheral region 121 of the MPS diode.

[0052] The P-type or N-type grid 102 and the P-type or N-type protection trench 103 are formed by diffusion of dopants from the polycrystalline SiC layer 104 into the SiC epitaxial layer 101. The polycrystalline SiC layer 104 is formed from amorphous SiC during a heat treatment process.

[0053] Step 3, growing an insulating film 105 on the SiC epitaxial layer 101 and the polycrystalline SiC layer 104; patterning the top insulating film 105 to remove the silicon oxide in the active area 120; and then covering the active area 120 and a portion of the adjacent peripheral area 121 with an anode metal 106.

[0054] The anode metal 106 may be composed of multiple metal layers, such as Ni, Au, Pt, Ti, Al, Nb, Ta, etc. or a combination thereof. The anode metal 106 has Schottky contact characteristics with the SiC epitaxial layer 101 and has Ohmic contact characteristics with the polycrystalline SiC layer 104 .

[0055] Step 4: Cover the lower end of the SiC substrate 100 with cathode metal 107 to form ohmic contact characteristics.

[0056] In this embodiment, the silicon carbide power device prepared by the above preparation method is as follows: Figure 4 As shown, it includes an N+ type SiC substrate 100 and an N-type SiC epitaxial layer 101 arranged on the N+ type SiC substrate 100, a plurality of polycrystalline SiC layers 104 are formed on the upper end of the N-type SiC epitaxial layer 101, a plurality of P-type junctions corresponding to the polycrystalline SiC layer 104 are formed on the upper part of the N-type SiC epitaxial layer 101, the P-type junction located in the active area 120 is a P-type grid 102, and the P-type junction located in the peripheral area 121 is a P-type protective junction; an insulating film 105 is provided on the N-type SiC epitaxial layer 101 and the polycrystalline SiC layer 104, and the insulating film 105 is located in the peripheral area 121; an anode metal is provided on a part of the active area 120 and the adjacent peripheral area 121, and the anode metal 106 has a Schottky contact characteristic with the N-type SiC epitaxial layer 101 and an ohmic contact characteristic with the polycrystalline SiC layer 104.

[0057] Embodiment 3

[0058] Based on the dopant injection method of the first embodiment described above, this embodiment discloses a method for preparing a silicon carbide power device. The silicon carbide power device prepared by the method is a MOSFET device. The preparation method is specifically as follows:

[0059] Step 1, growing a SiC epitaxial layer on a SiC substrate;

[0060] Step 2: forming a polycrystalline SiC layer and a P-type body on the SiC epitaxial layer by adopting the above-mentioned dopant implantation method;

[0061] Step 3, removing the polycrystalline SiC layer, and continuing to use the above-mentioned dopant injection method to form a polycrystalline SiC layer, a P-type junction and an N-type junction on the P-type body, wherein the P-type junction is a P+ type band region, and the N-type junction is an N+ type source region;

[0062] Step 4, forming a gate insulating film on the P-type body and the SiC epitaxial layer, and then patterning the gate insulating film so that the gate insulating film covers a portion of the N+ type source region and is not included above the P+ type band region;

[0063] Step 5: forming a gate on the gate insulating film, then growing an insulating film on the gate and the N+ source region and the P+ type band region, and then patterning the insulating film to open a contact area, which is above the polycrystalline SiC layer;

[0064] Step 6: Set a source metal in the contact area to form the source of the MOSFET device; set a drain metal under the SiC substrate to form an ohmic contact, thereby forming the drain of the MOSFET device.

[0065] Specifically, in this embodiment, the SiC substrate is an N-type substrate, and the epitaxial layer is an N-type epitaxial layer.

[0066] Figure 5 As shown, an N-type epitaxial layer 101 is grown on an N-type substrate 100. A P-type body 201 is formed by injecting selective P-type dopants (such as Al, B, etc.) and then using the above-mentioned doping method. An N+ type source region 202 and a P+ type band region 203 are in the middle of the P-type body 201. An N-type polycrystalline SiC204 is above the N+ type source region 202. A P-type polycrystalline SiC205 is above the P+ type band region 203. The N+ type source region 202 and the P+ band region 203 are formed by diffusion of n-type polycrystalline SiC204 and P-type polycrystalline SiC205 into the P-type body, respectively, as described in the first embodiment. The N-type polycrystalline SiC204 and the P-type polycrystalline SiC205 can be formed by amorphous SiC during heat treatment. The implementation method of injecting n-type dopants into the P-type doping layer is as described in the first embodiment.

[0067] The gate insulating film 206 is formed on the surface of the P-type body 201 and the N-type epitaxial layer 101, excluding the N+ type source region 202 and the P+ type band region 203. The gate insulating film 206 extends to one side of the N+ type source 202. The gate insulating film 206 can be formed by thermal oxidation or deposition process. The gate insulating film 206 is a gate material 207; it is placed on the top of the polycrystalline SiC, and the gate material 207 is set inside the insulating film 206. The gate material 207, the gate insulating film 206, the N-type polycrystalline SiC204, and the P-type polycrystalline SiC205 insulating film 208 are on the upper part; after the silicon oxide film is grown, the contact area 209 is patterned and opened, and the contact area includes the P-type polycrystalline SiC205 and the N-type polycrystalline SiC204. The P-type polycrystalline SiC205 and the N-type polycrystalline SiC204 in the contact area 209 are covered with the source metal 210 to form a source. A drain metal 211 is prepared under the N-type substrate 100 to form an ohmic contact characteristic.

[0068] The SiC MOSFET formed by the above method is a simple process, because the N+ source and P+ band regions can be formed by injection at room temperature, and no expensive equipment is required. The injection of impurities at room temperature will not damage the SiC substrate, and the reverse bias leakage current and Schottky barrier lowering effect of the device can be improved. In addition, the ohmic contact characteristics of the source metal and the N+ source region or the P+ band region can be improved to improve the current driving capability of the SiCMOSFET.

[0069] The key to the present invention is that the present invention first deposits amorphous SiC at room temperature and injects dopants, and then utilizes high-temperature thermal diffusion to infiltrate the SiC substrate. This process does not rely on high-temperature ion injection technology and expensive equipment, and the degree of damage is small, while improving the ohmic contact characteristics. The MPS diode, MOSFET and other power devices also use the above-mentioned ion implantation method during the preparation process, which does not rely on high-temperature ion injection technology and expensive equipment, does not damage the SiC substrate, and improves the reverse bias leakage current of the device and the Schottky barrier lowering effect. At the same time, the ohmic contact characteristics of the anode metal and the grid layer are improved, and the device can be effectively protected in the case of large current surges.

[0070] The above description is merely an embodiment of the present invention and does not limit the technical scope of the present invention. Therefore, any minor modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A silicon carbide power device, characterized in that: The power device is an MPS diode, and the MPS diode is provided with an active area and a peripheral area; The preparation method of the MPS diode is as follows: Step 1, growing a SiC epitaxial layer on a SiC substrate; Step 2: forming a polycrystalline SiC layer and a P-type junction or an N-type junction on the SiC epitaxial layer, wherein the P-type junction or the N-type junction is located in the active area of ​​the MPS diode to form a P-type or N-type grid, and is located in the peripheral area of ​​the MPS diode to form a P-type or N-type protection trench; specifically as follows: Step 2.1, growing an amorphous SiC layer on a SiC substrate and injecting dopants at room temperature; or, growing an amorphous SiC layer containing dopants on a SiC substrate; Step 2.2, after defining the area where the dopant needs to be injected, photolithography is performed to remove the amorphous SiC layer in the area where the dopant does not need to be injected; Step 2.3, depositing a covering layer on the SiC substrate and the amorphous SiC layer, and then performing heat treatment to form a polycrystalline SiC layer and a P-type junction or an N-type junction, wherein the polycrystalline SiC layer is formed by the transformation of the amorphous SiC layer at high temperature, and the P-type junction or the N-type junction is formed by the dopant in the amorphous SiC penetrating into the SiC substrate at high temperature; after the heat treatment is completed, removing the covering layer; Step 3, growing an insulating film on the SiC epitaxial layer and the polycrystalline SiC layer; Patterning the top insulating film and removing the insulating film in the active area; then covering the active area and a portion of the adjacent peripheral area with an anode metal; the anode metal has a Schottky contact characteristic with the SiC epitaxial layer and an Ohmic contact characteristic with the polycrystalline SiC layer; Step 4: Cover the lower end of the SiC substrate with cathode metal to form ohmic contact characteristics; The MPS diode comprises a SiC substrate and an N-type SiC epitaxial layer arranged on the SiC substrate, a plurality of polycrystalline SiC layers are formed on the upper end of the SiC epitaxial layer, a plurality of P-type junctions corresponding to the polycrystalline SiC layers are formed on the upper part of the SiC epitaxial layer, the P-type junctions located in the active area are P-type grids, the P-type junctions located in the peripheral area are P-type guard junctions, and the P-type grids and the P-type guard trenches are formed by diffusion of P-type dopants in the polycrystalline SiC layer into the epitaxial layer; An insulating film is provided on the SiC epitaxial layer and the polycrystalline SiC layer, and the insulating film is located in the peripheral area; an anode metal is provided on the active area and a part of the adjacent peripheral area, and the anode metal has Schottky contact characteristics with the SiC epitaxial layer and ohmic contact characteristics with the polycrystalline SiC layer.

2. The silicon carbide power device according to claim 1, characterized in that: The SiC substrate is an N-type SiC substrate or a P-type SiC substrate, and the SiC epitaxial layer is an N-type SiC epitaxial layer or a P-type SiC epitaxial layer.

3. The silicon carbide power device according to claim 1, characterized in that: The material of the cover layer is photoresist, aluminum nitride or boron nitride.

4. A method for preparing a silicon carbide power device, wherein the silicon carbide power device prepared by the method is a MOSFET device, characterized in that: The preparation method is as follows: Step 1, growing a SiC epitaxial layer on a SiC substrate; Step 2: forming a polycrystalline SiC layer and a P-type body on the SiC epitaxial layer; specifically as follows: Step 2.1, growing an amorphous SiC layer on the SiC epitaxial layer, and injecting dopants at room temperature; or, growing an amorphous SiC layer containing dopants on the SiC epitaxial layer; Step 2.2, after defining the area where the dopant needs to be injected, photolithography is performed to remove the amorphous SiC layer in the area where the dopant does not need to be injected; Step 2.3, depositing a cover layer on the SiC epitaxial layer and the amorphous SiC layer, and then performing heat treatment to form a polycrystalline SiC layer and a P-type body, wherein the polycrystalline SiC layer is formed by the transformation of the amorphous SiC layer at high temperature, and the P-type body is formed by the dopant in the amorphous SiC penetrating into the SiC epitaxial layer at high temperature; after the heat treatment is completed, removing the cover layer; Step 3, removing the polycrystalline SiC layer, and continuing to form a polycrystalline SiC layer, a P-type junction and an N-type junction on the P-type body, wherein the P-type junction is a P+ type band region, and the N-type junction is an N+ type source region; the details are as follows: Step 3.1, growing an amorphous SiC layer on the P-type body and injecting dopants at room temperature; or, growing an amorphous SiC layer containing dopants on the SiC epitaxial layer; Step 3.2, after defining the area where the dopant needs to be injected, perform photolithography to remove the amorphous SiC layer in the area where the dopant does not need to be injected; Step 3.3, depositing a cover layer on the SiC epitaxial layer and the amorphous SiC layer, and then performing heat treatment to form a polycrystalline SiC layer, a P-type junction and an N-type junction, wherein the polycrystalline SiC layer is formed by the transformation of the amorphous SiC layer at high temperature, and the P-type junction and the N-type junction are formed by the dopant in the amorphous SiC penetrating into the SiC epitaxial layer at high temperature; after the heat treatment is completed, removing the cover layer; Step 4, forming a gate insulating film on the P-type body and the SiC epitaxial layer, and then patterning the gate insulating film so that the gate insulating film covers a portion of the N+ type source region and is not included above the P+ type band region; Step 5: forming a gate on the gate insulating film, then growing an insulating film on the gate and the N+ source region and the P+ type band region, and then patterning the insulating film to open a contact area, which is above the polycrystalline SiC layer; Step 6: Disposing source metal in the contact area to form the source of the MOSFET device; A cathode metal is disposed under the SiC substrate to form an ohmic contact, thereby forming the drain of the MOSFET device.

5. A silicon carbide power device prepared by the method according to claim 4, wherein the silicon carbide power device is a MOSFET device, characterized in that: The MOSFET device includes a SiC substrate and a SiC epitaxial layer arranged above the SiC substrate. A P-type body is provided on the SiC epitaxial layer, a plurality of N+-type polycrystals and P+-type polycrystals are provided above the P-type body, an N+-source region corresponding to the N+-type polycrystals is provided in the P-type body, and a P+-type band region corresponding to the P+-type polycrystals is also provided in the P-type body; A gate insulating film is provided above the P-type body and the SiC epitaxial layer, the gate insulating film covers a portion of the N+ type source region and is not included above the P+ type band region; a gate is provided above the gate insulating film; An insulating layer is provided above the gate, a contact region is provided on the insulating layer, the contact region is located above the N+ type polycrystalline and the P+ type polycrystalline, and a source is formed in the contact region; A drain is formed under the SiC substrate.

6. The silicon carbide power device according to claim 5, characterized in that: The SiC substrate is an N-type SiC substrate or a P-type SiC substrate, and the SiC epitaxial layer is an N-type SiC epitaxial layer or a P-type SiC epitaxial layer.

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